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TPL7407L
SLRS066D – JANUARY 2014 – REVISED MARCH 2016
TPL7407L 40-V 7-Channel Low Side Driver
1 Features
2 Applications
•
•
•
1
•
•
•
•
•
•
•
•
•
•
•
600-mA Rated Drain Current (Per Channel)
CMOS Pin-to-Pin Improvement of 7-channel
Darlington Array (e.g. ULN2003A)
Power Efficient (Very low VOL)
– Less Than 4 Times Lower VOL at 100 mA Than
Darlington Array
Very Low Output Leakage < 10 nA Per Channel
Extended Ambient Temperature Range:
TA = –40°C to 125°C
High-Voltage Outputs 40 V
Compatible with 1.8-V to 5.0-V Micro-controllers
and Logic Interface
Internal Free-wheeling Diodes for Inductive Kickback Protection
Input Pull-down Resistors Allows Tri-stating the
Input Driver
Input RC-Snubber to Eliminate Spurious
Operation in Noisy Environment
Inductive Load Driver Applications
ESD Protection Exceeds JESD 22
– 2-kV HBM, 500-V CDM
Available in 16-pin SOIC and TSSOP Packages
•
•
•
Inductive Loads
– Relays
– Unipolar Stepper & Brushed DC Motors
– Solenoids & Valves
LEDs
Logic Level Shifting
Gate & IGBT Drive
3 Description
The TPL7407L is a high-voltage, high-current NMOS
transistor array. This device consists of seven NMOS
transistors that feature high-voltage outputs with
common-cathode clamp diodes for switching
inductive loads. The maximum drain-current rating of
a single NMOS channel is 600 mA. New regulation
and drive circuitry added to give maximum drive
strength across all GPIO ranges (1.8 V – 5.0 V).The
transistors can be paralleled for higher current
capability.
The TPL7407L's key benefit is its improved power
efficiency and lower leakage than a Bipolar Darlington
Implementation. With the lower VOL the user is
dissipating less than half the power than traditional
relay drivers with currents less than 250 mA per
channel.
Device Information(1)
PART NUMBER
PACKAGE (PINS)
BODY SIZE (NOM)
TPL7407LD
SOIC (16)
9.90 mm x 3.91 mm
TPL7407LPW
TSSOP (16)
5.00 mm x 4.40 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Simple Application Schematic
VSUP
Logic Inputs
(1.8 V to 5 V)
+
TPL7407L
VSUP
IN1
OUT1
IN2
OUT2
IN3
OUT3
IN4
OUT4
IN5
OUT5
IN6
OUT6
IN7
OUT7
GND
M
_
VSUP
COM
CCOM
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPL7407L
SLRS066D – JANUARY 2014 – REVISED MARCH 2016
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Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
3
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
3
4
4
4
4
5
5
6
Absolute Maximum Ratings .....................................
ESD Ratings ............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Switching Characteristics ..........................................
Typical Characteristics ..............................................
Thermal Characteristics ............................................
Detailed Description .............................................. 7
7.1 Overview ................................................................... 7
7.2 Functional Block Diagram ......................................... 7
7.3 Feature Description................................................... 7
7.4 Device Functional Modes.......................................... 7
8
Application and Implementation .......................... 8
8.1 Application Information.............................................. 8
8.2 Typical Application .................................................... 8
9 Power Supply Recommendations...................... 13
10 Layout................................................................... 13
10.1 Layout Guidelines ................................................. 13
10.2 Layout Example .................................................... 13
10.3 Thermal Considerations ........................................ 14
11 Device and Documentation Support ................. 15
11.1
11.2
11.3
11.4
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
15
15
15
15
12 Mechanical, Packaging, and Orderable
Information ........................................................... 15
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (September 2015) to Revision D
Page
•
Added note about driving inductive loads in Inductive Load Driver section. ......................................................................... 8
•
Changed Inductive Load Drive Schematic to reflect note about driving inductive loads. ...................................................... 8
Changes from Revision B (September 2014) to Revision C
•
Changed schematic to correct Zener diode connection ...................................................................................................... 11
Changes from Revision A (August 2014) to Revision B
•
2
Page
Added Handling Rating table, Feature Description section, Device Functional Modes, Application and
Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation
Support section, and Mechanical, Packaging, and Orderable Information section. .............................................................. 1
Changes from Original (January 2014) to Revision A
•
Page
Page
Initial release of full verison. ................................................................................................................................................... 1
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5 Pin Configuration and Functions
D/PW
16-PIN SOIC/TSSOP
TOP VIEW
IN1 1
EMF
Clamp
16 OUT1
IN2 2
EMF
Clamp
15 OUT2
IN3 3
EMF
Clamp
14 OUT3
IN4 4
EMF
Clamp
13 OUT4
IN5 5
EMF
Clamp
12 OUT5
IN6 6
EMF
Clamp
11 OUT6
IN7 7
EMF
Clamp
10 OUT7
GND 8
LDO
9 COM
Pin Functions
PIN
NAME
I/O
NO.
DESCRIPTION
COM
9
—
Supply pin that should be tied to 8.5 V or higher for proper operation (see
Power Supply Recommendations for further instruction)
GND
8
—
Ground pin
IN(X)
1, 2, 3, 4, 5, 6, 7
I
GPIO inputs that will drive the outputs "low" (or sink current) when driven
"high"
16, 15, 14, 13, 12,
11, 10
O
Driver output that sinks currents after input is driven "high"
OUT(X)
6 Specifications
6.1 Absolute Maximum Ratings
at 25°C free-air temperature (unless otherwise noted)
VOUT
(1)
Pins OUT1-OUT7 to GND voltage
VOK
Output Clamp diode reverse voltage
VCOM
COM pin voltage (2)
VIN
Pins IN1-IN7 to GND voltage
(2)
(2)
MIN
MAX
UNIT
–0.3
42
V
–0.3
42
V
–0.3
42
V
–0.3
30
V
(3) (4)
IDS
Continuous drain current per channel
600
mA
IOK
Output clamp current
500
mA
IGND
Total continuous GND-pin current
–2
A
TA
Operating free-air temperature range
–40
125
°C
TJ
Operating virtual junction temperature
–40
150
°C
Tstg
Storage temperature range
–65
150
°C
(1)
(2)
(3)
(4)
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to the GND/substrate pin, unless otherwise noted.
Maximum power dissipation is a function of TJ(max), θJA, and TA. The maximum allowable power dissipation at any allowable ambient
temperature is PD = (TJ(max) – TA)/θJA. Operating at the absolute maximum TJ of 150°C can affect reliability.
The package thermal impedance is calculated in accordance with JESD 51-7.
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6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 500-V HBM is possible with the necessary precautions.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 250-V CDM is possible with the necessary precautions.
6.3 Recommended Operating Conditions
Over operating temperature range
MIN
MAX
0
40
V
VOUT
OUT1 – OUT7 pin voltage for recommended operation
VCOM
COM pin voltage range for full output drive
VIL
IN1- IN7 input low voltage ("Off" high impedance output)
VIH
IN1- IN7 input high voltage ("Full Drive" low impedance output)
1.5
TJ
Operating virtual junction temperature
IDS
Continuous drain current
8.5
UNIT
40
V
0.9
V
–40
125
°C
0
500
mA
V
6.4 Thermal Information
TPL7407L
THERMAL METRIC (1)
SOIC (D)
TSSOP (PW)
16 PINS
16 PINS
UNIT
θJA
Junction-to-ambient thermal resistance
91.9
115.2
°C/W
θJCtop
Junction-to-case (top) thermal resistance
50.1
49.5
°C/W
θJB
Junction-to-board thermal resistance
49.4
60.8
°C/W
ψJT
Junction-to-top characterization parameter
18.6
8.5
°C/W
ψJB
Junction-to-board characterization parameter
49.1
60.2
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report (SPRA953).
6.5 Electrical Characteristics
TJ= –40°C to 125°C; Typical Values at TA=TJ= 25°C
PARAMETER
VOL (VDS)
TEST CONDITIONS
VIN ≥ 1.5 V
OUT1- OUT7 low-level output
voltage
TYP
MAX
ID = 100 mA
200
320
ID = 200 mA
420
650
VIN ≤ 1.0 V
10
500
nA
1.4
V
500
nA
10
μA
25
μA
IOUT(OFF) (IDS_OFF) OUT1- OUT7 OFF-state leakage
current
VOUT = 24 V,
VF
Clamp forward voltage
IF = 200 mA
IIN(off)
IN1- IN7 Off-state input current
VINX= 0 V
IIN(ON)
IN1- IN7 ON state input current
VINX=1.5 V - 5.0
V
ICOM
Static current flowing through COM
pin
VCOM = 8.5 V - 40 V
4
MIN
VOUT = 40 V
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UNIT
mV
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6.6 Switching Characteristics
Typical Values at TA=TJ= 25°C
PARAMETER
TEST CONDITIONS
MIN
tPLH
Propagation delay time, low- to high-level output
VINX ≥ 1.65 V, Vpull-up = 24 V, Rpull-up =
48 Ω
tPHL
Propagation delay time, high- to low-level output
VINX ≥ 1.65 V, Vpul-lup = 24 V, Rpull-up =
48 Ω
Ci
Input capacitance
VI = 0,
TYP
f = 100 kHz
MAX
UNIT
350
ns
350
ns
5
pF
6.7 Typical Characteristics
1.6
0.8
25°C
70°C
105°C
-40°C
1.4
1.2
0.7
0.6
0.5
IF (A)
VOL (V)
1
0.8
0.4
0.6
0.3
0.4
0.2
0.2
0.1
0
0
200
400
600
Output Drain Current IDS (mA)
800
0
0
0.2
D001
Figure 1. VOL (VDS)
0.4
0.6
0.8
VF (V)
1
1.2
1.4
1.6
D002
Figure 2. Flyback Diode Forward Voltage
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6.8 Thermal Characteristics
0.55
N
N
N
N
N
N
N
0.5
0.45
0.4
0.35
0.3
=1
=2
=3
=4
=5
=6
=7
0.25
0.2
0.15
0.1
0.05
0
25
45
65
85
Ambient Temperature (°C)
105
Maximum Current Per Channel (A)
Maximum Current Per Channel (A)
0.55
N
N
N
N
N
N
N
0.5
0.45
0.4
0.35
0.3
0.25
0.2
0.15
0.1
0.05
0
25
125
105
125
D004
0.55
N
N
N
N
N
N
N
0.5
0.45
0.4
0.35
0.3
=1
=2
=3
=4
=5
=6
=7
0.25
0.2
0.15
0.1
0.05
Maximum Current Per Channel (A)
Maximum Current Per Channel (A)
65
85
Ambient Temperature (°C)
Figure 4. Maximum Output Current vs. Temperature
(TSSOP)
0.55
0
N
N
N
N
N
N
N
0.5
0.45
0.4
0.35
0.3
=1
=2
=3
=4
=5
=6
=7
0.25
0.2
0.15
0.1
0.05
0
0
20%
40%
60%
Duty Cycle
80%
100%
0
20%
D005
Figure 5. D Package Maximum Collector Current vs. Duty
Cycle at 25°C
40%
60%
Duty Cycle
80%
100%
D006
Figure 6. D Package Maximum Collector Current vs. Duty
Cycle at 70°C
0.55
N
N
N
N
N
N
N
0.5
0.45
0.4
0.35
0.3
=1
=2
=3
=4
=5
=6
=7
0.25
0.2
0.15
0.1
0.05
0
Maximum Current Per Channel (A)
0.55
Maximum Current Per Channel (A)
45
D003
Figure 3. Maximum Output Current vs. Temperature (SOIC)
N
N
N
N
N
N
N
0.5
0.45
0.4
0.35
0.3
=1
=2
=3
=4
=5
=6
=7
0.25
0.2
0.15
0.1
0.05
0
0
20%
40%
60%
Duty Cycle
80%
100%
0
D007
Figure 7. PW Package Maximum Collector Current vs. Duty
Cycle at 25°C
6
=1
=2
=3
=4
=5
=6
=7
20%
40%
60%
Duty Cycle
80%
100%
D008
Figure 8. PW Package Maximum Collector Current vs. Duty
Cycle at 70°C
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7 Detailed Description
7.1 Overview
This device has proven ubiquity and versatility across a wide range of applications. This is due to it's integration
of 7 low side NMOS transistors that are capable of sinking up to 600mA and wide GPIO range capability.
The TPL7407L comprises seven high voltage, high current NMOS transistors tied to a common ground driven by
internal level shifting and gate drive circuitry. The TPL7407L offers solutions to many interface needs, including
solenoids, relays, lamps, small motors, and LEDs. Applications requiring sink currents beyond the capability of a
single output may be accommodated by paralleling the outputs.
The TPL7407L also enables pin to pin replacement with legacy 7 channel darlington pair implementations
This device can operate over a wide temperature range (–40°C to 125°C).
7.2 Functional Block Diagram
COM
Regulation
Circuitry
OUT(1-7)
50k
DRIVER
IN(1-7)
1M
OVP
7.3 Feature Description
Each channel of TPL7407L consists of high power low side NMOS transistors driven by level shifting and gate
driving circuitry. The gate drivers allow for high output current drive with a very low input voltage, essentially
equating to operability with low GPIO voltages.
In order to enable floating inputs a 1MΩ pull-down resistor exists on each channel. Another 50-kΩ resistor exists
between the input and gate driving circuitry. This exists to limit the input current whenever there is an over
voltage and the internal Zener clamps. It also interacts with the inherent capacitance of the gate driving circuitry
to behave as an RC snubber to help prevent spurious switching in noisy environment.
In order to power the gate driving circuitry an LDO exists. See Power Supply Recommendations for further detail
on this circuitry.
The diodes connected between the output and COM pin is used to surpress kick-back voltage from an inductive
load that is excited when the NMOS drivers are turned off (stop sinking) and the stored energy in the coils
causes a reverse current to flow into the coil supply.
7.4 Device Functional Modes
7.4.1 Inductive Load Drive
When the COM pin is tied to the coil supply voltage, TPL7407L is able to drive inductive loads and supress the
kick-back voltage via the internal free wheeling diodes.
7.4.2 Resistive Load Drive
When driving a resistive load, a pull-up resistor is needed in order for TPL7407L to sink current and for there to
be a logic high level. The COM pin should be supplied ≥8.5V for full functionality.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
TPL7407L will typically be used to drive a high voltage and/or current peripheral from an MCU or logic device
that cannot tolerate these conditions. The following design is a common application of TPL7407L, driving
inductive loads. This includes motors, solenoids & relays. Each load type can be modeled by what's seen in
Figure 9.
8.2 Typical Application
8.2.1 Inductive Load Driver
Please note that inductive loads, such as stepper motors or relays, can generate negative transients on the
OUTx pins of the device. Typically this occurs when the output channel FET turns ON, pulling the OUTx node to
ground. This can cause the OUTx node to go below the voltage rating listed in the Absolute Maximum Ratings
table, which in effect causes excessive ground current leakage. This effect is only seen on the OUT7 pin, and
prolonged usage in this condition can cause permanent damage to the device.
If the application has an inductive load connected to OUT7, it is recommended to use an external Schottky diode
to protect the OUT7 pin from negative transients larger than those listed in the Absolute Maximum Ratings table,
such as in Figure 9 below.
Figure 9. Inductive Load Driver Schematic
8
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Typical Application (continued)
8.2.1.1 Design Requirements
For this design example, use the parameters listed in Table 1 as the input parameters.
Table 1. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
GPIO Voltage
1.8 V, 3.3 V or 5.0 V
Coil Supply Voltage
8.5 V to 40 V
Number of Channels
7
Output Current (RCOIL)
20 mA to 300 mA per channel
CCOM
0.1 µF
Duty Cycle
100%
8.2.1.2 Detailed Design Procedure
When using TPL7407L in a coil driving application, determine the following:
• Input Voltage Range
• Temperature Range
• Output & Drive Current
• Power Dissipation
8.2.1.2.1 TTL and other Logic Inputs
TPL7407L input interface is specified for standard 1.8 V through 5 V CMOS logic interface and can tolerate up to
30 V. At any input voltage the output drivers will be driven at it's maximum when Vcom is greater than or equal to
8.5 V.
8.2.1.2.2 Input RC Snubber
TPL7407L features an input RC snubber that helps prevent spurious switching in noisy environments. Connect
an external 1 kΩ to 5 kΩ resistor in series with the input to further enhance TPL7407L’s noise tolerance.
8.2.1.2.3 High-impedance Input Drivers
TPL7407L features a 1-MΩ input pull-down resistor. The presence of this resistor allows the input drivers to be
tri-stated. When a high-impedance driver is connected to a channel input the TPL7407L detects the channel
input as a low level input and remains in the OFF position. The input RC snubber helps improve noise tolerance
when input drivers are in the high-impedance state.
8.2.1.2.4 Drive Current
The coil current is determined by the coil voltage (VSUP), coil resistance & output low voltage (VOL).
ICOIL= (VSUP - VOL)/RCOIL
(1)
8.2.1.2.5 Output Low Voltage
The output low voltage (VOL) is drain to source (VDS) voltage of the output NMOS transistors when the input is
driven high and it is sinking current and can be determined by Specifications or Figure 1.
8.2.1.3 Application Curves
The following curve was generated with TPL7407L driving an OMRON G5NB relay -- Vin = 5.0 V; Vsup = 24 V &
RCOIL = 2.8 kΩ
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29
27
25
23
21
Voltage (V)
19
17
15
13
11
9
7
5
3
1
-1
0
0.005
0.01
0.015
0.02
0.025
Time (s)
Figure 10. Output Response With De-activation of Coil (Turn Off)
10
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8.2.2 Unipolar Stepper Motor Driver
Motor
VSUP
Motor Control Pulses
(1.8 V to 5 V)
TPL7407L
IN1
OUT1
Phase_A
IN2
OUT2
Phase_C
IN3
OUT3
IN4
OUT4
IN5
OUT5
IN6
OUT6
IN7
OUT7
GND
Phase_B
Optional
Phase_D
COM
CCOM
Figure 11. Stepper Motor Driver Schematic
8.2.2.1 Design Requirements
Figure 11 shows an implementation of TPL7407L for driving a uniploar stepper motor. The unconnected input
channels can be used for other functions. When an input pin is left open the internal 1 MΩ pull down resistor
pulls the respective input pin to GND potential. For higher noise immunity use an external short across an
unconnected input and GND pins. The COM pin must be tied to the supply of whichever inductive load is being
driven for the driver to be protected by the free-wheeling diode.
Whenever a Zener diode is used between Vcom and the motor supply, the Vcom pin will slew from the coil
supply to a voltage that is the sum of the Zener voltage and the coil supply when there is a flyback event.
Depending on the coil inductance and resistance, this can be very rapid. Whenever the COM pin experiences a
slew rate greater than 0.5 V/µs, a capacitor must be added to limit the slew to < 0.5 V/µs. See Power Supply
Recommendations for further explanation.
8.2.2.2 Detailed Design Procedure
Refer to Design Requirements.
8.2.2.3 Application Curves
Refer to Thermal Characteristics.
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8.2.3 Multi-Purpose Sink Driver
VSUP
Logic Inputs
(1.8 V to 5 V)
+
TPL7407L
VSUP
IN1
OUT1
IN2
OUT2
IN3
OUT3
IN4
OUT4
IN5
OUT5
IN6
OUT6
IN7
OUT7
GND
M
_
VSUP
COM
CCOM
Figure 12. Multi-Purpose Sink Driver Schematic
8.2.3.1 Design Requirements
When configured as per Figure 12 TPL7407L may be used as a multi-purpose driver. The output channels may
be tied together to sink more current. TPL7407L can easily drive motors, relays & LEDs with little power
dissipation. COM must be tied to highest load voltage, which may or may not be same as inductive load supply.
8.2.3.2 Detailed Design Procedure
Refer to Design Requirements.
8.2.3.3 Application Curves
Refer to Thermal Characteristics.
12
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9 Power Supply Recommendations
The COM pin is the power supply pin of this device to power the gate drive circuitry. This ensures full drive
potential with any GPIO above 1.5 V. The gate drive circuitry is based on low voltage CMOS transistors that can
only handle a max gate voltage of 7 V. An integrated LDO reduces the COM voltage of 8.5 V to 40 V to a
regulated voltage of 7 V. Though 8.5 V minimum is recommended for Vcom, the part will still function with a
reduced COM voltage that has a reduced gate drive voltage and a resulting higher Rdson.
The COM pin must be limited to below 0.5 V/μsTo prevent overvoltage on the internal LDO output due to a line
transient on the COM pin. Faster slew-rate (or hot-plug) may cause damage to the internal gate driving circuitry
due to the LDO's inability to clamp a fast input transient fast enough. Since most modern power supplies are
loaded by capacitors > 10 μF, this should not be of any concern. It is recommended to use a bypass capacitor
that will limit the slew rate to below 0.5 V/μs.
Figure 11 is a great example where repetitive slew rates may occur on the Vcom pin. Whenever a Zener diode is
used between Vcom and the motor supply, the Vcom pin will slew from the coil supply to a voltage that is the
sum of the Zener voltage and the coil supply when there is a flyback event. Depending on the coil inductance
and resistance, this can be very rapid.
In summary, whenever the COM pin may experience a slew rate greater than 0.5 V/µs a capacitor must be
added to limit the slew to < 0.5 V/µs.
10 Layout
10.1 Layout Guidelines
Thin traces can be used on the input due to the low current logic that is typically used to drive TPL7407L. Care
must be taken to separate the input channels as much as possible, as to eliminate cross-talk. Thick traces are
recommended for the output, in order to drive whatever high currents that may be needed. Wire thickness can be
determined by the trace material's current density and desired drive current.
Since all of the channels currents return to a common ground, it is best to size that trace width to be very wide.
Some applications require up to 2 A.
Since the COM pin will only draw up to 25 µA thick traces are not necessary.
10.2 Layout Example
TPL7407L
IN1
OUT1
IN2
OUT2
IN3
OUT3
IN4
OUT4
IN5
OUT5
IN6
OUT6
IN7
OUT7
GND
COM
GND
CCOM
Only needed for
fluctuating or
high slew rate
supplies
Ground
Figure 13. Package Layout
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TPL7407L
SLRS066D – JANUARY 2014 – REVISED MARCH 2016
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10.3 Thermal Considerations
The number of coils driven is dependent on the coil current and on-chip power dissipation. The number of coils
driven can be determined by Figure 3, Figure 4, Figure 5, Figure 6, Figure 7, or Figure 8.
For a more accurate determination of number of coils possible, use the below equation to calculate TPL7407L
on-chip power dissipation PD:
N
PD = å VOLi ´ ILi
i=1
Where:
N is the number of channels active together.
VOLi is the OUTi pin voltage for the load current ILi. This is the same as VCE(SAT)
(2)
In order to guarantee reliability of TPL7407L and the system, the on-chip power dissipation must be lower than or
equal to the maximum allowable power dissipation (PD(MAX)) dictated by below equation Equation 3.
PD(MAX) =
(T
J(MAX)
- TA )
qJA
Where:
TJ(MAX) is the target maximum junction temperature.
TA is the operating ambient temperature.
θJA is the package junction to ambient thermal resistance.
(3)
It is recommended to limit TPL7407L IC’s die junction temperature to less than 125°C. The IC junction
temperature is directly proportional to the on-chip power dissipation.
10.3.1 Improving Package Thermal Performance
θJA value depends on the PC board layout. An external heat sink and/or a cooling mechanism, like a cold air fan,
can help reduce θJA and thus improve device thermal capabilities. Refer to TI’s design support web page at
www.ti.com/thermal for a general guidance on improving device thermal performance.
14
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Product Folder Links: TPL7407L
TPL7407L
www.ti.com
SLRS066D – JANUARY 2014 – REVISED MARCH 2016
11 Device and Documentation Support
11.1 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.2 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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15
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPL7407LDR
ACTIVE
SOIC
D
16
2500
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
TPL7407L
TPL7407LPWR
ACTIVE
TSSOP
PW
16
2000
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
TPL7407L
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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