TPS2011DR

TPS2010, TPS2011, TPS2012, TPS2013 POWER-DISTRIBUTION SLVS097A – DECEMBER 1994 – REVISED AUGUST 1995 D D D D D D D D D D D PACKAGE (TOP VIEW) 95-mΩ Max (5.5-V Input) High-Side MOSFET Switch With Logic Compatible Enable Input Short-Circuit and Thermal Protection Typical Short-Circuit Current Limits: 0.4 A, TPS2010; 1.2 A, TPS2011; 2 A, TPS2012; 2.6 A, TPS2013 Electrostatic-Discharge Protection, 12-kV Output, 6-kV All Other Terminals Controlled Rise and Fall Times to Limit Current Surges and Minimize EMI SOIC-8 Package Pin Compatible With the Popular Littlefoot Series When GND Is Connected 2.7-V to 5.5-V Operating Range 10-µA Maximum Standby Current Surface-Mount SOIC-8 and TSSOP-14 Packages – 40°C to 125°C Operating Junction Temperature Range GND IN IN EN 1 8 2 7 3 6 4 5 OUT OUT OUT OUT PW PACKAGE (TOP VIEW) GND IN IN IN IN IN EN 1 14 2 13 3 12 4 11 5 10 6 9 7 8 OUT OUT OUT OUT OUT OUT OUT description The TPS201x family of power-distribution switches is intended for applications where heavy capacitive loads and short circuits are likely to be encountered. The high-side switch is a 95-mΩ N-channel MOSFET. Gate drive is provided by an internal driver and charge pump designed to control the power switch rise times and fall times to minimize current surges during switching. The charge pump operates at 100 kHz, requires no external components, and allows operation from supplies as low as 2.7 V. When the output load exceeds the current-limit threshold or a short circuit is present, the TPS201x limits the output current to a safe level by switching into a constant-current mode. Continuous heavy overloads and short circuits increase power dissipation in the switch and cause the junction temperature to rise. If the junction temperature reaches approximately 180°C, a thermal protection circuit shuts the switch off to prevent damage. Recovery from thermal shutdown is automatic once the device has cooled sufficiently. The members of the TPS201x family differ only in short-circuit current threshold. The TPS2010 is designed to limit at 0.4-A load; the other members of the family limit at 1.2 A, 2 A, and 2.6 A (see the available options table). The TPS201x family is available in 8-pin small-outline integrated circuit (SOIC) and 14-pin thin shink small-outline (TSSOP) packages and operates over a junction temperature range of – 40°C to 125°C. Versions in the 8-pin SOIC package are drop-in replacements for Siliconix’s Littlefoot power PMOS switches, except that GND must be connected. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright  1995, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 TPS2010, TPS2011, TPS2012, TPS2013 POWER-DISTRIBUTION SLVS097A – DECEMBER 1994 – REVISED AUGUST 1995 AVAILABLE OPTIONS TJ PACKAGED DEVICES RECOMMENDED MAXIMUM CONTINUOUS LOAD CURRENT (A) TYPICAL SHORT-CIRCUIT OUTPUT CURRENT LIMIT AT 25°C (A) SOIC (D)† TSSOP (PW)‡ CHIP FORM (Y) 0.2 0.4 TPS2010D TPS2010PWLE TPS2010Y 0.6 1.2 TPS2011D TPS2011PWLE TPS2011Y 1 2 TPS2012D TPS2012PWLE TPS2012Y – 40°C to 125°C 1.5 2.6 TPS2013D TPS2013PWLE TPS2013Y † The D package is available taped and reeled. Add an R suffix to device type (e.g., TPS2010DR). ‡ The PW package is only available left-end taped and reeled (indicated by the LE suffix on the device type; e.g., TPS2010PWLE). functional block diagram Power Switch CS IN † OUT Charge Pump Driver EN GND Current Limit Thermal Sense † Current sense Terminal Functions TERMINAL NAME NO. I/O DESCRIPTION D PW EN 4 7 I Enable input. Logic low turns power switch on. GND 1 1 I Ground IN 2, 3 2–6 I Input voltage OUT 5–8 8 – 14 O Power-switch output detailed description power switch The power switch is an N-channel MOSFET with a maximum on-state resistance of 95 mΩ (VI(IN) = 5.5 V), configured as a high-side switch. charge pump An internal 100-kHz charge pump supplies power to the driver circuit and provides the necessary voltage to pull the gate of the MOSFET above the source. The charge pump operates from input voltages as low as 2.7 V and requires very little supply current. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TPS2010, TPS2011, TPS2012, TPS2013 POWER-DISTRIBUTION SLVS097A – DECEMBER 1994 – REVISED AUGUST 1995 detailed description (continued) driver The driver controls the gate voltage of the power switch. To limit large current surges and reduce the associated electromagnetic interference (EMI) produced, the driver incorporates circuitry that controls the rise times and fall times of the output voltage. The rise and fall times are typically in the 2-ms to 4-ms range instead of the microsecond or nanosecond range for a standard FET. enable (EN) A logic high on the EN input turns off the power switch and the bias for the charge pump, driver, and other circuitry to reduce the supply current to less than 10 µA. A logic zero input restores bias to the drive and control circuits and turns the power on. The enable input is compatible with both TTL and CMOS logic levels. current sense A sense FET monitors the current supplied to the load. The sense FET is a much more efficient way to measure current than conventional resistance methods. When an overload or short circuit is encountered, the current-sense circuitry sends a control signal to the driver. The driver in turn reduces the gate voltage and drives the power FET into its linear region, which switches the output into a constant current mode and simply holds the current constant while varying the voltage on the load. thermal sense An internal thermal-sense circuit shuts the power switch off when the junction temperature rises to approximately 180°C. Hysteresis is built into the thermal sense, and after the device has cooled approximately 20 degrees, the switch turns back on. The switch continues to cycle off and on until the fault is removed. TPS201xY chip information This chip, when properly assembled, displays characteristics similar to the TPS201xC. Thermal compression or ultrasonic bonding may be used on the doped aluminum bonding pads. The chip may be mounted with conductive epoxy or a gold-silicon preform. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 TPS2010, TPS2011, TPS2012, TPS2013 POWER-DISTRIBUTION SLVS097A – DECEMBER 1994 – REVISED AUGUST 1995 BONDING PAD ASSIGNMENTS (8) (1) (7) GND IN IN EN (1) (8) (2) (7) (3) TPS201xY (4) (6) (5) OUT OUT OUT OUT (2) 81 (3) CHIP THICKNESS: 15 MILS TYPICAL BONDING PADS: 4 × 4 MILS MINIMUM TJmax = 150°C TOLERANCES ARE ± 10% (4) (5) (6) ALL DIMENSIONS ARE IN MILS 72 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Input voltage range, VI(IN) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 7 V Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to VI(IN) + 0.3 V Input voltage range, VI at EN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 7 V Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . internally limited Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table Operating virtual junction temperature range, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 40°C to 125°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C Lead temperature soldering 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . 260°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltages are with respect to GND. DISSIPATION RATING TABLE 4 PACKAGE TA ≤ 25°C POWER RATING D PW 725 mW 700 mW DERATING FACTOR ABOVE TA = 25°C 5.8 mW/°C 5.6 mW/°C POST OFFICE BOX 655303 TA = 70°C POWER RATING TA = 125°C POWER RATING 464 mW 448 mW 145 mW 140 mW • DALLAS, TEXAS 75265 TPS2010, TPS2011, TPS2012, TPS2013 POWER-DISTRIBUTION SLVS097A – DECEMBER 1994 – REVISED AUGUST 1995 recommended operating conditions Input voltage, VI(IN) Input voltage, VI at EN Continuous output current current, IO MIN MAX 2.7 5.5 V V 0 5.5 TPS2010 0 0.2 TPS2011 0 0.6 TPS2012 0 1 TPS2013 0 1.5 – 40 125 Operating virtual junction temperature, TJ UNIT A °C electrical characteristics over recommended operating junction temperature range, VI(IN) = 5.5 V, IO = rated current, EN = 0 V (unless otherwise noted) power switch TPS2010, TPS2011 TPS2012, TPS2013 TEST CONDITIONS† PARAMETER MIN UNIT TYP MAX 95 VI(IN) = 5.5 V, VI(IN) = 4.5 V, TJ = 25°C TJ = 25°C 75 80 110 VI(IN) = 3 V, VI(IN) = 2.7 V, TJ = 25°C TJ = 25°C 120 175 140 215 Output leakage current EN = VI(IN) TJ = 25°C – 40°C ≤ TJ ≤ 125°C tr Output rise time VI(IN) = 5.5 V, VI(IN) = 2.7 V, TJ = 25°C, TJ = 25°C, CL = 1 µF 4 CL = 1 µF 3.8 tf Output fall time VI(IN) = 5.5 V, VI(IN) = 2.7 V, TJ = 25°C, TJ = 25°C, CL = 1 µF 3.9 CL = 1 µF 3.5 On state resistance On-state 0.001 1 10 mΩ µA ms ms † Pulse-testing techniques maintain junction temperature close to ambient temperature; thermal effects must be taken into account separately. enable input (EN) PARAMETER TPS2010, TPS2011 TPS2012, TPS2013 TEST CONDITIONS MIN 2.7 V ≤ VI(IN) ≤ 5.5 V High-level input voltage Low level input voltage Low-level tPLH tPHL TYP UNIT MAX 2 V 4.5 V ≤ VI(IN) ≤ 5.5 V 0.8 2.7 V ≤ VI(IN) < 4.5 V 0.4 Input current EN = 0 V or EN = VI(IN) Propagation (delay) time, low-to-high-level output CL = 1 µF – 0.5 0.5 20 Propagation (delay) time, high-to-low-level output CL = 1 µF 40 V µA ms current limit PARAMETER Short circuit current Short-circuit TPS2010, TPS2011 TPS2012, TPS2013 TEST CONDITIONS† TJ = 25°C 25 C, VI(IN) = 5.5 V, OUT connected to GND, device enabled into short circuit UNIT MIN TYP MAX TPS2010 0.22 0.4 0.6 TPS2011 0.66 1.2 1.8 TPS2012 1.1 2 3 A TPS2013 1.65 2.6 4.5 † Pulse-testing techniques maintain junction temperature close to ambient temperature; thermal effects must be taken into account separately. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 TPS2010, TPS2011, TPS2012, TPS2013 POWER-DISTRIBUTION SLVS097A – DECEMBER 1994 – REVISED AUGUST 1995 electrical characteristics over recommended operating junction temperature range, VI(IN) = 5.5 V, IO = rated current, EN = 0 V (unless otherwise noted) (continued) supply current PARAMETER TEST CONDITIONS TPS2010, TPS2011 TPS2012, TPS2013 MIN UNIT TYP MAX 1 level output Supply current current, low low-level TJ = 25°C – 40°C ≤ TJ ≤ 125°C 0.015 EN = VI(IN) Supply current, current high-level high level output EN = 0 V TJ = 25°C – 40°C ≤ TJ ≤ 125°C 73 10 100 100 µA µA electrical characteristics over recommended operating junction temperature range, VI(IN) = 5.5 V, IO = rated current, EN = 0 V, TJ = 25°C (unless otherwise noted) power switch TEST CONDITIONS† PARAMETER TPS2010Y, TPS2011Y TPS2012Y, TPS2013Y MIN On state resistance On-state TYP VI(IN) = 5.5 V, VI(IN) = 4.5 V, 75 VI(IN) = 3 V, VI(IN) = 2.7 V, 120 UNIT MAX 80 mΩ 140 Output leakage current EN = VI(IN) Output rise time VI(IN) = 5.5 V, VI(IN) = 2.7 V, CL = 1 µF 4 CL = 1 µF 3.8 Output fall time VI(IN) = 5.5 V, VI(IN) = 2.7 V, CL = 1 µF 3.9 CL = 1 µF 3.5 µA 0.001 ms ms † Pulse-testing techniques maintain junction temperature close to ambient temperature; thermal effects must be taken into account separately. current limit TEST CONDITIONS† PARAMETER TPS2010Y, TPS2011Y TPS2012Y, TPS2013Y MIN VI(IN) = 5.5 V, OUT connected to GND, Device enabled into short circuit Short-circuit current TYP UNIT MAX 0.4 A † Pulse-testing techniques maintain junction temperature close to ambient temperature; thermal effects must be taken into account separately. supply current PARAMETER TEST CONDITIONS TPS2010Y, TPS2011Y TPS2012Y, TPS2013Y MIN Supply current, low-level output EN = VI(IN) Supply current, high-level output EN = 0 V 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TYP UNIT MAX 0.015 µA 73 µA TPS2010, TPS2011, TPS2012, TPS2013 POWER-DISTRIBUTION SLVS097A – DECEMBER 1994 – REVISED AUGUST 1995 4 2 0 6 4 2 0 –1 6 Enable Voltage – V 6 V O – Output Voltage – V V O – Output Voltage – V Enable Voltage – V PARAMETER MEASUREMENT INFORMATION 0 1 2 3 4 5 6 7 8 9 4 2 0 6 4 2 0 –1 0 5 10 t – Time – ms Enable Voltage – V 4 2 0 4 2 0 0 1 2 3 4 5 20 25 30 35 40 45 Figure 2. Propagation Delay and Fall Time With 1-µF Load, VI(IN) = 5.5 V V O – Output Voltage – V V O – Output Voltage – V Enable Voltage – V Figure 1. Propagation Delay and Rise Time With 1-µF Load, VI(IN) = 5.5 V –1 15 t – Time – ms 6 7 8 9 4 2 0 4 2 0 –1 0 5 t – Time – ms 10 15 20 25 30 35 40 45 t – Time – ms Figure 3. Propagation Delay and Rise Time With 1-µF Load, VI(IN) = 2.7 V POST OFFICE BOX 655303 Figure 4. Propagation Delay and Fall Time With 1-µF Load, VI(IN) = 2.7 V • DALLAS, TEXAS 75265 7 TPS2010, TPS2011, TPS2012, TPS2013 POWER-DISTRIBUTION SLVS097A – DECEMBER 1994 – REVISED AUGUST 1995 V O – Output Voltage – V 5 0 8 6 I O – Output Current – A I O – Output Current – A V O – Output Voltage – V PARAMETER MEASUREMENT INFORMATION 4 2 0 –1 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 0 8 6 4 2 0 –1 0 0.5 1 t – Time – ms 5 0 8 2.5 3 3.5 4 4.5 5 0 8 6 I O – Output Current – A I O – Output Current – A 6 4 2 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 4 2 0 –1 0 t – Time – ms 0.5 1 1.5 2 2.5 3 3.5 4 4.5 t – Time – ms Figure 7. TPS2012, Short-Circuit Current. Short is Applied to Enabled Device, VI(IN) = 5.5 V 8 2 Figure 6. TPS2011, Short-Circuit Current. Short is Applied to Enabled Device, VI(IN) = 5.5 V V O – Output Voltage – V V O – Output Voltage – V Figure 5. TPS2010, Short-Circuit Current. Short is Applied to Enabled Device, VI(IN) = 5.5 V –1 1.5 t – Time – ms POST OFFICE BOX 655303 Figure 8. TPS2013 – Short-Circuit Current. Short is Applied to Enabled Device, VI(IN) = 5.5 V • DALLAS, TEXAS 75265 TPS2010, TPS2011, TPS2012, TPS2013 POWER-DISTRIBUTION SLVS097A – DECEMBER 1994 – REVISED AUGUST 1995 V O – Output Voltage – V V O – Output Voltage – V PARAMETER MEASUREMENT INFORMATION 5 0 I O – Output Current – A I O – Output Current – A 0 4 3 3 2 1 0 –1 5 0 2 4 6 8 10 12 14 16 18 20 2 1 0 –1 0 2 4 6 t – Time – ms V O – Output Voltage – V V O – Output Voltage – V 12 14 16 18 20 Figure 10. TPS2011 – Threshold Current, VI(IN) = 5.5 V 5 0 4 3 5 0 8 6 I O – Output Current – A I O – Output Current – A 10 t – Time – ms Figure 9. TPS2010 – Threshold Current, VI(IN) = 5.5 V 2 1 0 –1 8 0 2 4 6 8 10 12 14 16 18 20 4 2 0 –1 0 2 4 t – Time – ms 6 8 10 12 14 16 18 20 t – Time – ms Figure 11. TPS2012 – Threshold Current, VI(IN) = 5.5 V POST OFFICE BOX 655303 Figure 12. TPS2013 – Threshold Current, VI(IN) = 5.5 V • DALLAS, TEXAS 75265 9 TPS2010, TPS2011, TPS2012, TPS2013 POWER-DISTRIBUTION SLVS097A – DECEMBER 1994 – REVISED AUGUST 1995 PARAMETER MEASUREMENT INFORMATION 3 IO – Output Current – A 2.5 TPS2013 2 TPS2012 1.5 TPS2011 1 0.5 TPS2010 0 –1 0 1 2 3 4 5 6 7 8 9 10 t – Time – ms Figure 13. Turned-On (Enabled) Into Short Circuit, VI(IN) = 5.5 V VI IN OUT IN VI VI(EN) 50% 50% OUT TPS201x ENABLE VO GND OUT OUT tPLH tPHL VI 90% 90% EN CL GND 10% VO 10% tr TEST CIRCUIT tf VOLTAGE WAVEFORMS Figure 14. Test Circuit and Voltage Waveforms 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 GND TPS2010, TPS2011, TPS2012, TPS2013 POWER-DISTRIBUTION SLVS097A – DECEMBER 1994 – REVISED AUGUST 1995 TYPICAL CHARACTERISTICS TURN-ON DELAY TIME vs INPUT VOLTAGE TURN-OFF DELAY TIME vs INPUT VOLTAGE 4.9 25 TJ = 25°C RL = 50 Ω CL = 1 µF TJ = 25°C RL = 50 Ω CL = 1 µF Turn-Off Delay Time – ms Turn-On Delay Time – ms 4.7 4.5 4.3 4.1 3.9 20 15 10 3.7 3.5 2.5 3 3.5 4.5 4 5 5 2.5 5.5 3 3.5 VI – Input Voltage – V Figure 15 4.5 5 5.5 Figure 16 FALL TIME vs OUTPUT CURRENT RISE TIME vs OUTPUT CURRENT 4 5 TJ = 25°C CL = 1 µF TJ = 25°C CL = 1 µF 3.8 4.5 3.6 tf – Fall Time – ms tr – Rise Time – ms 4 VI – Input Voltage – V 4 3.5 VI = 5.5 V VI = 2.7 V 3 3.4 3.2 VI = 5.5 V 3 2.8 VI = 2.7 V 2.6 2.4 2.5 2.2 2 2 0 0.3 1.2 0.6 0.9 IO – Output Current – A 1.5 0 Figure 17 0.3 1.2 0.6 0.9 IO – Output Current – A 1.5 Figure 18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 TPS2010, TPS2011, TPS2012, TPS2013 POWER-DISTRIBUTION SLVS097A – DECEMBER 1994 – REVISED AUGUST 1995 TYPICAL CHARACTERISTICS SUPPLY CURRENT (OUTPUT DISABLED) vs JUNCTION TEMPERATURE SUPPLY CURRENT (OUTPUT ENABLED) vs JUNCTION TEMPERATURE 10 IO = 0 A 70 I DD – Supply Current (Output Disabled) – µ A I DD – Supply Current (Output Enabled) – µ A 80 VI = 5.5 V 60 50 40 VI = 2.7 V 30 20 – 50 1 0.1 VI = 5.5 V 0.01 VI = 2.7 V 0.001 – 25 0 25 50 75 100 TJ – Junction Temperature – °C – 50 125 – 25 Figure 19 75 100 125 10 IO = 0 A I DD – Supply Current (Output Disabled) – µ A I DD – Supply Current (Output Enabled) – µ A 50 SUPPLY CURRENT (OUTPUT DISABLED) vs INPUT VOLTAGE 80 70 60 TJ = 125°C 50 TJ = 25°C 40 3 3.5 4 4.5 VI – Input Voltage – V 5 5.5 TJ = 125°C 1 0.1 0.01 TJ = 25°C 0.001 2.5 Figure 21 12 25 Figure 20 SUPPLY CURRENT (OUTPUT ENABLED) vs INPUT VOLTAGE 30 2.5 0 TJ – Junction Temperature – °C 3 3.5 4 4.5 VI – Input Voltage – V Figure 22 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 5.5 TPS2010, TPS2011, TPS2012, TPS2013 POWER-DISTRIBUTION SLVS097A – DECEMBER 1994 – REVISED AUGUST 1995 TYPICAL CHARACTERISTICS ON-STATE RESISTANCE vs JUNCTION TEMPERATURE ON-STATE RESISTANCE vs INPUT VOLTAGE 190 140 170 130 ron – On-State Resistance – mΩ ron – On-State Resistance – mΩ TJ = 25°C 150 VI = 2.7 V 130 110 ÁÁ ÁÁ VI = 3 V VI = 4.5 V – 25 0 100 25 90 80 70 VI = 5.5 V 50 – 50 110 ÁÁ ÁÁ 90 70 120 50 75 100 60 2.5 125 TJ – Junction Temperature – °C 3 Figure 23 4 4.5 5 5.5 Figure 24 SHORT-CIRCUIT CURRENT vs INPUT VOLTAGE INPUT VOLTAGE TO OUTPUT VOLTAGE vs INPUT VOLTAGE 3 0.25 TPS2013 2.5 0.2 Short-Circuit Current – A VI to VO – Input Voltage to Output Voltage – V 3.5 VI – Input Voltage – V 0.15 IO = 1.5 A 0.1 IO = 1 A 2 TPS2012 1.5 TPS2011 1 IO = 600 mA 0.05 0.5 IO = 200 mA 0 2.5 3 3.5 4 4.5 VI – Input Voltage – V TPS2010 5 5.5 0 2.5 3 Figure 25 3.5 4 4.5 VI – Input Voltage – V 5 5.5 Figure 26 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13 TPS2010, TPS2011, TPS2012, TPS2013 POWER-DISTRIBUTION SLVS097A – DECEMBER 1994 – REVISED AUGUST 1995 TYPICAL CHARACTERISTICS THRESHOLD TRIP CURRENT vs INPUT VOLTAGE SHORT-CIRCUIT CURRENT vs JUNCTION TEMPERATURE 5.5 3 VI(IN) = 5.5 V 5 TPS2013 TPS2013 4.5 Short-Circuit Current – A Threshold Trip Current – A 2.5 TPS2012 4 3.5 TPS2011 3 2.5 TPS2012 2 1.5 TPS2011 1 TPS2010 1.5 2.5 TPS2010 0.5 2 3 3.5 4.5 4 5 0 – 50 5.5 – 25 VI – Input Voltage – V 0 25 50 75 100 125 TJ – Junction Temperature – °C Figure 27 Figure 28 APPLICATION INFORMATION TPS2010D 2 Power Supply 2.7 V – 5.5 V 3 + 1 µF IN OUT IN OUT 0.1 µF OUT OUT External Load 5 6 7 8 0.1 µF 4 Load Enable EN GND 1 Figure 29. Typical Application power supply considerations The TPS201x family has multiple inputs and outputs, which must be connected in parallel to minimize voltage drop and prevent unnecessary power dissipation. A 0.047-µF to 0.1-µF ceramic bypass capacitor between IN and GND, close to the device, is recommended. A high-value electrolytic capacitor is also desirable when the output load is heavy or has large paralleled capacitors. Bypassing the output with a 0.1-µF ceramic capacitor improves the immunity of the device to electrostatic discharge (ESD). 14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TPS2010, TPS2011, TPS2012, TPS2013 POWER-DISTRIBUTION SLVS097A – DECEMBER 1994 – REVISED AUGUST 1995 APPLICATION INFORMATION overcurrent A sense FET is employed to check for overcurrent conditions. Unlike sense resistors and polyfuses, sense FETs do not increase series resistance to the current path. When an overcurrent condition is detected, the device maintains a constant output current and reduces the output voltage accordingly. Shutdown only occurs if the fault is present long enough to activate thermal limiting. Three possible overload conditions can occur. In the first condition, the output has been shorted before the device is enabled or before VI(IN) has been applied (see Figure 30). The TPS201x senses the short and immediately switches into a constant-current output. Under the second condition, the short occurs while the device is enabled. At the instant the short occurs, very high currents flow for a short time before the current-limit circuit can react (see Figures 5, 6, 7, and 8). After the current-limit circuit has tripped, the device limits normally. Under the third condition, the load has been gradually increased beyond the recommended operating current. The current is permitted to rise until the current-limit threshold is reached (see Figures 9, 10, 11, and 12). The TPS201x family is capable of delivering currents up to the current-limit threshold without damage. Once the threshold has been reached, the device switches into its constant-current mode. 3 IO– Output Current – A 2.5 TPS2013 2 TPS2012 1.5 TPS2011 1 0.5 TPS2010 0 0 1 2 3 4 5 6 7 8 9 10 t – Time – ms Figure 30. Turned-On (Enabled) Into Short Circuit, VI(IN) = 5.5 V POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 15 TPS2010, TPS2011, TPS2012, TPS2013 POWER-DISTRIBUTION SLVS097A – DECEMBER 1994 – REVISED AUGUST 1995 APPLICATION INFORMATION power dissipation and junction temperature The low on resistance of the N-channel MOSFET allows small surface-mount packages, such as SOIC or TSSOP to pass large currents. The thermal resistances of these packages are high compared to that of power packages; it is good design practice to check power dissipation and junction temperature. The first step is to find ron at the input voltage and operating temperature. As an initial estimate, use the highest operating ambient temperature of interest and read ron from Figure 23. Next calculate the power dissipation using: P D + ron I2 Finally, calculate the junction temperature: T J + PD R qJA ) TA Where: TA = Ambient temperature RθJA = Thermal resistance SOIC = 172°C/W, TSSOP = 179°C/W Compare the calculated junction temperature with the initial estimate. If they do not agree within a few degrees, repeat the calculation using the calculated value as the new estimate. Two or three iterations are generally sufficient to get a reasonable answer. thermal protection Thermal protection is provided to prevent damage to the IC when heavy-overload or short-circuit faults are present for extended periods of time. The faults force the TPS201x into its constant current mode, which causes the voltage across the high-side switch to increase; under short-circuit conditions, the voltage across the switch is equal to the input voltage. The increased dissipation causes the junction temperature to rise to dangerously high levels. The protection circuit senses the junction temperature of the switch and shuts it off. The switch remains off until the junction has dropped approximately 20°C. The switch continues to cycle in this manner until the load fault or input power is removed. ESD protection All TPS201x terminals incorporate ESD-protection circuitry designed to withstand a 6-kV human-body-model discharge as defined in MIL-STD-883C. Additionally, the output is protected from discharges up to 12 kV. 16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PACKAGE OPTION ADDENDUM www.ti.com 14-Oct-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) TPS2010D NRND SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 2010 TPS2010DR NRND SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 2010 TPS2010DRG4 NRND SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 2010 TPS2011D NRND SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 2011 TPS2011DR NRND SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 2011 TPS2012D NRND SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 2012 TPS2012DR NRND SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 2012 TPS2013D NRND SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 2013 TPS2013DR NRND SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 2013 TPS2013DRG4 NRND SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 2013 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of