TPS2070DAP

TPS2070 TPS2071 www.ti.com SLVS287B – SEPTEMBER 2000 – REVISED SEPTEMBER 2007 FOUR-PORT USB HUB POWER CONTROLLERS FEATURES 1 • Complete USB Hub Power Solution • Meets USB Specifications 1.1 and 2.0 • Independent Thermal and Short-Circuit Protection • 3.3-V Regulator for USB Hub Controller • Overcurrent Logic Outputs • 4.5-V to 5.5-V Operating Range • CMOS- and TTL-Compatible Enable Inputs • 185 μA Bus-Power Supply Current • Available in 32-Pin HTSSOP PowerPAD™ Package • –40°C to 85°C Ambient Temperature Range 2 DESCRIPTION The TPS2070 and TPS2071 provide a complete USB hub power solution by incorporating four major functions: current-limited power switches for four ports, a 3.3-V 100-mA regulator, a 5-V regulator controller for self-power, and a DP0 line control to signal attach/detach of the hub. These devices are designed to meet bus-powered and self-powered hub requirements. These devices are also designed for hybrid hub implementations and allow for automatic switching from self-powered mode to bus-powered mode if loss of self-power is experienced (can be disabled by applying a logic high to BP_DIS). Each port has a current-limited 107-mΩ N-channel MOSFET high-side power switch for 500-mA self-powered operation. Each port also has a current-limited 560-mΩ N-channel MOSFET high-side power switch for 100-mA bus-powered operation. All the N-channel MOSFETs are designed without parasitic diodes, preventing current backflow into the inputs. For applications not requiring a 5-V regulator controller, use the TPS2074 or TPS2075 device. DAP Package (Top View) NC EN1 AGND NC PG SP SP NC VEXT GATE 3.3V_OUT (1) BPMODE DP0_RST EN_REG EN2 DGND 1 32 2 31 12 21 13 20 14 19 15 18 BP OUT1 OUT2 OUT3 OUT4 OC4 OC3 OC2 OC1 EN4 EN3 CP_M CP_P 16 17 VCP 3 30 4 29 5 28 6 27 7 26 8 25 9 24 10 23 11 22 NC - No internal connection (1) PG_DLY BP_DIS P0073-01 Pin 12 is active-low (BPMODE) for TSS2070 and active-high (BPMODE) for TPS2071. (1) 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2000–2007, Texas Instruments Incorporated TPS2070 TPS2071 www.ti.com SLVS287B – SEPTEMBER 2000 – REVISED SEPTEMBER 2007 Simplified Hybrid-Hub Diagram(1) OUT1 SP GATE Power Supply D+ D– 5V GND OUT2 VEXT DP0_RST TPS2070 D+ D– 5V GND OUT3 OUT4 BP 3.3 V_OUT BPMODE 1.5 kW Downstream Ports VCC EN OC Upstream Port D+ D– 5V GND DP0 DM0 D+ D– 5V GND DP1 DM1 DP2 DM2 DP3 DM3 DP4 DM4 Hub Controller D+ D– 5V GND B0269-01 (1) See Figure 38 for complete implementation. SELECTION GUIDE TA USB HUB POWER CONTROLLERS Four-port with internal LDO controller PACKAGED DEVICES PIN COUNT 32 –40°C to 85°C Four-port without internal LDO controller (1) 2 24 BP MODE HTSSOP (DAP) (1) SSOP (DB) Active low TPS2070DAP — Active high TPS2071DAP — Active low — TPS2074DB Active high — TPS2075DB The DAP package is available taped and reeled. Add an R suffix to the device type (e.g., TPS2070DAPR). Submit Documentation Feedback Copyright © 2000–2007, Texas Instruments Incorporated Product Folder Link(s): TPS2070 TPS2071 TPS2070 TPS2071 www.ti.com SLVS287B – SEPTEMBER 2000 – REVISED SEPTEMBER 2007 FUNCTIONAL BLOCK DIAGRAM 3.3 V/100 mA LDO 3.3V_OUT PG PG_DLY BP S1 OUT1 SP S2 SP S3 OUT2 S4 S5 OUT3 S6 S7 OUT4 S8 DPO_RST BP_DIS AGND DGND EN1 Control Logic OC1 EN2 OC2 EN3 OC3 EN4 GATE OC4 BPMODE (TPS2070) BPMODE (TPS2071) LDO Controller VEXT VCP CP_P CP_M EN_REG B0270-01 Copyright © 2000–2007, Texas Instruments Incorporated Product Folder Link(s): TPS2070 TPS2071 Submit Documentation Feedback 3 TPS2070 TPS2071 www.ti.com SLVS287B – SEPTEMBER 2000 – REVISED SEPTEMBER 2007 TERMINAL FUNCTIONS TERMINAL NAME NO. I/O 3.3V_OUT 11 AGND 3 BP 30 I Bus power voltage input, connect to VBUS BP_DIS 31 I Active-high logic input, disables autoswitch to bus power when self-power is disconnected. Connect to BP or GND BPMODE 12 O CP_M 19 Charge-pump-capacitor connection from CP_P. Recommend 0.01-μF between CP_P and CP_M. CP_P 18 Charge-pump-capacitor connection from CP_M. Recommend 0.01-μF between CP_P and CP_M. DGND 16 Digital ground DP0_RST 13 O Connects to DP signal from upstream hub/host through an external 1.5-kΩ resistor EN1 2 I Active-low enable for OUT1 EN2 15 I Active-low enable for OUT2 EN3 20 I Active-low enable for OUT3 EN4 21 I Active-low enable for OUT4 EN_REG 14 I Active-high enable, enables external voltage regulator. Connect to BP or GND 10 O Output gate drive for an external N-channel MOSFET (1) GATE NC O DESCRIPTION 3.3-V internal voltage regulator output Analog ground 1, 4, 8 A logic signal that indicates if the outputs source from the bus-powered supply. BPMODE (TPS2070) or BPMODE (TPS2071) can be used to signal hub controller. No internal connection OC1 22 O Logic output, overcurrent response for OUT1 OC2 23 O Logic output, overcurrent response for OUT2 OC3 24 O Logic output, overcurrent response for OUT3 OC4 25 O Logic output, overcurrent response for OUT4 OUT1 29 O Power switch output for downstream ports OUT2 28 O Power switch output for downstream ports OUT3 27 O Power switch output for downstream ports OUT4 26 O Power switch output for downstream ports PG 5 O Logic output, power good PG_DLY (2) 32 SP 6, 7 VCP 17 VEXT 9 (1) (2) Adjusts the PG time delay with a capacitor to ground. Adjust the pulse duration to fit the application. I Self-power voltage input, connects to local power supply Charge-pump output, source for an external voltage-regulator driver. Recommend 0.1-μF capacitor to DGND. I Input voltage for the external voltage regulator Pin 12 is active-low for TPS2070 and active-high for TPS2071. Use the following formula to calculate the capacitance needed: C = (desired pulse duration × 3 × 10–6)/1.22 DETAILED DESCRIPTION BP The bus-powered supply input (BP) serves as the source for the internal 3.3-V LDO and for all logic functions in the device. In bus-powered mode, BP also serves as the source for all the outputs (OUTx). If BP is below the undervoltage threshold, all power switches turn off and the LDO is disabled. BP must be connected to a voltage source for the device to operate. SP The self-powered supply input (SP) serves as the source for all the outputs (OUTx) in self-powered mode. The enable logic for the SP switches requires that BP be connected to a voltage source. OUT1, OUT2, OUT2, OUT4 OUTx are the outputs of the integrated power switches. 4 Submit Documentation Feedback Copyright © 2000–2007, Texas Instruments Incorporated Product Folder Link(s): TPS2070 TPS2071 TPS2070 TPS2071 www.ti.com SLVS287B – SEPTEMBER 2000 – REVISED SEPTEMBER 2007 3.3V_OUT The internal 3.3-V LDO output can be used to supply up to 100 mA of current to low-power functions, such as hub controllers. VEXT VEXT is used to generate a 5-V source for the SP input by using the internal LDO controller and an external N-channel MOSFET. This pin connects to a 6-V to 9-V power supply and to the drain of the MOSFET if the external LDO is needed. GATE GATE is the output of the 5-V LDO controller and connects to the gate of the external MOSFET. EN_REG The active-high input, EN_REG, is used to enable the 5-V regulator controller. EN_REG is compatible with TTL and CMOS logic levels. DP0_RST DP0_RST functions as a hub reset when a 1.5-kΩ resistor is connected between DP0_RST and the upstream DP0 data line in a hub system. To provide a clean attach signal on the DP0 data line, the DP0_RST output goes low momentarily (because of the upstream pulldown resistor) to discharge any parasitic charge on the cable, then goes to the high-impedance state and finally outputs a high signal. The low and Hi-Z pulse durations are adjustable using a capacitor between PG_DLY and ground, and are approximately 50% of the power-good time delay. Detachment is signaled by a Hi-Z on DP0_RST. Both DP0_RST and PG transition high at the same time. Power Good (PG) The power-good (PG) function serves as a reset for a USB hub controller. PG is asserted low when the output voltage on the internal voltage regulator is below a fixed threshold. A time delay to ensure a stable output voltage before PG goes high is adjustable using a small-value ceramic capacitor from PG_DLY to ground. PG_DLY PG_DLY connects to an external capacitor to adjust the time delay for PG and DP0_RST. For USB applications, a 0.1-μF capacitor is recommended; however, see the USB hub controller data sheet to determine the required pulse-duration criteria. BP_DIS BP_DIS is used to enable or disable the autoswitching function between bus-powered mode and self-powered mode. When BP_DIS is connected low and the voltage on SP is greater than the undervoltage-lockout (UVLO) threshold, the device switches to self-powered operation automatically; if the SP voltage falls lower than the UVLO threshold, the device switches to bus-powered operation. When BP_DIS is connected high, the autoswitching function is disabled and the device does not autoswitch to bus-powered operation if the SP voltage is below the UVLO threshold. BPMODE or BPMODE BPMODE (TPS2070) or BPMODE (TPS2071) is an output that signals when the device is in bus-powered mode. The logic state is set according to the voltages on BP, SP, and BP_DIS. For the TPS2070, BPMODE outputs a low signal to indicate bus-powered mode or a high signal to indicate self-powered mode. For the TPS2071, BPMODE outputs a high signal to indicate bus-powered mode or a low signal to indicate self-powered mode. This output can be used to inform a USB hub controller to configure for bus-powered mode or self-powered mode. Copyright © 2000–2007, Texas Instruments Incorporated Product Folder Link(s): TPS2070 TPS2071 Submit Documentation Feedback 5 TPS2070 TPS2071 www.ti.com SLVS287B – SEPTEMBER 2000 – REVISED SEPTEMBER 2007 OC1, OC2, OC3, OC4 OCx is an output signal that is asserted (active low) when an overcurrent or overtemperature condition is encountered for the corresponding channel. OCx remains asserted until the overcurrent or overtemperature condition is removed. EN1, EN2, EN3, EN4 The active-low logic input ENx enables or disables the power switches in the device. The enable input is compatible with both TTL and CMOS logic levels. The switches do not turn on until 3.3V_OUT is above the PG threshold. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) Input voltage range Output voltage range (2) VALUE UNIT VI(BP), VI(SP), VI(ENx), VI(EN_REG), VI(BP_DIS) –0.3 to 6 V VI(VEXT) –0.3 to 10 V VO(OUTx), VO(3.3V_OUT), VO(PG_DLY), VO(OCx), VO(BPMODE), VO(DP0_RST), VO(PG) –0.3 to 6 V –0.3 to 15 V VO(GATE), VO(CP_M), VO(CP_P), VO(VCP) Continuous output current Maximum output current IO(OUTx) Internally limited IO(3.3V_OUT) Internally limited IO(VCP) ±30 mA IO(BPMODE) or IO(BPMODE), IO(DP0_RST), IO(PG), IO(OCx) ±10 mA IO(GATE), sourcing 700 μA –2.2 mA IO(GATE), sinking Continuous total power dissipation See Dissipation Rating Table Operating virtual junction temperature range, TJ –40 to 125 °C Storage temperature range, Tstg –65 to 150 °C 260 °C Lead temperature (soldering), 1,6 mm (1/16 inch) from case for 10 seconds (1) (2) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages are with respect to GND. DISSIPATION RATINGS (1) 6 PACKAGE TA ≤ 25°C POWER RATING DERATING FACTOR ABOVE TA = 25°C 32-DAP 1162.8 mW 11.6 mW/°C 639.5 mW 465.1 mW 32-DAP (1) 4255.3 mW 42.5 mW/°C 2340.4 mW 1702.1 mW TA = 70°C POWER RATING TA = 85°C POWER RATING Using thermal pad as heatsink. Submit Documentation Feedback Copyright © 2000–2007, Texas Instruments Incorporated Product Folder Link(s): TPS2070 TPS2071 TPS2070 TPS2071 www.ti.com SLVS287B – SEPTEMBER 2000 – REVISED SEPTEMBER 2007 RECOMMENDED OPERATING CONDITIONS MIN MAX VI(BP) 4.5 5.5 VI(SP) 0 5.5 VI(VEXT) 0 9 0 5.5 VI(ENx) 0 5.5 VI(EN_REG) 0 5.5 VI(BP_DIS) IO TJ Input voltage Continuous output current BP to OUTx (per switch) 100 SP to OUTx (per switch) 500 BP to 3.3V_OUT 100 Operating virtual junction temperature Copyright © 2000–2007, Texas Instruments Incorporated Product Folder Link(s): TPS2070 TPS2071 –40 125 Submit Documentation Feedback UNIT V mA °C 7 TPS2070 TPS2071 www.ti.com SLVS287B – SEPTEMBER 2000 – REVISED SEPTEMBER 2007 ELECTRICAL CHARACTERISTICS over recommended operating junction temperature range, 4.5 V ≤ VI(BP) ≤ 5.5 V, 4.85 V ≤ VI(SP) ≤ 5.5 V, 6 V ≤ VI(VEXT) ≤ 9 V, ENx = 0 V, EN_REG = 0 V, BP_DIS = 0 V (unless otherwise noted) TEST CONDITIONS (1) PARAMETER MIN TYP MAX UNIT INPUT CURRENT Input current at BP, switches disabled No load on OUTx and 3.3V_OUT, ENx = VI(BP) II(BP) Input current at BP, switches enabled Input current at SP, switches disabled No load on OUTx and 3.3V_OUT, ENx = 0 V No load on OUTx and 3.3V_OUT, ENx = VI(SP) II(SP) Input current at SP, switches enabled II(VEXT) No load on OUTx and 3.3V_OUT, ENx = 0 V Input current at VEXT, LDO controller disabled VI(EN_REG) = 0 V or Hi-Z, VI(BP) = 5 V, VI(SP) = Hi-Z Input current, at VEXT, LDO controller enabled VI(EN_REG) = 5 V, VI(BP) = 5 V, VI(SP) = Hi-Z VI(SP) = Hi-Z 185 240 VI(SP) = 0 V 185 240 VI(SP) = 5 V 175 210 VI(SP) = Hi-Z 185 240 VI(SP) = 0 V 185 240 VI(SP) = 5 V 175 210 VI(SP) = Hi-Z 90 115 VI(SP) = 0 V 90 115 VI(SP) = 5 V 115 140 VI(SP) = Hi-Z 90 115 VI(SP) = 0 V 90 115 VI(SP) = 5 V 115 140 200 360 10 μA μA μA μA μA mA POWER SWITCHES rDS(on) Ilkg(OUTx) IOS (1) 8 Static drain-source on-state resistance SP to OUTx VI(SP) = VI(BP) = 5 V, IOx = 0.5 A BP to OUTx VI(BP) = 4.5 V, VI(SP) = open, IOx = 0.1 A Leakage current at OUTx Short-circui outputt current (1) TA = 25°C 107 TA = 70°C 125 TA = 25°C 560 160 TA = 70°C 630 900 ENx = VI(BP) = 5.5 V, VI(SP) = Hi-Z, OUTx connected to ground, VI(VIN) = Hi-Z, no load on 3.3V_OUT TJ = 25°C 0.5 10 ENx = VI(BP) = VI(SP) = 5.5 V, OUTx connected to ground, VI(EXT) = Hi-Z, no load on 3.3V_OUT TJ = 25°C 0.5 10 ENx = VI(BP) = Hi-Z or 0 V, VI(VEXT) = VI(SP) = VI(OUTx) = 5.5 V, no load on 3.3V_OUT TJ = 25°C 0.5 10 ENx = VI(BP) = VI(SP) = Hi-Z or 0 V, VI(VEXT) = VI(OUTx) = 5.5 V, no load on 3.3V_OUT TJ = 25°C 0.5 10 ENx = VI(BP) = VI(SP) = VI(VEXT) = Hi-Z or 0 V, VI(OUTx) = 5.5 V, no load on 3.3V_OUT TJ = 25°C 0.5 10 VI(BP) = VI(SP) = 5 V, OUTx connected to GND, device enabled into short circuit 0.6 0.9 1.2 VI(BP) = 5 V, VI(SP) = open, OUTx connected to GND, device enabled into short circuit 0.12 0.2 0.3 mΩ μA A Pulse-testing techniques maintain junction temperature close to ambient temperature; thermal effects must be taken into account separately. Submit Documentation Feedback Copyright © 2000–2007, Texas Instruments Incorporated Product Folder Link(s): TPS2070 TPS2071 TPS2070 TPS2071 www.ti.com SLVS287B – SEPTEMBER 2000 – REVISED SEPTEMBER 2007 ELECTRICAL CHARACTERISTICS over recommended operating junction temperature range, 4.5 V ≤ VI(BP) ≤ 5.5 V, 4.85 V ≤ VI(SP) ≤ 5.5 V, 6 V ≤ VI(VEXT) ≤ 9 V, ENx = 0 V, EN_REG = 0 V, BP_DIS = 0 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT INPUT SIGNALS (ENx, EN_REG, BP_DIS) VIH High-level input voltage VIL Low-level input voltage II Input current 2 0.8 Pullup Pulldown ENx (active-low) VI(ENx) = 0 V 5 EN_REG (active-high) VI(EN_REG) = 5 V 5 BP_DIS (active-high) VI(BP_DIS) = 5 V 5 V μA ELECTRICAL CHARACTERISTICS over recommended operating junction temperature range, 4.5 V ≤ VI(BP) ≤ 5.5 V, 4.85 V ≤ VI(SP) ≤ 5.5 V, 6 V ≤ VI(VEXT) ≤ 9 V, ENx = 0 V, EN_REG = 0 V, BP_DIS = 0 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT OUTPUT SIGNALS (BPMODE or BPMODE, OCx, DPO_RST) 4.25 V ≤ VI(BP) ≤ 5.5 V, 4.5 V ≤ VI(SP) ≤ 5.5 V 2.4 BPMODE 4.25 V ≤ VI(BP) ≤ 5.5 V, VI(SP) < 4 V 2.4 OCx 4.25 V ≤ VI(BP) ≤ 5.5 V, VI(ENx) = 3.3 V or Hi-Z DPO_RST 4.25 V ≤ VI(BP) ≤ 5.5 V, VI(PG_DLY) = 3.3 V BPMODE 4.25 V ≤ VI(BP) ≤ 5.5 V, VI(SP) < 4 V BPMODE High-level output voltage VOH Low-level output voltage VOL BPMODE 4.25 V ≤ VI(BP) ≤ 5.5 V, 4.5 V ≤ VI(SP) ≤ 5.5 V OCx 4.25 V ≤ VI(BP) ≤ 5.5 V, OUTx = 0 V VI(BP) Minimum input voltage at BP for low-level output IIkg Hi-Z leakage current at DP0_RST td Overcurrent response delay time IO = 2 mA V 2.4 2.4 0.4 IO = 3.2 mA 0.4 IO(OC) = 3.2 mA 0.4 IO = 300 μA, VO(BPMODE) ≤ 0.4 V 1.5 IO = 300 μA, VO(BPMODE) ≤ 0.4 V, VI(SP) = 5 V 1.5 0 V ≤ VI(DP0_RST) ≤ 3.3 V, VI(SP) = 0 V, VI(BP) = 5.5 V, VI(PG_DLY) = 0.9 V (1) V –5 5 1 10 μA ms UNDERVOLTAGE LOCKOUT (SP, BP, VEXT) SP Start threshold BP 4.5 VI(SP) = Hi-Z 4.25 VEXT Stop threshold Vhys (1) Hysteresis voltage (1) V 3 SP 4 BP 3.75 VEXT 2.5 SP 300 BP 300 VEXT 150 V mV Specified by design, not tested in production. Copyright © 2000–2007, Texas Instruments Incorporated Product Folder Link(s): TPS2070 TPS2071 Submit Documentation Feedback 9 TPS2070 TPS2071 www.ti.com SLVS287B – SEPTEMBER 2000 – REVISED SEPTEMBER 2007 ELECTRICAL CHARACTERISTICS over recommended operating junction temperature range, 4.5 V ≤ VI(BP) ≤ 5.5 V, 4.85 V ≤ VI(SP) ≤ 5.5 V, 6 V ≤ VI(VEXT) ≤ 9 V, ENx = 0 V, EN_REG = 0 V, BP_DIS = 0 V, CL(3.3V_OUT) = 10 μF (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX 3.2 3.3 3.4 UNIT INTERNAL VOLTAGE REGULATOR VO IOS Output voltage, dc VI(BP) = 4.25 V to 5.5 V, IO = 5 mA to 100 mA Dropout voltage IO = 100 mA Line regulation VI(BP) = 4.25 V to 5.25 V, IO = 5 mA Load regulation VI(BP) = 4.25 V, IO = 5 mA to 100 mA Short-circuit current limit PSRR (1) 0.6 0.1 Pulldown current through transistor at 3.3V_OUTPUT (2) VI(3.3V_OUT) = 3.3 V Power-supply ripple rejection (2) f = 1 kHz, CL(3.3V_OUT) = 4.7 μF, ESR = 0.25 Ω, IO = 5 mA, VI(BP)PP = 100 mV 0.12 0.2 40 High-level output voltage at PG 4.25 V ≤ VI(BP) ≤ 5.25 V, IO = 2 mA VOL Low-level output voltage at PG 4.25 V ≤ VI(BP) ≤ 5.25 V, IO = 3.2 mA Vref Reference voltage at PG_DLY 2.94 100 2.4 (2) (3) V mV V 0.4 Charge current at PG_DLY (1) 3 50 (2) (3) A dB 2.88 VOH %/V mA 5 Hysteresis voltage at PG (2) Delay time at PG 0.3 10 VI(3.3V_OUT) = 1 V Low-level trip threshold voltage at PG td V 0.6% VI(BP) = 4.25 V, 3.3V_OUT connected to GND Vhys V CL(PG_DLY) = 0.47 μF V 1.22 V 3 μA 190 ms Pulse-testing techniques maintain junction temperature close to ambient temperature; thermal effects must be taken into account separately. Specified by design, not tested in production. The PG delay time (td) is calculated using the PG_DLY reference voltage and charge current: td = CL(PG _ DLY ) ´ Vref Ch arg e Current ELECTRICAL CHARACTERISTICS over recommended operating junction temperature range, 4.5 V ≤ VI(BP) ≤ 5.5 V, 4.85 V ≤ VI(SP) ≤ 5.5 V, 6 V ≤ VI(VEXT) ≤ 9 V, ENx = 0 V, EN_REG = 3.3 V, BP_DIS = 0 V, CL(SP) = 220 μF (unless otherwise noted)) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VOLTAGE REGULATOR CONTROLLER VO(CP) Output voltage, charge pump VI(VEXT) = 6 V, IO(VCP) = 5 mA, C(CP_P) = 10 nF, C(VCP) = 100 nF fosc Oscillator frequency (1) 6 V ≤ VI(VEXT) ≤ 9 V, IO(VCP) = 5 mA, VO(VCP) = 10 V Gate drive current Open-loop gain (1) 10 10 V 850 kHz Sourcing VI(VCP) = 9 V, VO(GATE) = 7.5 V, VI(SP) = 4.5 V 500 μA Sinking VI(VCP) = 9 V, VO(GATE) = 5.5 V, VI(SP) = 5.5 V 1.5 mA (1) VI(VEXT) = 6 V, 0.5 V ≤ VO(GATE) ≤ 9 V Reference voltage at VI(SP), using external regulator VI(VEXT) = 6 V to 9 V, IRLZ24N FET Gate clamp voltage Gate to SP 80 4.9 5.1 10 dB 5.25 V V Specified by design, not tested in production. Submit Documentation Feedback Copyright © 2000–2007, Texas Instruments Incorporated Product Folder Link(s): TPS2070 TPS2071 TPS2070 TPS2071 www.ti.com SLVS287B – SEPTEMBER 2000 – REVISED SEPTEMBER 2007 POWER SWITCH TIMING REQUIREMENTS TEST CONDITIONS (1) PARAMETER ton Turnon time (2) toff Turnoff time (2) tr Rise time, output (2) tf Fall time, output (2) (1) (2) MIN TYP MAX BP to OUTx switch VI(BP) = 5 V, VI(SP) = open, TA = 25°C, CL = 100 μF, RL = 50 Ω 4.5 SP to OUTx switch VI(SP) = VI(BP) = 5 V, TA = 25°C, CL = 100 μF, RL = 10 Ω 4.5 BP to OUTx switch VI(BP) = 5 V, VI(SP) = open, TA = 25°C, CL = 100 μF, RL = 50 Ω 15 SP to OUTx switch VI(SP) = VI(BP) = 5 V, TA = 25°C, CL = 100 μF, RL = 10 Ω 10 BP to OUTx switch VI(BP) = 5 V, VI(SP) = open, TA = 25°C, CL = 100 μF, RL = 50 Ω 4 SP to OUTx switch VI(SP) = VI(BP) = 5 V, TA = 25°C, CL = 100 μF, RL = 10 Ω 3 BP to OUTx switch VI(BP) = 5 V, VI(SP) = open, TA = 25°C, CL = 100 μF, RL = 50 Ω 10 SP to OUTx switch VI(SP) = VI(BP) = 5 V, TA = 25°C, CL = 100 μF, RL = 10 Ω 3 UNIT ms ms ms ms Pulse-testing techniques maintain junction temperature close to ambient temperature; thermal effects must be taken into account separately. Specified by design, not tested in production. THERMAL SHUTDOWN over operating free-air temperature range (unless otherwise noted) PARAMETER TJ Thermal shutdown Hysteresis MIN TYP MAX First 140 Second 150 First 15 Second 25 Copyright © 2000–2007, Texas Instruments Incorporated Product Folder Link(s): TPS2070 TPS2071 Submit Documentation Feedback UNIT °C °C 11 TPS2070 TPS2071 www.ti.com SLVS287B – SEPTEMBER 2000 – REVISED SEPTEMBER 2007 PARAMETER MEASUREMENT INFORMATION Current Meter VI(ENx) DUT IN 50% ton tpd(off) tpd(on) toff OUT + 50% 90% VO(OUTx) 90% 10% 10% tr tf Test Circuit 90% VO(OUTx) S0298-01 90% 10% 10% Timing T0271-01 Figure 1. Current Limit Response Figure 2. Timing and Internal Voltage Regulator Transition Waveforms VI(BP) = 5 V TA = 25°C CL = 10 mF RL = 50 W VI(EN) (2 V/div) VI(EN) (2 V/div) VO(OUT) (2 V/div) VI(BP) = 5 V TA = 25°C CL = 10 mF RL = 50 W VO(OUT) (2 V/div) 0 2 4 6 8 10 12 14 16 18 20 0 2 4 6 8 10 12 14 16 18 t - Time - ms t - Time - ms G002 G001 Figure 3. Turnon Delay and Rise Time (BP Switch) 12 Submit Documentation Feedback 20 Figure 4. Turnoff Delay and Fall Time (BP Switch) Copyright © 2000–2007, Texas Instruments Incorporated Product Folder Link(s): TPS2070 TPS2071 TPS2070 TPS2071 www.ti.com SLVS287B – SEPTEMBER 2000 – REVISED SEPTEMBER 2007 PARAMETER MEASUREMENT INFORMATION (continued) VI(BP) = VI(SP) = 5 V TA = 25°C CL = 10 mF RL = 10 W VI(EN) (2 V/div) VI(EN) (2 V/div) VO(OUT) (2 V/div) VI(BP) = VI(SP) = 5 V TA = 25°C CL = 10 mF RL = 10 W VO(OUT) (2 V/div) 0 2 4 6 8 10 12 14 16 18 20 0 2 4 6 8 t - Time - ms 10 12 14 16 18 20 t - Time - ms G003 G004 Figure 5. Turnon Delay and Rise Time (SP Switch) Figure 6. Turnoff Delay and Fall Time (SP Switch) VI(BP) (2 V/div) TA = 25°C CL = 4.7 mF RL = 33 W VI(BP) (2 V/div) TA = 25°C CL = 4.7 mF RL = 33 W VO(3.3V_OUT) (1 V/div) VO(3.3V_OUT) (1 V/div) 0 4 8 12 16 20 24 28 32 36 40 0 20 t - Time - ms 40 60 80 100 120 140 160 180 200 t - Time - ms G005 Figure 7. Turnon Delay and Rise Time (3.3V_OUT) G006 Figure 8. Turnoff Delay and Fall Time (3.3V_OUT) Copyright © 2000–2007, Texas Instruments Incorporated Product Folder Link(s): TPS2070 TPS2071 Submit Documentation Feedback 13 TPS2070 TPS2071 www.ti.com SLVS287B – SEPTEMBER 2000 – REVISED SEPTEMBER 2007 PARAMETER MEASUREMENT INFORMATION (continued) VO(3.3V_OUT) (2 V/div) VO(3.3V_OUT) (2 V/div) VI(BP) = 5 V TA = 25°C CL(PG_DLY) = 0.47 mF VO(PG_DLY) (2 V/div) 0 0.4 0.8 1.2 1.6 2 2.4 2.8 3.2 3.6 VI(BP) = 5 V TA = 25°C CL(PG_DLY) = 0.47 mF VO(PG) (2 V/div) 4 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 t - Time - s t - Time - s G007 G008 Figure 9. PG_DLY Rise Time With a 0.47-μF Capacitor VI(BP) = 5 V TA = 25°C CL(PG_DLY) = 0.47 mF VO(3.3V_OUT) (2 V/div) 1 Figure 10. Turnon Delay (3.3V_OUT to PG) VI(BP) = 5 V TA = 25°C VI(EN) (2 V/div) VO(PG) (2 V/div) IO(OUT) (0.1 A/div) 0 1 2 3 4 5 6 7 8 9 10 0 1 2 t - Time - ms 3 4 5 6 7 8 9 10 t - Time - ms G009 G010 Figure 11. Turnoff Time (3.3V_OUT to PG) 14 Submit Documentation Feedback Figure 12. Short-Circuit Current (BP Switch), Device Enabled Into Short Copyright © 2000–2007, Texas Instruments Incorporated Product Folder Link(s): TPS2070 TPS2071 TPS2070 TPS2071 www.ti.com SLVS287B – SEPTEMBER 2000 – REVISED SEPTEMBER 2007 PARAMETER MEASUREMENT INFORMATION (continued) VI(BP) = VI(SP) = 5 V TA = 25°C VI(EN) (2 V/div) VO(OC) (2 V/div) IO(OUT) (0.5 A/div) IO(OUT) (0.5 A/div) 0 1 2 3 4 5 6 7 8 9 10 VI(BP) = VI(SP) = 5 V TA = 25°C 0 1 2 3 4 5 6 7 8 9 10 t - Time - ms t - Time - ms G012 G011 Figure 13. Short-Circuit Current (SP Switch), Device Enabled Into Short Figure 14. OC Response (SP Switch), Device Enabled Into Short, VI(BP) = 5 V TA = 25°C BP_DIS = 0 or Open CL(3.3V_OUT) = 4.7 mF RL(3.3V_OUT) = 33 W CL(PG_DLY) = 0.47 mF VO(PG) (2 V/div) VO(OC) (2 V/div) VO(3.3V_OUT) (1 V/div) IO(OUT) (0.1 A/div) VI(BP) = 5 V TA = 25°C 0 1 2 3 4 5 6 7 8 9 10 0 2 4 6 8 10 12 14 16 18 20 t - Time - ms t - Time - ms G014 G013 Figure 15. OC Response (BP Switch), Device Enabled Into Short Copyright © 2000–2007, Texas Instruments Incorporated Product Folder Link(s): TPS2070 TPS2071 Figure 16. SP to BP Automatic Switchover Enabled Submit Documentation Feedback 15 TPS2070 TPS2071 www.ti.com SLVS287B – SEPTEMBER 2000 – REVISED SEPTEMBER 2007 PARAMETER MEASUREMENT INFORMATION (continued) VO(PG) (2 V/div) VO(PG) (2 V/div) VO(3.3V_OUT) (1 V/div) VO(DPO_RST) (1 V/div) VI(BP) = 5 V TA = 25°C BP_DIS = 0 V or Open VI(BP) = 5 V TA = 25°C BP_DIS = 5 V 0 1 2 3 4 5 6 7 8 9 10 0 40 80 120 160 200 240 280 320 360 400 t - Time - ms t - Time - ms G016 G015 Figure 17. SP to BP Automatic Switchover Disabled Figure 18. SP to BP Automatic Switchover Enabled VI(BP) = 5 V TA = 25°C BP_DIS = 5 V VO(PG) (2 V/div) 5.25 V VI(BP) 4.25 V VO(DPO_RST) (1 V/div) DVO(3.3V_OUT) (50 mV/div) TA = 25°C CL(3.3V_OUT) = 4.7 mF IO(3.3V_OUT) = 100 mA 0 40 80 120 160 200 240 280 320 360 400 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 t - Time - ms t - Time - ms G018 G017 Figure 19. SP to BP Automatic Switchover Disabled 16 Submit Documentation Feedback 1 Figure 20. Line Transient Response Copyright © 2000–2007, Texas Instruments Incorporated Product Folder Link(s): TPS2070 TPS2071 TPS2070 TPS2071 www.ti.com SLVS287B – SEPTEMBER 2000 – REVISED SEPTEMBER 2007 PARAMETER MEASUREMENT INFORMATION (continued) TA = 25°C CL(3.3V_OUT) = 10 mF IO(3.3V_OUT) (100 mA/div) DVO(3.3V_OUT) (100 mV/div) 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 t - Time - ms G019 Figure 21. Load Transient Response TYPICAL CHARACTERISTICS BP SUPPLY CURRENT vs JUNCTION TEMPERATURE BP SUPPLY CURRENT vs INPUT VOLTAGE 205 196 200 192 195 190 II(BP) − Supply Current − µA II(BP) − Supply Current − µA VI(BP) = 5 V 194 Outputs Enabled 188 186 184 Outputs Disabled 190 Outputs Enabled 185 Outputs Disabled 180 175 170 182 180 −60 −40 −20 0 20 40 60 80 100 120 140 TJ − Junction Temperature − °C 165 4.25 4.50 4.75 5.00 5.25 VI(BP) − Input Voltage − V G020 Figure 22. 5.50 G021 Figure 23. Copyright © 2000–2007, Texas Instruments Incorporated Product Folder Link(s): TPS2070 TPS2071 Submit Documentation Feedback 17 TPS2070 TPS2071 www.ti.com SLVS287B – SEPTEMBER 2000 – REVISED SEPTEMBER 2007 TYPICAL CHARACTERISTICS (continued) SP SUPPLY CURRENT vs JUNCTION TEMPERATURE SP SUPPLY CURRENT vs INPUT VOLTAGE 120 120 VI(SP) = 5 V 115 110 II(SP) − Supply Current − µA II(SP) − Supply Current − µA 115 Outputs Disabled 105 Outputs Enabled 100 Outputs Enabled 105 100 95 −60 −40 −20 0 20 40 60 95 4.50 80 100 120 140 TJ − Junction Temperature − °C 4.75 5.25 5.50 G022 G023 Figure 24. Figure 25. STATIC DRAIN-SOURCE ON-STATE RESISTANCE vs JUNCTION TEMPERATURE (BUS-POWER SWITCHES) STATIC DRAIN-SOURCE ON-STATE RESISTANCE vs JUNCTION TEMPERATURE (SELF-POWER SWITCHES) 800 700 600 VI(BP) = 5.5 V 500 VI(BP) = 4.5 V 400 300 200 100 0 −50 0 50 100 TJ − Junction Temperature − °C 150 200 180 VI(SP) = 5 V 160 140 120 100 80 60 40 20 0 −50 0 Submit Documentation Feedback 50 100 TJ − Junction Temperature − °C G025 Figure 26. 18 5.00 VI(SP) − Input Voltage − V rDS(on) − Static Drain-Source On-State Resistance − mΩ rDS(on) − Static Drain-Source On-State Resistance − mΩ Outputs Disabled 110 150 G024 Figure 27. Copyright © 2000–2007, Texas Instruments Incorporated Product Folder Link(s): TPS2070 TPS2071 TPS2070 TPS2071 www.ti.com SLVS287B – SEPTEMBER 2000 – REVISED SEPTEMBER 2007 TYPICAL CHARACTERISTICS (continued) SHORT-CIRCUIT OUTPUT CURRENT vs JUNCTION TEMPERATURE (BUS-POWER SWITCHES) SHORT-CIRCUIT OUTPUT CURRENT vs JUNCTION TEMPERATURE (BUS-POWER SWITCHES) 300 250 VI(BP) = 5.5 V 280 IOS − Short-Circuit Output Current − mA IOS − Short-Circuit Output Current − mA VI(BP) = 4.25 V 260 240 220 200 180 160 140 −50 0 50 100 TJ − Junction Temperature − °C 170 150 130 0 50 100 150 TJ − Junction Temperature − °C G026 G027 Figure 29. SHORT-CIRCUIT OUTPUT CURRENT vs JUNCTION TEMPERATURE (SELF-POWER SWITCHES) INPUT VOLTAGE (BP UNDERVOLTAGE LOCKOUT) vs JUNCTION TEMPERATURE VI(BP) − Input Voltage (BP Undervoltage Lockout) − V IOS − Short-Circuit Output Current − mA 190 Figure 28. VI(SP) = 5 V 960 940 920 900 880 860 840 820 800 −50 210 110 −50 150 1000 980 230 0 50 100 TJ − Junction Temperature − °C 150 4.25 Start Threshold 4.20 4.15 4.10 4.05 4.00 3.95 3.90 3.85 Stop Threshold 3.80 3.75 −50 0 50 100 TJ − Junction Temperature − °C G028 Figure 30. 150 G029 Figure 31. Copyright © 2000–2007, Texas Instruments Incorporated Product Folder Link(s): TPS2070 TPS2071 Submit Documentation Feedback 19 TPS2070 TPS2071 www.ti.com SLVS287B – SEPTEMBER 2000 – REVISED SEPTEMBER 2007 TYPICAL CHARACTERISTICS (continued) INPUT CURRENT vs JUNCTION TEMPERATURE 4.50 150 Start Threshold 4.45 VI(VEXT) = 6 V EN_REG = LOW 145 4.40 II(VEXT) − Input Current − µA VI(SP) − Input Voltage (SP Undervoltage Lockout) − V INPUT VOLTAGE (SP UNDERVOLTAGE LOCKOUT) vs JUNCTION TEMPERATURE 4.35 4.30 4.25 4.20 4.15 135 130 4.10 4.00 −50 125 Stop Threshold 4.05 0 50 100 TJ − Junction Temperature − °C 120 −50 150 G030 100 Figure 33. INPUT CURRENT vs JUNCTION TEMPERATURE INPUT CURRENT vs INPUT VOLTAGE 150 G031 7 VI(VEXT) = 6 V EN_REG = HIGH VI(BP) = 5 V EN_REG = HIGH C(VCP) = 0.1 µF C(CP_P) = 0.01 µF TA = 25°C 6 II(VEXT) − Input Current − mA 4.8 4.7 4.6 4.5 4.4 5 4 3 2 1 4.3 0 50 100 TJ − Junction Temperature − °C 150 0 6.0 6.5 Submit Documentation Feedback 7.0 7.5 8.0 VI(VEXT) − Input Voltage − V G032 Figure 34. 20 50 Figure 32. 4.9 4.2 −50 0 TJ − Junction Temperature − °C 5.0 II(VEXT) − Input Current − mA 140 8.5 9.0 G033 Figure 35. Copyright © 2000–2007, Texas Instruments Incorporated Product Folder Link(s): TPS2070 TPS2071 TPS2070 TPS2071 www.ti.com SLVS287B – SEPTEMBER 2000 – REVISED SEPTEMBER 2007 TYPICAL CHARACTERISTICS (continued) INPUT CURRENT vs INPUT VOLTAGE UNDERVOLTAGE LOCKOUT vs JUNCTION TEMPERATURE 250 2.90 VI(VEXT) − Undervoltage Lockout − V Start Threshold II(VEXT) − Input Current − µA 200 150 100 50 0 6.0 VI(BP) = 5 V EN_REG = LOW C(VCP) = 0.1 µF C(CP_P) = 0.01 µF TA = 25°C 6.5 7.0 7.5 8.0 8.5 VI(VEXT) − Input Voltage − V 9.0 2.85 2.80 2.75 2.70 2.65 2.60 −50 G034 Figure 36. Stop Threshold 0 50 100 TJ − Junction Temperature − °C 150 G035 Figure 37. Copyright © 2000–2007, Texas Instruments Incorporated Product Folder Link(s): TPS2070 TPS2071 Submit Documentation Feedback 21 TPS2070 TPS2071 www.ti.com SLVS287B – SEPTEMBER 2000 – REVISED SEPTEMBER 2007 APPLICATION INFORMATION EXTERNAL CAPACITOR REQUIREMENTS A 0.1-μF ceramic bypass capacitor and a 10-μF bulk capacitor between BP and AGND, close to the device, are recommended. Similarly, a 0.1-μF ceramic and a 68-μF bulk capacitor, from SP to AGND, and from VEXT to AGND if an external 5-V LDO is required, are recommended because of much higher current in the self-powered mode. From each of the outputs (OUTx) to ground, a 33-μF or higher-valued bulk capacitor is recommended when the output load is heavy. This precaution reduces power-supply transients. Additionally, bypassing the outputs with a 0.1-μF ceramic capacitor improves the immunity of the device to short-circuit transients. An output capacitor connected between 3.3V_OUT and GND is required to stabilize the internal control loop. The internal LDO is designed for a capacitor range of 4.7 μF to 33 μF with an ESR of 0.2 Ω to 10 Ω. Solid tantalum-electrolytic, aluminum-electrolytic and multilayer ceramic capacitors are all suitable. Ceramic capacitors have different types of dielectric material, each exhibiting different temperature and voltage variations. The most common types are X5R, X7R, Y5U, Z5U, and NPO. The NPO-type ceramic capacitors are generally the most stable over temperature. However, the X5R and X7R are also relatively stable over temperature (with the X7R being the more stable of the two) and are therefore acceptable for use. The Y5U and Z5U types provide high capacitance in a small geometry, but exhibit large variations over temperature. For this reason, the Y5U and Z5U are not generally recommended. A transient condition occurs because of a sudden increase in output current. The output capacitor reduces the transient effect by providing the additional current needed by the load. Depending on the current demand at the output, a voltage drop occurs across the internal resistance, ESR, of the capacitor. Using a low-ESR capacitor helps minimize this voltage drop. A larger capacitor also reduces the voltage drop by supplying the current demand for a longer time, versus that provided by a smaller capacitor. OVERCURRENT An internal sense FET checks for overcurrent conditions. Unlike current-sense resistors, sense FETs do not increase the series resistance of the current path. When an overcurrent condition is detected, the device maintains a constant output current and reduces the output voltage accordingly. Complete shutdown occurs only if the fault is present long enough to activate thermal limiting. Three possible overload conditions can occur. In the first condition, the output has been shorted before the device is enabled or before BP and SP have been applied. The TPS2070 and TPS2071 sense the short and immediately switch into a constant-current output. In the second condition, the short occurs while the device is enabled. At the instant the short occurs, very high currents may flow for a very short time before the current-limit circuit can react. After the current-limit circuit has tripped (reached the overcurrent trip threshold), the device switches into constant-current mode. In the third condition, the load has been gradually increased beyond the recommended operating current. The current is permitted to rise until the current-limit threshold is reached or until the thermal limit of the device is exceeded. The TPS2070 and TPS2071 are capable of delivering current up to the current-limit threshold without damaging the device. Once the threshold has been reached, the device switches into its constant-current mode. OC RESPONSE The OCx output is asserted (active-low) when an overcurrent or overtemperature condition is encountered and remains asserted until the overcurrent or overtemperature condition is removed. Connecting a heavy capacitive load to an enabled device can cause momentary false overcurrent reporting from the inrush current flowing through the device and charging the downstream capacitor. The TPS2070 and TPS2071 are designed to reduce false overcurrent reporting by implementing an internal deglitch circuit. This circuit eliminates the need for an external filter, which requires extra components. Also, using low-ESR electrolytic capacitors on the outputs can reduce erroneous overcurrent reporting by providing a low-impedance energy source to lower the inrush current flow through the device during hot-plug events. The OCx outputs are logic outputs, thereby requiring no pullup or pulldown resistors. 22 Submit Documentation Feedback Copyright © 2000–2007, Texas Instruments Incorporated Product Folder Link(s): TPS2070 TPS2071 TPS2070 TPS2071 www.ti.com SLVS287B – SEPTEMBER 2000 – REVISED SEPTEMBER 2007 POWER DISSIPATION AND JUNCTION TEMPERATURE The major source of power dissipation for the TPS2070 and TPS2071 comes from the internal voltage regulator and the N-channel MOSFETs. Checking the power dissipation and junction temperature is always a good design practice. Begin by determining the rDS(on) of the N-channel MOSFET according to the input voltage and operating temperature. As an initial estimate, use the highest operating ambient temperature of interest and read rDS(on) from the graphs shown under the typical characteristics section of this data sheet. Using this value, the power dissipation per switch can be calculated by: PD = rDS(on) × I2 Multiply this number by four to get the total power dissipation coming from the N-channel MOSFETs. The power dissipation for the internal voltage regulator is calculated using: PD = (VI(BP) – VO(min)) × IO(OUT) The total power dissipation for the device becomes: PD(total) = PD(voltage regulator) + (4 × PD(switch)) Finally, calculate the junction temperature: TJ = PD × RθJA + TA where: TA = ambient temperature in °C RθJA = Thermal resistance in °C/W, equal to inverting of derating factor found on the power dissipation table in this data sheet Compare the calculated junction temperature with the initial estimate. If they do not agree within a few degrees, repeat the calculation, using the calculated value as the new estimate. Two or three iterations are generally sufficient to get a reasonable answer. THERMAL PROTECTION Thermal protection prevents damage to the IC when heavy-overload or short-circuit faults are present for extended periods. The faults force the TPS2070 and TPS2071 into constant-current mode at first, which causes the voltage across the high-side switch to increase; under short-circuit conditions, the voltage across the switch is equal to the input voltage. The increased dissipation causes the junction temperature to rise to high levels. The protection circuit senses the junction temperature of the switch and shuts it off. Hysteresis is built into the thermal sense circuit, and after the device has cooled approximately 20 degrees, the switch turns back on. The switch continues to cycle in this manner until the load fault or input power is removed. The TPS2070 and TPS2071 implement a dual thermal trip to allow fully independent operation of the power distribution switches. In an overcurrent or short-circuit condition, the junction temperature rises. Once the die temperature rises to approximately 140°C, the internal thermal-sense circuitry determines which power switch is in an overcurrent condition and turns only that power switch off, thus isolating the fault without interrupting operation of the adjacent power switch. If the die temperature exceeds the first thermal trip point of 140°C and reaches 150°C, the device turns off. The OC output is asserted (active-low) when overtemperature or overcurrent occurs. UNDERVOLTAGE LOCKOUT (UVLO) An undervoltage lockout ensures that the device (LDO and switches) is in the off state at power up. The UVLO also keeps the device from being turned on until the power supply has reached the start threshold (see undervoltage lockout table), even if the switches are enabled. The UVLO activates whenever the input voltage falls below the stop threshold as defined in the undervoltage lockout table. This facilitates the design of hot-insertion systems, where it is not possible to turn off the power switches before input power is removed. Upon reinsertion, the power switches are turned on with a controlled rise time to reduce EMI and voltage overshoots. Copyright © 2000–2007, Texas Instruments Incorporated Product Folder Link(s): TPS2070 TPS2071 Submit Documentation Feedback 23 TPS2070 TPS2071 www.ti.com SLVS287B – SEPTEMBER 2000 – REVISED SEPTEMBER 2007 SELF-POWER TO BUS-POWER OR BUS-POWER TO SELF-POWER TRANSITION An autoswitching function between bus-powered mode and self-powered mode is a feature of the TPS2070 and TPS2071. When this feature is enabled (BP_DIS is inactive) and SP is removed or applied, a transition is initiated. The transition sequence begins with the internal LDO being turned off and its external capacitance discharged. Any enabled switches are also turned off and the external capacitors discharged. Once the LDO and switch outputs are low, the internal logic turns the LDO back on. This entire sequence occurs whenever power to the SP input is removed or applied, regardless of the source of power, i.e., an external power supply or the use of the external regulator. UNIVERSAL SERIAL BUS (USB) APPLICATIONS The universal serial bus interface is a 1.5/12-Mb/s (for USB), or 480 Mb/s (for Hi-Speed USB), multiplexed serial bus designed for low-to-medium bandwidth PC peripherals (e.g., keyboards, printers, scanners, and mice). The four-wire USB interface is conceived for dynamic attach-detach (hot plug-unplug) of peripherals. Two lines are provided for differential data, and two lines are provided for 5-V power distribution. USB data is a 3.3-V-level signal, but power is distributed at 5 V to allow for voltage drops in cases where power is distributed through more than one hub or across long cables. Each function must provide its own regulated 3.3 V from the 5-V input or its own internal power supply. The USB specification defines the following five classes of devices, each differentiated by power-consumption requirements: • Hosts/self-powered hubs (SPH) • Bus-powered hubs (BPH) • Low-power, bus-powered functions • High-power, bus-powered functions • Self-powered functions Self-powered and bus-powered hubs distribute data and power to downstream functions. The TPS2070 and TPS2071 can provide power-distribution solutions for hybrid hubs that need switching between BPH and SPH according to power availability and application requirements. USB POWER-DISTRIBUTION REQUIREMENTS USB can be implemented in several ways, and, regardless of the type of USB device being developed, several power-distribution features must be implemented. • Hosts/self-powered hubs must: – Current-limit downstream ports – Report overcurrent conditions on USB VBUS – Output 5.25 V to 4.75 V at 500 mA • Bus-powered hubs must: – Enable/disable power to downstream ports – Power up at