TPS2114
TPS2115
www.ti.com
SLVS447A – DECEMBER 2002 – REVISED MARCH 2004
AUTOSWITCHING POWER MULTIPLEXER
•
FEATURES
•
•
•
•
•
•
•
•
•
•
Two-Input, One-Output Power Multiplexer
With Low rDS(on) Switches:
– 84 mΩ Typ (TPS2115)
– 120 mΩ Typ (TPS2114)
Reverse and Cross-Conduction Blocking
Wide Operating Voltage Range: 2.8 V to 5.5 V
Low Standby Current: 0.5 µA Typical
Low Operating Current: 55 µA Typical
Adjustable Current Limit
Controlled Output Voltage Transition Times,
Limits Inrush Current and Minimizes Output
Voltage Hold-Up Capacitance
CMOS and TTL Compatible Control Inputs
Manual and Auto-Switching Operating Modes
Thermal Shutdown
Available in a TSSOP-8 Package
APPLICATIONS
•
•
•
•
•
•
•
PCs
PDAs
Digital Cameras
Modems
Cell phones
Digital Radios
MP3 Players
PW PACKAGE
(TOP VIEW)
1
2
3
4
STAT
D0
D1
ILIM
8
7
6
5
IN1
OUT
IN2
GND
DESCRIPTION
The TPS211x family of power multiplexers enables seamless transition between two power supplies, such as a
battery and a wall adapter, each operating at 2.8-5.5 V and delivering up to 1 A. The TPS211x family includes
extensive protection circuitry, including user-programmable current limiting, thermal protection, inrush current
control, seamless supply transition, cross-conduction blocking, and reverse-conduction blocking. These features
greatly simplify designing power multiplexer applications.
TYPICAL APPLICATION
Switch Status
IN1: 2.8 - 5.5 V
TPS2115PW
1
2
3
4
STAT
0.1 µF
IN1
D0
OUT
D1
IN2
ILIM
GND
R1
8
7
6
CL
5
RL
RILIM
IN2: 2.8 - 5.5 V
0.1 µF
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2002–2004, Texas Instruments Incorporated
TPS2114
TPS2115
www.ti.com
SLVS447A – DECEMBER 2002 – REVISED MARCH 2004
These devices have limited built-in ESD protection. The leads should be shorted together or the device
placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
AVAILABLE OPTIONS
FEATURE
Current limit adjustment range
Switching modes
TPS2110
TPS2111
TPS2112
TPS2113
TPS2114
TPS2115
0.31-0.75A
0.63-1.25A
0.31-0.75A
0.63-1.25A
0.31-0.75A
0.63-1.25A
Manual
Yes
Yes
No
No
Yes
Yes
Automatic
Yes
Yes
Yes
Yes
Yes
Yes
No
No
Yes
Yes
Yes
Yes
TSSOP-8
TSSOP-8
TSSOP-8
TSSOP-8
TSSOP-8
TSSOP-8
Switch status output
Package
ORDERING INFORMATION
TA
PACKAGE
-40°C to 85°C
(1)
ORDERING NUMBER (1)
MARKINGS
TPS2114PW
2114
TPS2115PW
2115
TSSOP-8 (PW)
The PW package is available taped and reeled. Add an R suffix to the device type (e.g., TPS2114PWR) to indicate tape and reel.
PACKAGE DISSIPATION RATINGS
PACKAGE
DERATING FACTOR
ABOVE TA = 25°C
TA ≤ 25°C
POWER RATING
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
TSSOP-8 (PW)
3.87 mW/°C
386.84 mW
212.76 mW
154.73 mW
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted (1)
TPS2114, TPS2115
VI
Input voltage range
IN1, IN2, D0, D1, ILIM (2)
-0.3 V to 6 V
VO
Output voltage range (2)
OUT, STAT
-0.3 V to 6 V
IO
Output sink current
STAT
5 mA
TPS2114
0.9 A
IO
Continuous output current
TPS2115
Continuous total power dissipation
1.5 A
See Dissipation Rating Table
TJ
Operating virtual junction temperature range
-40°C to 125°C
Tstg
Storage temperature range
-65°C to 150°C
Lead temperature soldering 1,6 mm (1/16 inch) from case for 10 seconds
(1)
(2)
2
260°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages are with respect to GND.
TPS2114
TPS2115
www.ti.com
SLVS447A – DECEMBER 2002 – REVISED MARCH 2004
RECOMMENDED OPERATING CONDITIONS
VI
Input voltage at IN1
VI
Input voltage at IN2
VI
Input voltage at D0, D1
IO(OUT)
Current limit adjustment range
TJ
Operating virtual junction temperature
MIN
MAX
VI(IN2) ≥ 2.8 V
1.5
5.5
VI(IN2) < 2.8 V
2.8
5.5
VI(IN1) ≥ 2.8 V
1.5
5.5
VI(IN1) < 2.8 V
2.8
5.5
0
5.5
TPS2114
0.31
0.75
TPS2115
0.63
1.25
-40
125
UNIT
V
V
V
A
°C
ELECTROSTATIC DISCHARGE (ESD) PROTECTION
MIN
MAX
Human body model
CDM
UNIT
2
kV
500
V
ELECTRICAL CHARACTERISTICS
over recommended operating junction temperature range, VI(IN1) = VI(IN2) = 5.5 V, R(ILIM) = 400 Ω (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TPS2114
MIN
TPS2115
TYP
MAX
MIN
TYP MAX
VI(IN1) = VI(IN2) = 5.0 V
120
140
84
110
VI(IN1) = VI(IN2) = 3.3 V
120
140
84
110
VI(IN1) = VI(IN2) = 2.8 V
120
140
84
110
UNIT
POWER SWITCH
TJ = 25°C,
IL= 500 mA
rDS(on) (1)
Drain-source on-state
resistance (INx-OUT)
TJ = 125°C,
IL= 500 mA
(1)
VI(IN1) = VI(IN2) = 5.0 V
220
150
VI(IN1) = VI(IN2) = 3.3 V
220
150
VI(IN1) = VI(IN2) = 2.8 V
220
150
mΩ
mΩ
The TPS211x can switch a voltage as low as 1.5 V as long as there is a minimum of 2.8 V at one of the input power pins. In this specific
case, the lower supply voltge has no effect on the IN1 and IN2 switch on-resistances.
3
TPS2114
TPS2115
www.ti.com
SLVS447A – DECEMBER 2002 – REVISED MARCH 2004
ELECTRICAL CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TPS2115
MIN
TYP
MAX
UNIT
LOGIC INPUTS (D0 AND D1)
VIH
High-level input voltage
VIL
Low-level input voltage
Input current at D0 or D1
2
V
0.7
D0 or D1 = High, sink current
D0 or D1 = Low, source current
1
0.5
1.4
5
D1 = High, D0 = Low (IN1 active), VI(IN1) = 5.5 V,
VI(IN2) = 3.3 V, IO(OUT) = 0 A
55
90
D1 = High, D0 = Low (IN1 active), VI(IN1) = 3.3 V,
VI(IN2) = 5.5 V, IO(OUT) = 0 A
1
12
V
µA
SUPPLY AND LEAKAGE CURRENTS
Supply current from IN1 (operating)
Supply current from IN2 (operating)
Quiescent current from IN1 (STANDBY)
Quiescent current from IN2 (STANDBY)
µA
D0 = D1 = Low (IN2 active), VI(IN1) = 5.5 V,
VI(IN2) = 3.3 V, IO(OUT) = 0 A
75
D0 = D1 = Low (IN2 active), VI(IN1) = 3.3 V,
VI(IN2) = 5.5 V, IO(OUT) = 0 A
1
D1 = High, D0 = Low (IN1 active), VI(IN1) = 5.5 V,
VI(IN2) = 3.3 V, IO(OUT) = 0 A
1
D1 = High, D0 = Low (IN1 active), VI(IN1) = 3.3 V,
VI(IN2) = 5.5 V, IO(OUT) = 0 A
75
µA
D0 = D1 = Low (IN2 active), VI(IN1) = 5.5 V,
VI(IN2)= 3.3 V, IO(OUT) = 0 A
1
12
D0 = D1 = Low (IN2 active), VI(IN1) = 3.3 V,
VI(IN2) = 5.5 V, IO(OUT) = 0 A
55
90
D0 = D1 = High (inactive), VI(IN1) = 5.5 V,
VI(IN2) = 3.3 V, IO(OUT) = 0 A
0.5
2
µA
D0 = D1 = High (inactive), VI(IN1) = 3.3 V,
VI(IN2) = 5.5 V, IO(OUT) = 0 A
1
D0 = D1 = High (inactive), VI(IN1) = 5.5 V,
VI(IN2) = 3.3 V, IO(OUT) = 0 A
1
µA
D0 = D1 = High (inactive), VI(IN1) = 3.3 V,
VI(IN2) = 5.5 V, IO(OUT) = 0 A
0.5
2
Forward leakage current from IN1
(measured from OUT to GND)
D0 = D1 = High (inactive), VI(IN1) = 5.5 V, IN2 open,
VO(OUT) = 0 V (shorted), TJ = 25°C
0.1
5
µA
Forward leakage current from IN2
(measured from OUT to GND)
D0 = D1= High (inactive), VI(IN2) = 5.5 V, IN1 open,
VO(OUT)= 0 V (shorted), TJ = 25°C
0.1
5
µA
Reverse leakage current to INx
(measured from INx to GND)
D0 = D1 = High (inactive), VI(INx) = 0 V,
VO(OUT) = 5.5 V, TJ = 25°C
0.3
5
µA
CURRENT LIMIT CIRCUIT
TPS2114
Current limit
accuracy
TPS2115
td
(1)
4
R(ILIM) = 400 Ω
0.51
0.63
0.80
R(ILIM) = 700 Ω
0.30
0.36
0.50
R(ILIM) = 400 Ω
0.95
1.25
1.56
R(ILIM) = 700 Ω
0.47
0.71
0.99
Current limit settling time (1)
Time for short-circuit output current to settle within
10% of its steady state value.
Input current at ILIM
VI(ILIM) = 0 V, IO(OUT) = 0 A
Not tested in production.
1
-15
A
ms
0
µA
TPS2114
TPS2115
www.ti.com
SLVS447A – DECEMBER 2002 – REVISED MARCH 2004
ELECTRICAL CHARACTERISTICS (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TPS2115
MIN
TYP
1.15
1.25
MAX
UNIT
UNDERVOLTAGE LOCKOUT
IN1 and IN2 UVLO
Falling edge
Rising edge
IN1 and IN2 UVLO hysteresis (2)
Internal VDD UVLO (the higher of IN1 and IN2)
Falling edge
1.35
30
57
65
24
2.53
Rising edge
Internal VDD UVLO hysteresis (2)
UVLO deglitch for IN1, IN2 (2)
1.30
30
Falling edge
2.58
2.8
50
75
110
V
mV
V
mV
µs
REVERSE CONDUCTION BLOCKING
∆VO(I_block)
Minimum output-to-input voltage
difference to block switching
D0 = D1 = high, VI(INx) = 3.3 V. Connect OUT to a 5
V supply through a series 1-kΩ resistor. Let
D0 = low. Slowly decrease the supply voltage until
OUT connects to IN1.
80
100
120
mV
THERMAL SHUTDOWN
Thermal shutdown threshold (2)
TPS211x is in current limit.
135
Recovery from thermal shutdown (2)
TPS211x is in current limit.
125
Hysteresis (2)
°C
10
IN2-IN1 COMPARATORS
Hysteresis of IN2-IN1 comparator
0.1
Deglitch of IN2-IN1 comparator, (both↑↓ ) (2)
90
150
0.2
V
220
µs
µA
STAT OUTPUT
Leakage current
VO(STAT) = 5.5 V
0.01
1
Saturation voltage
II(STAT) = 2 mA, IN1 switch is on
0.13
0.4
Deglitch time (falling edge only)
(2)
150
V
µs
Not tested in production.
5
TPS2114
TPS2115
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SLVS447A – DECEMBER 2002 – REVISED MARCH 2004
SWITCHING CHARACTERISTICS
over recommended operating junction temperature range, VI(IN1) = VI(IN2) = 5.5 V, R(ILIM) = 400 Ω (unless otherwise noted)
PARAMETER
TPS2114
TEST CONDITIONS
TPS2115
MIN
TYP
MAX
MIN
TYP MAX
UNIT
POWER SWITCH
tr
Output rise time from an
enable (1)
VI(IN1) = VI(IN2) = 5 V
TJ = 25°C, CL = 1 µF,
IL = 500 mA,
See Figure 1(a)
0.5
1.0
1.5
1
1.8
3
ms
tf
Output fall time from a
disable (1)
VI(IN1) = VI(IN2) = 5 V
TJ = 25°C, CL = 1 µF,
IL = 500 mA,
See Figure 1(a)
0.35
0.5
0.7
0.5
1
2
ms
40
60
40
60
IN1 to IN2 transition,
VI(IN1) = 3.3 V,
VI(IN2) = 5 V
Transition time (1)
tt
TJ = 125°C,
CL = 10 µF,
IL= 500 mA [Measure
transition time as
10-90% rise time or
from 3.4 V to 4.8 V
on VO(OUT)],
See Figure 1(b)
IN2 to IN1 transition,
VI(IN1) = 5 V,
VI(IN2) = 3.3 V
tPLH1
Turnon propagation delay
from enable (1)
VI(IN1)= VI(IN2) = 5 V,
Measured from enable
to 10% of VO(OUT)
TJ = 25°C,
CL = 10 µF,
IL= 500 mA,
SeeFigure 1(a)
tPHL1
Turnoff propagation delay
from a disable (1)
VI(IN1) = VI(IN2) = 5 V,
Measured from disable
to 90% of VO(OUT)
tPLH2
tPHL2
(1)
µs
40
40
60
0.5
1
ms
TJ = 25°C,
CL = 10 µF,
IL= 500 mA,
See Figure 1(a)
3
5
ms
Switch-over rising
propagation delay (1)
Logic 1 to Logic 0 transition on D1,
VI(IN1) = 1.5 V,
VI(IN2) = 5 V,
VI(D0)= 0 V,
Measured from D1 to
10% of VO(OUT)
TJ = 25°C,
CL = 10 µF,
IL= 500 mA,
See Figure 1(c)
0.17
1
Switch-over falling
propagation delay (1)
Logic 0 to Logic 1 transition on D1,
VI(IN1) = 1.5 V,
VI(IN2) = 5V,
VI(D0)= 0 V, Measured
from D1 to 90% of
VO(OUT)
TJ = 25°C,
CL = 10 µF,
IL= 500 mA,
See Figure 1(c)
3
10
2
Not tested in production.
TRUTH TABLE
(1)
6
60
VI(IN2) > VI(IN1)
STAT
OUT (1)
0
X
Hi-Z
IN2
1
No
0
IN1
0
1
Yes
Hi-Z
IN2
1
0
X
0
IN1
1
1
X
0
Hi-Z
D1
D0
0
0
The under-voltage lockout circuit causes the output OUT to go Hi-Z
if the selected power supply does not exceed the IN1/IN2 UVLO, or
if neither of the supplies exceeds the internal VDD UVLO.
2
0.17
1
ms
5
10
ms
TPS2114
TPS2115
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SLVS447A – DECEMBER 2002 – REVISED MARCH 2004
Terminal Functions
TERMINAL
NAME
NO.
I/O
DESCRIPTION
D0
2
I
TTL and CMOS compatible input pins. Each pin has a 1-µA pullup resistor. The truth table shown above illustrates
the functionality of D0 and D1.
D1
3
I
GND
5
I
Ground
IN1
8
I
Primary power switch input. The IN1 switch can be enabled only if the IN1 supply is above the UVLO threshold and
at least one supply exceeds the internal VDD UVLO.
IN2
6
I
Secondary power switch input. The IN2 switch can be enabled only if the IN2 supply is above the UVLO threshold
and at least one supply exceeds the internal VDD UVLO.
ILIM
4
I
A resistor R(ILIM) from ILIM to GND sets the current limit IL to 250/R(ILIM) and 500/R(ILIM) for the TPS2114 and
TPS2115, respectively.
OUT
7
O
Power switch output
STAT
1
O
STAT is an open-drain output that is Hi-Z if the IN2 switch is ON. STAT pulls low if the IN1 switch is ON or if OUT is
Hi-Z (i.e., EN is equal to logic 0).
FUNCTIONAL BLOCK DIAGRAM
1 µA
IN1
IN2
1 µA
Internal VDD
Vf = 0 V
Vf = 0 V
IO(OUT)
Q1
8
Q2
6
7
Charge
Pump
VDD
ULVO
IN2
OUT
k* IO(OUT)
_
TPS2114: k = 0.2%
TPS2115: k = 0.1%
+
0.5 V
4
ILIM
ULVO
IN1
ULVO
Cross-Conduction
Detector
+
_
0.6 V
+
EN2
+
_
EN1
Q1 is ON
Q2 is ON
UVLO (VDD)
VO(OUT) > VI(INx)
UVLO (IN2)
UVLO (IN1)
D0
D1
GND
2
3
EN1
D0
D1
+
_
100 mV
+
Control
Logic
Thermal
Sense
IN2
+
_
5
IN1
1
STAT
Q2 is ON
7
TPS2114
TPS2115
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SLVS447A – DECEMBER 2002 – REVISED MARCH 2004
PARAMETER MEASUREMENT INFORMATION
90%
90%
VO(OUT)
10%
10%
0V
tr
tf
tPLH1
tPHL1
DO-D1
Switch Off
Switch Enabled
Switch Off
(a)
5V
4.8 V
VO(OUT)
3.4 V
3.3 V
tt
DO-D1
Switch #2 Enabled
Switch #1 Enabled
(b)
5V
VO(OUT)
1.5 V
4.65 V
1.85 V
tPLH2
tPHL2
DO-D1
Switch #1 Enabled
Switch #2 Enabled
Switch #1 Enabled
(c)
Figure 1. Propagation Delays and Transition Timing Waveforms
8
TPS2114
TPS2115
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SLVS447A – DECEMBER 2002 – REVISED MARCH 2004
TYPICAL CHARACTERISTICS
OUTPUT SWITCHOVER RESPONSE
VI(DO)
5V
2V/Div
TPS2115PW
NC
VI(D1)
2
f = 28 Hz
78% Duty Cycle
2V/Div
1
3
4
STAT
D0
D1
ILIM
400 Ω
0.1 µF
8
IN1
7
OUT
6
IN2
5
GND
50 Ω
1
µF
3.3 V
VO(OUT)
0.1 µF
2V/Div
Output Switchover Response Test Circuit
t - Time - 1 ms/div
Figure 2.
OUTPUT TURNON RESPONSE
VI(DO)
5V
2V/Div
TPS2115PW
f = 28 Hz
78% Duty Cycle
VI(D1)
NC
1
2
3
2V/Div
4
400 Ω
STAT
IN1
7
D0
OUT
D1
IN2
ILIM
0.1 µF
8
GND
6
5
1
µF
50 Ω
3.3 V
VO(OUT)
0.1 µF
2V/Div
Output Turnon Response Test Circuit
t − Time − 2 ms/div
Figure 3.
9
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TPS2115
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SLVS447A – DECEMBER 2002 – REVISED MARCH 2004
TYPICAL CHARACTERISTICS (continued)
OUTPUT SWITCHOVER VOLTAGE DROOP
VI(DO)
0 µF
5V
2V/Div
TPS2115PW
NC
1
2
VI(D1)
f = 580 Hz
90% Duty Cycle
2V/Div
3
4
CL = 1 µF
400 Ω
VO(OUT)
2V/Div
STAT
IN1
7
D0
OUT
D1
IN2
ILIM
0.1 µF
8
GND
6
5
CL
0.1 µF
CL = 0 µF
Output Switchover Voltage Droop Test Circuit
t - Time - 40 µs/div
Figure 4.
10
50 Ω
TPS2114
TPS2115
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SLVS447A – DECEMBER 2002 – REVISED MARCH 2004
TYPICAL CHARACTERISTICS (continued)
OUTPUT SWITCHOVER VOLTAGE DROOP
vs
LOAD CAPACITANCE
5
VI = 5 V
∆ VO(OUT) - Output Voltage Droop - V
4.5
4
3.5
RL = 10 Ω
3
2.5
2
1.5
RL = 50 Ω
1
0.5
0
0.1
1
10
CL - Load Capacitance - µF
100
VI
TPS2115PW
NC
1
2
f = 28 Hz
50% Duty Cycle
3
4
400 Ω
D0
IN1
D1
OUT
VSNS
ILIM
IN2
GND
8
0.1 µF
7
6
5
50 Ω
0.1 µF
0.1 µF
1 µF
10 µF
47 µF
10 Ω
100 µF
Output Switchover Voltage Droop Test Circuit
Figure 5.
11
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TPS2115
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SLVS447A – DECEMBER 2002 – REVISED MARCH 2004
TYPICAL CHARACTERISTICS (continued)
INRUSH CURRENT
vs
LOAD CAPACITANCE
300
200
VI = 5 V
150
VI = 3.3 V
100
I
I
- Inrush Current - mA
250
50
0
0
VI
f = 28 Hz
90% Duty Cycle
20
40
60
80
CL - Load Capacitance - µF
100
TPS2115PW
NC
1
2
NC
3
4
400 Ω
STAT
IN1
D0
OUT
D1
IN2
ILIM
GND
8
0.1 µF
To Oscilloscope
7
6
5
50 Ω
0.1 µF
0.1 µF
1 µF
Output Capacitor Inrush Current Test Circuit
Figure 6.
12
10 µF
47 µF
100 µF
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TPS2115
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SLVS447A – DECEMBER 2002 – REVISED MARCH 2004
TYPICAL CHARACTERISTICS (continued)
SWITCH ON-RESISTANCE
vs
JUNCTION TEMPERATURE
SWITCH ON-RESISTANCE
vs
SUPPLY VOLTAGE
120
rDS(on) − Switch On-Resistance − m Ω
rDS(on) − Switch On-Resistance − m Ω
180
160
TPS2114
140
120
TPS2115
100
80
60
−50
110
105
100
95
90
TPS2115
85
80
0
50
100
TJ − Junction Temperature − °C
2
150
3
4
5
VI(INx) − Supply Voltage − V
Figure 7.
Figure 8.
IN1 SUPPLY CURRENT
vs
SUPPLY VOLTAGE
IN1 SUPPLY CURRENT
vs
SUPPLY VOLTAGE
6
60
0.96
Device Disabled
VI(IN2) = 0 V
IO(OUT) = 0 A
IN1 Switch is ON
VI(IN2) = 0 V,
IO(OUT) = 0 A
58
I(IN1) − IN1 Supply Current − µ A
0.94
0.92
0.90
0.88
0.86
I
I I(IN1) − IN1 Supply Current − µ A
TPS2114
115
56
54
52
50
48
46
44
0.84
42
40
0.82
2
3
4
5
VI(IN1)− IN1 Supply Voltage − V
Figure 9.
6
2
3
4
5
VI(IN1) − Supply Voltage − V
6
Figure 10.
13
TPS2114
TPS2115
www.ti.com
SLVS447A – DECEMBER 2002 – REVISED MARCH 2004
TYPICAL CHARACTERISTICS (continued)
SUPPLY CURRENT
vs
JUNCTION TEMPERATURE
SUPPLY CURRENT
vs
JUNCTION TEMPERATURE
1.2
80
Device Disabled
VI(IN1) = 5.5 V
VI(IN2) = 3.3 V
IO(OUT) = 0 A
I I(INx) − Supply Current − µ A
I I(INx) − Supply Current − µ A
1
70
II(IN1) = 5.5 V
0.8
0.6
0.4
0.2
60
40
30
20
10
0
50
100
TJ − Junction Temperature − °C
Figure 11.
14
150
II(IN1)
50
II(IN2) = 3.3 V
0
−50
IN1 Switch is ON
VI(IN1) = 5.5 V,
VI(IN2) = 3.3 V
IO(OUT) = 0 A
0
−50
II(IN2)
0
50
100
TJ − Junction Temperature − °C
Figure 12.
150
TPS2114
TPS2115
www.ti.com
SLVS447A – DECEMBER 2002 – REVISED MARCH 2004
APPLICATION INFORMATION
The circuit in Figure 13 allows one or two battery packs to power a system. Two battery packs allow a longer run
time. The TPS2114/5 cycles between the battery packs until both packs are drained.
Switch Status
IN1: 2.8 - 5.5 V
TPS2115PW
1
NC
2
3
4
0.1 µF
IN1
STAT
D0
OUT
D1
IN2
ILIM
GND
R1
8
7
6
RL
CL
5
RILIM
IN2: 2.8 - 5.5 V
C2
0.1 µF
Figure 13. Running a System From Two Battery Packs
In Figure 14, the multiplexer selects between two power supplies based upon the D1 logic signal. OUT connects
to IN1 if D1 is logic 1, otherwise OUT connects to IN2. The logic thresholds for the D1 terminal are compatible
with both TTL and CMOS logic.
Switch Status
IN1: 2.8 - 5.5 V
TPS2115PW
1
2
3
4
STAT
0.1 µF
IN1
D0
OUT
D1
IN2
ILIM
GND
R1
8
7
6
CL
5
RL
RILIM
IN2: 2.8 - 5.5 V
0.1 µF
Figure 14. Manually Switching Power Sources
15
TPS2114
TPS2115
www.ti.com
SLVS447A – DECEMBER 2002 – REVISED MARCH 2004
DETAILED DESCRIPTION
AUTO-SWITCHING MODE
D0 equal to logic 1 and D1 equal to logic 0 selects the auto-switching mode. In this mode, OUT connects to the
higher of IN1 and IN2.
MANUAL SWITCHING MODE
D0 equal to logic 0 selects the manual-switching mode. In this mode, OUT connects to IN1 if D1 is equal to logic
1, otherwise OUT connects to IN2.
N-CHANNEL MOSFETs
Two internal high-side power MOSFETs implement a single-pole double-throw (SPDT) switch. Digital logic
selects the IN1 switch, IN2 switch, or no switch (Hi-Z state). The MOSFETs have no parallel diodes so
output-to-input current cannot flow when the FET is off. An integrated comparator prevents turnon of a FET
switch if the output voltage is greater than the input voltage.
CROSS-CONDUCTION BLOCKING
The switching circuitry ensures that both power switches never conduct at the same time. A comparator monitors
the gate-to-source voltage of each power FET and allows a FET to turn on only if the gate-to-source voltage of
the other FET is below the turnon threshold voltage.
REVERSE-CONDUCTION BLOCKING
When the TPS211x switches from a higher-voltage supply to a lower-voltage supply, current can potentially flow
back from the load capacitor into the lower-voltage supply. To minimize such reverse conduction, the TPS211x
does not connect a supply to the output until the output voltage has fallen to within 100 mV of the supply voltage.
Once a supply has been connected to the output, it remains connected regardless of output voltage.
CHARGE PUMP
The higher of supplies IN1 and IN2 powers the internal charge pump. The charge pump provides power to the
current limit amplifier and allows the output FET gate voltage to be higher than the IN1 and IN2 supply voltages.
A gate voltage that is higher than the source voltage is necessary to turn on the N-channel FET.
CURRENT LIMITING
A resistor R(ILIM) from ILIM to GND sets the current limit to 250/ R(ILIM) and 500/R(ILIM) for the TPS2114 and
TPS2115, respectively. Setting resistor R(ILIM) equal to zero is not recommended as that disables current limiting.
OUTPUT VOLTAGE SLEW-RATE CONTROL
The TPS2114/5 slews the output voltage at a slow rate when OUT switches to IN1 or IN2 from the Hi-Z state
(see Truth Table). A slow slew rate limits the inrush current into the load capacitor. High inrush currents can
adversely effect the voltage bus and cause a system to hang up or reset. It can also cause reliability issues—like
pit the connector power contacts, when hot plugging a load like a PCI card. The TPS2114/5 slews the output
voltage at a much faster rate when OUT switches between IN1 and IN2. The fast rate minimizes the output
voltage droop and reduces the output voltage hold-up capacitance requirement.
16
PACKAGE OPTION ADDENDUM
www.ti.com
14-Oct-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
TPS2114PW
ACTIVE
TSSOP
PW
8
150
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
2114
Samples
TPS2115PW
ACTIVE
TSSOP
PW
8
150
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
2115
Samples
TPS2115PWR
ACTIVE
TSSOP
PW
8
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
2115
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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