Sample &
Buy
Product
Folder
Support &
Community
Tools &
Software
Technical
Documents
TPS22954, TPS22953
SLVSCT5D – MARCH 2015 – REVISED SEPTEMBER 2016
TPS2295x 5.7 V, 5 A, 14 mΩ On-Resistance Load Switch
1 Features
3 Description
•
•
•
The TPS22953/54 are small, single channel load
switches with controlled turn on. The devices contain
a N-channel MOSFET that can operate over an input
voltage range of 0.7 V to 5.7 V and can support a
maximum continuous current of 5 A.
1
•
•
•
•
•
•
•
•
•
•
•
Integrated Single Channel Load Switch
Input Voltage Range: 0.7 V to 5.7 V
RON Resistance
– RON = 14 mΩ at VIN = 5 V (VBIAS = 5 V)
5-A Maximum Continuous Switch Current
Adjustable Undervoltage Lockout Threshold
(UVLO)
Adjustable Voltage Supervisor with
Power Good (PG) Indicator
Adjustable Output Slew Rate Control
Enhanced Quick Output Discharge Remains
Active after Power is Removed (TPS22954 Only)
– 15 Ω (Typ) Discharges 100 µF Within 10 ms
Reverse Current Blocking when Disabled
(TPS22953 Only)
Automatic Restart after Supervisor Fault Detection
When Enabled
Thermal Shutdown
Low Quiescent Current ≤ 50 µA
SON 10-pin Package with Thermal Pad
ESD Performance Tested Per JESD 22
– 2-kV HBM and 750-V CDM
The TPS22953/54 are available in small, spacesaving 10-SON packages with integrated thermal pad
allowing for high power dissipation. The device is
characterized for operation over the free-air
temperature range of –40°C to +105°C.
Device Information(1)
PART NUMBER
2 Applications
•
•
•
•
•
•
The integrated adjustable undervoltage lockout
(UVLO) and adjustable power good (PG) threshold
provides voltage monitoring as well as robust power
sequencing. The adjustable rise time control of the
device greatly reduces inrush current for a wide
variety of bulk load capacitances, thereby reducing or
eliminating power supply droop. The switch is
independently controlled by an on and off input (EN),
which is capable of interfacing directly with lowvoltage control signals. A 15-Ω on-chip load is
integrated into the device for a quick discharge of the
output when switch is disabled. The enhanced Quick
Output Discharge (QOD) remains active for short time
after power is removed from the device to finish
discharging the output.
Solid State Drives
Embedded and Industrial PC
Ultrabook™ and Notebooks
Desktops
Servers
Telecom Systems
TPS2295x
PACKAGE (PIN)
BODY SIZE (NOM)
WSON (10)
2.00 mm x 2.00 mm
WSON (10)
2.00 mm x 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Simplified Schematic
TPS22953/54
Power
Supply
IN
OUT
IN
OUT
BIAS
SNS
RSNS1
CIN
RSNS2
REN1
EN
REN2
Rpullup
PG
CL
RL
PG
GND
PAD
CT
CT
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS22954, TPS22953
SLVSCT5D – MARCH 2015 – REVISED SEPTEMBER 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
7.10
7.11
7.12
8
9
1
1
1
2
3
3
4
Absolute Maximum Ratings ...................................... 4
ESD Ratings ............................................................ 4
Recommended Operating Conditions....................... 4
Thermal Information .................................................. 5
Electrical Characteristics........................................... 5
Electrical Characteristics—VBIAS = 5 V ..................... 6
Electrical Characteristics—VBIAS = 3.3 V .................. 7
Electrical Characteristics—VBIAS = 2.5 V .................. 8
Switching Characteristics—CT = 1000 pF ................ 9
Switching Characteristics—CT = 0 pF .................. 10
Typical DC Characteristics.................................... 11
Typical Switching Characteristics ......................... 14
Parameter Measurement Information ................ 20
Detailed Description ............................................ 21
9.1
9.2
9.3
9.4
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes .......................................
21
21
22
28
10 Application and Implementation........................ 29
10.1 Application Information.......................................... 29
10.2 Typical Application ............................................... 34
11 Power Supply Recommendations ..................... 37
12 Layout................................................................... 37
12.1 Layout Guidelines ................................................ 37
12.2 Layout Example .................................................... 37
13 Device and Documentation Support ................. 38
13.1
13.2
13.3
13.4
13.5
13.6
13.7
Documentation Support ........................................
Related Links ........................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
38
38
38
38
38
38
38
14 Mechanical, Packaging, and Orderable
Information ........................................................... 39
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (July 2015) to Revision D
•
Page
Added Power Sequencing section. ...................................................................................................................................... 28
Changes from Revision B (May 2015) to Revision C
•
Page
Changed inverter part number from SN74LVC1G07 to SN74LVC1G06 in the Break-Before-Make Power MUX
Schematic. ............................................................................................................................................................................ 32
Changes from Revision A (April 2015) to Revision B
•
Page
Updated pin names and graphics throughout the document. ............................................................................................... 1
Changes from Original (March 2015) to Revision A
•
2
Page
Initial release of full version. .................................................................................................................................................. 1
Submit Documentation Feedback
Copyright © 2015–2016, Texas Instruments Incorporated
Product Folder Links: TPS22954 TPS22953
TPS22954, TPS22953
www.ti.com
SLVSCT5D – MARCH 2015 – REVISED SEPTEMBER 2016
5 Device Comparison Table
Device
Quick Output
Discharge
Reverse Current
Blocking
Yes
No
TPS22954
TPS22953
No
Package (Pin)
Body Size
Pin Pitch
DSQ (10)
2.00 mm x 2.00 mm
0.4 mm
DQC (10)
2.00 mm x 3.00 mm
0.5 mm
DSQ (10)
2.00 mm x 2.00 mm
0.4 mm
DQC (10)
2.00 mm x 3.00 mm
0.5 mm
Yes
6 Pin Configuration and Functions
DQC/DSQ Package
10 Pin WSON
Top View
IN
1
IN
2
GND
( Exposed
thermal pad)
DQC/DSQ Package
10 Pin WSON
Bottom View
10 OUT
OUT 10
9
OUT
BIAS
3
EN
4
7
GND
5
6
OUT
8 SNS
9
GND
(Exposed
thermal pad)
1
IN
2
IN
3
BIAS
SNS
8
PG
PG
7
4
EN
CT
CT
6
5
GND
Pin Functions
PIN (1)
NO.
1
NAME
I/O
DESCRIPTION
IN
I
Switch input. Bypass this input with a ceramic capacitor to GND
3
BIAS
I
Bias pin and power supply to the device
4
EN
I
Active high switch enable/disable input. Also acts as the input UVLO pin. Use external resistor divider to
adjust the UVLO level. Do not leave floating.
5
GND
—
Device ground
6
CT
O
VOUT slew rate control. Place ceramic cap from CT to GND to change the VOUT slew rate of the device
and limit the inrush current. CT Capacitormust be rated to 25 V or higher
7
PG
O
Power good. This pin is open drain which will pull low when the voltage on EN and/or SNS is below their
respective VIL level
8
SNS
I
Sense pin. Use external resistor divider to adjust the power good level. Do not leave floating
OUT
O
Switch output
Thermal Pad
—
Exposed thermal pad. Tie to GND
2
9
10
—
(1)
Pinout applies to all package versions.
Copyright © 2015–2016, Texas Instruments Incorporated
Product Folder Links: TPS22954 TPS22953
Submit Documentation Feedback
3
TPS22954, TPS22953
SLVSCT5D – MARCH 2015 – REVISED SEPTEMBER 2016
www.ti.com
7 Specifications
7.1 Absolute Maximum Ratings
Over operating free-air temperature range (unless otherwise noted)
(1)
MIN
MAX
UNIT
VIN
Input voltage
–0.3
6
V
VBIAS
Bias voltage
–0.3
6
V
VOUT
Output voltage
–0.3
6
V
VEN, VSNS,
VPG
EN, SNS, and PG voltage
–0.3
6
V
IMAX
Maximum continuous switch current, TA = 70°C
5
A
IPLS
Maximum pulsed switch current, pulse < 300 µs, 2% duty cycle
7
TJ,MAX
Maximum junction temperature
Tstg
Storage temperature
(1)
(2)
A
Internally limited
–65
150
(2)
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
See TSD specification in the Electrical Characteristics section and Thermal Considerations section.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
±750
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 500-V HBM is possible with the necessary precautions.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 250-V CDM is possible with the necessary precautions.
7.3 Recommended Operating Conditions
Over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
VIN
Input voltage
0.7
VBIAS
V
VBIAS
Bias voltage
2.5
5.7
V
VOUT
Output voltage
0
5.7
V
VEN, VSNS,
VPG
EN, SNS, and PG voltage
0
5.7
V
Operating free-air temperature
–40
105
°C
Operating junction temperature
–40
125
°C
TA
TJ
(1)
4
(1)
In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may
have to be derated. Maximum ambient temperature [TA(max)] is dependent on the maximum operating junction temperature [TJ(max)], the
maximum power dissipation of the device in the application [PD(max)], and the junction-to-ambient thermal resistance of the part/package
in the application (θJA), as given by the following equation: TA(max) = TJ(max) – (θJA × PD(max))
Submit Documentation Feedback
Copyright © 2015–2016, Texas Instruments Incorporated
Product Folder Links: TPS22954 TPS22953
TPS22954, TPS22953
www.ti.com
SLVSCT5D – MARCH 2015 – REVISED SEPTEMBER 2016
7.4 Thermal Information
TPS22953/54
THERMAL METRIC
(1)
DQC
(WSON)
DSQ
(WSON)
10 PINS
10 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
65.2
63.5
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
73.9
81.6
°C/W
RθJB
Junction-to-board thermal resistance
25.5
34.1
°C/W
ψJT
Junction-to-top characterization parameter
2
1.9
°C/W
ψJB
Junction-to-board characterization parameter
25.4
34.5
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
8.5
7.9
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.5 Electrical Characteristics
Unless otherwise noted, the specification in the following table applies over the operating ambient temperature
–40 °C ≤ TA ≤ +105 °C and the recommended VBIAS voltage range of 2.5 V to 5.7 V. Typical values are for TA = 25°C.
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX
UNIT
VOLTAGE THRESHOLDS
VIH, Rising threshold
VIN = 0.7 V to VBIAS
–40°C to +105°C
650
700
750
mV
VIL, Falling threshold
VIN = 0.7 V to VBIAS
–40°C to +105°C
560
600
640
mV
VIH, Rising threshold
VIN = 0.7 V to VBIAS
–40°C to +105°C
465
515
565
mV
VIL, Falling threshold
VIN = 0.7 V to VBIAS
–40°C to +105°C
410
455
500
mV
Blanking time for EN and SNS
EN or SNS rising
–40°C to +105°C
100
µs
tDEGLITCH Deglitch time for EN and SNS
EN or SNS falling
–40°C to +105°C
5
µs
VEN
VSNS
TIMINGS
tBLANK
tDIS
Output discharge time
(TPS22954 only)
CL = 100 µF
–40°C to +105°C
tRESTART
Output restart time
SNS falling
–40°C to +105°C
2
ms
tRCB
Response time for reverse
current blocking
(TPS22953 only)
VOUT = VBIAS
EN falling
–40°C to +105°C
10
µs
10
ms
THERMAL CHARACTERISTICS
TSD
Thermal shutdown
Junction temperature rising
—
TSDHYS
Thermal shutdown hysteresis
Junction temperature falling
—
130
150
170
2
µA
VOUT = 5 V, VIN = VEN = 0 V,
VBIAS = 0 V to 5.7 V
–40°C to +85°C
5
µA
–40°C to +105°C
11
µA
20
°C
°C
REVERSE CURRENT BLOCKING
25°C
IRCB,IN
Input reverse blocking current
(TPS22953 only)
Copyright © 2015–2016, Texas Instruments Incorporated
Product Folder Links: TPS22954 TPS22953
0.01
Submit Documentation Feedback
5
TPS22954, TPS22953
SLVSCT5D – MARCH 2015 – REVISED SEPTEMBER 2016
www.ti.com
7.6 Electrical Characteristics—VBIAS = 5 V
Unless otherwise noted, the specification in the following table applies over the operating ambient temperature
–40 °C ≤ TA ≤ +105 °C and VBIAS = 5 V. Typical values are for TA = 25°C.
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX
34
45
UNIT
POWER SUPPLIES AND CURRENTS
IQ, BIAS
BIAS quiescent current
IOUT = 0, VIN = 0.7 V to VBIAS, VEN = 5 V
ISD, BIAS
BIAS shutdown current
VOUT = 0 V, VIN = 0.7 V to VBIAS,
VEN = 0 V to VIL
VIN = 5 V
VIN = 3.3 V
ISD, IN
Input shutdown current
VEN = 0 V to VIL,
VOUT = 0 V
VIN = 1.8 V
VIN = 1.2 V
VIN = 0.7 V
–40°C to +85°C
–40°C to +105°C
–40°C to +85°C
5
–40°C to +105°C
–40°C to +85°C
0.02
–40°C to +105°C
–40°C to +85°C
0.01
µA
4
3
3
10
0.01
–40°C to +105°C
–40°C to +85°C
µA
8
10
0.01
–40°C to +105°C
–40°C to +85°C
7
13
–40°C to +105°C
–40°C to +85°C
µA
50
µA
2
8
0.01
2
–40°C to +105°C
8
IEN
EN pin input leakage current
VEN = 0 V to 5.7 V
–40°C to +105°C
0.1
µA
ISNS
SNS pin input leakage current
VSNS ≤ VBIAS
–40°C to +105°C
0.1
µA
RESISTANCE CHARACTERISTICS
25°C
VIN = 5 V
23
24
RON
ON-state resistance
IOUT = –200 mA
23
24
–40°C to +85°C
23
24
–40°C to +85°C
23
24
14
–40°C to +85°C
23
24
14
RPD
6
Output pulldown resistance
(TPS22954 Only)
Submit Documentation Feedback
VIN = VOUT = VBIAS, VEN = 0 V
25°C
–40°C to +105°C
mΩ
20
23
–40°C to +105°C
mΩ
20
–40°C to +105°C
–40°C to +85°C
mΩ
20
–40°C to +105°C
25°C
VIN = 0.7 V
14
mΩ
20
–40°C to +105°C
25°C
VIN = 1.2 V
14
mΩ
20
–40°C to +105°C
25°C
VIN = 1.5 V
14
–40°C to +85°C
25°C
VIN = 1.8 V
20
–40°C to +105°C
25°C
VIN = 3.3 V
14
–40°C to +85°C
mΩ
24
15
28
Ω
30
Ω
Copyright © 2015–2016, Texas Instruments Incorporated
Product Folder Links: TPS22954 TPS22953
TPS22954, TPS22953
www.ti.com
SLVSCT5D – MARCH 2015 – REVISED SEPTEMBER 2016
7.7 Electrical Characteristics—VBIAS = 3.3 V
Unless otherwise noted, the specification in the following table applies over the operating ambient temperature
–40 °C ≤ TA ≤ +105 °C and VBIAS = 3.3 V. Typical values are for TA = 25°C.
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX
19
35
UNIT
POWER SUPPLIES AND CURRENTS
IQ, BIAS
BIAS quiescent current
IOUT = 0, VIN = 0.7 V to VBIAS, VEN = 5 V
ISD, BIAS
BIAS shutdown current
VOUT = 0 V, VIN = 0.7 V to VBIAS,
VEN = 0 V to VIL
VIN = 3.3 V
VIN = 1.8 V
ISD, IN
Input shutdown current
VEN = 0 V to VIL,
VOUT = 0 V
VIN = 1.2 V
VIN = 0.7 V
–40°C to +85°C
–40°C to +105°C
–40°C to +85°C
4
–40°C to +105°C
–40°C to +85°C
0.01
–40°C to +105°C
–40°C to +85°C
0.01
µA
7
µA
3
3
10
0.01
–40°C to +105°C
–40°C to +85°C
6
10
–40°C to +105°C
–40°C to +85°C
µA
37
2
µA
8
0.01
2
–40°C to +105°C
8
IEN
EN pin input leakage current
VEN = 0 V to 5.7 V
–40°C to +105°C
0.1
µA
ISNS
SNS pin input leakage current
VSNS ≤ VBIAS
–40°C to +105°C
0.1
µA
RESISTANCE CHARACTERISTICS
25°C
VIN = 3.3 V
15
–40°C to +85°C
24
–40°C to +105°C
25°C
VIN = 1.8 V
ON-state resistance
IOUT = –200 mA
VIN = 1.5 V
RPD
Output pulldown resistance
(TPS22954 Only)
VIN = VOUT = VBIAS, VEN = 0 V
20
23
–40°C to +105°C
24
14
23
–40°C to +105°C
24
14
23
–40°C to +105°C
24
25°C
Copyright © 2015–2016, Texas Instruments Incorporated
Product Folder Links: TPS22954 TPS22953
13
mΩ
20
–40°C to +85°C
–40°C to +105°C
mΩ
20
–40°C to +85°C
25°C
VIN = 0.7 V
mΩ
24
14
–40°C to +85°C
25°C
VIN = 1.2 V
20
23
–40°C to +105°C
RON
mΩ
25
14
–40°C to +85°C
25°C
21
mΩ
28
Ω
30
Ω
Submit Documentation Feedback
7
TPS22954, TPS22953
SLVSCT5D – MARCH 2015 – REVISED SEPTEMBER 2016
www.ti.com
7.8 Electrical Characteristics—VBIAS = 2.5 V
Unless otherwise noted, the specification in the following table applies over the operating ambient temperature
–40 °C ≤ TA ≤ +105 °C and VBIAS = 2.5 V. Typical values are for TA = 25°C.
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX
16
25
UNIT
POWER SUPPLIES AND CURRENTS
IQ, BIAS
BIAS quiescent current
IOUT = 0, VIN = 0.7 V to VBIAS, VEN = 5 V
ISD, BIAS
BIAS shutdown current
VOUT = 0 V, VIN = 0.7 V to VBIAS,
VEN = 0 V to VIL
VIN = 2.5 V
VIN = 1.8 V
ISD, IN
Input shutdown current
VEN = 0 V to VIL,
VOUT = 0 V
VIN = 1.2 V
VIN = 0.7 V
–40°C to +85°C
–40°C to +105°C
–40°C to +85°C
4
–40°C to +105°C
–40°C to +85°C
0.01
–40°C to +105°C
–40°C to +85°C
0.01
µA
6
µA
3
3
10
0.01
–40°C to +105°C
–40°C to +85°C
5
10
–40°C to +105°C
–40°C to +85°C
µA
27
2
µA
8
0.01
2
–40°C to +105°C
8
IEN
EN pin input leakage current
VEN = 0 V to 5.7 V
–40°C to +105°C
0.1
µA
ISNS
SNS pin input leakage current
VSNS ≤ VBIAS
–40°C to +105°C
0.1
µA
RESISTANCE CHARACTERISTICS
25°C
VIN = 2.5 V
16
–40°C to +85°C
26
–40°C to +105°C
25°C
VIN = 1.8 V
ON-state resistance
IOUT = –200 mA
VIN = 1.5 V
RPD
8
Output pulldown resistance
(TPS22954 Only)
Submit Documentation Feedback
VIN = VOUT = VBIAS, VEN = 0 V
22
25
–40°C to +105°C
26
15
24
–40°C to +105°C
25
14
24
–40°C to +105°C
25
25°C
12
mΩ
21
–40°C to +85°C
–40°C to +105°C
mΩ
22
-40°C to 85°C
25°C
VIN = 0.7 V
mΩ
26
15
–40°C to +85°C
25°C
VIN = 1.2 V
22
25
–40°C to +105°C
RON
mΩ
27
15
–40°C to +85°C
25°C
23
mΩ
28
Ω
30
Ω
Copyright © 2015–2016, Texas Instruments Incorporated
Product Folder Links: TPS22954 TPS22953
TPS22954, TPS22953
www.ti.com
SLVSCT5D – MARCH 2015 – REVISED SEPTEMBER 2016
7.9 Switching Characteristics—CT = 1000 pF
Refer to the timing test circuit in Figure 51 (unless otherwise noted) for references to external components used for the test
condition in the switching characteristics table. Switching characteristics shown below are only valid for the power-up
sequence where VIN and VBIAS are already in steady state condition before the EN terminal is asserted high.
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNIT
VIN = 5 V, VEN = VBIAS = 5 V, TA = 25°C
tON
Turnon time
RL = 10 Ω, CL = 0.1 µF, CT = 1000 pF
1265
tOFF
Turnoff time
RL = 10 Ω, CL = 0.1 µF, CT = 1000 pF
6
tR
VOUT rise time
RL = 10 Ω, CL = 0.1 µF, CT = 1000 pF
1492
tF
VOUT fall time
RL = 10 Ω, CL = 0.1 µF, CT = 1000 pF
2.2
tD
ON delay time
RL = 10 Ω, CL = 0.1 µF, CT = 1000 pF
519
µs
VIN = 2.5 V, VEN = VBIAS = 5 V, TA = 25°C
tON
Turnon time
RL = 10 Ω, CL = 0.1 µF, CT = 1000 pF
813
tOFF
Turnoff time
RL = 10 Ω, CL = 0.1 µF, CT = 1000 pF
6.1
tR
VOUT rise time
RL = 10 Ω, CL = 0.1 µF, CT = 1000 pF
765
tF
VOUT fall time
RL = 10 Ω, CL = 0.1 µF, CT = 1000 pF
2.2
tD
ON delay time
RL = 10 Ω, CL = 0.1 µF, CT = 1000 pF
430
µs
VIN = 0.7 V, VEN = VBIAS = 5 V, TA = 25°C
tON
Turnon time
RL = 10 Ω, CL = 0.1 µF, CT = 1000 pF
476
tOFF
Turnoff time
RL = 10 Ω, CL = 0.1 µF, CT = 1000 pF
6.2
tR
VOUT rise time
RL = 10 Ω, CL = 0.1 µF, CT = 1000 pF
245
tF
VOUT fall time
RL = 10 Ω, CL = 0.1 µF, CT = 1000 pF
2.1
tD
ON delay time
RL = 10 Ω, CL = 0.1 µF, CT = 1000 pF
353
813
µs
VIN = 2.5 V, VEN = 5 V, VBIAS = 2.5 V, TA = 25°C
tON
Turnon time
RL = 10 Ω, CL = 0.1 µF, CT = 1000 pF
tOFF
Turnoff time
RL = 10 Ω, CL = 0.1 µF, CT = 1000 pF
4.9
tR
VOUT rise time
RL = 10 Ω, CL = 0.1 µF, CT = 1000 pF
765
tF
VOUT fall time
RL = 10 Ω, CL = 0.1 µF, CT = 1000 pF
2.2
tD
ON delay time
RL = 10 Ω, CL = 0.1 µF, CT = 1000 pF
430
476
µs
VIN = 0.7 V, VEN = 5 V, VBIAS = 2.5 V, TA = 25°C
tON
Turnon time
RL = 10 Ω, CL = 0.1 µF, CT = 1000 pF
tOFF
Turnoff time
RL = 10 Ω, CL = 0.1 µF, CT = 1000 pF
6.1
tR
VOUT rise time
RL = 10 Ω, CL = 0.1 µF, CT = 1000 pF
245
tF
VOUT fall time
RL = 10 Ω, CL = 0.1 µF, CT = 1000 pF
2.1
tD
ON delay time
RL = 10 Ω, CL = 0.1 µF, CT = 1000 pF
353
Copyright © 2015–2016, Texas Instruments Incorporated
Product Folder Links: TPS22954 TPS22953
Submit Documentation Feedback
µs
9
TPS22954, TPS22953
SLVSCT5D – MARCH 2015 – REVISED SEPTEMBER 2016
www.ti.com
7.10 Switching Characteristics—CT = 0 pF
Refer to the timing test circuit in Figure 51 (unless otherwise noted) for references to external components used for the test
condition in the switching characteristics table. Switching characteristics shown below are only valid for the power-up
sequence where VIN and VBIAS are already in steady state condition before the EN terminal is asserted high.
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNIT
VIN = 5 V, VEN = VBIAS = 5 V, TA = 25°C
tON
Turnon time
RL = 10 Ω, CL = 0.1 µF, CT = 0 pF
235
tOFF
Turnoff time
RL = 10 Ω, CL = 0.1 µF, CT = 0 pF
6
tR
VOUT rise time
RL = 10 Ω, CL = 0.1 µF, CT = 0 pF
140
tF
VOUT fall time
RL = 10 Ω, CL = 0.1 µF, CT = 0 pF
2.2
tD
ON delay time
RL = 10 Ω, CL = 0.1 µF, CT = 0 pF
165
µs
VIN = 2.5 V, VEN = VBIAS = 5 V, TA = 25°C
tON
Turnon time
RL = 10 Ω, CL = 0.1 µF, CT = 0 pF
200
tOFF
Turnoff time
RL = 10 Ω, CL = 0.1 µF, CT = 0 pF
6
tR
VOUT rise time
RL = 10 Ω, CL = 0.1 µF, CT = 0 pF
79
tF
VOUT fall time
RL = 10 Ω, CL = 0.1 µF, CT = 0 pF
2.1
tD
ON delay time
RL = 10 Ω, CL = 0.1 µF, CT = 0 pF
160
µs
VIN = 0.7 V, VEN = VBIAS = 5 V, TA = 25°C
tON
Turnon time
RL = 10 Ω, CL = 0.1 µF, CT = 0 pF
170
tOFF
Turnoff time
RL = 10 Ω, CL = 0.1 µF, CT = 0 pF
6
tR
VOUT rise time
RL = 10 Ω, CL = 0.1 µF, CT = 0 pF
32
tF
VOUT fall time
RL = 10 Ω, CL = 0.1 µF, CT = 0 pF
2
tD
ON delay time
RL = 10 Ω, CL = 0.1 µF, CT = 0 pF
154
200
µs
VIN = 2.5 V, VEN = 5 V, VBIAS = 2.5 V, TA = 25°C
tON
Turnon time
RL = 10 Ω, CL = 0.1 µF, CT = 0 pF
tOFF
Turnoff time
RL = 10 Ω, CL = 0.1 µF, CT = 0 pF
6
tR
VOUT rise time
RL = 10 Ω, CL = 0.1 µF, CT = 0 pF
79
tF
VOUT fall time
RL = 10 Ω, CL = 0.1 µF, CT = 0 pF
2.1
tD
ON delay time
RL = 10 Ω, CL = 0.1 µF, CT = 0 pF
160
170
µs
VIN = 0.7 V, VEN = 5 V, VBIAS = 2.5 V, TA = 25°C
tON
Turnon time
RL = 10 Ω, CL = 0.1 µF, CT = 0 pF
tOFF
Turnoff time
RL = 10 Ω, CL = 0.1 µF, CT = 0 pF
6
tR
VOUT rise time
RL = 10 Ω, CL = 0.1 µF, CT = 0 pF
32
tF
VOUT fall time
RL = 10 Ω, CL = 0.1 µF, CT = 0 pF
2
tD
ON delay time
RL = 10 Ω, CL = 0.1 µF, CT = 0 pF
154
10
Submit Documentation Feedback
µs
Copyright © 2015–2016, Texas Instruments Incorporated
Product Folder Links: TPS22954 TPS22953
TPS22954, TPS22953
www.ti.com
SLVSCT5D – MARCH 2015 – REVISED SEPTEMBER 2016
7.11 Typical DC Characteristics
36
40
105°C
85°C
25°C
-40°C
35
35
34
33
32
IQ,BIAS (PA)
IQ,BIAS (PA)
30
25
31
30
29
28
20
27
25
105°C
85°C
25°C
-40°C
24
0.5
1
26
15
10
2.5
3
3.5
4
4.5
VBIAS (V)
VIN = 1.8 V
5
5.5
6
1.5
VEN = 5.7 V
VOUT = 0 V
2.5
3
VIN (V)
VBIAS = 5 V
Figure 1. IQ,BIAS vs VBIAS
3.5
4
4.5
5
D002
VEN = 5.7 V
VOUT = 0 V
Figure 2. IQ,BIAS vs VIN
2.5
6
105°C
85°C
25°C
-40°C
5.5
105°C
85°C
25°C
-40°C
2.25
2
1.75
1.5
5
ISD,IN (PA)
ISD,BIAS (PA)
2
D001
4.5
1.25
1
0.75
0.5
4
0.25
0
3.5
-0.25
3
2.5
3
3.5
4
4.5
VBIAS (V)
VIN = 1.8 V
5
5.5
-0.5
0.5
6
1
1.5
2
D003
VEN = 0 V
VOUT = 0 V
VBIAS = 5 V
3.5
4
4.5
5
D004
VEN = 0 V
Figure 3. ISD,BIAS vs VBIAS
VOUT = 0 V
Figure 4. ISD,IN vs VIN
0.01
2.4
105°C
85°C
25°C
-40°C
2.2
2
1.8
25°C
-40°C
0.009
0.008
0.007
IRCB,IN (PA)
1.6
IRCB,IN (PA)
2.5
3
VIN (V)
1.4
1.2
1
0.8
0.006
0.005
0.004
0.003
0.6
0.002
0.4
0.001
0.2
0
0.5
1
1.5
VBIAS = 0 V to 5.7 V
2
2.5
3 3.5
VOUT (V)
4
4.5
5
5.5
6
0
0.5
1
1.5
D035
VEN = 0 V
VIN = 0 V
VBIAS = 0 V to 5.7 V
Figure 5. IRCB,IN vs VOUT
Copyright © 2015–2016, Texas Instruments Incorporated
Product Folder Links: TPS22954 TPS22953
2
2.5
3
3.5
VOUT (V)
4
4.5
VEN = 0 V
5
5.5
6
D036
VIN = 0 V
Figure 6. IRCB,IN vs VOUT
Submit Documentation Feedback
11
TPS22954, TPS22953
SLVSCT5D – MARCH 2015 – REVISED SEPTEMBER 2016
www.ti.com
Typical DC Characteristics (continued)
22
19
VIN = 2.5V
VIN = 1.8V
VIN = 0.7V
20
17
16
RON (m:)
18
RON (m:)
VIN = 3.3V
VIN = 2.5V
VIN = 1.8V
VIN = 0.7V
18
16
14
15
14
13
12
12
11
10
-40
-20
0
20
40
60
80
Ambient Temperature (qC)
VBIAS = 2.5 V
100
10
-40
120
Iout = –200 mA
VEN = 5 V
Figure 7. RON vs Temperature, VBIAS = 2.5 V
20
40
60
80
Ambient Temperature (qC)
100
120
D006
Iout = –200 mA
VEN = 5 V
Figure 8. RON vs Temperature, VBIAS = 3.3 V
22
105°C
85°C
25°C
-40°C
22
20
105°C
85°C
25°C
-40°C
20
RON (m:)
18
18
16
16
14
14
12
12
10
0.6
0.8
1
1.2
VBIAS = 2.5 V
1.4
1.6 1.8
VIN (V)
2
2.2
2.4
10
0.6 0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4
VIN (V)
D009
2.6
D008
Iout = –200 mA
VEN = 5 V
VBIAS = 3.3 V
Figure 9. RON vs VIN, VBIAS = 2.5 V
Iout = –200 mA
VEN = 5 V
Figure 10. RON vs VIN, VBIAS = 3.3 V
22
16
105°C
85°C
25°C
-40°C
20
VBIAS = 2.5V
VBIAS = 3.3V
VBIAS = 5V
VBIAS = 5.7V
15.75
15.5
15.25
RON (m:)
18
RON (m:)
0
VBIAS = 3.3 V
24
RON (m:)
-20
D005
16
15
14.75
14.5
14.25
14
14
12
13.75
10
0.6
13.25
0.5
13.5
1
1.4
VBIAS = 5 V
1.8
2.2
2.6 3
VIN (V)
3.4
3.8
4.2
4.6
5
1
1.5
D010
Iout = –200 mA
VEN = 5 V
TA = 25°C
Figure 11. RON vs VIN, VBIAS = 5 V
12
Submit Documentation Feedback
2
2.5
3
3.5
VIN (V)
4
4.5
Iout = –200 mA
5
5.5
6
D011
VEN = 5 V
Figure 12. RON vs VIN
Copyright © 2015–2016, Texas Instruments Incorporated
Product Folder Links: TPS22954 TPS22953
TPS22954, TPS22953
www.ti.com
SLVSCT5D – MARCH 2015 – REVISED SEPTEMBER 2016
Typical DC Characteristics (continued)
15.4
17.5
VIN = 2.5V
VIN = 1.8V
VIN = 0.7V
VIN = 3.3V
VIN = 2.5V
VIN = 1.8V
VIN = 0.7V
15.2
15
16.5
14.8
16
14.6
RON (m:)
RON (m:)
17
15.5
15
14.4
14.2
14
13.8
14.5
13.6
14
13.4
13.5
13.2
0
0.5
1
1.5
2
VBIAS = 2.5 V
2.5
3
IOUT (A)
3.5
4
4.5
5
0
0.5
VEN = 5 V
Figure 13. RON vs IOUT, VBIAS = 2.5 V
2
2.5
3
IOUT (A)
3.5
4
4.5
5
D033
VEN = 5 V
Figure 14. RON vs IOUT, VBIAS = 3.3 V
22
VIN = 5V
VIN = 3.3V
VIN = 2.5V
VIN = 1.8V
VIN = 0.7V
14.2
14.1
14
105°C
25°C
-40°C
20
18
16
13.9
RPD (:)
RON (m:)
1.5
VBIAS = 3.3 V
14.3
13.8
13.7
13.6
14
12
10
8
13.5
6
13.4
13.3
4
13.2
2
0.6
0
0.5
1
1.5
VBIAS = 5 V
2
2.5
3
IOUT (A)
3.5
4
4.5
5
0.8
VEN = 5 V
1.4
1.6 1.8
VOUT (V)
2
2.2
2.4
2.6
D012
VIN = VOUT
VEN = 0 V
Figure 16. RPD vs VOUT, VBIAS = 2.5 V
18
105°C
25°C
-40°C
12
12
RPD (:)
14
10
10
8
8
6
6
4
4
0.9
1.2
VBIAS = 3.3 V
105°C
25°C
-40°C
16
14
2
0.6
1.2
VBIAS = 2.5 V
Figure 15. RON vs IOUT, VBIAS = 5 V
16
1
D034
18
RPD (:)
1
D032
1.5
1.8
2.1
VOUT (V)
2.4
2.7
3
3.3
2
0.5
1
1.5
D016
VIN = VOUT
VEN = 0 V
Figure 17. RPD vs VOUT, VBIAS = 3.3 V
VBIAS = 5 V
2
2.5
3
VOUT (V)
3.5
4
4.5
VIN = VOUT
5
D014
VEN = 0 V
Figure 18. RPD vs VOUT, VBIAS = 5 V
Copyright © 2015–2016, Texas Instruments Incorporated
Product Folder Links: TPS22954 TPS22953
Submit Documentation Feedback
13
TPS22954, TPS22953
SLVSCT5D – MARCH 2015 – REVISED SEPTEMBER 2016
www.ti.com
7.12 Typical Switching Characteristics
800
750
700
650
1600
105°C
85°C
25°C
-40°C
1400
1200
550
tR (Ps)
tR (Ps)
600
500
450
105°C
85°C
25°C
-40°C
1000
800
400
600
350
300
400
250
200
0.6
0.8
1
1.2
VBIAS = 2.5 V
1.4
1.6 1.8
VIN (V)
2
2.2
2.4
200
0.5
2.6
1
CT = 1000 pF
VEN = Low to High
Figure 19. tR vs VIN , VBIAS = 2.5 V
105°C
85°C
25°C
-40°C
2.13
2.1
2.07
2.06
2.04
2.04
2.01
0.8
1
1.2
VBIAS = 2.5 V
1.4
1.6 1.8
VIN (V)
2
2.2
2.4
1.98
0.5
2.6
1
1.5
2
D022
CT = 1000 pF
VEN = High to Low
VBIAS = 5 V
VEN = Low to High
2.5
3
VIN (V)
3.5
4
4.5
5
D023
CT = 1000 pF
VEN = High to Low
Figure 22. tF vs VIN , VBIAS = 5 V
900
1400
105°C
85°C
25°C
-40°C
1300
1200
750
1100
700
1000
tON (Ps)
tON (Ps)
D021
CT = 1000 pF
105°C
85°C
25°C
-40°C
Figure 21. tF vs VIN , VBIAS = 2.5 V
650
600
800
700
500
600
450
500
0.8
1
1.2
1.4
1.6 1.8
VIN (V)
CT = 1000 pF
2
2.2
2.6
400
0.5
1
1.5
D024
VEN = Low to High
Figure 23. tON vs VIN , VBIAS = 2.5 V
Submit Documentation Feedback
2.4
105°C
85°C
25°C
-40°C
900
550
VBIAS = 2.5 V
14
5
2.1
2.08
400
0.6
4.5
2.19
2.12
800
4
2.22
2.16
850
3.5
Figure 20. tR vs VIN , VBIAS = 5 V
2.14
2.02
0.6
2.5
3
VIN (V)
2.25
tF (Ps)
tF (Ps)
2.16
2
VBIAS = 5 V
2.2
2.18
1.5
D020
VBIAS = 5 V
2
2.5
3
VIN (V)
3.5
CT = 1000 pF
4
4.5
5
D025
VEN = Low to High
Figure 24. tON vs VIN , VBIAS = 5 V
Copyright © 2015–2016, Texas Instruments Incorporated
Product Folder Links: TPS22954 TPS22953
TPS22954, TPS22953
www.ti.com
SLVSCT5D – MARCH 2015 – REVISED SEPTEMBER 2016
Typical Switching Characteristics (continued)
7.25
6.4
105°C
85°C
25°C
-40°C
7
6.75
6.3
6.5
6.25
6.25
tOFF (Ps)
tOFF (Ps)
105°C
85°C
25°C
-40°C
6.35
6
5.75
6.2
6.15
6.1
5.5
6.05
5.25
5
6
4.75
0.6
5.95
0.5
0.8
1
1.2
VBIAS = 2.5 V
1.4
1.6 1.8
VIN (V)
2
2.2
2.4
2.6
1
CT = 1000 pF
VEN = High to Low
Figure 25. tOFF vs VIN , VBIAS = 2.5 V
3.5
4
4.5
5
D027
CT = 1000 pF
VEN = High to Low
Figure 26. tOFF vs VIN , VBIAS = 5 V
105°C
85°C
25°C
-40°C
510
480
400
450
380
420
360
390
340
360
320
330
300
300
0.8
1
VBIAS = 2.5 V
105°C
85°C
25°C
-40°C
540
420
280
0.6
2.5
3
VIN (V)
570
tD (Ps)
tD (Ps)
440
2
VBIAS = 5 V
480
460
1.5
D031
D025
1.2
1.4
1.6 1.8
VIN (V)
2
2.2
2.4
270
0.5
2.6
1
1.5
2
D028
CT = 1000 pF
VEN = Low to High
VBIAS = 5 V
Figure 27. tD vs VIN , VBIAS = 2.5 V
2.5
3
VIN (V)
3.5
CT = 1000 pF
4
4.5
5
D029
VEN =Low to High
Figure 28. tD vs VIN , VBIAS= 5 V
810
105°C
85°C
25°C
-40°C
800
790
780
tR (Ps)
770
760
750
740
730
720
710
700
690
2.5
3
VIN = 2.5 V
3.5
4
4.5
VBIAS (V)
5
CT = 1000 pF
5.5
6
D030
VEN = Low to High
Figure 29. tR vs VBIAS
Copyright © 2015–2016, Texas Instruments Incorporated
Product Folder Links: TPS22954 TPS22953
Submit Documentation Feedback
15
TPS22954, TPS22953
SLVSCT5D – MARCH 2015 – REVISED SEPTEMBER 2016
www.ti.com
Typical Switching Characteristics (continued)
VIN = 0.7 V
CIN = 1 µF
VBIAS = 2.5 V
CL = 0.1 µF
CT = 1000 pF
RL = 10 Ω
Figure 30. Turnon Waveform, VBIAS = 2.5 V
VIN = 0.7 V
CIN = 1 µF
VBIAS = 5 V
CL = 0.1 µF
CT = 1000 pF
RL = 10 Ω
Figure 32. Turnon Waveform, VBIAS = 5 V
VIN = 2.5 V
CIN = 1 µF
VBIAS = 2.5 V
CL = 0.1 µF
CT = 1000 pF
RL = 10 Ω
Figure 34. Turnon Waveform, VBIAS = 2.5 V
16
Submit Documentation Feedback
VIN = 0.7 V
CIN = 1 µF
VBIAS = 2.5 V
CL = 0.1 µF
CT = 1000 pF
RL = 10 Ω
Figure 31. Turnoff Waveform, VBIAS = 2.5 V
VIN = 0.7 V
CIN = 1 µF
VBIAS = 5 V
CL = 0.1 µF
CT = 1000 pF
RL = 10 Ω
Figure 33. Turnoff Waveform, VBIAS = 5 V
VIN = 2.5 V
CIN = 1 µF
VBIAS = 2.5 V
CL = 0.1 µF
CT = 1000 pF
RL = 10 Ω
Figure 35. Turnoff Waveform, VBIAS = 2.5 V
Copyright © 2015–2016, Texas Instruments Incorporated
Product Folder Links: TPS22954 TPS22953
TPS22954, TPS22953
www.ti.com
SLVSCT5D – MARCH 2015 – REVISED SEPTEMBER 2016
Typical Switching Characteristics (continued)
VIN = 2.5 V
CIN = 1 µF
VBIAS = 5 V
CL = 0.1 µF
CT = 1000 pF
RL = 10 Ω
Figure 36. Turnon Waveform, VBIAS = 5 V
VIN = 3.3 V
CIN = 1 µF
VBIAS = 5 V
CL = 0.1 µF
CT = 1000 pF
RL = 10 Ω
Figure 38. Turnon Waveform, VBIAS = 5 V
VIN = 5 V
CIN = 1 µF
VBIAS = 5 V
CL = 0.1 µF
CT = 1000 pF
RL = 10 Ω
Figure 40. Turnon Waveform, VBIAS = 5 V
VIN = 2.5 V
CIN = 1 µF
VBIAS = 5 V
CL = 0.1 µF
CT = 1000 pF
RL = 10 Ω
Figure 37. Turnoff Waveform, VBIAS = 5 V
VIN = 3.3 V
CIN = 1 µF
VBIAS = 5 V
CL = 0.1 µF
CT = 1000 pF
RL = 10 Ω
Figure 39. Turnoff Waveform, VBIAS = 5 V
VIN = 5 V
CIN = 1 µF
VBIAS = 5 V
CL = 0.1 µF
CT = 1000 pF
RL = 10 Ω
Figure 41. Turnoff Waveform, VBIAS = 5 V
Copyright © 2015–2016, Texas Instruments Incorporated
Product Folder Links: TPS22954 TPS22953
Submit Documentation Feedback
17
TPS22954, TPS22953
SLVSCT5D – MARCH 2015 – REVISED SEPTEMBER 2016
www.ti.com
Typical Switching Characteristics (continued)
VIN = 3.3 V
CIN = 1 µF
VBIAS = 5 V
CL = 0.1 µF
CT = 1000 pF
RL = Open
Figure 42. Turnon Waveform, No Load
VIN = 3.3 V
CIN = 1 µF
VBIAS = 5 V
CL = 0.1 µF
CT = 1000 pF
RL = 1 Ω
Figure 44. Turnon Waveform, Heavy Load
VIN = 5 V
CIN = 1 µF
VBIAS = 5 V
CL = 100 µF
CT = 1000 pF
RL = 10 Ω
Figure 46. PG Response to EN Falling (tDEGLITCH)
18
Submit Documentation Feedback
VIN = 5 V
CIN = 1 µF
VBIAS = 5 V
CL = 0.1 µF
CT = 1000 pF
RL = Open
Figure 43. Turnon Waveform, No Load
VIN = 5 V
CIN = 1 µF
VBIAS = 5 V
CL = 0.1 µF
CT = 1000 pF
RL = 1 Ω
Figure 45. Turnon Waveform, Heavy Load
VIN = 5 V
CIN = 1 µF
VBIAS = 5 V
CL = 100 µF
CT = 1000 pF
RL = 10 Ω
Figure 47. PG Response to SNS Falling with Auto-Restart
(tDEGLITCH and tRESTART)
Copyright © 2015–2016, Texas Instruments Incorporated
Product Folder Links: TPS22954 TPS22953
TPS22954, TPS22953
www.ti.com
SLVSCT5D – MARCH 2015 – REVISED SEPTEMBER 2016
Typical Switching Characteristics (continued)
VIN = 5 V
CIN = 1 µF
VBIAS = 5 V
CL = 100 µF
CT = 1000 pF
RL = 10 Ω
Figure 48. PG Response to SNS Rising (tBLANK)
VIN = 10 Ω to GND
CIN = 0.2 µF
VIN = 5 V
CIN = 1 µF
VBIAS = 5 V
CL = 100 µF
CT = 1000 pF
RL = None
Figure 49. Quick Output Discharge of 100-µF Load (tDIS)
VBIAS = 5 V
VOUT = 5 V
Figure 50. Reverse Current Blocking Response Time (tRCB)
Copyright © 2015–2016, Texas Instruments Incorporated
Product Folder Links: TPS22954 TPS22953
Submit Documentation Feedback
19
TPS22954, TPS22953
SLVSCT5D – MARCH 2015 – REVISED SEPTEMBER 2016
www.ti.com
8 Parameter Measurement Information
IN
OUT
EN
SNS
CIN = 1µF
ON
+
-
(A)
CL
RL
10kΩ
OFF
BIAS
PG
GND
GND
GND
+
-
A.
CT
TPS22953/54
Rise and fall times of the control signal is 100 ns.
Figure 51. Timing Test Circuit
t DEGLITCH
VEN
50%
50%
t DEGLITCH
50%
50%
tON
tOFF
90%
tD
VOUT
90%
50%
50%
10%
t BLANK
t BLANK
10%
tR
tF
Figure 52. Timing Waveforms
20
Submit Documentation Feedback
Copyright © 2015–2016, Texas Instruments Incorporated
Product Folder Links: TPS22954 TPS22953
TPS22954, TPS22953
www.ti.com
SLVSCT5D – MARCH 2015 – REVISED SEPTEMBER 2016
9 Detailed Description
9.1 Overview
The TPS22953/4 are 5.7-V, 5-A load switches in 10-pin SON packages. To reduce voltage drop for low voltage,
high current rails the device implements a low resistance N-channel MOSFET, which reduces the drop out
voltage through the device at high currents. The integrated adjustable undervoltage lockout (UVLO) and
adjustable power good (PG) threshold provides voltage monitoring as well as robust power sequencing.
The adjustable rise time control of the device greatly reduces inrush current for a wide variety of bulk load
capacitances, thereby reducing or eliminating power supply droop. The switch is independently controlled by an
on and off input (EN), which is capable of interfacing directly with low-voltage control signals. A 15-Ω on-chip
load resistor is integrated into the device for output quick discharge when switch is turned off.
During shutdown, the device has very low leakage currents, thereby reducing unneccessary leakages for
downstream modules during standby. Integrated power monitoring functionality, control logic, driver, power
supply, and output discharge FET eliminates the need for any external components, which reduces solution size
and BOM count.
9.2 Functional Block Diagram
Reverse Current
Blocking*
(TPS22953 Only)
IN
Power
supply
module
BIAS
EN
Control
Logic
PG
Driver
VEN
OUT
Thermal
Shutdown
CT
QOD Resistance*
(TPS22954 Only)
SNS
VSNS
GND
(*) Only active when the switch is disabled.
Copyright © 2015–2016, Texas Instruments Incorporated
Product Folder Links: TPS22954 TPS22953
Submit Documentation Feedback
21
TPS22954, TPS22953
SLVSCT5D – MARCH 2015 – REVISED SEPTEMBER 2016
www.ti.com
9.3 Feature Description
9.3.1 On and Off Control (EN pin)
The EN pin controls the state of the switch. When the voltage on EN has exceeded VIH,EN the switch is enabled.
When EN goes below VIL,EN the switch is disabled.
The EN pin has a blanking time of tBLANK on the rising edge once the VIH,EN threshold has been exceeded. It also
has a de-glitch time of tDEGLITCH when the voltage has gone below VIL,EN.
The EN pin can also be configured via an external resistor divider to monitor a voltage signal for input UVLO.
See Equation 1 and Figure 53 on how to configure the EN pin for input UVLO.
REN2
VIH,EN = VIN ´
REN1 + REN2
where
•
•
•
VIH,EN is the rising threshold of the EN pin (see the Electrical Characteristics table)
VIN is the input voltage being monitored (this could be VIN, VBIAS, or an external power supply)
REN1, REN2 is the resistor divider values
(1)
VIN or VBIAS
REN1
EN
REN2
Figure 53. Resistor Divider (EN Pin)
22
Submit Documentation Feedback
Copyright © 2015–2016, Texas Instruments Incorporated
Product Folder Links: TPS22954 TPS22953
TPS22954, TPS22953
www.ti.com
SLVSCT5D – MARCH 2015 – REVISED SEPTEMBER 2016
Feature Description (continued)
9.3.2 Voltage Monitoring (SNS Pin)
The SNS pin of the device can be used to monitor the output voltage of the device or another voltage rail. The
pin can be configured with an external resistor divider to set the desired trip point for the voltage being monitored
or be tied to OUT directly. If the voltage on the SNS pin exceeds VIH,SNS, the voltage being monitored on the
SNS pin is considered to be valid high. The voltage on the SNS pin must be greater than VIH,SNS for at least
tBLANK before PG is asserted high. If the voltage on the SNS pin goes below VIL,SNS, then the switch powers cycle
(i.e., the switch is disabled and re-enabled). For proper functionality of the device, this pin must not be left
floating. If a resistor divider is not being used for voltage sensing, this pin can be tied directly to VOUT.
The SNS pin has a blanking time of tBLANK on the rising edge once the VIH,SNS threshold has been exceeded. It
has a de-glitch time of tDEGLITCH when the voltage has gone below VIL,SNS.
See Equation 2 and Figure 54 on how to configure the SNS pin for voltage monitoring.
RSNS2
VIH,SNS = VOUT ´
RSNS1 + RSNS2
where
•
•
•
VIH,SNS is the the rising threshold of the SNS pin (see Electrical Characteristics table)
VOUT is the voltage on the OUTpin
RSNS1, RSNS2 is the resistor divider values
(2)
VOUT
RSNS1
SNS
RSNS2
Figure 54. Voltage Divdier (SNS Pin)
Copyright © 2015–2016, Texas Instruments Incorporated
Product Folder Links: TPS22954 TPS22953
Submit Documentation Feedback
23
TPS22954, TPS22953
SLVSCT5D – MARCH 2015 – REVISED SEPTEMBER 2016
www.ti.com
Feature Description (continued)
9.3.3 Power Good (PG Pin)
The PG pin is only asserted high when the voltage on EN has exceeded VIH,EN and the voltage on SNS has
exceeded VIH,SNS. There is a tBLANK time, typically 100 µs, between the SNS voltage exceeding VIH,SNS and PG
being asserted high. If the voltage on EN goes below VIL,EN or the voltage on SNS goes below VIL,SNS, PG is deasserted. There is a tDEGLITCH time, typically 5µs, between the EN voltage or SNS voltage going below their
respective VIL levels and PG being pulled low.
PG is an open drain pin and must be pulled up with a pull-up resistor. Be sure to never exceed the maximum
operating voltage on this pin. If PG is not being used in the application, tie it to GND for proper device
functionality.
For proper PG operation, the BIAS voltage must be within the recommended operating range. In systems that
are very sensitive to noise or have long PG traces, it is recommended to add a small capacitance from PG to
GND for decoupling.
9.3.4 Supervisor Fault Detection and Automatic Restart
The falling edge of the SNS pin below VIL,SNS is considered a fault case and causes the load switch to be
disabled for tRESTART (typically 2 ms). After the tRESTART time, the switch is automatically re-enabled as long as EN
is still above VIH,EN . In the case the SNS pin is being used to monitor VOUT or a downstream voltage, the restart
helps to protect against excessive over-current if there is a quick short to GND. See Figure 55.
IN
BIAS
EN
VIN
0
VBIAS
0
VEN
tR
0
VOUT
OUT
0
SNS
tD
90%
Voltage
Pulled
Down
VSNS
10%
tRESTART
VIL,SNS
VIH,SNS
0
tBLANK
tDEGLITCH
VPG
PG
0
Time
Figure 55. Automatic Restart after Quick Short to GND
24
Submit Documentation Feedback
Copyright © 2015–2016, Texas Instruments Incorporated
Product Folder Links: TPS22954 TPS22953
TPS22954, TPS22953
www.ti.com
SLVSCT5D – MARCH 2015 – REVISED SEPTEMBER 2016
Feature Description (continued)
9.3.5 Manual Restart
The falling edge of the SNS pin below VIL,SNS is considered a fault case and causes the load switch to be
disabled for tRESTART (typically 2 ms). The SNS pin can be driven by an MCU to manually reset the load switch.
After the tRESTART time, the switch is automatically re-enabled as long as EN is still above VIH,EN , even is SNS is
held low. The PG pin stays low until the switch is re-enabled and the SNS pin rises above VIH,SNS. See Figure 56.
VIN
IN
0
VBIAS
BIAS
0
VEN
EN
tR
0
VOUT
tD
90%
OUT
10%
0
tRESTART
VSNS
VIL,SNS
SNS
0
tDEGLITCH
VPG
PG
0
Time
Figure 56. Manual Restart (SNS Held Low)
If the SNS pin is brought above VIH,SNS within the tRESTART time, the switch still waits to re-enable. The PG pin
also stays low until tBLANK after switch is re-enabled. In this case, PG indicates when the switch is enabled and
capable of being reset again. See Figure 57.
VIN
IN
0
VBIAS
BIAS
0
VEN
EN
tR
0
tD
VOUT
90%
OUT
10%
0
t RESTART
VSNS
VIL,SNS
SNS
0
tBLANK
tDEGLITCH
VPG
PG
0
Time
Figure 57. Manual Restart (SNS Toggled Low to High)
Copyright © 2015–2016, Texas Instruments Incorporated
Product Folder Links: TPS22954 TPS22953
Submit Documentation Feedback
25
TPS22954, TPS22953
SLVSCT5D – MARCH 2015 – REVISED SEPTEMBER 2016
www.ti.com
Feature Description (continued)
9.3.6 Thermal Shutdown
If the junction temperature of the device exceeds TSD, the switch is disabled. The device is enabled once the
junction temperature drops by TSDHYS as long as EN is still greater than VIH,EN.
9.3.7 Reverse Current Blocking (TPS22953 Only)
When the switch is disabled (either by de-asserting EN or SNS, triggering thermal shutdown, or losing power),
the reverse current blocking (RCB) feature of the device is engaged within tRCB, typically 10 μs. Once the RCB is
engaged, the reverse current from the OUT pin to the IN pin is limited to IRCB,IN, typically 0.01 μA.
9.3.8 Quick Output Discharge (QOD) (TPS22954 Only)
The quick output discharge (QOD) transistor is engaged indefinitely whenever the switch is disabled and the
recommended VBIAS voltage is met. During this state, the QOD resistance (RPD) discharges VOUT to GND. It is
not recommended to apply a continuous DC voltage to OUT when the device is disabled.
The QOD transistor can remain active for a short period of time even after VBIAS loses power. This brief period of
time is defined as tDIS. For best results, it is recommended the device get disabled before VBIAS goes below the
minimum recommended voltage. The waveform in Figure 58 shows the behaviour when power is applied and
then removed in a typical application.
VIN
IN
0
VBIAS
BIAS
0
EN
VEN
VIH,EN
0
VOUT
VIL,EN
tDEGLITCH
tBLANK
OUT
VOUT < 100mV
0
VSNS
SNS
0
tDIS
VIH,SNS
tBLANK
VIL,SNS
tDEGLITCH
VPG
PG
0
Time
Figure 58. Power Applied and then Removed in a Typical Application
At the end of the tDIS time, it is not guaranteed that VOUT will be 0 V since the final voltage is dependent upon the
initial voltage and the CL capacitor. The final VOUT can be calculated with Equation 3 for a given initial voltage
and CL capacitor.
-t
Vƒ = Vo ´ e RC
where
•
•
•
•
26
Vf is the final VOUT voltage
Vo is the initial VOUT voltage
R is the the value of the output discharge resistor, RPD (see the Electrical Characteristics table)
C is the output bulk capacitance on OUT
Submit Documentation Feedback
(3)
Copyright © 2015–2016, Texas Instruments Incorporated
Product Folder Links: TPS22954 TPS22953
TPS22954, TPS22953
www.ti.com
SLVSCT5D – MARCH 2015 – REVISED SEPTEMBER 2016
Feature Description (continued)
9.3.9 VIN and VBIAS Voltage Range
For optimal RON performance, make sure VIN ≤ VBIAS. The device is still functional if VIN > VBIAS but it exhibits RON
greater than what is listed in the Electrical Characteristics table. See Figure 59 for an example of a typical
device. Notice the increasing RON as VIN increases. Be sure to never exceed the maximum voltage rating for VIN
and VBIAS.
55
VBIAS = 2.5V
VBIAS = 3.3V
VBIAS = 5V
VBIAS = 5.7V
50
45
RON (m:)
40
35
30
25
20
15
10
0.5
1
1.5
2
2.5
3 3.5
VIN (V)
4
4.5
5
5.5
6
D031
Figure 59. RON When VIN > VBIAS
9.3.10 Adjustable Rise Time (CT pin)
A capacitor to GND on the CT pin sets the slew rate for VOUT. An appropriate capacitance value must be placed
on CT such that the IMAX and IPLS specifications of the device are not violated. The capacitor to GND on the CT
pin must be rated for 25 V or higher. An approximate formula for the relationship between CT (except for CT =
open) and the slew rate for any VBIAS is shown in Equation 4.
SR = 0.35 × CT + 20
where
•
•
•
•
SR is the slew rate (in μs/V)
CT is the the capacitance value on the CT terminal (in pF)
The units for the constant 20 are μs/V.
The units for the constant 0.35 are μs/(V*pF).
(4)
Rise time can be calculated by multiplying the input voltage (typically 10% to 90%) by the slew rate. Table 1
contains rise time values measured on a typical device.
Table 1. Rise Time
CTx (pF)
RISE TIME (µs) 10%–90%, CL = 0.1 µF, VBIAS = 2.5 V to 5.7 V, RL=10 Ω LOAD.
TYPICAL VALUES AT 25°C, 25 V X7R 10% CERAMIC CAP
5V
3.3 V
1.8 V
1.5 V
1.2 V
0.7 V
Open
140
98
62
54
46
32
220
444
301
175
150
124
81
470
767
518
299
255
210
133
1000
1492
994
562
474
387
245
2200
3105
2050
1151
961
787
490
4700
6420
4246
2365
1980
1612
998
10000
14059
9339
5183
4331
3533
2197
Copyright © 2015–2016, Texas Instruments Incorporated
Product Folder Links: TPS22954 TPS22953
Submit Documentation Feedback
27
TPS22954, TPS22953
SLVSCT5D – MARCH 2015 – REVISED SEPTEMBER 2016
www.ti.com
9.3.11 Power Sequencing
The TPS2295x operates regardless of power-on and power-off sequencing order. The order in which voltages
are applied to IN, BIAS, and EN will not damage the device as long as the voltages do not exceed the absolute
maximum operating conditions. If voltage is applied to EN before IN and BIAS, the slew rate of VOUT will not be
controlled. Also, turning off IN and/or BIAS while EN is high will not damage the device.
9.4 Device Functional Modes
Table 2 describes what the OUT pin is connected to for a particular device as determined by the EN pin.
Table 2. Function Table
28
EN
TPS22953
TPS22954
L
OPEN
RPD to GND
H
IN
IN
Submit Documentation Feedback
Copyright © 2015–2016, Texas Instruments Incorporated
Product Folder Links: TPS22954 TPS22953
TPS22954, TPS22953
www.ti.com
SLVSCT5D – MARCH 2015 – REVISED SEPTEMBER 2016
10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
This section will highlights some of the design considerations when implementing this device in various
applications. A PSPICE model for this device is also available on www.ti.com for further aid.
10.1.1 Input to Output Voltage Drop
The input to output voltage drop in the device is determined by the RON of the device and the load current. The
RON of the device depends upon the VIN and VBIAS conditions of the device. Refer to the RON specification of the
device in the Electrical Characteristics table of this datasheet. Once the RON of the device is determined based
upon the VIN and VBIAS voltage conditions, use Equation 5 to calculate the input to output voltage drop.
DV = ILOAD ´ RON
where
•
•
•
ΔV is the voltage drop from IN to OUT
ILOAD is the load current
RON is the On-Resistance of the device for a specific VIN and VBIAS
(5)
An appropriate ILOAD must be chosen such that the IMAX specification of the device is not violated.
10.1.2 Thermal Considerations
The maximum IC junction temperature must be restricted to just under the thermal shutdown (TSD) limit of the
device. To calculate the maximum allowable dissipation, PD(max) for a given output current and ambient
temperature, use Equation 6.
TJ(max) - TA
PD(max) =
qJA
where
•
•
•
•
PD(max) is the maximum allowable power dissipation
TJ(max) is the maximum allowable junction temperature before hitting thermal shutdown (see the Electrical
Characteristics table)
TA is the ambient temperature of the device
θJA is the junction to air thermal impedance. See the Thermal Information section. This parameter is highly
dependent upon board layout.
Copyright © 2015–2016, Texas Instruments Incorporated
Product Folder Links: TPS22954 TPS22953
Submit Documentation Feedback
(6)
29
TPS22954, TPS22953
SLVSCT5D – MARCH 2015 – REVISED SEPTEMBER 2016
www.ti.com
Application Information (continued)
10.1.3 Automatic Power Sequencing
The PG pin of the TPS22953/54 allows for automatic sequencing of multiple system rails or loads. The accurate
SNS voltage monitoring ensures the first rail is up before the next starts to turn on. This approach provides
robust system sequencing and reduces the total inrush current by preventing overlap. Figure 60 shows how two
rails can be sequenced. There is no limit to the number of rails that can be sequenced in this way
TPS22953/54
Power
Supply
CIN
IN
OUT
IN
OUT
BIAS
SNS
System
Module 1
RSNS1
REN1
RSNS2
CL
EN
REN2
PG
GND
CT
PAD
CT
TPS22953/54
IN
OUT
IN
OUT
System
Module 2
RSNS1
BIAS
SNS
RSNS2
REN1
EN
REN2
Rpullup
PG
PG
GND
PAD
CL
CT
CT
Figure 60. Power Sequencing with PG Control Schematic
30
Submit Documentation Feedback
Copyright © 2015–2016, Texas Instruments Incorporated
Product Folder Links: TPS22954 TPS22953
TPS22954, TPS22953
www.ti.com
SLVSCT5D – MARCH 2015 – REVISED SEPTEMBER 2016
Application Information (continued)
10.1.4 Monitoring a Downstream Voltage
The SNS pin can be used to monitor other system voltages in addition to VOUT. The status of the monitored
voltage are indicated by the PG pin which can be pulled up to VOUT or another voltage. Figure 61 shows an
example of the TPS22953/54 monitoring the output of a downstream DC/DC regulator. In this case, the switch
turns on when the power supply is above the UVLO, but the PG is not asserted until the DC/DC regulator has
started up.
TPS22953/54
Power
Supply
IN
OUT
IN
OUT
DC/DC
Regulator
CL
RSNS1
BIAS
CIN
SNS
REN1
RSNS2
EN
RL
Rpullup
REN2
GND
PG
PAD
CT
PG
CT
Figure 61. Monitoring a Downstream Voltage Schematic
In this application, if the DC/DC Regulator is shut down, the supervisor registers this as a fault case and reset
the load switch.
10.1.5 Monitoring the Input Voltage
The SNS pin can also be used to monitor VIN in the case a MCU GPIO is being used to control the EN. This
allows PG to report on the status of the input voltage when the switch is enabled. See Figure 62.
TPS22953/54
Power
Supply
CIN
RSNS1
RSNS2
IN
OUT
IN
OUT
BIAS
MCU
GPIO
CL
SNS
RL
EN
Rpullup
GND
PG
PAD
CT
PG
CT
Figure 62. Monitoring The Input Voltage Schematic
Copyright © 2015–2016, Texas Instruments Incorporated
Product Folder Links: TPS22954 TPS22953
Submit Documentation Feedback
31
TPS22954, TPS22953
SLVSCT5D – MARCH 2015 – REVISED SEPTEMBER 2016
www.ti.com
Application Information (continued)
10.1.6 Break-Before-Make Power MUX (TPS22953 Only)
The reverse current blocking feature of the TPS22953 makes it suitable for power multiplexing (MUXing)
between two power supplies with different voltages. The SNS and PG pin can be configured to implement breakbefore-make logic. The circuit in Figure 63 shows how the detection of Power Supply 1 can be used to disable
the load switch for Power Supply 2. By tying the SNS of Load Switch 1 directly to the input, its PG pin is pulled
up as soon as the device is enabled.
TPS22953
(Load Switch 1)
Power
Supply 1
IN
OUT
IN
OUT
BIAS
SNS
System
Load
CL
REN1
EN
REN2
PG
GND
CT
PAD
Rpullup
SN74LVC1G06
TPS22953
(Load Switch 2)
Power
Supply 2
IN
OUT
IN
OUT
BIAS
SNS
RSNS1
REN1
Rpullup
RSNS2
EN
REN2
PG
PG Signal
GND
PAD
CT
Figure 63. Break-Before-Make Power MUX Schematic
The break-before-make logic ensures that Power Supply 2 is completely disconnected before Power Supply 1 is
connected. This approach provides very robust reverse current blocking. However, in most cases, this also
results in a dip in the output voltage when switching between supplies.
The amount of voltage dip depends on the loading, the output capacitance, and the turnon delay of the load
switch. In this application, leaving the CT pin open results in the shortest turn on delay and minimize the output
voltage dip.
Table 3 summarizes the logic of the PG Signal for Figure 63.
Table 3. Break-Before-Make PG Signal
PG Signal
32
Indication
H
Power supply 1 not present. System powered from power supply 2.
L
Power supply 1 present. System powered from power supply 1.
Submit Documentation Feedback
Copyright © 2015–2016, Texas Instruments Incorporated
Product Folder Links: TPS22954 TPS22953
TPS22954, TPS22953
www.ti.com
SLVSCT5D – MARCH 2015 – REVISED SEPTEMBER 2016
10.1.7 Make-Before-Break Power MUX (TPS22953 Only)
The reverse current blocking feature of the TPS22953 makes it suitable for power multiplexing (MUXing)
between two power supplies with different voltages. The SNS and PG pin can be configured to implement makebefore-break logic. The circuit in Figure 64 shows how the detection of Load Switch 1 turning on can be used to
disable the load switch for Power Supply 2. By tying SNS to the Load, the PG is pulled up when the output
voltage starts to rise. This disables an active low load switch such as the TPS22910A.
TPS22953
Power Supply 1
(4.5V to 5.5V)
IN
OUT
IN
OUT
BIAS
SNS
System
Load
RSNS1 = 10kΩ
REN1 = 10kΩ
RSNS2 = 1.45kΩ
CL
EN
REN2 = 2.05kΩ
PG
GND
CT
PAD
Rpullup
PG Signal
TPS22910A
Power Supply 2
(3.0V to 3.6V)
IN
OUT
ON
GND
Figure 64. Make-Before-Break Power MUX Schematic
The make-before-break logic ensures that Power Supply 2 is not disconnected until Power Supply 1 is
connected. Unlike break-before-make logic, this approach is ideal for preventing voltage dip on the output when
switching between supplies. However, in most cases, this also results in temporary reverse current flow.
The TPS22910A is well suited for this application because it can detect and block reverse current even before it
is disabled by the TPS22953 PG signal. Also, the active low enable of the TPS22910A eliminates the need for an
inverter as shown in the previous example.
In order to ensure correct logic, the SNS pin must be configured to toggle PG when the load voltage is between
the two supply voltages (3.6 V to 4.5 V). The SNS resistor values in Figure 64 are assuming a tolerance of ±1%
or better.
Table 4 summarizes the logic of the PG Signal for Figure 64.
Table 4. Make-Before-Break PG Signal
PG Signal
Indication
H
Power supply 1 present. System powered from power supply 1.
L
Power supply 1 not present. System powered from power supply 2.
Copyright © 2015–2016, Texas Instruments Incorporated
Product Folder Links: TPS22954 TPS22953
Submit Documentation Feedback
33
TPS22954, TPS22953
SLVSCT5D – MARCH 2015 – REVISED SEPTEMBER 2016
www.ti.com
10.2 Typical Application
This application demonstrates how the TPS22953/54 can use used to limit inrush current to output capacitance.
TPS22953/54
Power
Supply
IN
OUT
IN
OUT
BIAS
SNS
RSNS1
RSNS2
REN1
CIN
EN
REN2
Rpullup
PG
CL
RL
PG
GND
PAD
CT
CT
Figure 65. Powering a Downstream Module Schematic
10.2.1 Design Requirements
For this design example, use the input parameters shown in Table 5.
Table 5. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
VIN
3.3 V
VBIAS
5V
CL
47 µF
Maximum Acceptable Inrush Current
150 mA
RL
None
10.2.2 Detailed Design Procedure
To
•
•
•
•
•
begin the design process, the designer needs to know the following:
Input voltage
BIAS voltage
Load current
Load capacitance
Maximum acceptable inrush current
10.2.2.1 Inrush Current
To determine how much inrush current is caused by the CL capacitor, use Equation 7.
dV
IINRUSH = CL ´ OUT
dt
where
•
•
•
•
IINRUSH is the amount of inrush caused by CL
CL is the load capacitance on VOUT
dt is the VOUT Rise Time (typically 10% to 90%)
dVOUT is the Change in VOUT Voltage (typically 10% to 90%)
(7)
In this case, a Slew Rate slower than 314 μs/V is required to meet the maximum acceptable inrush requirement.
Equation 4 can be used to estimate the CT capacitance (as shown in Equation 8 and Equation 9) required for
this slew rate.
34
Submit Documentation Feedback
Copyright © 2015–2016, Texas Instruments Incorporated
Product Folder Links: TPS22954 TPS22953
TPS22954, TPS22953
www.ti.com
SLVSCT5D – MARCH 2015 – REVISED SEPTEMBER 2016
314 μs/V = 0.35 × CT + 20
CT = 840 pF
(8)
(9)
10.2.3 Application Curves
The following Application Curves show the inrush with multiple different CT values. These curves show only a CT
capacitance greater than 840 pF results in the acceptable inrush current of 150 mA.
CT = 0 pF
CT = 220 pF
Figure 66. Inrush with CT = 0 pF
CT = 470 pF
Figure 67. Inrush with CT = 220 pF
CT = 1000 pF
Figure 68. Inrush with CT = 470 pF
Figure 69. Inrush with CT = 1000 pF
Copyright © 2015–2016, Texas Instruments Incorporated
Product Folder Links: TPS22954 TPS22953
Submit Documentation Feedback
35
TPS22954, TPS22953
SLVSCT5D – MARCH 2015 – REVISED SEPTEMBER 2016
www.ti.com
CT = 2200 pF
Figure 70. Inrush with CT = 2200 pF
36
Submit Documentation Feedback
Copyright © 2015–2016, Texas Instruments Incorporated
Product Folder Links: TPS22954 TPS22953
TPS22954, TPS22953
www.ti.com
SLVSCT5D – MARCH 2015 – REVISED SEPTEMBER 2016
11 Power Supply Recommendations
The device is designed to operate from a VBIAS range of 2.5 V to 5.7 V and a VIN range of 0.7 V to 5.7 V. The
power supply must be well regulated and placed as close to the device terminals as possible. It must be able to
withstand all transient and load current steps. In most situations, using an input capacitance of 1 µF is sufficient
to prevent the supply voltage from dipping when the switch is turned on. In cases where the power supply is
slow to respond to a large transient current or large load current step, additional bulk capacitance may be
required on the input.
The requirements for larger input capacitance can be mitigated by adding additional capacitance to the CT pin.
This causes the load switch to turn on more slowly. Not only does this reduce transient inrush current, but it also
gives the power supply more time to respond to the load current step.
12 Layout
12.1 Layout Guidelines
•
•
•
•
•
•
Input and Output traces must be as short and wide as possible to accommodate for high current.
Use vias under the exposed thermal pad for thermal relief for high current operation.
The CT Capacitor must be placed as close as possible to the device to minimize parasitic trace capacitance.
It is also recommended to cutout copper on other layers directly below CT to minimize parasitic capacitance.
The IN terminal must be bypassed to ground with low ESR ceramic bypass capacitors. The typical
recommended bypass capacitance is ceramic with X5R or X7R dielectric. This capacitor must be placed as
close to the device pins as possible.
The OUT terminal must be bypassed to ground with low ESR ceramic bypass capacitors. The typical
recommended bypass capacitance is ceramic with X5R or X7R dielectric. This capacitor must be placed as
close to the device pins as possible.
The BIAS terminal must be bypassed to ground with low ESR ceramic bypass capacitors. The typical
recommended bypass capacitance is ceramic with X5R or X7R dielectric.
12.2 Layout Example
VIA to Power Ground Plane
VIA to PG pin
Input Bypass
Capacitor
Output Bypass
Capacitor
IN
OUT
IN
OUT
BIAS
SNS
EN
PG
GND
CT
To Bias Supply
To µC
To GPIO
control or
resistor
divider
Exposed Thermal
Pad Area
Figure 71. Recommended Board Layout
Copyright © 2015–2016, Texas Instruments Incorporated
Product Folder Links: TPS22954 TPS22953
Submit Documentation Feedback
37
TPS22954, TPS22953
SLVSCT5D – MARCH 2015 – REVISED SEPTEMBER 2016
www.ti.com
13 Device and Documentation Support
13.1 Documentation Support
13.1.1 Related Documentation
For related documentation see the following:
• TPS22953/54 User’s Guide
• Basics of Load Switches
• Managing Inrush Current
• Reverse Current Protection in Load Switches
• Quiescent Current vs Shutdown Current for Load Switch Power Consumption
• Load Switch Thermal Considerations
13.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 6. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
TPS22953
Click here
Click here
Click here
Click here
Click here
TPS22954
Click here
Click here
Click here
Click here
Click here
13.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
13.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
13.5 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
13.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
13.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
38
Submit Documentation Feedback
Copyright © 2015–2016, Texas Instruments Incorporated
Product Folder Links: TPS22954 TPS22953
TPS22954, TPS22953
www.ti.com
SLVSCT5D – MARCH 2015 – REVISED SEPTEMBER 2016
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2015–2016, Texas Instruments Incorporated
Product Folder Links: TPS22954 TPS22953
Submit Documentation Feedback
39
PACKAGE OPTION ADDENDUM
www.ti.com
30-Apr-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS22953DQCR
ACTIVE
WSON
DQC
10
3000
RoHS & Green
TPS22953DSQR
ACTIVE
WSON
DSQ
10
3000
TPS22954DQCR
ACTIVE
WSON
DQC
10
TPS22954DSQR
ACTIVE
WSON
DSQ
10
NIPDAU
Level-2-260C-1 YEAR
-40 to 105
RB953
RoHS & Green NIPDAU | NIPDAUAG
Level-2-260C-1 YEAR
-40 to 105
ZFDI
3000
RoHS & Green
Level-2-260C-1 YEAR
-40 to 105
RB954
3000
RoHS & Green NIPDAU | NIPDAUAG
Level-2-260C-1 YEAR
-40 to 105
ZDKI
NIPDAU
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
工商网监
湘ICP备2023018690号
