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TPS22993
SLVSCA3A – NOVEMBER 2013 – REVISED MARCH 2014
TPS22993 Quad Channel Load Switch with GPIO and I2C Control
1 Features
2 Applications
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1
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Input Voltage: 1.0V to 3.6V
Low ON-State Resistance (VBIAS = 7.2V)
– RON = 15mΩ at VIN = 3.3V
– RON = 15mΩ at VIN = 1.8V
– RON = 15mΩ at VIN = 1.5V
– RON = 15mΩ at VIN = 1.05V
VBIAS voltage range: 4.5V to 17.2V
– Suitable for 2S/3S/4S Li-ion Battery
Topologies
1.2A Max Continuous Current per Channel
Quiescent Current
– Single Channel < 9µA
– All Four Channels < 17µA
Shutdown Current (all four channels) < 6µA
Four 1.2V Compatible GPIO Control Inputs
I2C Configuration (per channel)
– On/Off Control
– Programmable Slew Rate Control (5 options)
– Programmable ON-delay (4 options)
– Programmable Output Discharge (4 options)
I2C SwitchALL™ Command for Multichannel/Multi-chip Control
QFN-20 package, 3mm x 3mm, 0.75mm height
Ultrabook™
Ultrathin PC
Notebook PC
Tablets
Servers
All-In-One PC
3 Description
The TPS22993 is a multi-channel, low RON load
switch with user programmable features. The device
contains four N-channel MOSFETs that can operate
over an input voltage range of 1.0V to 3.6V. The
switch can be controlled by I2C making it ideal for
usage with processors that have limited GPIO
available. The rise time of the TPS22993 device is
internally controlled in order to avoid inrush current.
The TPS22993 has five programmable slew rate
options, four ON-delay options, and four quick output
discharge (QOD) resistance options.
The channels of the device can be controlled via
either GPIO or I2C. The default mode of operation is
GPIO control through the ONx terminals. The I2C
slave address terminals can be tied high or low to
assign seven unique device addresses.
The TPS22993 is available in a space-saving RLW
package (0.4mm pitch) and is characterized for
operation over the free-air temperature range of
–40°C to 85°C.
Device Information
ORDER NUMBER
TPS22993PRLWR
PACKAGE
WQFN (20)
BODY SIZE
3mm x 3mm
4 Simplified Schematic
VBIAS
(4.5V to 17.2V)
VIN1
VOUT1
ON1
VIN2
CL
RL
CL
RL
CL
RL
CL
RL
VOUT2
ON2
PMIC or
PMU
VIN3
TPS22993
VOUT3
ON3
VOUT4
VIN4
ON4
ADD1
ADD2
SDA SCL
µC
ADD3
VDD
(1.62 to 3.6)
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS22993
SLVSCA3A – NOVEMBER 2013 – REVISED MARCH 2014
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features .................................................................
Applications ..........................................................
Description ............................................................
Simplified Schematic ............................................
Revision History ...................................................
Terminal Configuration and Functions ...............
Specifications ........................................................
1
1
1
1
2
3
4
7.1
7.2
7.3
7.4
7.5
7.6
7.7
4
5
5
5
6
8
9
Recommended Operating Conditions ......................
Absolute Maximum Ratings .....................................
Handling Ratings ......................................................
Thermal Information .................................................
Electrical Characteristics ..........................................
Switching Characteristics .........................................
Typical Characteristics .............................................
8
9
Parametric Measurement Information .............. 14
Detailed Description ........................................... 15
9.1 Block Diagram ........................................................ 15
9.2 Register Map .......................................................... 16
10 Application and Implementation ....................... 18
10.1 Application Information ........................................ 18
10.2 Typical Applications ............................................. 23
11 Layout ................................................................. 29
11.1 Board Layout ........................................................ 29
12 Device and Documentation Support ................ 31
12.1 Trademarks .......................................................... 31
12.2 Electrostatic Discharge Caution ........................... 31
12.3 Glossary ............................................................... 31
13 Mechanical, Packaging, and Orderable
Information .......................................................... 31
5 Revision History
Changes from Original (November 2013) to Revision A
•
2
Page
Revised document to full version. ......................................................................................................................................... 1
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SLVSCA3A – NOVEMBER 2013 – REVISED MARCH 2014
Device Comparison Table
TPS22993
RON TYPICAL AT 3.3 V (VBIAS = 7.2V)
15 mΩ
RISE TIME (1)
Programmable
(1)
ON DELAY
Programmable
QUICK OUTPUT DISCHARGE (1) (2)
Programmable
MAXIMUM OUTPUT CURRENT (per channel)
1.2 A
GPIO ENABLE
Active High
OPERATING TEMP
(1)
(2)
–40°C to 85°C
See Application Information section.
This feature discharges output of the switch to GND through an internal resistor, preventing the output from floating. See Application
information section.
6 Terminal Configuration and Functions
Bottom View
NC
10
16
ADD2 ADD2
ON2
9
17
SCL
ON3
8
18
ON4
7
ADD1
6
VIN4
VOUT4
13
12
11
NC
10
ON1
SCL
17
9
ON2
VDD
VDD
18
8
ON3
19
SDA
SDA
19
7
ON4
20
ADD3 ADD3
20
6
ADD1
20-RLW (3mm x 3mm x 0.75mm)
NC
1
2
3
4
5
VOUT1
NC
VIN1
1
VOUT2
VIN1
2
VIN2
VOUT1
3
VBIAS
4
14
16
NC
5
15
NC
ON1
NC
GND
VOUT3
15
VBIAS
VIN3
14
VIN3
GND
13
VIN2
VIN4
12
VOUT2
VOUT4
11
NC
VOUT3
Top View
20-RLW (3mm x 3mm x 0.75mm)
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SLVSCA3A – NOVEMBER 2013 – REVISED MARCH 2014
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Terminal Functions
Terminal
I/O
DESCRIPTION
NO.
NAME
NC
NO
CONNECT
-
Attached terminal to PCB. Leave the terminals floating or tie to GND.
1
VOUT2
O
Channel 2 output.
2
VIN2
I
Channel 2 input.
3
VBIAS
I
Bias voltage. Power supply to the device. Recommended voltage range for this terminal is 5.2V to 14V.
See Application Information section.
4
VIN1
I
Channel 1 input.
5
VOUT1
O
Channel 1 output.
6
ADD1
I
Device address terminal. Tie high or low. See Application Information section.
7
ON4
I
Active high channel 4 control input. Do not leave floating.
8
ON3
I
Active high channel 3 control input. Do not leave floating.
9
ON2
I
Active high channel 2 control input. Do not leave floating.
10
ON1
I
Active high channel 1 control input. Do not leave floating.
11
VOUT4
O
Channel 4 output.
12
VIN4
I
Channel 4 input.
13
GND
-
Device ground.
14
VIN3
I
Channel 3 input.
15
VOUT3
O
Channel 3 output.
16
ADD2
I
Device address terminal. Tie high or low. See Application Information section.
17
SCL
I
Serial clock input.
18
VDD
I
I2C device supply input. Tie this terminal to the I2C SCL/SDA pull-up voltage. See Application Information
section.
19
SDA
I/O
20
ADD3
I
Serial data input/output.
Device address terminal. Tie high or low. See Application Information section.
7 Specifications
7.1 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
VINx
Input voltage for VIN1, VIN2, VIN3, VIN4
1.0
3.6
V
VBIAS
Supply voltage for VBIAS
4.5
17.2
V
VDD
Supply voltage for VDD
1.62
3.6
V
VADDx
Input voltage for ADD1, ADD2, ADD3
0
3.6
V
VONx
Input voltage for ON1, ON2, ON3, ON4
0
5
V
VOUTx
Output voltage for VOUT1, VOUT2, VOUT3, VOUT4
0
VINx
CINx
Input capacitor on VIN1, VIN2, VIN3, VIN4
(1)
4
1
(1)
V
µF
Refer to application section.
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7.2 Absolute Maximum Ratings (1)
over operating free-air temperature range (unless otherwise noted)
VALUE
MIN
MAX
UNIT (2)
VINx
Input voltage for VIN1, VIN2, VIN3, VIN4
–0.3
4
V
VBIAS
Supply voltage for VBIAS
–0.3
20
V
VOUTx
Output voltage for VOUT1, VOUT2, VOUT3, VOUT4
–0.3
4
V
VDD, VSCL,
VSDA, VADDx
Input voltage for VDD, SCL, SDA, ADD1, ADD2, ADD3
–0.3
4
V
VONx
Input voltage for ON1, ON2, ON3, ON4
–0.3
6
V
IMAX
Maximum continuous switch current per channel
TA
Operating free-air temperature (3)
TJ
Maximum junction temperature
TLEAD
Maximum lead temperature (10-s soldering time)
(1)
(2)
(3)
1.2
A
–40
85
°C
125
125
°C
300
°C
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.
All voltage values are with respect to network ground terminal.
In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may
have to be derated. Maximum ambient temperature [TA(max)] is dependent on the maximum operating junction temperature [TJ(max)],
the maximum power dissipation of the device in the application [PD(max)], and the junction-to-ambient thermal resistance of the
part/package in the application (θJA), as given by the following equation: TA(max) = TJ(max) – (θJA × PD(max))
7.3 Handling Ratings
Tstg
Storage temperature
ESD (1)
(1)
(2)
(3)
Electrostatic discharge protection
MIN
MAX
UNIT
–65
150
°C
2000
V
500
V
Human-Body Model (HBM) (2)
Charged-Device Model (CDM)
(3)
Electrostatic discharge (ESD) to measure device sensitivity and immunity to damage caused by assembly line electrostatic discharges in
to the device.
Level listed above is the passing level per ANSI/ESDA/JEDEC JS-001. JEDEC document JEP155 states that 500V HBM allows safe
manufacturing with a standard ESD control process.
Level listed above is the passing level per EIA-JEDEC JESD22-C101. JEDEC document JEP157 states that 250V CDM allows safe
manufacturing with a standard ESD control process.
7.4 Thermal Information
TPS22993
THERMAL METRIC (1) (2)
RLW
(20 TERMINALS)
ΘJA
Junction-to-ambient thermal resistance
58
ΘJC(top)
Junction-to-case(top) thermal resistance
24
ΘJB
Junction-to-board thermal resistance
10
ΨJT
Junction-to-top characterization parameter
0.7
ΨJB
Junction-to-board characterization parameter
10
ΘJC(bottom)
Junction-to-case(bottom) thermal resistance
N/A
(1)
(2)
UNIT
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
For thermal estimates of this device based on PCB copper area, see the TI PCB Thermal Calculator.
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7.5 Electrical Characteristics
The specification applies over the operating ambient temperature –40°C ≤ TA ≤ 85°C (Full) (unless otherwise noted). Typical
values are for TA = 25°C. VBIAS = 7.2V (unless otherwise noted).
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX
VBIAS = 4.5V
14.8
26
VBIAS = 5.2V
14.9
26
VBIAS = 7.2V
16.2
28
16.6
30
VBIAS = 12.6V
16.7
30
VBIAS = 17.2V
16.8
30
VBIAS = 4.5V
7.7
15
VBIAS = 5.2V
7.8
15
VBIAS = 7.2V
8.5
16
8.7
16
VBIAS = 12.6V
8.8
16
VBIAS = 17.2V
8.9
16
VDD = 1.8V
0.6
2
Quiescent current for VDD
IOUT1,2,3,4 = 0A,
VIN1,2,3,4 = VON1,2,3,4 = 3.6V,
fSCL = 0Hz
1.2
2
Average dynamic current for
VDD during I2C
communication
IOUT1,2,3,4 = 0A,
VIN1,2,3,4 = VON1,2,3,4 = 3.6V,
fSCL = 1MHz
VDD = 1.8V
Average dynamic current for
VBIAS (all four channels)
during I2C communication
IOUT1,2,3,4 = 0A,
VIN1,2,3,4 = VON1,2,3,4 = 3.6V,
fSCL=1MHz
UNIT
POWER SUPPLIES CURRENTS AND LEAKAGES
Quiescent current for VBIAS
(all four channels)
IQ,
VBIAS
Quiescent current for VBIAS
(single channel)
IQ,
IOUT1,2,3,4 = 0 A,
VIN1,2,3,4 = 3.6 V,
VON1,2,3,4 = 3.6 V,
VDD = 0 V
VDD
IDYN, VDD
IOUT1,2,3,4 = 0A,
VIN1 = VON1 = 3.6V,
VIN2,3,4 = VON2,3,4 = 0V,
VDD = 0V
VBIAS = 10.8V
VBIAS = 10.8V
VDD = 3.6V
VDD = 3.6V
Full
Full
Full
IDYN, VBIAS
µA
35
µA
85
85
Full
85
VBIAS = 12.6V
85
VBIAS = 5.2V
75
µA
Average dynamic current for
VBIAS (single channel) during
I2C communication
IOUT1,2,3,4 = 0A,
VIN1 = VON1 = 3.6V,
VIN2,3,4 = VON2,3,4 = 0V,
fSCL=1MHz
VON1,2,3,4 = 0V, VOUT1,2,3,4 = 0V, VDD = 3.6V,
VBIAS = 17.2V
Full
5.7
13
µA
VON1,2,3,4 = 0V, VOUT1,2,3,4 = 0V,
VDD = 3.6V
Full
1.2
2
µA
VINx = 3.3V
0.009
4
VINx = 1.8V
0.006
3
0.006
3
ISD,
VBIAS
Shutdown current for VBIAS
(all four channels)
ISD,
VDD
Shutdown current for VDD
ISD,
VBIAS = 10.8V
µA
20
Full
VBIAS = 5.2V
VBIAS = 7.2V
µA
VBIAS = 7.2V
VBIAS = 10.8V
75
Full
75
VBIAS = 12.6V
µA
75
Shutdown current for VINx
VONx = 0V, VOUTx = 0V, VDD = 3.6V
0.006
2.5
IONx
Leakage current for ONx
VONx = 5V
Full
0.01
0.1
µA
IADDx
Leakage current for ADDx
VADDx = 3.6V
Full
0.01
0.2
µA
ISCL
Leakage current for SCL
VSCL = 3.6V
Full
0.01
0.2
µA
ISDA
Leakage current for SDA
VSDA = 3.6V
Full
0.01
0.2
µA
25°C
15
20
VINx
VINx = 1.5V
Full
VINx = 1.05V
µA
RESISTANCE CHARACTERISTICS
VIN = 3.3V
VIN = 2.5V
RON
On-state resistance
VBIAS = 7.2V, IOUT = –200mA
VIN = 1.8V
VIN = 1.5V
VIN = 1.05V
6
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Full
25°C
22
15
Full
25°C
22
15
Full
25°C
Full
20
22
15
Full
25°C
20
20
22
15
20
22
mΩ
mΩ
mΩ
mΩ
mΩ
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Electrical Characteristics (continued)
The specification applies over the operating ambient temperature –40°C ≤ TA ≤ 85°C (Full) (unless otherwise noted). Typical
values are for TA = 25°C. VBIAS = 7.2V (unless otherwise noted).
PARAMETER
TEST CONDITIONS
TA
VIN = 3.3V
VIN
RON
On-state resistance
VBIAS = 5.2V, IOUT = –200mA
= 2.5V
VIN = 1.8V
VIN = 1.5V
VIN = 1.05V
RPD
Output pulldown resistance
MIN
25°C
TYP
MAX
18
25
Full
28
25°C
16
Full
22
24
25°C
15
Full
20
23
25°C
15
Full
20
22
25°C
15
Full
20
22
VIN = 3.3V, VON = 0V, IOUT = 1mA, QOD[1:0] = 00
25°C
110
VIN = 3.3V, VON = 0V, IOUT = 1mA, QOD[1:0] = 01
25°C
483
VIN = 3.3V, VON = 0V, IOUT = 1mA, QOD[1:0] = 10
25°C
949
VIN = 3.3V, VON = 0V, IOUT = 1mA, QOD[1:0] = 11
UNIT
mΩ
mΩ
mΩ
mΩ
mΩ
Ω
No
QOD
THRESHOLD CHARACTERISTICS
VIH,
ADDx
High-level input voltage for
ADDx
Full
0.7×VDD
VDD
V
VIL,
ADDx
Low-level input voltage for
ADDx
Full
0
0.3×VDD
V
VIH,
ONx
High-level input voltage for
ONx
Full
1.05
5
V
VIL,
ONx
Low-level input voltage for
ONx
Full
0
0.4
V
VBIAS = 5.2V
VHYS, ONx
Hysteresis for ONx
VBIAS = 7.2V
VBIAS = 10.8V
130
130
Full
mV
130
VBIAS = 12.6V
130
I2C CHARACTERISTICS
fSCL
tSU,
tHD,
(1)
SDA
SDA
Clock frequency
(1)
Setup time for SDA
(1)
Hold time for SDA
Full
fSCL = 1MHz (fast mode plus)
50
Full
0
25°C
MHz
ns
ns
IOL,
SDA
SDA output low current
VIH,
SDA
High-level input voltage for
SDA
Full
0.7×VDD
VDD
V
VIH,
SCL
High-level input voltage for
SCL
Full
0.7×VDD
VDD
V
VIL,
SDA
Low-level input voltage for
SDA
Full
0
0.3×VDD
V
VIL,
SCL
Low-level input voltage for
SCL
Full
0
0.3×VDD
V
(1)
VOL,SDA = 0.4V
1
Full
8
mA
Parameter verified by design.
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7.6 Switching Characteristics
Values below are typical values at TA = 25°C. VBIAS = 7.2V (unless otherwise noted).
PARAMETER
tON
tOFF
tR
tF
tD
8
VOUTx turn-on time
VOUTx turn-off time
VOUTx rise time
VOUTx fall time
VOUTx ON delay time
VIN VOLTAGE
TEST CONDITION
VBIAS = 7.2V,
RL=10Ω, CL=0.1µF,
QOD[1:0] = 10,
ON-delay[6:5] = 00
3.3V
1.8V
1.5V
1.05V
Slew rate[4:2] = 000
11
11
11
11
Slew rate[4:2] = 001
247
181
167
146
Slew rate[4:2] = 010
416
302
279
243
Slew rate[4:2] = 011
761
549
505
438
Slew rate[4:2] = 100
848
1481
1066
980
VBIAS = 7.2V, RL=10Ω, CL=0.1µF, QOD[1:0] = 10, ON-delay[6:5] = 00
2
2
2
2
Slew rate[4:2] = 000
2
1.1
1
0.8
Slew rate[4:2] = 001
307
203
180
147
Slew rate[4:2] = 010
527
346
307
248
VBIAS = 7.2V, RL=10Ω, CL=0.1µF,
QOD[1:0] = 10, ON-delay[6:5] = 00
Slew rate[4:2] = 011
970
638
566
459
Slew rate[4:2] = 100
1898
1245
1105
888
2
2
2
2
ON delay[4:2] = 00
11
11
11
11
ON delay[4:2] = 01
102
104
105
106
ON delay[4:2] = 10
324
332
334
338
ON delay[4:2] = 11
923
946
953
965
VBIAS = 7.2V, RL=10Ω, CL=0.1µF, QOD[1:0] = 10, ON-delay[6:5] = 00
VBIAS = 7.2V, RL=10Ω, CL=0.1µF,
QOD[1:0] = 10, Slew rate[6:5] = 000
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UNIT
µs
µs
µs
µs
µs
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7.7 Typical Characteristics
1.6
1.6
-40°C
-40°C
25°C
1.4
25°C
1.4
85°C
1.2
1.2
1
1
ISD,VDD (µA)
IQ,VDD (µA)
85°C
0.8
0.8
0.6
0.6
0.4
0.4
0.2
0.2
0
0
1.5
2
2.5
3
3.5
1.5
4
2
2.5
3
3.5
4
VDD (V)
VDD (V)
C001
C005
Figure 1. IQ,VDD vs. VDD
Figure 2. ISD,VDD vs. VDD
25
14
-40°C
-40°C
25°C
25°C
85°C
85°C
12
IQ,VBIAS (µA)
IQ,VBIAS (µA)
20
15
10
8
10
6
5
4
4.5
6.5
8.5
10.5
12.5
14.5
16.5
4.5
6.5
8.5
10.5
VBIAS (V)
12.5
14.5
16.5
VBIAS (V)
C002
C003
Figure 3. IQ,VBIAS vs. VBIAS (all channels)
Figure 4. IQ,VBIAS vs. VBIAS (single channel)
8
0.35
7
0.3
-40°C
25°C
85°C
6
0.25
ISD,VIN (µA)
ISD,VBIAS (µA)
5
4
0.2
0.15
3
0.1
2
-40°C
1
0.05
25°C
85°C
0
0
4.5
6.5
8.5
10.5
12.5
14.5
1
16.5
1.5
2
2.5
3
3.5
VIN (V)
VBIAS (V)
C024
C004
Figure 6. ISD,VIN vs. VIN
Figure 5. ISD,VBIAS vs. VDD
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Typical Characteristics (continued)
60
20
VBIAS = 4.5V
18
VBIAS = 5.2V
50
VBIAS = 7.2V
16
VBIAS = 10.8V
14
VBIAS = 14V
RON (m
)
12
RON (m
)
VBIAS = 12.6V
40
10
VBIAS = 17.2V
30
8
20
6
4
-40°C
10
25°C
2
VBIAS = 7.2V, IOUT = -200mA
0
1
1.5
2
85°C
2.5
3
TA = 25C, IOUT = -200mA
0
1
3.5
1.5
2
2.5
3
3.5
VIN (V)
VIN (V)
C010
C009
Figure 8. RON vs. VIN vs. VBIAS (TA = 25°C)
Figure 7. RON vs. VIN (VBIAS = 7.2V)
3.5
3.5
VBIAS = 4.5V
VBIAS = 4.5V
VBIAS = 5.2V
VBIAS = 5.2V
VBIAS = 7.2V
VBIAS = 7.2V
VBIAS = 10.8V
VBIAS = 10.8V
VBIAS = 12.6V
VBIAS = 12.6V
VBIAS = 14V
VBIAS = 14V
VBIAS = 17.2V
VBIAS = 17.2V
3
3
2
2.5
2
1.5
1.5
1
VOUT (V)
VOUT (V)
2.5
1
0.5
0.5
TA = 25°C
0
0
TA = 25°C
0.4
0.8
1.2
1.6
2
2
0
1.6
1.2
VON (V)
0.8
0.4
0
VON (V)
C006
C007
Figure 9. Output voltage vs. VOUT rising
Figure 10. Output voltage vs. VOUT falling
0.14
QOD = 00
TA = 25°C
1400
QOD = 01
0.12
QOD = 10
1200
0.1
0.08
RPD (
)
VHYS, ONx (V)
1000
0.06
800
600
0.04
400
0.02
200
25°C
VIN = 3.3V
0
4.5
6.5
0
8.5
10.5
12.5
14.5
4.5
16.5
6.5
8.5
10.5
12.5
14.5
C023
C008
Figure 11. VHYS,
10
16.5
VBIAS (V)
VBIAS (V)
Figure 12. RPD vs. VBIAS
ONx vs. VBIAS
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Typical Characteristics (continued)
2.5
350
-40°C
-40°C
25°C
25°C
85°C
2
85°C
300
1.5
tR (µs)
tR (µs)
250
1
200
0.5
150
Slew rate [4:2] = 000, CIN = 1µF, CL = 0.1µF, RL = 10
0
1
1.5
2
2.5
3
Slew rate [4:2] = 001, CIN = 1µF, CL = 0.1µF, RL = 10
100
3.5
1
1.5
2
VIN (V)
2.5
3
3.5
VIN (V)
C015
C016
Figure 13. tR vs. VIN (Slew rate [4:2] = 000)
Figure 14. tR vs. VIN (Slew rate [4:2] = 001)
1000
600
-40°C
-40°C
25°C
25°C
900
85°C
85°C
500
800
400
tR (µs)
tR (µs)
700
600
300
500
200
400
Slew rate [4:2] -= 010, CIN = 1µF, CL = 0.1µF, RL = 10
100
1
1.5
2
2.5
3
Slew rate [4:2] = 011, CIN = 1µF, CL = 0.1µF, RL = 10
300
1
3.5
1.5
2
2.5
3
3.5
VIN (V)
VIN (V)
C018
C017
Figure 15. tR vs. VIN (Slew rate [4:2] = 010)
Figure 16. tR vs. VIN (Slew rate [4:2] = 011)
14
2000
-40°C
25°C
12
1800
85°C
10
1400
8
tR (µs)
tD (µs)
1600
1200
6
1000
4
800
2
-40°C
Slew rate [4:2] = 100, CIN = 1µF, CL = 0.1µF, RL = 10
600
1
1.5
2
2.5
3
0
4.5
3.5
25°C
ON delay [6:5] = 00, VIN = 3.6V, CIN = 1µF,
CL = 0.1µF, RL = 10
6.5
8.5
10.5
12.5
85°C
14.5
16.5
VBIAS (V)
VIN (V)
C011
C019
Figure 17. tR vs. VIN (Slew rate [4:2] = 100)
Figure 18. tD vs. VBIAS (ON delay [6:5] = 00)
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Typical Characteristics (continued)
102
320
100
310
98
300
tD (µs)
tD (µs)
96
94
290
280
92
270
-40°C
-40°C
90
88
4.5
6.5
8.5
10.5
12.5
260
25°C
ON delay [6:5] = 01, VIN = 3.6V, CIN = 1µF,
CL = 0.1µF, RL = 10
85°C
14.5
250
4.5
16.5
25°C
ON delay [6:5] = 10, VIN = 3.6V,
CIN = 1µF, CL = 0.1µF, RL = 10
6.5
8.5
85°C
10.5
12.5
14.5
16.5
VBIAS (V)
VBIAS (V)
C013
C012
Figure 19. tD vs. VBIAS (ON delay [6:5] = 01)
Figure 20. tD vs. VBIAS (ON delay [6:5] = 10)
900
-40°C
920
25°C
800
85°C
900
700
tON (µs)
tD (µs)
880
860
600
500
840
-40°C
820
400
25°C
ON delay [6:5] = 11, VIN = 3.6V,
CIN = 1µF, CL = 0.1µF, RL = 10
800
4.5
6.5
8.5
Slew rate [4:2] = 011, CIN = 1µF, CL = 0.1µF, RL = 10
85°C
300
10.5
12.5
14.5
1
16.5
1.5
2
2.5
3
3.5
VIN (V)
VBIAS (V)
C020
C014
Figure 21. tD vs. VBIAS (ON delay [6:5] = 11)
Figure 22. tON vs. VIN (VBIAS = 7.2V)
4
4
-40°C
-40°C
25°C
3.5
25°C
3.5
85°C
3
3
2.5
2.5
tOFF (µs)
tF (µs)
85°C
2
2
1.5
1.5
1
1
0.5
0.5
Slew rate [4:2] = 011, CIN = 1µF, CL = 0.1µF, RL = 10
0
Slew rate [4:2] = 011, CIN = 1µF, CL = 0.1µF, RL = 10
0
1
1.5
2
2.5
3
3.5
1
VIN (V)
1.5
2
2.5
3
3.5
VIN (V)
C021
Figure 23. tF vs. VIN (VBIAS = 7.2V)
12
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Figure 24. tOFF vs. VIN (VBIAS = 7.2V)
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Typical Characteristics (continued)
Figure 25. +Power up with different slew rate settings
Figure 26. Power up with different tD settings
Figure 28. Power up with default settings
Figure 27. Power down with different QOD settings
Figure 29. Channel 1 powered up via GPIO control, and
control is switched over to I2C control without any glitches
on VOUT.
Figure 30. Enabling channel 1 across two TPS22993 devices
with the SwitchALLTM command.
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8 Parametric Measurement Information
VINx
VOUTx
CIN = 1µF
ON
+
-
(A)
OFF
ONx
CL
RL
VBIAS
GND
TPS22993
GND
GND
Single channel shown for clarity.
TEST CIRCUIT
VONx
50%
50%
tOFF
tON
tF
tR
VOUTx
VOUTx
50%
90%
10%
10%
tD
90%
50%
10%
tON/tOFF WAVEFORMS
(A) Rise and fall times of the control signal is 100ns.
(B) All switching measurements are done using GPIO control only.
Figure 31. Test Circuit and tON/tOFF Waveforms
14
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9 Detailed Description
9.1 Block Diagram
Power supply
and bandgap
VBIAS
VIN1
Driver
VOUT1
PD_EN
ON1
ON2
ON3
VIN2
GPIO ON
Buffer
Driver
ON4
VOUT2
PD_EN
ADD1
ADD2
ADD3
Address
Buffers &
Level Shifters
I2C
Digital Control
VIN3
Driver
VDD
SCL
SDA
VOUT3
I2C
SCL/SDA
Buffers &
Level Shifters
PD_EN
VIN4
Driver
VOUT4
PD_EN
* PD_EN = Pulldown Enable
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9.2 Register Map
Configuration registers (default register values shown below)
Channel 1 configuration register (Address: 01h)
BIT
B7
DESCRIPTION
X
DEFAULT
X
B6
B5
B4
ON-DELAY
0
B3
B2
SLEW RATE
0
0
1
1
B5
B4
B3
B2
B1
B0
QUICK OUTPUT
DISCHARGE
1
0
Channel 2 configuration register (Address: 02h)
BIT
B7
DESCRIPTION
X
DEFAULT
X
B6
ON-DELAY
0
SLEW RATE
0
0
1
1
B5
B4
B3
B2
B1
B0
QUICK OUTPUT
DISCHARGE
1
0
Channel 3 configuration register (Address: 03h)
BIT
B7
DESCRIPTION
X
DEFAULT
X
B6
ON-DELAY
0
SLEW RATE
0
0
1
1
B5
B4
B3
B2
B1
B0
QUICK OUTPUT
DISCHARGE
1
0
Channel 4 configuration register (Address: 04h)
BIT
B7
DESCRIPTION
X
DEFAULT
X
B6
ON-DELAY
0
SLEW RATE
0
0
B1
B0
QUICK OUTPUT
DISCHARGE
1
0
1
1
B3
ENABLE CH
4
0
B2
ENABLE CH
3
0
B1
ENABLE CH
2
0
B0
ENABLE CH
1
0
B3
ENABLE CH
4
0
B2
ENABLE CH
3
0
B1
ENABLE CH
2
0
B0
ENABLE CH
1
0
B3
ENABLE CH
4
0
B2
ENABLE CH
3
0
B1
ENABLE CH
2
0
B0
ENABLE CH
1
0
B3
ENABLE CH
4
0
B2
ENABLE CH
3
0
B1
ENABLE CH
2
0
B0
ENABLE CH
1
0
Control register (default register values shown below)
Control register (Address: 05h)
BIT
DESCRIPTION
DEFAULT
B7
GPIO/I2C ch
4
0
B6
GPIO/I2C ch
3
0
B5
GPIO/I2C ch
2
0
B4
GPIO/I2C ch
1
0
Mode registers (default register values shown below)
Mode1 (Address: 06h)
BIT
B7
B6
B5
B4
DESCRIPTION
X
X
X
X
DEFAULT
X
X
X
X
BIT
B7
B6
B5
B4
DESCRIPTION
X
X
X
X
DEFAULT
X
X
X
X
BIT
B7
B6
B5
B4
DESCRIPTION
X
X
X
X
DEFAULT
X
X
X
X
Mode2 (Address: 07h)
Mode3 (Address: 08h)
16
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Mode4 (Address: 09h)
BIT
B7
B6
B5
B4
DESCRIPTION
X
X
X
X
DEFAULT
X
X
X
X
BIT
B7
B6
B5
B4
DESCRIPTION
X
X
X
X
DEFAULT
X
X
X
X
BIT
B7
B6
B5
B4
DESCRIPTION
X
X
X
X
DEFAULT
X
X
X
X
BIT
B7
B6
B5
B4
DESCRIPTION
X
X
X
X
DEFAULT
X
X
X
X
BIT
B7
B6
B5
B4
DESCRIPTION
X
X
X
X
DEFAULT
X
X
X
X
BIT
B7
B6
B5
B4
DESCRIPTION
X
X
X
X
DEFAULT
X
X
X
X
BIT
B7
B6
B5
B4
DESCRIPTION
X
X
X
X
DEFAULT
X
X
X
X
BIT
B7
B6
B5
B4
DESCRIPTION
X
X
X
X
DEFAULT
X
X
X
X
BIT
B7
B6
B5
B4
DESCRIPTION
X
X
X
X
DEFAULT
X
X
X
X
B3
ENABLE CH
4
0
B2
ENABLE CH
3
0
B1
ENABLE CH
2
0
B0
ENABLE CH
1
0
B3
ENABLE CH
4
0
B2
ENABLE CH
3
0
B1
ENABLE CH
2
0
B0
ENABLE CH
1
0
B3
ENABLE CH
4
0
B2
ENABLE CH
3
0
B1
ENABLE CH
2
0
B0
ENABLE CH
1
0
B3
ENABLE CH
4
0
B2
ENABLE CH
3
0
B1
ENABLE CH
2
0
B0
ENABLE CH
1
0
B3
ENABLE CH
4
0
B2
ENABLE CH
3
0
B1
ENABLE CH
2
0
B0
ENABLE CH
1
0
B3
ENABLE CH
4
0
B2
ENABLE CH
3
0
B1
ENABLE CH
2
0
B0
ENABLE CH
1
0
B3
ENABLE CH
4
0
B2
ENABLE CH
3
0
B1
ENABLE CH
2
0
B0
ENABLE CH
1
0
B3
ENABLE CH
4
0
B2
ENABLE CH
3
0
B1
ENABLE CH
2
0
B0
ENABLE CH
1
0
B3
ENABLE CH
4
0
B2
ENABLE CH
3
0
B1
ENABLE CH
2
0
B0
ENABLE CH
1
0
Mode5 (Address: 0Ah)
Mode6 (Address: 0Bh)
Mode7 (Address: 0Ch)
Mode8 (Address: 0Dh)
Mode9 (Address: 0Eh)
Mode10 (Address: 0Fh)
Mode11 (Address: 10h)
Mode12 (Address: 11h)
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10 Application and Implementation
10.1 Application Information
10.1.1 I2C Control
When power is applied to VBIAS, the device comes up in its default mode of GPIO operation where the channel
outputs can be controlled solely via the ON terminals. At any time, if SDA and SCL are present and valid, the
device can be configured to be controlled via I2C (if in GPIO control) or GPIO (if in I2C control).
The control register (address 05h) can be configured for GPIO or I2C enable on a per channel basis.
10.1.1.1 Operating Frequency
The TPS22993 is designed to be compatible with fast-mode plus and operate up to 1MHz clock frequency for
bus communication. The device is also compatible with standard-mode (100kHz) and fast-mode (400kHz). This
device can reside on the same bus as high-speed mode (3.4MHz) devices, but the device is not designed to
respond to I2C commands for frequencies greater than 1MHz. See table below for characteristics of the fastmode plus, fast-mode, and standard-mode bus speeds.
Table 1. I2C Interface Timing Requirements (1)
STANDARD
MODE
I2C BUS
PARAMETER
FAST MODE
PLUS (FM+)
I2C BUS
FAST MODE
I2C BUS
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
fscl
I2C clock frequency
0
100
0
400
0
1000
tsch
I2C clock high time
4
2
tscl
I C clock low time
tsp
I2C spike time
tsds
I2C serial data setup time
4.7
250
I C serial data hold time
ticr
I2C input rise time
tbuf
I2C bus free time between Stop and Start
100
0
2
20
50
50
0
1000
μs
0.5
50
ns
ns
0
300
kHz
μs
0.26
1.3
50
2
tsdh
0.6
ns
120
ns
4.7
1.3
0.5
μs
tsts
I C Start or repeater Start condition setup time
4.7
0.6
0.26
μs
tsth
I2C Start or repeater Start condition hold time
4
0.6
0.26
μs
tsps
I2C Stop condition setup time
4
0.6
0.26
tvd(data) Valid data time; SCL low to SDA output valid
tvd(ack)
(1)
18
Valid data time of ACK condition; ACK signal from SCL
low to SDA (out) low
μs
3.45
0.3
0.9
0.45
μs
3.45
0.3
0.9
0.45
μs
over operating free-air temperature range (unless otherwise noted)
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10.1.1.2 SDA/SCL Terminal Configuration
The SDA and SCL terminals of the device operate use an open-drain configuration, and therefore, need pull up
resistors to communicate on the I2C bus. The graph below shows recommended values for max pullup resistors
(RP) and bus capacitances (Cb) to ensure proper bus communications. The SDA and SCL terminals should be
pulled up to VDD through an appropriately sized RP based on the graphs below.
10.1.1.3 Address (ADDx) Terminal Configuration
The TPS22993 can be configured with an unique I2C slave addresses by using the ADDx terminals. There are 3
ADDx terminals that can be tied high to VDD or low to GND (independent of each other) to get up to 7 different
slave addresses. The ADDx terminals should be tied to GND if the I2C functionality of the device is not to be
used. External pull-up resistors for the ADDx are optional as the ADDx inputs are high impedance. The following
table shows the ADDx terminal tie-offs with their associated slave addresses (assuming an eight bit word, where
the LSB is the read/write bit and the device address bits are the 7 MSB bits) :
Hex Address
ADD3
ADD2
ADD1
E0/E1
GND
GND
GND
E2/E3
GND
GND
VDD
E4/E5
GND
VDD
GND
E6/E7
GND
VDD
VDD
E8/E9
VDD
GND
GND
EA/EB
VDD
GND
VDD
EC/ED
VDD
VDD
GND
EE
Invalid unique device address.
This address is the SwitchALLTM address.
10.1.2 GPIO Control
There are four ON terminals to enable/disable the four channels. Each ON terminal controls the state of the
switch by default upon power up. Asserting ON high enables the switch. ON is active high and has a low
threshold, making it capable of interfacing with low-voltage signals. The ON terminal is compatible with standard
GPIO logic threshold. It can be used with any microcontroller with 1.2V or higher voltage GPIO.
10.1.3 On-Delay Control
Using the I2C interface, the configuration register for each channel can be set for different ON delays for power
sequencing. The options for delay are as follows:
00
01
10
11
=
=
=
=
11µs delay (default register value)
105µs delay
330µs delay
950µs delay
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10.1.4 Slew Rate Control
Using the I2C interface, the configuration register for each channel can be set for different slew rates for inrush
current control and power sequencing. The options for slew rate are as follows:
000
001
010
011
100
101
110
111
=
=
=
=
=
=
=
=
1µs/V
150µs/V
250µs/V
460µs/V (default register value)
890µs/V
invalid slew rate
invalid slew rate
reserved
10.1.5 Quick Output Discharge (QOD) Control
Using the I2C interface, the configuration register for each channel can be set for different output discharge
resistors. The options for QOD are as follows:
00
01
10
11
=
=
=
=
110Ω
490Ω
951Ω (default register value)
No QOD (high impedance)
10.1.6 Mode Registers
Using the I2C interface, the mode registers can be programmed to the desired on/off status for each channel.
The contents of these registers are copied over to the control registers when a SwitchALL™ command is issued,
allowing all channels of the device to transition to their desired output states synchronously. See the I2C Protocol
section and the Application Scenario section for more information on how to use the mode registers in
conjunction with the SwitchALLTM command.
10.1.7 SwitchALL™ Command
I2C controlled channels can respond to a common slave address. This feature allows multiple load switches on
the same I2C bus to respond simultaneously. The SwitchALL™ address is EEh. During a SwitchALL™
command, the lower four bits (bits 0 through 3) of the mode register is copied to the lower four bits (bits 0
through 3) of the control register. The mode register to be invoked is referenced in the body of the SwitchALL™
command. The structure of the SwitchALL™ command is as follows (as shown in Figure 32):
. See the I2C Protocol section and the Application Scenario
section for more information on how to use the SwitchALLTM command in conjunction with the mode registers.
SCL
SwitchALLTM Address
SDA ST 1
1
1
0
1
Start
1
1
Mode Register Address
0
A D7 D6 D5 D4 D3 D2 D1 D0 A SP
W/R
Ack. from slave
Ack
from Stop
slave
Figure 32. Composition of SwitchALL™ Command
10.1.8 VDD Supply For I2C Operation
The SDA and SCL terminals of the device must be pulled up to the VDD voltage of the device for proper I2C bus
communication.
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10.1.9 Input Capacitor (Optional)
To limit the voltage drop on the input supply caused by transient in-rush currents when the switch turns on into a
discharged load capacitor or short-circuit, a capacitor needs to be placed between VIN and GND. A 1-µF ceramic
capacitor, CIN, placed close to the terminals, is usually sufficient. Higher values of CIN can be used to further
reduce the voltage drop during high-current application. When switching heavy loads, it is recommended to have
an input capacitor about 10 times higher than the output capacitor to avoid excessive voltage drop. For the
fastest slew rate setting of the device, a CIN to CL ratio of at least 100 to 1 is recommended to avoid excessive
voltage drop.
10.1.10 Output Capacitor (Optional)
Due to the integrated body diode of the NMOS switch, a CIN greater than CL is highly recommended. A CL
greater than CIN can cause VOUT to exceed VIN when the system supply is removed. This could result in current
flow through the body diode from VOUT to VIN. A CIN to CL ratio of at least 10 to 1 is recommended for minimizing
VIN dip caused by inrush currents during startup. For the fastest slew rate setting of the device, a CIN to CL ratio
of at least 100 to 1 is recommended to minimize VIN dip caused by inrush currents during startup.
10.1.11 I2C Protocol
The following section will cover the standard I2C protocol used in the TPS22993. In the I2C protocol, the following
basic blocks are present in every command (except for the SwitchALLTM command):
• Start/stop bit – marks the beginning and end of each command.
• Slave address – the unique address of the slave device.
• Sub address – this includes the register address and the auto-increment bit.
• Data byte – data being written to the register. Eight bits must always be transferred even if a single bit is
being written or read.
• Auto-increment bit – setting this bit to ‘1’ turns on the auto-increment functionality; setting this bit to ‘0’ turns
off the auto-increment functionality.
• Write/read bit – this bit signifies if the command being sent will result in reading from a register or writing to a
register. Setting this bit to ‘0’ signifies a write, and setting this bit to ‘1’ signifies a read.
• Acknowledge bit – this bit signifies if the master or slave has received the preceding data byte.
10.1.11.1
Start and Stop Bit
2
In the I C protocol, all commands contain a START bit and a STOP bit. A START bit, defined by high to low
transition on the SDA line while SCL is high, marks the beginning of a command. A STOP bit, defined by low to
high transition on the SDA line while SCL is high, marks the end of a command. The START and STOP bits are
generated by the master device on the I2C bus. The START bit indicates to other devices that the bus is busy,
and some time after the STOP bit the bus is assumed to be free.
10.1.11.2
Auto-increment Bit
The auto-increment feature in the I2C protocol allows users to read from and write to consecutive registers in
fewer clock cycles. Since the register addresses are consecutive, this eliminates the need to resend the register
address. The I2C core of the device automatically increments the register address pointer by one when the autoincrement bit is set to ‘1’. When this bit is set to ‘0’, the auto-increment functionality is disabled.
10.1.11.3
Write Command
During the write command, the write/read bit is set to ‘0’, signifying that the register in question will be written to.
Figure 33 the composition of the write protocol to a single register:
SCL
Slave Address
SDA
ST A6 A5 A4 A3 A2 A1 A0 0
Start
Sub Address
A
0
0
0
0
0
0
Data Byte
0
W/R
Ack. from slave
Register Address N
Auto-Inc.
0
Data Byte
A D7 D6 D5 D4 D3 D2 D1 D0 A D7 D6 D5 D4 D3 D2 D1 D0 A SP
Ack
from
slave
Data to Register N
Ack
from
slave
Data to Register N
Ack Stop
from
slave
Figure 33. Data Write to a Single Register
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Number of clock cycles for single register write: 29
If multiple consecutive registers must be written to, a short-hand version of the write command can be used.
Using the auto-increment functionality of I2C, the device will increment the register address after each byte.
Figure 34 shows the composition of the write protocol to multiple consecutive registers:
SCL
Slave Address
SDA
Sub Address
ST A6 A5 A4 A3 A2 A1 A0 0
Start
A
1
0
0
0
0
Data Byte
0
0
0
W/R
Ack. from slave
Register Address N
Auto-Inc.
Data Byte
A D7 D6 D5 D4 D3 D2 D1 D0 A D7 D6 D5 D4 D3 D2 D1 D0 A
Ack
from
slave
Data to Register N
Ack
from
slave
Data to Register N+1
Ack
from
slave
Figure 34. Data Write to Consecutive Registers
Number of clock cycles for consecutive register write: 20 + (Number of registers) x 9
The write command is always ended with a STOP bit after the desired registers have been written to. If multiple
non-consecutive registers must be written to, then the format in Figure 33 must be followed.
10.1.11.4
Read Command
During the read command, the write/read bit is set to ‘1’, signifying that the register in question will be read from.
However, a read protocol includes a “dummy” write sequence to ensure that the memory pointer in the device is
pointing to the correct register that will be read. Failure to precede the read command with a write command may
result in a read from a random register. Figure 35 shows the composition of the read protocol to a single register:
SCL
Slave Address
SDA
ST A6 A5 A4 A3 A2 A1 A0 0
Start
Sub Address
A
0
0
0
W/R
Ack. from slave
Auto-Inc.
0
0
0
Slave Address
0
0
Data Byte
A RS A6 A5 A4 A3 A2 A1 A0 1
A D7 D6 D5 D4 D3 D2 D1 D0 NA SP
Ack Re-Start
W/R
Register Address from
Ack. from slave
slave
Continued
Data from Register N
Stop
No Ack. from master (message ends)
Figure 35. Data Read to a Single Register
Number of clock cycles for single register read: 39
If multiple registers must be read from, a short-hand version of the read command can be used. Using the autoincrement functionality of I2C, the device will increment the register address after each byte. Figure 36 shows the
composition of the read protocol to multiple consecutive registers:
SCL
Slave Address
SDA
ST A6 A5 A4 A3 A2 A1 A0 0
Start
Sub Address
A
1
0
W/R
Ack. from slave
Auto-Inc.
0
0
0
0
Slave Address
0
0
A RS A6 A5 A4 A3 A2 A1 A0 1
Data Byte
A D7 D6 D5 D4 D3 D2 D1 D0
Ack Re-Start
W/R
Register Address from
Ack. from slave
slave
Continued
Data Byte
Data from Register N
Data Byte
A D7 D6 D5 D4 D3 D2 D1 D0 A D7 D6 D5 D4 D3 D2 D1 D0 NA SP
Ack. from master
Data from Register N+1
Ack. from master
Data from Register N+2
Stop
No Ack. from master (Message ends)
Figure 36. Data Read to Consecutive Registers
Number of clock cycles for consecutive register write: 30 + (Number of registers) x 9
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The read command is always ended with a STOP bit after the desired registers have been read from. If multiple
non-consecutive registers must be read from, then the format in Figure 35 must be followed.
10.1.11.5
SwitchALLTM Command
The SwitchALLTM command allows multiple devices in the same I2C bus to respond synchronously to the same
command from the master. Every TPS22993 device has a shared address which allows for multiple devices to
respond or execute a pre-determined action with a single command. Figure 37 shows the composition of the
SwitchALLTM command:
SCL
SwitchALLTM Address
SDA ST 1
1
1
0
1
Start
1
1
Mode Register Address
0
A D7 D6 D5 D4 D3 D2 D1 D0 A SP
W/R
Ack. from slave
Ack
from Stop
slave
Figure 37. SwitchALLTM Command Structure
Number of clock cycles for a SwitchALLTM command: 20
10.2 Typical Applications
This section will cover applications of I2C in the TPS22993. Registers discussed here are specific to the
TPS22993.
10.2.1 Switch from GPIO Control to I2C Control (and vice versa)
The TPS22993 can be switched from GPIO control to I2C (and vice versa) mode by writing to the control register
of the device. Each device has a single control register and is located at register address 05h. The register’s
composition is as follows:
Control register (Address: 05h)
BIT
DESCRIPTION
DEFAULT
B7
B6
B5
B4
B3
GPIO/I2C CH GPIO/I2C CH GPIO/I2C CH GPIO/I2C CH ENABLE CH
4
3
2
1
4
0
0
0
0
0
B2
ENABLE CH
3
0
B1
ENABLE CH
2
0
B0
ENABLE CH
1
0
Figure 38. Control Register Composition
The higher four bits of the control register dictates if the device is in GPIO control (bit set to ‘0’) or I2C control (bit
set to ‘1’). The transition from GPIO control to I2C control can be made with a single write command to the
control register. See Figure 33 for the composition of a single write command. It is recommended that the
channel of interest is transitioned from GPIO control to I2C control with the first write command and followed by a
second write command to enable the channel via I2C control. This will ensure a smooth transition from GPIO
control to I2C control.
10.2.2 Configuration of Configuration Registers
The TPS22993 contains four configuration registers (one for each channel) and are located at register addresses
01h through 04h. The register’s composition is as follows (single channel shown for clarity):
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Channel 1 configuration register (Address: 01h)
BIT
DESCRIPTION
B7
X
B6
DEFAULT
X
0
B5
B4
B3
SLEW RATE
B2
0
0
1
0
ON-DELAY
B1
B0
QUICK OUTPUT
DISCHARGE
1
0
Figure 39. Configuration Register Composition
10.2.2.1
Single Register Configuration
A single configuration register can be written to using the write command sequence shown in Figure 33.
Multiple register writes to non-consecutive registers is treated as multiple single register writes and follows the
same write command as that of a single register write as shown in Figure 33.
10.2.2.2
Multi-register Configuration (Consecutive Registers)
Multiple consecutive configuration registers can be written to using the write command sequence shown in
Figure 34.
10.2.3 Configuration of Mode Registers
The TPS22993 contains twelve mode registers located at register addresses 06h through 11h. These mode
registers allow the user to turn-on or turn-off multiple channels in a single TPS22993 or multiple channels
spanning multiple TPS22993 devices with a single SwitchALLTM command.
For example, an application may have multiple power states (e.g. sleep, active, idle, etc.) as shown in Figure 40.
SwitchALLTM command with Mode2
register
TM
SwitchALL command with Mode1
register
Sleep
Active
S
co witch
Mo mma ALL TM
de nd
2r
eg with
is t
er
TM
S
co witch
Mo mma ALL TM
de nd
3r
eg with
ist
er
L
AL ith
itch d w er
Sw man gist
re
m
co de1
Mo
TM
L
AL ith
itch d w er
Sw man gist
re
m
co de3
Mo
Idle
Figure 40. Application Example of Power States
In each of the different power states, different combinations of channels may be on or off. Each power state may
be associated with a single mode register (Mode1, Mode2, etc.) across multiple TPS22993 as shown in Table 2.
For example, with 7 quad-channel devices, up to 28 rails can be enabled/disabled with a single SwitchALLTM
command.
Table 2. Application Example of State of Each Channel in Multiple TPS22993 in Different Power States
Load Switch #1
Load Switch #2
Load Switch #N
Mode
Register
Power
State
Ch. 1
Ch. 2
Ch. 3
Ch. 4
Ch. 1
Ch. 2
Ch. 3
Ch. 4
Ch. 1
Ch. 2
Ch. 3
Ch. 4
Mode1
Sleep
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Mode2
Active
On
On
On
On
On
Off
On
Off
On
Off
On
Off
Mode3
Idle
On
Off
On
Off
On
On
On
On
On
On
On
On
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The contents of the lower four bits of the mode register is copied into the lower four bits of the control register
during an SwitchALLTM command. The address of the mode register to be copied is specified in the SwitchALLTM
command (see Figure 37 for the structure of the SwitchALLTM command). By executing a SwitchALLTM
command, the application will apply the different on/off combinations for the various power states with a single
command rather than having to turn on/off each channel individually by re-configuring the control register. This
reduces the latency and allows the application to control multiple channels synchronously. The example above
shows the application using three mode registers, but the TPS22993 contains twelve mode registers, allowing for
up to twelve power states.
The mode register’s composition is as follows (single mode register shown for clarity):
Mode1 (Address: 06h)
BIT
DESCRIPTION
B7
X
B6
X
B5
X
B4
X
DEFAULT
X
X
X
X
B3
ENABLE
CH 4
0
B2
ENABLE
CH 3
0
B1
ENABLE
CH 2
0
B0
ENABLE
CH 1
0
Figure 41. Mode Register Composition
The lower four bits of the mode registers are copied into the lower four bits of the control register during an allcall command.
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10.2.4 Turn-on/Turn-off of Channels
By default upon power up VBIAS, all the channels of the TPS22993 are controlled via the ONx terminals. Using
the I2C interface, each channel be controlled via I2C control as well. The channels of the TPS22993 can also be
switched on or off by writing to the control register of the device. Each device has a single control register and is
located at register address 05h. The register’s composition is as follows:
Control Register (Address: 05h)
BIT
DESCRIPTION
DEFAULT
B7
B6
B5
B4
B3
GPIO/I2C CH GPIO/I2C CH GPIO/I2C CH GPIO/I2C CH ENABLE CH
4
3
2
1
4
0
0
0
0
0
B2
ENABLE CH
3
0
B1
ENABLE CH
2
0
B0
ENABLE CH
1
0
Figure 42. Control Register Composition
The lower four bits of the control register dictate if the channels of the device are off (bit set to ‘0’) or on (bit set
to ‘1’) during I2C control. The transition from off to on can be made with a single write command to the control
register. See Figure 33 for the composition of a single write command.
10.2.5 Tying Multiple Channels in Parallel
Two or more channels of the device can be tied in parallel for applications that require lower RON and/or more
continous current. Tying two channels in parallel will result in half of the RON and two times the IMAX capability.
Tying three channels in parallel will result in one-third of the RON and three times the IMAX capability. Tying four
channels in parallel will result in one-fourth of the RON and four times the IMAX capability. For the channels that
are tied in parallel, it is recommended that the ONx terminals be tied together for synchronous control of the
channels when in GPIO control. In I2C control, all four channels can be enabaled or disabled synchronously by
writing to the control register of the device. Figure 43 shows an application example of tying all four channels in
parallel.
VBIAS
(4.5V to 17.2V)
VIN1
PMIC or
PMU
VOUT1
ON1
CL
VIN2
RL
VOUT2
ON2
VIN3
TPS22993
VOUT3
ON3
VOUT4
VIN4
ON4
ADD1
GPIO >>
ADD2
SDA SCL
µC
ADD3
VDD
(1.62 to 3.6)
Figure 43. Parallel Channels
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10.2.6 Cold Boot Programming of all Registers
Since the TPS22993 has a digital core with volatile memory, upon power cycle of the VBIAS terminal, the
registers will revert back to their default values (see register map for default values). Therefore, the application
must reprogram the configuration registers, control register, and mode registers if non-default values are desired.
The TPS22993 contains 17 programmable registers (4 configuration registers, 1 control register, 12 mode
registers) in total.
During cold boot when the microcontroller and the I2C bus is not yet up and running, the channels of the
TPS22993 can still be enabled via GPIO control. One method to achieve this is to tie the ONx terminal to the
respective VINx terminal for the channels that need to turn on by default during cold boot. With this method,
when VINx is applied to the TPS22993, the channel will be enabled as well. Once the I2C bus is active, the
channel can be switched over to I2C control to be disabled. See Figure 44 for an example of how the ONx
terminals can be tied to VINx for default enable during cold boot.
VBIAS
(4.5V to 17.2V)
VIN1
VOUT1
ON1
VIN2
CL
RL
CL
RL
CL
RL
CL
RL
VOUT2
ON2
PMIC or
PMU
VIN3
TPS22993
VOUT3
ON3
VOUT4
VIN4
ON4
ADD1
ADD2
SDA SCL
µC
ADD3
VDD
(1.62 to 3.6)
Figure 44. Cold Boot Programming
It is also possible to power sequence the channels of the device during a cold boot when there is no I2C bus
present for control. One method to accomplish this it to tie the VOUT of one channel to the ON terminal of the
next channel in the sequence. For example, if the desired power up sequence is VOUT3, VOUT1, VOUT2, and
VOUT4 (in that order), then the device can be configured for GPIO control as shown in Figure 45. The device will
power up with default slew rate, ON-delay, and QOD values as specified in the register map.
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VBIAS
(4.5V to 17.2V)
VIN1
VOUT1
ON1
VIN2
CL
RL
CL
RL
CL
RL
CL
RL
VOUT2
ON2
PMIC or
PMU
VIN3
TPS22993
VOUT3
ON3
VOUT4
VIN4
ON4
ADD1
ADD2
SDA SCL
µC
ADD3
VDD
(1.62 to 3.6)
Figure 45. Power Sequencing Without I2C
10.2.7 Reading From the Registers
Reading any register from the TPS22993 follows the same standard I2C read protocol as outlined in the I2C
Protocol section of this datasheet.
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11 Layout
11.1 Board Layout
For best performance, all traces should be as short as possible. To be most effective, the input and output
capacitors should be placed close to the device to minimize the effects that parasitic trace inductances may have
on normal operation. Using wide traces for VIN, VOUT, and GND helps minimize the parasitic electrical effects
along with minimizing the case to ambient thermal impedance.
The maximum IC junction temperature should be restricted to 125°C under normal operating conditions. To
calculate the maximum allowable power dissipation, PD(max) for a given output current and ambient temperature,
use the following equation:
PD(max) =
TJ(max) - TA
QJA
(1)
Where:
PD(max) = maximum allowable power dissipation
TJ(max) = maximum allowable junction temperature (125°C for the TPS22993)
TA = ambient temperature of the device
ΘJA = junction to air thermal impedance. See Thermal Information section. This parameter is highly
dependent upon board layout.
The figure below shows an example of a layout.
Figure 46. Top View of the TPS22993 EVM
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Board Layout (continued)
Figure 47. Bottom View of the TPS22993 EVM.
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12 Device and Documentation Support
12.1 Trademarks
SwitchALL is a trademark of Texas Instruments.
Ultrabook is a trademark of Intel.
12.2 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.3 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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4-Feb-2021
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS22993RLWR
ACTIVE
WQFN-HR
RLW
20
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
22993P
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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