TPS23785B
www.ti.com
SLUSB90A – DECEMBER 2012 – REVISED DECEMBER 2012
High-Power, High-Efficiency PoE PD and DC-to-DC Controller
FEATURES
DESCRIPTION
•
•
The TPS23785B is a combined Power over Ethernet
(PoE) powered device (PD) interface and currentmode DC-to-DC controller optimized specifically for
non-isolated converters. The PoE interface supports
the IEEE 802.3at standard.
1
Powers up to 30-W (Input) PDs
DC-to-DC Control Optimized for Non-Isolated
Converters
Supports High-Efficiency Topologies
Complete PoE Interface
Enhanced Classification per IEEE 802.3at with
Status Flag
Adapter ORing Support
Robust 100-V, 0.5-Ω Hotswap MOSFET
–40°C to 125°C Junction Temperature Range
Industry Standard PowerPAD™ TSSOP-24
2
•
•
•
•
•
•
•
The TPS23785B supports a number of input voltage
ORing options including highest voltage, external
adapter preference, and PoE preference. These
features allow the designer to determine which power
source will carry the load under all conditions.
The PoE interface features the two-event, physicallayer classification necessary for compatibility with
high-power midspan power sourcing equipment
(PSE) per IEEE 802.3at. The detection signature pin
can also be used to force power from the PoE source
off. Classification can be programmed to any of the
defined types with a single resistor.
APPLICATIONS
•
•
•
•
•
IEEE 802.3at Compliant Devices
Video and VoIP Telephones
RFID Readers
Surveillance Cameras
Wireless Access Points
From Ethernet
Pairs 1,2
Typical Application Diagram
T1
COUT
DVC1
RVC
M2
CIZ
RCS
CVC
CVB
RCTL
DT
RDT
BLNK
GATE
CS
GAT2
TLV431
RFBU
M1
RFBL
VDD1
VDD
RT2P
TPS23785B
RBLNK
RFRS
RAPD1
RAPD2
Adapter
DA
T2P
VOUT
CIN
VC
VB
RTN
COM
ARTN
DEN
NC
CLS
PAD
VSS
APD
CTL
FRS
RCLS
From Ethernet
Pairs 3,4
0.1uF
58V
RDEN
Type 2 PSE
Indicator
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2012, Texas Instruments Incorporated
TPS23785B
SLUSB90A – DECEMBER 2012 – REVISED DECEMBER 2012
www.ti.com
DESCRIPTION (CONT.)
The DC-to-DC controller features two complementary gate drivers with programmable dead time. This simplifies
design for highly-efficient flyback topologies utilizing secondary synchronous rectification. The second gate driver
may be disabled if desired for single MOSFET topologies. The controller also features internal softstart, bootstrap
startup source, current-mode compensation, and a 78% maximum duty cycle. A programmable and
synchronizable oscillator allows design optimization for efficiency and eases use of the controller to upgrade
existing power supply designs. Accurate programmable blanking, with a default period, simplifies the usual
current-sense filter design trade-offs.
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
PRODUCT INFORMATION
DUTY CYCLE
POE UVLO
ON / HYST.
(V)
CONVERTER UVLO
ON / HYST.
(V)
PACKAGE
MARKING
0–78%
35 / 4.5
15 / 6.5
TSSOP-24 PowerPAD™
TPS23785B
TPS23785BPWP
(1)
(1)
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or consult your
TI salesperson.
ABSOLUTE MAXIMUM RATINGS (1)
(2)
Voltage with respect to VSS unless otherwise noted. Over recommended operating junction temperature range.
VALUE
Input voltage range
ARTN (2), COM (2), DEN, RTN (3), VDD, VDD1
–0.3 to 100
CLS (4)
-0.3 to 6.5
[APD, BLNK (4), CTL, DT (4), FRS (4), VB
COM]
Voltage range
Sinking current
(4)
] to [ARTN,
–0.3 to 6.5
[P1, P2 (4)] to [ARTN,COM]
–0.3 to 6.5
CS to [ARTN,COM]
–0.3 to VB
[ARTN, COM] to RTN
T2P (4), VC to [ARTN, COM]
GATE (4), GAT2 (4) to [ARTN, COM]
UNIT
V
–2 to 2
–0.3 to 19
–0.3 to VC+0.3
RTN
Internally limited
T2P
20
mA
Sourcing current
VB
Average Sourcing or
sinking current
GATE, GAT2
25
mARMS
Human body model (HBM)
2
kV
ESD rating
Charged device model (CDM)
500
Machine model (MM)
50
ESD – system level (contact/air) at RJ-45 (5)
Operating junction temperature range, TJ
(1)
(2)
(3)
(4)
(5)
2
Internally limited
V
8 / 15
kV
–40 to Internally limited
°C
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
ARTN and COM tied to RTN.
IRTN = 0 for VRTN > 80V.
Do not apply voltage to these pins
ESD per EN61000-4-2. A power supply containing the TPS23785B was subjected to the highest test levels in the standard.
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TPS23785B
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SLUSB90A – DECEMBER 2012 – REVISED DECEMBER 2012
RECOMMENDED OPERATING CONDITIONS (1)
Voltage with respect to VSS (unless otherwise noted)
MIN
Input voltage range
Sinking current
NOM
MAX
ARTN, COM, RTN, VDD, VDD1
0
T2P (2), VC to [ARTN, COM]
0
18
[APD, CTL, DT, FRS (3), P1, P2] to [ARTN, COM]
0
VB
CS to [ARTN, COM]
0
2
57
T2P
V
2
Continuous RTN current (TJ ≤ 125°C) (4)
825
Sourcing current
VB
0
Capacitance
VB
0.08
RBLNK
2.5
mA
5
μF
0
Synchronization pulse width input (when used)
350
kΩ
25
Operating junction temperature range, TJ
(1)
(2)
(3)
(4)
UNIT
ns
–40
125
°C
ARTN and COM tied to RTN.
T2P current is limited.
Pulse voltage applied for synchronization.
This is the minimum current-limit value. Viable systems will be designed for maximum currents below this value with reasonable margin.
IEEE 802.3at permits 600mA continuous loading.
THERMAL INFORMATION
TPS23785B
THERMAL METRIC (1)
TSSOP
UNITS
24 PINS
θJA
Junction-to-ambient thermal resistance (2)
32.6
θJCtop
Junction-to-case (top) thermal resistance (3)
16.9
θJB
Junction-to-board thermal resistance (4)
17.9
(5)
ψJT
Junction-to-top characterization parameter
ψJB
Junction-to-board characterization parameter (6)
7.4
θJCbot
Junction-to-case (bottom) thermal resistance (7)
1.8
(1)
(2)
(3)
(4)
(5)
(6)
(7)
0.2
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDECstandard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
Spacer
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TPS23785B
SLUSB90A – DECEMBER 2012 – REVISED DECEMBER 2012
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ELECTRICAL CHARACTERISTICS
Unless otherwise noted: CS=COM=APD=CTL=RTN=ARTN, GATE and GAT2 float, RFRS= 68.1 kΩ, RBLNK= 249 kΩ, DT = VB,
T2P open, CVB= CVC= 0.1 μF, RDEN= 24.9 kΩ, RCLS open, 0 V ≤ (VDD, VDD1) ≤ 57 V, 0 V ≤ VC ≤ 18 V, –40°C ≤ TJ ≤ 125°C. P1
= P2 = VB. Typical specifications are at 25°C.
CONTROLLER SECTION ONLY
[VSS = RTN and VDD= VDD1] or [VSS= RTN=VDD], all voltages referred to [ARTN, COM].
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
14.3
15
15.7
6.2
6.5
6.8
UNIT
VC
VCUV
VCUVH
tST
UVLO
VC rising
Hysteresis
(1)
Operating current
VC = 12 V, CTL = VB, RDT = 75 kΩ
0.74
0.96
1.24
Bootstrap startup time,
CVC = 22 μF
VDD1 = 19.2 V, VC(0) = 0 V
49
81
166
VDD1 = 35 V, VC(0) = 0 V
44
75
158
VDD1 = 19.2 V, VC = 13.9 V
1.7
3.4
5.5
VDD1 = 48 V, VC = 0 V
2.7
4.8
6.8
6.5 V ≤ VC ≤ 18 V, 0 ≤ IVB ≤ 5 mA
4.8
5.10
5.25
227
253
278
76%
78%
80%
2
2.2
2.4
Startup current source - IVC
V
mA
ms
mA
VB
Voltage
V
FRS
Switching frequency
CTL = VB, measure GATE
RFRS = 68.1 kΩ
kHz
DMAX
Duty cycle
CTL= VB, measure GATE
VSYNC
Synchronization
Input threshold
0% duty cycle threshold
VCTL ↓ until GATE stops
1.3
1.5
1.7
V
Softstart period
Interval from switching start to VCSMAX
1.9
3.9
6.2
ms
70
100
145
kΩ
BLNK = RTN
35
55
78
RBLNK = 49.9 kΩ
38
55
70
RDT = 24.9 kΩ, GAT2 ↓ to GATE ↑
40
50
62.5
RDT = 24.9 kΩ, GATE ↓ to GAT2 ↑
40
50
62.5
V
CTL
VZDC
Input resistance
BLNK
Blanking delay
(In addition to t1)
ns
DT
CTL = VB, CGATE = 1 nF,
CGAT2 = 1 nF, measure GATE, GAT2
tDT1
tDT2
Dead time
See Figure 1 for tDTx definition
tDT1
RDT = 75 kΩ, GAT2 ↓ to GATE ↑
120
150
188
tDT2
RDT = 75 kΩ, GATE ↓ to GAT2 ↑
120
150
188
(1)
4
ns
The hysteresis tolerance tracks the rising threshold for a given device.
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TPS23785B
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SLUSB90A – DECEMBER 2012 – REVISED DECEMBER 2012
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
CS
VCSMAX
Maximum threshold voltage
VCTL = VB, VCS rising until GATE duty cycle drops
0.5
0.55
0.6
V
t1
Turnoff delay
VCS = 0.65 V
24
40
70
ns
VSLOPE
Internal slope compensation voltage
Peak voltage at maximum duty cycle, referenced
to CS
120
155
185
mV
ISL_EX
Peak slope compensation current
VCTL = VB, ICS at maximum duty cycle
Bias current (sourcing)
DC component of ICS
Source current
30
42
54
1
2.5
4.3
VCTL = VB, VC = 12 V, GATE high, pulsed
measurement
0.37
0.6
0.95
Sink current
VCTL = VB, VC = 12 V, GATE low, pulsed
measurement
0.7
1
1.4
Source current
VCTL = VB, VC = 12 V, GAT2 high, RDT = 24.9 kΩ,
pulsed measurement
0.37
0.6
0.95
Sink current
VCTL = VB, VC = 12 V, GAT2 low, RDT = 24.9 kΩ,
pulsed measurement
0.7
1
1.4
1.43
1.5
1.57
0.29
0.31
0.33
μA
GATE
A
GAT2
A
APD
VAPDEN
VAPDH
APD threshold voltage
VAPD rising
Hysteresis
(2)
V
APD leakage current
(source or sink)
VC = 12 V, VAPD = VB
1
μA
Leakage current
Source or sink
1
μA
P1, P2
(2)
The hysteresis tolerance tracks the rising threshold for a given device.
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SLUSB90A – DECEMBER 2012 – REVISED DECEMBER 2012
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ELECTRICAL CHARACTERISTICS – PoE AND CONTROL
[VDD = VDD1] or [VDD1 = RTN], VC = RTN, COM = RTN = ARTN, all voltages referred to VSS unless otherwise noted
PARAMETER
DETECTION (DEN)
TEST CONDITIONS
MIN
TYP MAX
UNIT
(VDD = VDD1 = RTN = VSUPPLY positive)
Measure ISUPPLY
Detection current
Detection bias current
VPD_DIS
VDD = 1.6 V
62
64.3
66.5
VDD = 10 V
399
406
414
5.6
10
μA
4
5
V
0.1
5
μA
1.8
2.1
2.4
RCLS = 243 Ω (Class 1)
9.9
10.4
10.9
RCLS = 137 Ω (Class 2)
17.6
18.5
19.4
RCLS = 90.9 Ω (Class 3)
26.5
27.7
29.3
42
VDD = 10 V, float DEN, measure ISUPPLY,
Note: Not during Mark state
Hotswap disable threshold
DEN leakage current
CLASSIFICATION (CLS)
3
VDEN = VDD = 57 V, float VDD1 and RTN, measure IDEN
μA
(VDD = VDD1 = RTN = VSUPPLY positive)
13 V ≤ VDD ≤ 21 V, Measure ISUPPLY
RCLS = 1270 Ω (Class 0)
Classification current,
applies to both cycles
ICLS
mA
RCLS = 63.4 Ω (Class 4)
38
39.7
Classification mark resistance
5.6 V ≤ VDD ≤ 9.4 V
7.5
9.7
12
Classification regulator lower
threshold
Regulator turns on, VDD rising
11.2
11.9
12.6
Hysteresis (1)
1.55
1.65
1.75
Classification regulator upper
threshold
Regulator turns off, VDD rising
21
22
23
VCU_H
Hysteresis (1)
0.5
0.75
1
VMSR
Mark state reset
VDD falling
3
4
5
V
Leakage current
VDD = 57 V, VCLS = 0 V, DEN = VSS, measure ICLS
1
μA
0.75
Ω
VCL_ON
VCL_H
VCU_OFF
PASS DEVICE (RTN)
kΩ
V
V
(VDD1 = RTN)
On resistance
0.25
0.43
Current limit
VRTN = 1.5 V, VDD = 48 V, pulsed measurement
850
970 1100
mA
Inrush limit
VRTN = 2 V, VDD: 0 V → 48 V, pulsed measurement
100
140
180
mA
Foldback voltage threshold
VDD rising
11
12.3
13.6
V
VDD rising
33.9
35
36.1
4.4
4.55
4.76
UVLO
VUVLO_R
VUVLO_H
UVLO threshold
Hysteresis (1)
V
T2P
tT2P
ON characteristic
Perform classification algorithm, VT2P-RTN = 1 V,
CTL = ARTN
Leakage current
VT2P = 18 V, CTL = VB
Delay
From start of switching to T2P active
2
mA
10
μA
5
9
15
ms
135
145
155
°C
THERMAL SHUTDOWN
Turnoff temperature
Hysteresis
(1)
(2)
6
TJ rising
(2)
20
°C
The hysteresis tolerance tracks the rising threshold for a given device.
These parameters are specified by design and are not production tested.
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SLUSB90A – DECEMBER 2012 – REVISED DECEMBER 2012
GATE
Timing Diagram
hi
50%
GAT2
lo
hi
50%
time
lo
tDT1
tDT2
Figure 1. GATE and GAT2 Timing and Phasing Diagram
DEVICE INFORMATION
TPS28785B
PWP PACKAGE
(TOP VIEW)
P1
P2
CTL
VB
CS
COM
GATE
VC
GAT2
ARTN
RTN
VSS (pad)
1
2
3
4
5
6
7
8
9
10
11
12
Thermal
Pad
24
23
22
21
20
19
18
17
16
15
14
13
N/C
N/C
T2P
FRS
BLNK
APD
DT
CLS
N/C
DEN
VDD
VDD1
N/C = Leave Pin Unused
PAD = VSS
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Functional Block Diagram
VC
VDD1
f
f
Oscillator
FRS
CTL
50kW
Control
D Q
CK
1
+
0.75V
CLRB
GATE
DT
COM
GAT2
f
ARTN
t2
Converter
Thermal
Monitor
+
ss
CTL
-
0.55V
T2P Logic
Switch
Matrix
T2P
ARTN
BLNK
ARTN
VDD
Ref
Global Cvtr.
Enable enb
enb
+
ARTN 42mA
(pk)
3.69kW
CS
VB
Deadtime
50kW
3.9ms
Softstart
CONV.
OFF
Reg
uvlo, fpd
11.9V & pa, sa, den
10.3V
2.5V
Class
Logic &
Regulator
CLS
uvlo
T2
State
Eng.
t2
22V &
21.25V
12.3V
VSS
DEN
4V
35V &
30.5V
R Q
uvlo
Common
Circuits and
PoE Thermal
Monitor
VSS
S
H
L
1
ILIM
+
0
-
Hotswap
MOSFET
RTN
50mW
den
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EN
fpd
sa
8
CONV.
OFF
400ms
1.5V
&1.2V
ARTN
APD
4V
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TPS23785B
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SLUSB90A – DECEMBER 2012 – REVISED DECEMBER 2012
PIN FUNCTIONS
NAME
PIN
TYPE
DESCRIPTION
P1
1
I
Tie this pin to VB.
P2
2
I
Tie this pin to VB.
CTL
3
I
This is the control loop input to the PWM (pulse width modulator), typically driven by output regulation
feedback (e.g. optocoupler). Use VB as a pullup for CTL.
VB
4
O
5.1 V bias rail for dc/dc control circuits and the feedback optocoupler. Typically bypass with a 0.1 μF to
ARTN.
CS
5
I/O
DC/DC converter switching MOSFET current sense input. See RCS in the Typical Application Diagram.
COM
6
–
Gate driver return, connect to ARTN and RTN.
GATE
7
O
Gate drive output for the main dc/dc converter switching MOSFET.
VC
8
I/O
DC/DC converter bias voltage. Connect a 0.47 μF (minimum) ceramic capacitor to ARTN at the pin, and a
larger capacitor to power startup.
GAT2
9
O
Gate drive output for a second dc/dc converter switching MOSFET.
ARTN
10
–
ARTN is the dc/dc converter analog return. Tie to RTN and COM on the circuit board.
RTN
11
–
RTN is the output of the PoE hotswap MOSFET.
VSS
12
–
Connect to the negative power rail derived from the PoE source.
VDD1
13
I
Source of dc/dc converter startup current. Connect to VDD for many applications.
VDD
14
I
Connect to the positive PoE input power rail. VDD powers the PoE interface circuits. Bypass with a 0.1 μF
capacitor and protect with a TVS.
DEN
15
I/O
N/C
16
–
Do not connect this pin.
CLS
17
I
Connect a resistor from CLS to VSS to program classification current. 2.5 V is applied to the program resistor
during classification to set class current.
DT
18
I
Connect a resistor from DT to ARTN to set the GATE to GAT2 dead time. Tie DT to VB to disable GAT2
operation.
APD
19
I
Raising VAPD-VARTN above 1.5 V disables the internal hotswap switch, turns class off, and forces T2P active.
This forces power to come from a external VDD1-RTN adapter. Tie APD to ARTN when not used.
BLNK
20
I
Connect to ARTN to utilize the internally set current-sense blanking period, or connect a resistor from BLNK
to ARTN to program a more accurate period.
FRS
21
I
Connect a resistor from FRS to ARTN to program the converter switching frequency. FRS may be used to
synchronize the converter to an external timing source.
T2P
22
O
Active low output that indicates a PSE has performed the IEEE 802.3at type 2 hardware classification, or
APD is active. T2P pulls current to ARTN
N/C
23
–
Do not connect this pin.
N/C
24
–
Do not connect this pin.
Pad
–
Connect a 24.9 kΩ resistor from DEN to VDD to provide the PoE detection signature. Pulling this pin to VSS
during powered operation causes the internal hotswap MOSFET to turn off.
Connect to VSS.
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Detailed Pin Description
See the Typical Application Diagram for component reference designators (RCS for example), and the Electrical
Characteristics table for values denoted by reference (VCSMAX for example). Electrical Characteristic values take
precedence over any numerical values used in the following sections.
APD
APD forces power to come from an external adapter connected from VDD1 to RTN by opening the hotswap
switch, disabling the CLS output, and enabling the T2P output. A resistor divider is recommended on APD when
it is connected to an external adapter. The divider provides ESD protection, leakage discharge for the adapter
ORing diode, and input voltage qualification. Voltage qualification assures the adapter output voltage is high
enough that it can support the PD before the PoE current is cut off.
Select the APD divider resistors per Equation 1 where VADPTR-ON is the desired adapter voltage that enables the
APD function as adapter voltage rises.
RAPD1 = RAPD2 ´
VADPTR_OFF =
(VADPTR_ON
R APD1 + R APD2
R APD2
- VAPDEN
´
(VAPDEN
) VAPDEN
- VAPDH )
(1)
SLVA306A (or most recent) provides a sample calculation.
Place the APD pull-down resistor adjacent to the APD pin.
APD should be tied to ARTN when not used.
BLNK
Blanking provides an interval between GATE going high and the current-control comparators on CS actively
monitoring the input. This delay allows the normal turn-on current transient (spike) to subside before the
comparators are active, preventing undesired short duty cycles and premature current limiting.
Connect BLNK to ARTN to obtain the internally set blanking period. Connect a resistor from BLNK to ARTN for a
more accurate, programmable blanking period. The relationship between the desired blanking period and the
programming resistor is defined by Equation 2.
RBLNK (kW ) = tBLNK (ns )
(2)
Place the resistor adjacent to the BLNK pin when it is used.
10
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CLS
A resistor from CLS to VSS programs the classification current per the IEEE standard. The PD power ranges and
corresponding resistor values are listed in Table 1. The power assigned should correspond to the maximum
average power drawn by the PD during operation.
High-power PSEs may perform two-event classification if Class 4 is advertised by the PD. The TPS23785B
presents the same (resistor-programmed) class each cycle per the standard.
Table 1. Class Resistor Selection
PD INPUT POWER
RESISTOR
(Ω)
CLASS
MINIMUM
(W)
MAXIMUM
(W)
0
0.44
12.95
1270
1
0.44
3.84
243
2
3.84
6.49
137
3
6.49
12.95
90.9
4
12.95
25.5
63.4
NOTES
Minimum may be reduced by pulsed loading. Serves as a catch-all default class.
Not allowed for IEEE 802.3-2008. Use to indicate a Type 2 PD (high power) per
IEEE 802.3at.
CS
The CS (current-sense) input for the dc/dc converter should be connected to the high side of the switching
MOSFET’s current sense resistor (RCS). The current-limit threshold, VCSMAX, defines the voltage on CS above
which the GATE ON time will be terminated regardless of the voltage on CTL.
The TPS23785B provides internal slope compensation (150 mV, VSLOPE), an output current for additional slope
compensation, a peak current limiter, and an off-time pull-down to this pin.
Routing between the current-sense resistor and the CS pin should be short to minimize cross-talk from noisy
traces such as the gate drive signal.
CTL
CTL (control) is the voltage-control loop input to the PWM (pulse width modulator). Pulling VCTL below VZDC (zero
duty cycle voltage) causes GATE to stop switching. Increasing VCTL above VZDC raises the switching MOSFET
programmed peak current. The maximum (peak) current is requested at approximately VZDC + (2 × VCSMAX). The
ac gain from CTL to the PWM comparator is 0.5 V/V. The total internal divider resistance from CTL to ARTN is
approximately 100 kΩ.
Use VB as a pull up source for CTL.
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DEN
DEN (detection and enable) is a multifunction pin for PoE detection and inhibiting operation from PoE power.
Connect a 24.9 kΩ resistor from DEN to VDD to provide the PoE detection signature. DEN is pulled to VSS for
VVDD-VSS below the classification voltage range, and goes to a high-impedance state when VVDD-VSS is outside of
the detection range. Pulling DEN to VSS during powered operation causes the internal hotswap MOSFET and
class regulator to turn off, while the reduced detection resistance prevents the PD from properly re-detecting.
DT
Dead-time programming sets the delay between GATE and GAT2 to synchronize MOSFET ON times as shown
in Figure 1. GAT2 should turn the second MOSFET on when it transitions high. GAT2 should transition low
before GATE goes high and transition high after GATE goes low. The maximum GATE ON time is reduced by
the programmed dead-time period. The dead time period is specified with 1 nF of capacitance on GATE and
GAT2. Different loading on these pins will change the effective dead time.
A resistor connected from DT to ARTN sets the delay between GATE and GAT2 per Equation 3.
RDT (kW ) =
tDT (ns )
2
(3)
Connect DT to VB to set the dead time to 0 and turn GAT2 off.
FRS
Connect a resistor from FRS (frequency and synchronization) to ARTN to program the converter switching
frequency. Select the resistor per the following relationship.
RFRS (kW) =
17250
fSW (kHz)
(4)
The converter may be synchronized to a frequency above its maximum free-running frequency by applying short
ac-coupled pulses into the FRS pin.
The FRS pin is high impedance. Keep the connections short and apart from potential noise sources. Special care
should be taken to avoid crosstalk when synchronizing circuits are used.
GATE
Gate drive output for the dc/dc converter’s main switching MOSFET. GATE’s phase turns the main switch on
when it transitions high, and off when it transitions low. GATE is held low when the converter is disabled.
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GAT2
GAT2 is the second gate drive output for the dc/dc converter. GAT2 turns the second switch on when it
transitions high. GAT2 drives a secondary FET used as a synchronous rectifier in a flyback converter. See the
DT Pin Description for GATE to GAT2 timing. Connecting DT to VB disables GAT2 in a high-impedance
condition. GAT2 is low when the converter is disabled.
RTN, ARTN, COM
RTN is internally connected to the drain of the PoE hotswap MOSFET, while ARTN is the quiet analog reference
for the dc/dc controller return. COM serves as the return path for the gate drivers and should be tied to ARTN on
the circuit board. The ARTN / COM / RTN net should be treated as a local reference plane (ground plane) for the
dc/dc control and converter primary. RTN and (ARTN/COM) may be separated by several volts for special
applications.
T2P
T2P (Type 2 PSE) is an active low output that indicates [ (VAPD > 1.5 V) OR (type 2 hardware classification
observed) ]. T2P is valid after both a delay of tT2P from the start of converter switching, and [VCTL ≤ (VB – 1 V)].
Once T2P is valid, VCTL will not affect it. T2P will become invalid if the converter goes back into softstart, overtemperature, or is held off by the PD during CIN recharge (inrush). T2P is referenced to ARTN and drives the
diode side of an optocoupler. T2P should be left open or tied to ARTN if not used.
VB
VB is an internal 5.1V regulated dc/dc controller supply rail that is typically bypassed by a 0.1 μF capacitor to
ARTN. VB should be used to bias the feedback optocoupler.
VC
VC is the bias supply for the dc/dc controller. The MOSFET gate drivers run directly from VC. VB is regulated
down from VC, and is the bias voltage for the rest of the converter control. A startup current source from VDD1 to
VC is controlled by a comparator with hysteresis to implement the converter bootstrap startup. VC must be
connected to a bias source, such as a converter auxiliary output, during normal operation.
A minimum 0.47 μF capacitor, located adjacent to the VC pin, should be connected from VC to COM to bypass
the gate driver. A larger total capacitance is required for startup to provide control power between the time the
converter starts switching and the availability of the converter auxiliary output voltage.
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VDD
VDD is the positive input power rail that is derived from the PoE source (PSE). VDD should be bypassed to VSS
with a 0.1 μF capacitor as required by the IEEE standard. A transient suppressor diode (TVS), a special type of
Zener diode, such as SMAJ58A should be connected from VDD to VSS to protect against over-voltage transients.
VDD1
VDD1 is the dc/dc converter startup supply. Connect to VDD for many applications. VDD1 may be isolated by a
diode from VDD to support PoE priority operation.
VSS
VSS is the PoE input-power return side. It is the reference for the PoE interface circuits, and has a current-limited
hotswap switch that connects it to RTN. VSS is clamped to a diode drop above RTN by the hotswap switch.
A local VSS reference plane should be used to connect the input bypass capacitor, TVS, RCLS, and the
PowerPad. This plane becomes the main heatsink for the TPS23785B.
VSS is internally connected to the PowerPAD.
PowerPAD™
The PowerPAD must be connected to VSS on the circuit board. It should be tied to a large VSS copper area on
the PCB to provide a low resistance thermal path to the circuit board. It is recommended that a clearance of
0.025” be maintained between VSS, RTN, and various control signals to high-voltage signals such as VDD and
VDD1.
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TYPICAL CHARACTERISTICS
DETECTION BIAS CURRENT
vs
VOLTAGE
PoE CURRENT LIMIT
vs
TEMPERATURE
970
8
Pulsed Current Measurement
7
960
PoE − Current Limit − mA
IVDD − Bias Current − µA
6
25°C
5
125°C
4
3
2
950
940
930
−40°C
920
1
0
0
2
4
6
8
910
−40
10
(VVDD − VVSS) − PoE Voltage − V
20
40
60
80
100
G001
Figure 2.
Figure 3.
CONVERTER START TIME
vs
TEMPERATURE
CONVERTER STARTUP CURRENT
vs
VVDD1
6
120
G002
VVC = 13.9V
CVC = 22 µF
o
TJ = -40 C
140
5
IVC − Source Current − mA
VVDD1 = 19.2 V
Converter Start Time − ms
0
TJ − Junction Temperature − °C
160
120
100
80
VVDD1 = 35 V
60
o
TJ = 25 C
4
o
TJ = 125 C
3
2
1
40
20
−40
−20
0
−20
0
20
40
60
80
TJ − Junction Temperature − °C
Figure 4.
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100
5
120
10
15 20
25
30
35
40
45 50
55 60
VVDD1-RTN − V
G003
Figure 5.
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TYPICAL CHARACTERISTICS (continued)
CONTROLLER BIAS CURRENT
vs
TEMPERATURE
CONTROLLER BIAS CURRENT
vs
VOLTAGE
3000
3500
GATE and GAT2 Open
VVC = 12 V
3000
IC − Controller Bias Current − mA
2500
IVC − Sinking −mA
GATE and GAT2 Open
TJ = 25°C
2000
937 kHz
484 kHz
1500
245 kHz
100 kHz
1000
500
937 kHz
2500
484 kHz
2000
245 kHz
100 kHz
1500
1000
500
50 kHz
0
−40
VCTL = 0 V
50 kHz
VCTL = 0 V
0
−20
0
20
40
60
80
100
9
120
TJ - Junction Temperature - °C
10
11
12
13
14
15
16
G005
Figure 6.
Figure 7.
SWITCHING FREQUENCY
vs
TEMPERATURE
SWITCHING FREQUENCY
vs
PROGRAM CONDUCTANCE
1200
600
17
18
VC − Controller Bias Voltage − V
G006
1200
RFRS = 34.6 kΩ (484 kHz)
1100
300
1000
RFRS = 17.35 kΩ (937 kHz)
900
RFRS = 69.8 kΩ (245 kHz)
RFRS = 347 kΩ (50 kHz)
200
800
RFRS = 173 kΩ (100 kHz)
700
100
Switching Frequency − kHz
400
1000
Switching Frequency − kHz
Switching Frequency − kHz
500
Ideal
800
600
Typical
400
200
0
−40
600
−20
0
20
40
60
80
TJ - Junction Temperature - °C
100
120
G007
0
0
10
20
30
40
50
Programmed Resistance (106 / RFRS) − Ω−1
Figure 8.
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G008
Figure 9.
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SLUSB90A – DECEMBER 2012 – REVISED DECEMBER 2012
TYPICAL CHARACTERISTICS (continued)
MAXIMUM DUTY CYCLE
vs
TEMPERATURE
CURRENT SLOPE COMPENSATION VOLTAGE
vs
TEMPERATURE
79
155
78
RFRS = 347 kW (50 kHz)
154
RFRS = 69.8 kW (245 kHz)
76
153
VSLOPE − mVPP
Maximum Duty Cycle − %
77
75
RFRS = 34.6 kW (484 kHz)
74
RFRS = 26.7 kW (623 kHz)
73
152
151
RFRS = 21.5 kW (766 kHz)
72
150
70
−40
−20
0
20
40
60
80
100
149
−40
120
TJ - Junction Temperature - °C
0
20
40
60
G009
Figure 10.
Figure 11.
CURRENT SLOPE COMPENSATION CURRENT
vs
TEMPERATURE
BLANKING PERIOD
vs
TEMPERATURE
Blanking Period − ns
45
40
G010
105
260
95
255
RBLNK = 100 kΩ
250
85
RBLNK = 249 kΩ
245
75
240
RBLNK = RTN
RBLNK = 49.9 kΩ
55
−20
0
20
40
60
80
TJ − Junction Temperature − °C
Figure 12.
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100
120
265
45
−40
30
−40
100
115
65
35
80
TJ − Junction Temperature − °C
50
ISLOPE − µAPP
−20
235
230
−20
0
20
40
60
80
100
120
TJ - Junction Temperature - °C
120
Blanking Period − ns
RFRS = 17.3 kW (937 kHz)
71
G012
G011
Figure 13.
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TYPICAL CHARACTERISTICS (continued)
DEAD TIME
vs
DEAD TIME RESISTANCE (RDT )
450
18
900
400
14
800
350
10
300
6
250
2
200
−2
150
−6
100
−10
50
−14
0
−18
400
700
Dead Time - ns
Difference From Computed − ns
Blanking Period − ns
BLANKING PERIOD
vs
Blanking Resistance (RBLNK)
Ideal
600
500
400
Typical
300
200
100
0
50
100
150
200
250
300
350
0
RBLNK − kW
0
50
100 150 200 250 300
Dead Time Resistance - kW
Figure 14.
350
400
Figure 15.
T2P DELAY TIME
vs
TEMPERATURE
11
T2P Delay Time - ms
10
9
8
7
6
-40
-20
0
20
40
60
80
Temperature - °C
100
120
Figure 16.
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DETAILED DESCRIPTION
Introduction
The TPS23785B is based on the TPS23754 platform with a secondary gate drive output that is out-of-phase with
the primary gate drive. The secondary gate drive output can be used directly or through an isolating transformer
to drive a synchronous rectifier. See the Typical Application Diagram for a schematic.
PoE OVERVIEW
The following text is intended as an aid in understanding the operation of the TPS23785B but not as a substitute
for the IEEE 802.3at standard. The IEEE 802.3at standard is an update to IEEE 802.3-2008 clause 33 (PoE),
adding high-power options and enhanced classification. Generally speaking, a device compliant to IEEE 802.32008 is referred to as a type 1 device, and devices with high power and enhanced classification will be referred
to as type 2 devices. Standards change and should always be referenced when making design decisions.
The IEEE 802.3at standard defines a method of safely powering a PD (powered device) over a cable by power
sourcing equipment (PSE), and then removing power if a PD is disconnected. The process proceeds through an
idle state and three operational states of detection, classification, and operation. The PSE leaves the cable
unpowered (idle state) while it periodically looks to see if something has been plugged in; this is referred to as
detection. The low power levels used during detection are unlikely to damage devices not designed for PoE. If a
valid PD signature is present, the PSE may inquire how much power the PD requires; this is referred to as
classification. The PSE may then power the PD if it has adequate capacity.
Type 2 PSEs are required to do type 1 hardware classification plus a (new) data-layer classification, or an
enhanced type 2 hardware classification. Type 1 PSEs are not required to do hardware or data link layer (DLL)
classification. A type 2 PD must do type 2 hardware classification as well as DLL classification. The PD may
return the default, 13W current-encoded class, or one of four other choices. DLL classification occurs after
power-on and the ethernet data link has been established.
Shutdown
Classify
Detect
6.9
Maximum Input
Voltage
Must Turn On byVoltage Rising
Lower Limit Operating Range
Must Turn Off by Voltage Falling
Classification
Upper Limit
Classification
Lower Limit
Detection
Upper Limit
Detection
Lower Limit
IEEE 802.3-2005
Once started, the PD must present the maintain power signature (MPS) to assure the PSE that it is still present.
The PSE monitors its output for a valid MPS, and turns the port off if it loses the MPS. Loss of the MPS returns
the PSE to the idle state. Figure 17 shows the operational states as a function of PD input voltage. The upper
half is for IEEE 802.3-2008, and the lower half shows specific differences for IEEE 802.3at. The dashed lines in
the lower half indicate these are the same (e.g., Detect and Class) for both.
Normal Operation
42.5
0
30
37
57 PI Voltage (V)
42
Normal Operation
250ms
Transient
Class-Mark
Transition
20.5
Lower Limit 13W Op.
10.1 14.5
Mark
T2 Reset
Range
IEEE 802.3at
2.7
Figure 17. Operational States for PD
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The PD input, typically an RJ-45 eight-lead connector, is referred to as the power interface (PI). PD input
requirements differ from PSE output requirements to account for voltage drops and operating margin. The
standard allots the maximum loss to the cable regardless of the actual installation to simplify implementation.
IEEE 802.3-2008 was designed to run over infrastructure including ISO/IEC 11801 class C (CAT3 per TIA/EIA568) that may have had AWG 26 conductors. IEEE 802.3at type 2 cabling power loss allotments and voltage
drops have been adjusted for 12.5 Ω power loops per ISO/IEC11801 class D (CAT5 or higher per TIA/EIA-568,
typically AWG #24 conductors). Table 2 shows key operational limits broken out for the two revisions of the
standard.
Table 2. Comparison of Operational Limits
STANDARD
POWER LOOP
RESISTANCE
(max)
PSE
OUTPUT POWER
(min)
PSE STATIC
OUTPUT VOLTAGE
(min)
PD INPUT
POWER
(max)
POWER ≤
12.95 W
STATIC PD INPUT VOLTAGE
POWER >
12.95 W
IEEE 802.3-2008
802.3at (Type 1)
20 Ω
15.4 W
44 V
12.95 W
37 V–57 V
N/A
802.3at (Type 2)
12.5 Ω
30 W
50 V
25.5 W
37 V–57 V
42.5 V–57 V
The PSE can apply voltage either between the RX and TX pairs (pins 1 - 2 and 3 - 6 for 10baseT or 100baseT),
or between the two spare pairs (4 - 5 and 7 - 8). Power application to the same pin combinations in 1000baseT
systems is recognized in IEEE 802.3at. 1000baseT systems can handle data on all pairs, eliminating the spare
pair terminology. The PSE may only apply voltage to one set of pairs at a time. The PD uses input diode bridges
to accept power from any of the possible PSE configurations. The voltage drops associated with the input
bridges create a difference between the standard limits at the PI and the TPS23785B specifications.
A compliant type 2 PD has power management requirements not present with a type 1 PD. These requirements
include the following:
1. Must interpret type 2 hardware classification
2. Must present hardware class 4
3. Must implement DLL negotiation
4. Must behave like a type 1 PD during inrush and startup
5. Must not draw more than 13 W for 80 ms after PSE applies operating voltage (power-up)
6. Must not draw more than 13 W if it has not received a type 2 hardware classification or received permission
through DLL
7. Must meet various operating and transient templates
8. Optionally monitor for the presence or absence of an adapter (assume high power).
As a result of these requirements, the PD must be able to dynamically control its loading, and monitor T2P for
changes. In cases where the design needs to know specifically if an adapter is plugged in and operational, the
adapter should be individually monitored, typically with an optocoupler.
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Threshold Voltages
The TPS23785B has a number of internal comparators with hysteresis for stable switching between the various
states. Figure 18 relates the parameters in the Electrical Characteristics section to the PoE states. The mode
labeled idle between classification and operation implies that the DEN, CLS, and RTN pins are all high
impedance. The state labeled Mark, which is drawn in dashed lines, is part of the new type 2 hardware class
state machine.
Functional
State
PD Powered
Idle
Classification
Mark
VDD-VSS
Detection
VCL_H
VMSR
VCL_ON
VCU_H
VUVLO_H
VCU_OFF
VUVLO_R
Note: Variable names refer to Electrical Characteristic
Table parameters
Figure 18. Threshold Voltages
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PoE Startup Sequence
50 mA/div
The waveforms of Figure 19 demonstrate detection, classification, and startup from a PSE with type 2 hardware
classification. The key waveforms shown are VVDD-VVSS, VRTN-VVSS, and IPI. IEEE 802.3at requires a minimum of
two detection levels, two class and mark cycles, and startup from the second mark event. VRTN to VSS falls as the
TPS23785B charges CIN following application of full voltage. Subsequently, the converter starts up, drawing
current as seen in the IPI waveform.
Cvtr. Starts
Inrush
IPI
Class
VVDD-VSS
10 V/div
Mark
Detect
VRTN-VSS
t - Time - 25 ms/div
Figure 19. Startup
Detection
The TPS23785B drives DEN to VSS whenever VVDD-VVSS is below the lower classification threshold. When the
input voltage rises above VCL-ON, the DEN pin goes to an open-drain condition to conserve power. While in
detection, RTN is high impedance, and almost all the internal circuits are disabled. An RDEN of 24.9 kΩ (1%),
presents the correct signature. It may be a small, low-power resistor since it only sees a stress of about 5 mW. A
valid PD detection signature is an incremental resistance ( ΔV / ΔI ) between 23.75 kΩ and 26.25 kΩ at the PI.
The detection resistance seen by the PSE at the PI is the result of the input bridge resistance in series with the
parallel combination of RDEN and internal VDD loading. The input diode bridge’s incremental resistance may be
hundreds of ohms at the very low currents drawn when 2.7 V is applied to the PI. The input bridge resistance is
partially cancelled by the TPS23785B's effective resistance during detection.
The type 2 hardware classification protocol of IEEE 802.3at specifies that a type 2 PSE drops its output voltage
into the detection range during the classification sequence. The PD is required to have an incorrect detection
signature in this condition, which is referred to as the mark event (see Figure 19). After the first mark event, the
TPS23785B will present a signature less than 12 kΩ until it has experienced a VVDD-VVSS voltage below the mark
reset (VMSR). This is explained more fully under Hardware Classification.
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Hardware Classification
Hardware classification allows a PSE to determine a PD’s power requirements before powering, and helps with
power management once power is applied. Type 2 hardware classification permits high power PSEs and PDs to
determine whether the connected device can support high-power operation. A type 2 PD presents class 4 in
hardware to indicate it is a high-power device. A type 1 PSE will treat a class 4 device like a class 0 device,
allotting 13 W if it chooses to power the PD. A PD that receives a 2 event class understands that it is powered
from a high-power PSE and it may draw up to 25.5 W immediately after the 80 ms startup period completes. A
type 2 PD that does not receive a 2-event hardware classification may choose to not start, or must start in a 13
W condition and request more power through the DLL after startup. The standard requires a type 2 PD to
indicate that it is underpowered if this occurs. Startup of a high-power PD under 13 W implicitly requires some
form of powering down sections of the application circuits.
The maximum power entries in Table 1 determine the class the PD must advertise. The PSE may disconnect a
PD if it draws more than its stated Class power, which may be the hardware class or a lower DLL-derived power
level. The standard permits the PD to draw limited current peaks that increase the instantaneous power above
the Table 1 limit, however the average power requirement always applies.
The TPS23785B implements two-event classification. Selecting an RCLS of 63.4 Ω provides a valid type 2
signature. TPS23785B may be used as a compatible type 1 device simply by programming class 0–3 per
Table 1. DLL communication is implemented by the ethernet communication system in the PD and is not
implemented by the TPS23785B.
The TPS23785B disables classification above VCU_OFF to avoid excessive power dissipation. CLS voltage is
turned off during PD thermal limit or when APD or DEN are active. The CLS output is inherently current limited,
but should not be shorted to VSS for long periods of time.
Figure 20 shows how classification works for the TPS23785B. Transition from state-to-state occurs when
comparator thresholds are crossed (see Figure 17 and Figure 18). These comparators have hysteresis, which
adds inherent memory to the machine. Operation begins at idle (unpowered by PSE) and proceeds with
increasing voltage from left to right. A 2-event classification follows the (heavy lined) path towards the bottom,
ending up with a latched type 2 decode along the lower branch that is highlighted. This state results in a low T2P
during normal operation. Once the valid path to type 2 PSE detection is broken, the input voltage must transition
below the mark reset threshold to start anew.
Mark
Reset
Idle
Class
UVLO
Falling
Class
Between
Ranges
Mark
Class
Between
Ranges
Mark
Class
Between
Ranges
Mark
Detect
Mark
Reset
TYPE 2 PSE
Hardware Class
UVLO
Rising
Operating
T2P
open-drain
TYPE 1 PSE
Hardware Class
UVLO
Rising
Operating
T2P low
UVLO
Falling
Figure 20. Two-Event Class Internal States
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Inrush and Startup
802.3at has a startup current and time limitation, providing type 2 PSE compatibility for type 1 PDs. A type 2 PSE
limits output current to between 400 mA and 450 mA for up to 75 ms after power-up (applying “48 V” to the PI) in
order to mirror type 1 PSE functionality. The type 2 PSE will support higher output current after 75 ms. The
TPS23785B implements a 140 mA inrush current, which is compatible with all PSE types. A high-power PD must
control its converter startup peak and operational currents drawn to below 400 mA for 80 ms. The TPS23785B’s
internal softstart permits control of the converter startup, however the application circuits must assure that their
power draw does not cause the PD to exceed the current/time limitation. This requirement implicitly requires
some form of powering down sections of the application circuits. T2P becomes valid within tT2P after switching
starts, or if an adapter is plugged in while the PD is operating from a PSE.
Maintain Power Signature
The MPS is an electrical signature presented by the PD to assure the PSE that it is still present after operating
voltage is applied. A valid MPS consists of a minimum dc current of 10 mA (or a 10 mA pulsed current for at
least 75 ms every 225 ms) and an ac impedance lower than 26.25 kΩ in parallel with 0.05 μF. The ac impedance
is usually accomplished by the minimum operating CIN requirement of 5 μF. When either APD or DEN is used to
force the hotswap switch off, the dc MPS will not be met. A PSE that monitors the dc MPS will remove power
from the PD when this occurs. A PSE that monitors only the ac MPS may remove power from the PD.
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Startup and Converter Operation
The internal PoE UVLO (Under Voltage Lock Out) circuit holds the hotswap switch off before the PSE provides
full voltage to the PD. This prevents the converter circuits from loading the PoE input during detection and
classification. The converter circuits will discharge CIN, CVC, and CVB while the PD is unpowered. Thus VVDD-VRTN
will be a small voltage just after full voltage is applied to the PD, as seen in Figure 19. The PSE drives the PI
voltage to the operating range once it has decided to power up the PD. When VVDD rises above the UVLO turnon threshold (VUVLO-R, ~35 V) with RTN high, the TPS23785B enables the hotswap MOSFET with a ~140 mA
(inrush) current limit as seen in Figure 21. Converter switching is disabled while CIN charges and VRTN falls from
VVDD to nearly VVSS, however the converter startup circuit is allowed to charge CVC (the bootstrap startup
capacitor). Converter switching is allowed if the PD is not in inrush, OTSD is not active, and the VC UVLO
permits it. Once the inrush current falls about 10% below the inrush current limit, the PD current limit switches to
the operational level (~970 mA). Continuing the startup sequence shown in Figure 21, VVC continues to rise until
the startup threshold (VCUV, ~15 V or ~9 V) is exceeded, turning the startup source off and enabling switching.
The VB regulator is always active, powering the internal converter circuits as VVC rises. There is a slight delay
between the removal of charge current and the start of switching as the softstart ramp sweeps above the VZDC
threshold. VVC falls as it powers both the internal circuits and the switching MOSFET gates. If the converter
control bias output rises to support VVC before it falls to VCUV – VCUVH (~8.5 V or ~5.5 V), a successful startup
occurs. T2P in Figure 19 becomes active within tT2P from the start of switching, indicating that a type 2 PSE or an
adapter is plugged in.
10
5 V/div
99
88
200 mA/div
T2P @ output
Inrush
I PI
7
66
10 V/div
5
PI Powered
V C -RTN
Switching starts
44
2 V/div
33
VOUT
2
11
50 V/div
V DD -RTN
0
t - Time - 10 ms/div
Figure 21. Power Up and Start
If VVDD- VVSS drops below the lower PoE UVLO (VUVLO-R - VUVLO-H, ~30.5 V), the hotswap MOSFET is turned off,
but the converter will still run. The converter will stop if VVC falls below the converter UVLO (VCUV – VCUVH, ~8.5 V
or ~5.5 V), the hotswap is in inrush current limit, 0% duty cycle is demanded by VCTL (VCTL < VZDC, ~1.5 V), or
the converter is in thermal shutdown.
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PD Hotswap Operation
IEEE 802.3at has taken a new approach to PSE output limiting. A type 2 PSE must meet an output current vs.
time template with specified minimum and maximum sourcing boundaries. The peak output current may be as
high as 50 A for 10 μs or 1.75 A for 75 ms. This makes robust protection of the PD device even more important
than it was in IEEE 802.3-2008.
I PI
CIN completes charge
while converter operates
10 V/div
500 mA/div
The internal hotswap MOSFET is protected against output faults and input voltage steps with a current limit and
deglitched (time-delay filtered) foldback. An overload on the pass MOSFET engages the current limit, with VRTNVVSS rising as a result. If VRTN rises above ~12 V for longer than ~400 μs, the current limit reverts to the inrush
value, and turns the converter off. The 400 μs deglitch feature prevents momentary transients from causing a PD
reset, provided that recovery lies within the bounds of the hotswap and PSE protection. Figure 22 shows an
example of recovery from a 16 V PSE rising voltage step. The hotswap MOSFET goes into current limit,
overshooting to a relatively low current, recovers to ~950 mA full current limit, and charges the input capacitor
while the converter continues to run. The MOSFET did not go into foldback because VRTN-VVSS was below 12 V
after the 400 μs deglitch.
V RTN-VSS
20 V/div
16 V Input step
VRTN < 12 V @ 400 ms
Recovery from PI dropout
V VDD-VSS
t - Time - 200 ms/div
Figure 22. Response to PSE Step Voltage
The PD control has a thermal sensor that protects the internal hotswap MOSFET. Conditions like startup or
operation into a VDD to RTN short cause high power dissipation in the MOSFET. An over-temperature shutdown
(OTSD) turns off the hotswap MOSFET and class regulator, which are restarted after the device cools. The
hotswap MOSFET will be re-enabled with the inrush current limit when exiting from an over-temperature event.
Pulling DEN to VSS during powered operation causes the internal hotswap MOSFET to turn off. This feature
allows a PD with Option three ORing per Figure 23 to achieve adapter priority. Care must be taken with
synchronous converter topologies that can deliver power in both directions.
The hotswap switch will be forced off under the following conditions:
1. VAPD above VAPDEN (~1.5 V)
2. VDEN < VPD-DIS when VVDD– VVSS is in the operational range
3. PD over-temperature
4. (VVDD– VVSS) < PoE UVLO (~30.5 V).
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Converter Controller Features
The TPS23785B dc/dc controller implements a typical current-mode control as shown in the Functional Block
Diagram. Features include oscillator, over-current and PWM comparators, current-sense blanker, dead-time
control, softstart, and gate driver. In addition, an internal slope-compensation ramp generator, frequency
synchronization logic, thermal shutdown, and startup current source with control are provided.
There is an offset of VZDC (~1.5 V) and 2:1 resistor divider between the CTL pin and the PWM. A VCTL below
VZDC will stop converter switching, while voltages above (VZDC + (2 × VCSMAX)) will not increase the requested
peak current in the switching MOSFET.
Bootstrap Topology
The internal startup current source and control logic implement a bootstrap-type startup as discussed in Startup
and Converter Operation. The startup current source charges CVC from VDD1 when the converter is disabled
(either by the PD control or the VC control) to store enough energy to start the converter. Steady-state operating
power must come from a converter (bias winding) output or other source. Loading on VC and VB must be minimal
while CVC charges, otherwise the converter may never start. The optocoupler will not load VB when the converter
is off for most situations, however care should be taken in ORing topologies where the output is powered when
PoE is off.
The converter will shut off when VC falls below its lower UVLO. This can happen when power is removed from
the PD, or during a fault on a converter output rail. When one output is shorted, all the output voltages fall
including the one that powers VC. The control circuit discharges VC until it hits the lower UVLO and turns off. A
restart will initiate as described in Startup and Converter Operation if the converter turns off and there is sufficient
VDD1 voltage. This type of operation is sometimes referred to as hiccup mode which provides robust output short
protection by providing time-average heating reduction of the output rectifier.
The bootstrap control logic disables most of the converter controller circuits except the VB regulator and internal
reference. Both GATE and GAT2 (assuming GAT2 is enabled) will be low when the converter is disabled. FRS,
BLNK, and DT will be at ARTN while the VC UVLO disables the converter. While the converter runs, FRS, BLNK,
and DT will be about 1.25 V.
The startup current source transitions to a resistance as (VVDD1 – VVC) falls below 7 V, but will start the converter
from adapters within tST. The lower test voltage for tST was chosen based on an assumed adapter tolerance, but
is not meant to imply a hard cutoff exists. Startup takes longer and eventually will not occur as VDD1 decreases
below the test voltage. The bootstrap source provides reliable startup from widely varying input voltages, and
eliminates the continual power loss of external resistors. The startup current source will not charge above the
maximum recommended VVC if the converter is disabled and there is sufficient VDD1 to charge higher.
Current Slope Compensation and Current Limit
Current-mode control requires addition of a compensation ramp to the sensed inductive (transformer or inductor)
current for stability at duty cycles near and over 50%. The TPS23785B has a maximum duty cycle limit of 78%,
permitting the design of wide input-range flyback converters with a lower voltage stress on the output rectifiers.
While the maximum duty cycle is 78%, converters may be designed that run at duty cycles well below this for a
narrower, 36 V to 57 V PI range. The TPS23785B provides a fixed internal compensation ramp that suffices for
most applications.
The TPS23785B provides internal, frequency independent, slope compensation (150 mV, VSLOPE) to the PWM
comparator input for current-mode control-loop stability. This voltage is not applied to the current-limit comparator
whose threshold is 0.55 V (VCSMAX). If the provided slope is not sufficient, the effective slope may be increased
by addition of RS per Figure 27. The additional slope voltage is provided by (ISL-EX × RS). There is also a small dc
offset caused by the ~2.5 μA pin current. The peak current limit does not have duty cycle dependency unless RS
is used. This makes it easier to design the current limit to a fixed value. See Current Slope Compensation for
more information.
The internal comparators monitoring CS are isolated from the IC pin by the blanking circuits while GATE is low,
and for a short time (blanking period) just after GATE switches high. A 440 Ω (max) equivalent pull down on CS
is applied while GATE is low.
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Blanking - RBLNK
The TPS23785B provides a choice between internal fixed and programmable blanking periods. The blanking
period is specified as an increase in the minimum GATE on time over the inherent gate driver and comparator
delays. The default period (see the Electrical Characteristics table) is selected by connecting BLNK to RTN, and
the programmable period is set with RBLNK.
The TPS23785B blanker timing is precise enough that the traditional R-C filters on CS can be eliminated. This
avoids current-sense waveform distortion, which tends to get worse at light output loads. There may be some
situations or designers that prefer an R-C approach. The TPS23785B provides a pull-down on CS during the
GATE off time to improve sensing when an R-C filter must be used. The CS input signal should be protected
from nearby noisy signals like GATE drive and the switching MOSFET drain.
Dead Time
The TPS23785B features two switching MOSFET gate drivers to ease implementation of high-efficiency
topologies such as a flyback converter with synchronous driver that is hard-driven by the control circuit. In these
cases, there is a need to assure that both driven MOSFETs are not on at the same time. The DT pin programs a
fixed time period delay between the turn-off of one gate driver until the turn-on of the next. This feature is an
improvement over the repeatability and accuracy of discrete solutions while eliminating a number of discrete
parts on the board. Converter efficiency is easily tuned with this one repeatable adjustment. The programmed
dead time is the same for both GATE-to-GAT2 and GAT2-to-GATE transitions. The dead time is triggered from
internal signals that are several stages back in the driver to eliminate the effects of gate loading on the period,
however the observed and actual dead-time will be somewhat dependent on the gate loading. The turnoff of
GAT2 coincides with the start of the internal clock period.
DT may be used to disable GAT2, which goes to a high-impedance state.
GATE’s phase turns the main switch on when it transitions high, and off when it transitions low. Likewise, GAT2’s
phase turns the second switch on when it transitions high, and off during the dead time. The signal phasing is
shown in Figure 1. Use of the two gate drives is shown in Figure 24 and the Typical Application Diagram.
FRS and Synchronization
The FRS pin programs the (free-running) oscillator frequency, and may also be used to synchronize the
TPS23785B converter to a higher frequency. The internal oscillator sets the maximum duty cycle at 78% and
controls the slope-compensation ramp circuit. Synchronization may be accomplished by applying a short pulse
(TSYNC) of magnitude VSYNC to FRS as shown in Figure 26. The synchronization pulse terminates the potential
on-time period, and the off-time period does not begin until the pulse terminates.
T2P, Startup and Power Management
T2P (type 2 PSE) is an active-low multifunction pin that indicates if:
[(PSE = Type_2) + (VAPD > 1.5 V) + (VCTL < 4 V) × (pd current limit ≠ Inrush)]
(5)
The term with VCTL prevents an optocoupler connected to the secondary-side from loading VC before the
converter is started. The APD terms allow the PD to operate from an adapter at high-power if a type 2 PSE is not
present, assuming the adapter has sufficient capacity. Applications must monitor the state of T2P to detect power
source transitions. Transitions could occur when a local power supply is added or dropped or when a PSE is
enabled on the far end. The PD may be required to adjust the load appropriately. The usage of T2P is
demonstrated in the Typical Application Diagram.
In order for a type 2 PD to operate at less than 13 W the first 80 ms after power application, the various delays
must be estimated and used by the application controller to meet the requirement. The bootup time of many
applications processors may be long enough to eliminate the need to do any timing.
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Thermal Shutdown
The dc/dc controller has an OTSD that can be triggered by heat sources including the VB regulator, GATE driver,
bootstrap current source, and bias currents. The controller OTSD turns off VB, the GATE driver, and forces the
VC control into an under-voltage state.
Adapter ORing
Many PoE-capable devices are designed to operate from either a wall adapter or PoE power. A local power
solution adds cost and complexity, but allows a product to be used if PoE is not available in a particular
installation. While most applications only require that the PD operate when both sources are present, the
TPS23785B supports forced operation from either of the power sources. Figure 23 illustrates three options for
diode ORing external power into a PD. Only one option would be used in any particular design. Option 1 applies
power to the TPS23785B PoE input, option 2 applies power between the TPS23785B PoE section and the power
circuit, and option 3 applies power to the output side of the converter. Each of these options has advantages and
disadvantages. Many of the basic ORing configurations and discussion contained in application note Advanced
Adapter ORing Solutions using the TPS23753 (literature number SLVA306), apply to the TPS23785B.
The IEEE standards require that the Ethernet cable be isolated from ground and all other system potentials. The
adapter must meet a minimum 1500 Vac dielectric withstand test between the output and all other connections
for ORing options 1 and 2. The adapter only needs this isolation for option 3 if it is not provided by the converter.
Adapter ORing diodes are shown for all the options to protect against a reverse voltage adapter, a short on the
adapter input pins, and damage to a low-voltage adapter. ORing is sometimes accomplished with a MOSFET in
option 3.
--
RCLS
D1
C1
From Spare
Pairs or
Transformers
VPOE
DEN
CLS
Low Voltage
Output
VDD1
RDEN
+
VDD
From Ethernet
Transformers
Optional for PoE Priority
Power
Circuit
VSS
TPS23785B
RTN
Adapter
Option 1
Adapter
Option 2
Adapter
Option 3
Figure 23. Adapter ORing Diodes
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Using DEN to Disable PoE
The DEN pin may be used to turn the PoE hotswap switch OFF by pulling it to VSS while in the operational state,
or to prevent detection when in the idle state. A low on DEN forces the hotswap MOSFET OFF during normal
operation. Additional information is available in the Advanced Adapter ORing Solutions using the TPS23753
(literature number SLVA306) application report.
ORing Challenges
Preference of one power source presents a number of challenges. Combinations of adapter output voltage
(nominal and tolerance), power insertion point, and which source is preferred determine solution complexity.
Several factors adding to the complexity are the natural high-voltage selection of diode ORing (the simplest
method of combining sources), the current limit implicit in the PSE, and PD inrush and protection circuits
(necessary for operation and reliability). Creating simple and seamless solutions is difficult if not impossible for
many of the combinations. However the TPS23785B offers several built-in features that simplify some
combinations.
Several examples will demonstrate the limitations inherent in ORing solutions. Diode ORing a 48 V adapter with
PoE (option 1) presents the problem that either source might be higher. A blocking switch would be required to
ensure which source was active. A second example is combining a 12 V adapter with PoE using option 2. The
converter will draw approximately four times the current at 12 V from the adapter than it does from PoE at 48 V.
Transition from adapter power to PoE may demand more current than can be supplied by the PSE. The
converter must be turned off while CIN capacitance charges, with a subsequent converter restart at the higher
voltage and lower input current. A third example is use of a 12 V adapter with ORing option 1. The PD hotswap
would have to handle four times the current, and have 1/16 the resistance (be 16 times larger) to dissipate equal
power. A fourth example is that MPS is lost when running from the adapter, causing the PSE to remove power
from the PD. If ac power is then lost, the PD will stop operating until the PSE detects and powers the PD.
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APPLICATION INFORMATION
The TPS23785B supports many power supply topologies that require a single PWM gate drive or two
complementary gate drives and will operate with current-mode control. The Typical Application Diagram and
Figure 24 provide an example of a synchronous-rectification flyback that uses the second gate driver to control
M2, the active element in the clamp. The TPS23785B may be used in topologies that do not require GAT2, which
may be disabled to reduce its idling loss.
Selecting a converter topology along with a design procedure is beyond the scope of this applications section.
Examples to help in programming the TPS23785B are shown below. Additional special topics are included to
explain the ORing capabilities, frequency dithering, and other design considerations.
From Ethernet
Pairs 1,2
For more specific converter design examples refer to the following application notes:
• Designing with the TPS23753 Powered Device and Power Supply Controller, SLVA305
• Advanced Adapter ORing Solutions using the TPS23753, SLVA306A
T1
DVC1
VT2P_OUT
VB
M2
ROB
CIZ
GAT2
RFBU
VB
GATE
CS
CCTL
RCTL
M1
TLV431
RFBL
RCS
CVC
T2
CVB
BLNK
RTN, COM
ARTN
DT
TPS23785B
COUT2
RT2P_OUT
RT2P
COUT1
VDD1
VDD
T2P
RBLNK
RFRS
RAPD1
RAPD2
Adapter
DA
VOUT
LOUT
VC
RDT
DEN
NC
CLS
PAD
VSS
APD
CTL
FRS
RCLS
0.1uF
From Ethernet
Pairs 3,4
58V
RDEN
CIN
CIO
Figure 24. Example of Isolated Converter with TPS23785B
Input Bridges and Schottky Diodes
Using Schottky diodes instead of PN junction diodes for the PoE input bridges and DVDD will reduce the loss of
this function by about 30%. There are however some things to consider when using them.
The IEEE standard specifies a maximum backfeed voltage of 2.8 V. A 100 kΩ resistor is placed between the
unpowered pairs and the voltage is measured across the resistor. Schottky diodes often have a higher reverse
leakage current than PN diodes, making this a harder requirement to meet. Use conservative design for diode
operating temperature, select lower-leakage devices where possible, and match leakage and temperatures by
using packaged bridges to help with this.
Schottky diode leakage current and lower dynamic resistance can impact the detection signature. Setting
reasonable expectations for the temperature range over which the detection signature is accurate is the simplest
solution. Increasing RDEN slightly may also help meet the requirement.
Schottky diodes have proven less robust to the stresses of ESD transients, failing as a short or becoming leaky.
Care must be taken to provide adequate protection in line with the exposure levels. This protection may be as
simple as ferrite beads and capacitors.
A general recommendation for the input rectifiers are 1 A or 2 A, 100 V rated discrete or bridge diodes.
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Protection, D1
A TVS, D1, across the rectified PoE voltage per Figure 25 must be used. An SMAJ58A, or a part with equivalent
or better performance, is recommended for general indoor applications. If an adapter is connected from VDD1 to
RTN, as in ORing option 2 above, voltage transients caused by the input cable inductance ringing with the
internal PD capacitance can occur. Adequate capacitive filtering or a TVS must limit this voltage to be within the
absolute maximum ratings. Outdoor transient levels or special applications require additional protection.
Use of diode DVDD for PoE priority may dictate the use of additional protection around the TPS23785B. ESD
events between the PD power inputs, or the inputs and converter output, cause large stresses in the hotswap
MOSFET if DVDD becomes reverse biased and transient current around the TPS23785B is blocked. The use of
CVDD and DRTN in Figure 25 provides additional protection should over-stress of the TPS23785B be an issue. An
SMAJ58A would be a good initial selection for DRTN. Individual designs may have to tune the value of CVDD.
VDD1
CIN
VDD
RDEN
DEN
CLS
COM
ARTN
VSS
RTN
RCLS
D1 58V
C 1 0.1?F
DVDD
D RTN
58V
From Spare
Pairs or
Transformers
From Ethernet
Transformers
C VDD
0.01?F
Figure 25. Example of Added ESD Protection for PoE Priority
Capacitor, C1
The IEEE 802.3at standard specifies an input bypass capacitor (from VDD to VSS) of 0.05 μF to 0.12 μF. Typically
a 0.1 μF, 100 V, 10% ceramic capacitor is used.
Detection Resistor, RDEN
The IEEE 802.3at standard specifies a detection signature resistance, RDEN between 23.75 kΩ and 26.25 kΩ, or
25 kΩ ± 5%. Choose an RDEN of 24.9 kΩ.
Classification Resistor, RCLS
Connect a resistor from CLS to VSS to program the classification current according to the IEEE 802.3at standard.
The class power assigned should correspond to the maximum average power drawn by the PD during operation.
Select RCLS according to Table 1.
For a high power design, choose class 4 and RCLS = 63.4 Ω.
APD Pin Divider Network, RAPD1, RAPD2
The APD pin can be used to disable the TPS23785B internal hotswap MOSFET giving the adapter source
priority over the PoE source. An example calculation is provided, see literature number SLVA306A.
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Setting Frequency (RFRS) and Synchronization
The converter switching frequency is set by connecting RFRS from the FRS pin to ARTN. The frequency may be
set as high as 1 MHz with some loss in programming accuracy as well as converter efficiency. Synchronization
at high duty cycles may become more difficult above 500 kHz due to the internal oscillator delays reducing the
available on-time. As an example:
1. Assume a desired switching frequency (fSW) of 250 kHz.
2. Compute RFRS:
17250
17250
RFRS (k W ) =
=
= 69
fSW (kHz)
250
(a)
(b) Select 69.8 kΩ.
VSYNC
TSYNC
RFRS
FRS
47pF
VSYNC
TSYNC
1000pF
RTN
ARTN
COM
47pF
Synchronization
Pulse
RFRS
FRS
RT
Synchronization
Pulse
RTN
ARTN
COM
The TPS23785B may be synchronized to an external clock to eliminate beat frequencies from a sampled system,
or to place emission spectrum away from an RF input frequency. Synchronization may be accomplished by
applying a short pulse (TSYNC) of magnitude VSYNC to FRS as shown in Figure 26. RFRS should be chosen so that
the maximum free-running frequency is just below the desired synchronization frequency. The synchronization
pulse terminates the potential on-time period, and the off-time period does not begin until the pulse terminates.
The pulse at the FRS pin should reach between 2.5 V and VB, with a minimum width of 22 ns (above 2.5 V) and
rise/fall times less than 10 ns. The FRS node should be protected from noise because it is high-impedance. An
RT on the order of 100 Ω in the isolated example reduces noise sensitivity and jitter.
1:1
Figure 26. Synchronization
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Current Slope Compensation
The TPS23785B provides a fixed internal compensation ramp that suffices for most applications. RS (see
Figure 27) may be used if the internally provided slope compensation is not enough.
Most current-mode control papers and application notes define the slope values in terms of VPP/TS (peak ramp
voltage / switching period), however the electrical characteristics table specifies the slope peak (VSLOPE) based
on the maximum (78%) duty cycle. Assuming that the desired slope, VSLOPE-D (in mV/period), is based on the full
period, compute RS per the following equation where VSLOPE, DMAX, and ISL-EX are from the electrical
characteristics table with voltages in mV, current in μA, and the duty cycle is unitless (e.g., DMAX = 0.78).
é
æ VSLOPE (mV) ö ù
ê VSLOPE_D (mV) - ç
÷ú
DMAX
è
ø ûú
ëê
´ 1000
RS (W) =
ISL_EX (mA)
(6)
RTN
COM
ARTN
GATE
CS
RS
CS
RCS
Figure 27. Additional Slope Compensation
CS may be required if the presence of RS causes increased noise, due to adjacent signals like the gate drive, to
appear at the CS pin.
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Blanking Period, RBLNK
Selection of the blanking period is often empirical because it is affected by parasitics and thermal effects of every
device between the gate-driver and output capacitors. The minimum blanking period prevents the current limit
and PWM comparators from being falsely triggered by the inherent current spike that occurs when the switching
MOSFET turns on. The maximum blanking period is bounded by the output rectifier's ability to withstand the
currents experienced during a converter output short.
If blanking beyond the internal default is desired choose RBLNK using RBLNK (kΩ) = tBLNK (ns).
1. For a 100 ns blanking interval
(a) RBLNK (kΩ) = 100
(b) Choose RBLNK = 100 kΩ.
The blanking interval can also be chosen as a percentage of the switching period.
1. Compute RBLNK as follows for 2% blanking interval in a switcher running at 250 kHz.
BIanking_Interval(%)
2
RBLNK (k W ) =
´ 10 4 =
´ 10 4 = 80
f
(kHz)
250
SW
(a)
(b) Select RBLNK = 80.6 kΩ.
Dead Time Resistor, RDT
The required dead time period depends on the specific topology and parasitics. The easiest technique to obtain
the optimum timing resistor is to build the supply and tune the dead time to achieve the best efficiency after
considering all corners of operation (load, input voltage, and temperature). A good initial value is 100 ns.
Program the dead time with a resistor connected from DT to ARTN per Equation 3.
1. Choose RDT as follows assuming a tDT of 100 ns:
t (ns)
100
RDT (kW) = DT
=
= 50
2
2
(a)
(b) Choose RDT = 49.9 kΩ
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TPS23785B
SLUSB90A – DECEMBER 2012 – REVISED DECEMBER 2012
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Estimating Bias Supply Requirements and CVC
The bias supply (VC) power requirements determine the CVC sizing and frequency of hiccup during a fault. The
first step is to determine the power/current requirements of the power supply control, then use this to select CVC.
The control current draw will be assumed constant with voltage to simplify the estimate, resulting in an
approximate value.
First determine the switching MOSFET gate drive power.
1. Let VQG be the gate voltage swing that the MOSFET QG is rated to (often 10 V).
æ
VC
PGATE = VC ´ fSW ´ ç QGATE ´
ç
VQG
è
ö
æ
VC
÷÷ PGAT2 = VC ´ fSW ´ çç QGATE2 ´
VQG
ø
è
ö
÷÷
ø
(a)
(b) Compute gate drive power if VC is 12 V, QGATE is 17 nC, and QGAT2 is 8 nC.
12
PGATE = 12 V ´ 250 kHz ´ 17 nC ´
= 61.2 mW
10
12
PG AT2 = 12 V ´ 250 kHz ´ 8 nC ´
= 28.8 mW
10
(c)
PDRIVE = 61.2 mW + 28.8 mW = 90 mW
(d) This illustrates why MOSFET QG should be an important consideration in selecting the switching
MOSFETs.
2. Estimate the required bias current at some intermediate voltage during the CVC discharge. For the
TPS23785B, 12 V provides a reasonable estimate. Add the operating bias current to the gate drive current.
P
90 mW
IDRIVE = DRIVE =
= 7.5 mA
V
12 V
C
(a)
(b) ITOTAL = IDRIVE + IOPERATING = 7.5 mA + 0.92 mA = 8.42 mA
3. Compute the required CVC based on startup within the typical softstart period of approximately 4 ms.
CVC1 + CVC2 =
TSTARTUP ´ ITOTAL
4 ms ´ 8.42 mA
=
= 5.18 mF
VCUVH
6.5 V
(a)
(b) For this case, a standard 10 μF electrolytic plus a 0.47 μF should be sufficient.
4. Compute the initial time to start the converter when operating from PoE.
(a) Using a typical bootstrap current of 4 mA, compute the time to startup.
C
´ VCUV
10.47 mF ´ 15 V
TST = VC1
=
= 39 ms
IVC
4 mA
(b)
5. Compute the fault duty cycle and hiccup frequency
(C VC1 + CVC2 ) ´ VCUVH
(10 mF + 0.47 mF) ´ 6.5 V
TRECHARGE =
=
= 17 m s
IVC
4 mA
(a)
(C VC1 + CVC2 ) ´ VCUVH
(10 mF + 0.47 mF) ´ 6.5V
TDISCHARGE =
=
= 8.08 ms
ITOTAL
8.42 m A
(b)
(a) Note that the optocoupler current is 0 mA because the output is in current limit.
(b) Also, it is assumed IT2P is 0 mA.
TDISCHARGE
8.08 ms
Duty Cycle: D =
=
= 32%
T
+
T
8.08
ms + 17 ms
DISCHARGE
RECHARGE
(c)
1
1
Hiccup Frequency: F =
=
= 39.9 Hz
T
+
T
8.08
ms
+ 17 ms
DISCHARGE
RECHARGE
(d)
6. With the TPS23785B, the voltage rating of CVC1 and CVC2 should be 25 V minimum.
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TPS23785B
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SLUSB90A – DECEMBER 2012 – REVISED DECEMBER 2012
Switching Transformer Considerations and RVC
Care in design of the transformer and VC bias circuit is required to obtain hiccup overload protection. Leadingedge voltage overshoot on the bias winding may cause VC to peak-charge, preventing the expected tracking with
output voltage. Some method of controlling this is usually required. This may be as simple as a series resistor, or
an R-C filter in front of DVC1. Good transformer bias-to-output-winding coupling results in reduced overshoot and
better voltage tracking.
RVC as shown in Figure 28 helps to reduce peak charging from the bias winding. This becomes especially
important when tuning hiccup mode operation during output overload. Typical values for RVC will be between 10
Ω and 100 Ω.
ARTN
RVC
DVC1
T1
Bias Winding
CVC
VC
Figure 28. RVC Usage
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TPS23785B
SLUSB90A – DECEMBER 2012 – REVISED DECEMBER 2012
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T2P Pin Interface
The T2P pin is an active low, open-drain output indicating a high power source is available. An optocoupler is
typically used to interface with the T2P pin to signal equipment on the secondary side of the converter of T2P
status. Optocoupler current-gain is referred to as CTR (current transfer ratio), which is the ratio of transistor
collector current to LED current. To preserve efficiency, a high-gain optocoupler ( 250% ≤ CTR ≤ 500%, or 300%
≤ CTR ≤ 600% ) along with a high-impedance (e.g., CMOS) receiver are recommended. Design of the T2P
optocoupler interface can be accomplished as follows:
1. T2P ON characteristic: IT2P = 2 mA minimum, VT2P = 1 V
2. Let VC = 12 V, VOUT = 5 V, RT2P-OUT = 10 kΩ, VT2P-OUT (low) = 400 mV max
V
- VT2P-OUT (low)
5 - 0.4
IRT2P-OUT = OUT
=
= 0.46 m A
R
10000
T2P-OUT
(a)
3. The optocoupler CTR will be needed to determine RT2P. A device with a minimum CTR of 300% at 5 mA
LED bias current is selected. CTR will also vary with temperature and LED bias current. The strong variation
of CTR with diode current makes this a problem that requires some iteration using the CTR versus IDIODE
curve on the optocoupler data sheet.
(a) Using the (normalized) curves, a current of 0.4 mA to 0.5 mA is required to support the output current at
the minimum CTR at 25°C.
(a) Pick an IDIODE. For example one around the desired load current.
(b) Use the optocoupler datasheet curve to determine the effective CTR at this operating current. It is
usually necessary to apply the normalized curve value to the minimum specified CTR. It might be
necessary to ratio or offset the curve readings to obtain a value that is relative to the current that the
CTR is specified at.
(c) If IDIODE × CTRI_DIODE is substantially different from IRT2P_OUT, choose another IDIODE and repeat.
(b) This manufacturer’s curves also indicate a –20% variation of CTR with temperature. The approximate
forward voltage of the optocoupler diode is 1.1 V from the data sheet.
100
100
IRT2P @ IMIN ´
= 0.5 mA ´
= 0.625 mA
100 - D CTRTEMP
100 - 20
(c) VFLED = 1.1 V
V - VT2P - VFLED
12 - 1 - 1.1
RT2P = C
=
= 15.48 kW
IRT2P
0.625 mA
(d) Select a 15.4 kΩ resistor. Even though the minimum CTR and temperature variation were considered,
the designer might choose a smaller resistor for a little more margin.
VOUT
VC
RT2P
RT2P_OUT
Type 2 PSE
Indicator
Low = T2
T2P From
TPS23785B
Figure 29. T2P Interface
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TPS23785B
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SLUSB90A – DECEMBER 2012 – REVISED DECEMBER 2012
Softstart
Converters require a softstart on the voltage error amplifier to prevent output overshoot on startup. Figure 30
shows a common implementation of a secondary-side softstart that works with the typical TL431 error amplifier.
The softstart components consist of DSS, RSS, and CSS. They serve to control the output rate-of-rise by pulling
VCTL down as CSS charges through ROB, the optocoupler, and DSS. This has the added advantage that the TL431
output and CIZ are preset to the proper value as the output voltage reaches the regulated value, preventing
voltage overshoot due to the error amplifier recovery. The secondary-side error amplifier will not become active
until there is sufficient voltage on the secondary. The TPS23785B provides a primary-side softstart which
persists long enough (~4 ms) for secondary side voltage-loop softstart to take over. The primary-side currentloop softstart controls the switching MOSFET peak current by applying a slowly rising ramp voltage to a second
PWM control input. The PWM is controlled by the lower of the softstart ramp or the CTL-derived current demand.
The actual output voltage rise time is usually much shorter than the internal softstart period. Initially the internal
softstart ramp limits the maximum current demand as a function of time. Either the current limit, secondary-side
softstart, or output regulation assume control of the PWM before the internal softstart period is over. Figure 21
shows a smooth handoff between the primary and secondary-side softstart with minimal output voltage
overshoot.
From Regulated
Output Voltage
ROB
RSS
CIZ
DSS
CSS
RFBU
RFBL
TLV431
Figure 30. Error Amplifier Soft Start
Thermal Considerations and OTSD
Sources of nearby local PCB heating should be considered during the thermal design. Typical calculations
assume that the TPS23785B is the only heat source contributing to the PCB temperature rise. It is possible for a
normally operating TPS23785B device to experience an OTSD event if it is excessively heated by a nearby
device.
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TPS23785B
SLUSB90A – DECEMBER 2012 – REVISED DECEMBER 2012
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Frequency Dithering for Conducted Emissions Control
The international standard CISPR 22 (and adopted versions) is often used as a requirement for conducted
emissions. Ethernet cables are covered as a telecommunication port under section 5.2 for conducted emissions.
Meeting EMI requirements is often a challenge, with the lower limits of Class B being especially hard. Circuit
board layout, filtering, and snubbing various nodes in the power circuit are the first layer of control techniques. A
more detailed discussion of EMI control is presented in Practical Guidelines to Designing an EMI Compliant PoE
Powered Device With Isolated Flyback, TI literature number SLUA469. Additionally, IEEE802.3at sections 33.3
and 33.4 have requirements for noise injected onto the Ethernet cable based on compatibility with data
transmission.
Occasionally, a technique referred to as frequency dithering is utilized to provide additional EMI measurement
reduction. The switching frequency is modulated to spread the narrowband individual harmonics across a wider
bandwidth, thus lowering peak measurements. The circuit of Figure 31 modulates the switching frequency by
feeding a small ac signal into the FRS pin. These values may be adapted to suit individual needs.
10kW
49.9kW
VB
+
-
6.04kW
TL331IDBV
4.99kW
0.01mF
10kW
301kW
1mF
To
FRS
ARTN
Figure 31. Frequency Dithering
REVISION HISTORY
Changes from Original (December 2012) to Revision A
•
40
Page
Changed PRODUCT INFORMATION table. ........................................................................................................................ 2
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS23785BPWP
ACTIVE
HTSSOP
PWP
24
60
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
TPS23785B
TPS23785BPWPR
ACTIVE
HTSSOP
PWP
24
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
TPS23785B
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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