TPS2459RHBR

厂商：
BURR-BROWN(德州仪器)
封装：
VQFN-32_5X5MM-EP
描述：
IC HOT SWAP CONTROLLER I2C 32QFN

数据手册：

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数据手册
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TPS2459RHBR 数据手册

TPS2459 www.ti.com SLUS917E – FEBRUARY 2009 – REVISED MAY 2013 12-V/3.3-V Hot Swap and ORing Controller with I2C™ and Load Current Monitor for AdvancedMC™ Check for Samples: TPS2459 FEATURES APPLICATIONS • • • • • • • 1 23 • • • • • • • • • ATCA AdvancedMC™ Compliant Full Power Control for an AdvancedMC™ Module Independently Programmable 12-V Current Limit and Fast Trip 3.3-V and 12-V FET ORing Control for MicroTCA™ 12-V Output Shuts Off If 3.3-V Output Shuts Off Internal 3.3-V Current Limit and ORing I2C™ Power Good and Fault Reporting I2C™ Programmable Fault Times and Limits FET Status Bits for 3.3-V and 12-V Channels Load Current Monitors for 12-V and 3.3-V 32-Pin QFN Package ATCA Carrier Boards MicroTCA™Power Modules AdvancedMC™ Slots Systems Using 12-V and 3.3-V Channels Base Stations DESCRIPTION The TPS2459 hot-plug controller performs all necessary power interface functions for an AdvancedMC™ (Advanced Mezzanine Card). A fully integrated 3.3-V channel provides inrush control, over-current protection, and FET ORing. A 12-V channel provides the same functions using external FETs and sense resistors. The 3.3-V current limit is factory set to AdvancedMC™ compliant levels while the 12-V current limit is programmed using external sense resistors. The accurate current sense comparators of the TPS2459 satisfy the narrow ATCA™ AdvancedMC™ current limit requirements. TYPICAL APPLICATION 0.005 W 12 V VIN 12 V 100 W 422 W 15 3.3 V VIN 14 13 12 16 IN3 IN12 SENP SET { { Enable I2C Interface 11 6 AdvancedMCTM 8 SENM PASS BLK OUT12 OUT3 17 22 VDD3 PG12 4 28 EN12 FLT12 7 TPS2459 10 OREN SDA 3 SCL 1 VINT Status Outputs PG3 20 26 EN3 2 3.3 V FLT3 19 6810 W SUM12 5 3320 W A0 A1 A2 30 18 25 GND SUM3 21 UDG-09031 1 2 3 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. AdvancedMC, MicroTCA are trademarks of PCI Industrial Computer Manufacturers Group. I2C is a trademark of Phillips. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2009–2013, Texas Instruments Incorporated TPS2459 SLUS917E – FEBRUARY 2009 – REVISED MAY 2013 www.ti.com ORDERING INFORMATION DEVICE TEMPERATURE PACKAGE ORDERING CODE MARKING TPS2459 -40°C to 85°C QFN-32 TPS2459RHB TPS2459 ABSOLUTE MAXIMUM RATINGS (1) over –40°C ≤ TJ ≤ 85°C (unless otherwise noted) VALUE BLK, PASS 0 to 30 IN12, OUT12, SENM, SENP, SET, EN12 0 to 17 EN3 , IN3, OUT3, OREN, SCL, SDA, SUM, VDD, 0 to 5 AGND, GND 0 to VINT Human Body Model 2 Charged Device Model kV 0.5 SUMx 5 VINT –1 to 1 OUT3 continuous current (1) V –0.3 to 0.3 A0, A1, A2 ESD UNIT mA 250 Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only. Functional operation of the device under any conditions beyond those indicated under recommended operating conditions is neither implied nor guaranteed. Exposure to absolute maximum rated conditions for extended periods of time may affect device reliability. DISSIPATION RATINGS PACKAGE θJA HIGH-K (°C/W) θJA LOW-K (°C/W) QFN32 - RHB 34 93 RECOMMENDED OPERATING CONDITIONS over –40°C ≤ TJ ≤ 85°C (unless otherwise noted) PARAMETER VIN12 VIN3 VVDD3 12-V input supply 3.3-V input supply IOUT3 3.3-V output current ISUMx Summing pin current MAX 12 15 3 3.3 4 3 3.3 4 100 -1 VINT bypass capacitance 2 TYP 8.5 165 PASS pin board leakage current TJ MIN 1 Operating junction temperature range -40 Submit Documentation Feedback 1000 1 10 UNIT V mA μA 250 nF 125 °C Copyright © 2009–2013, Texas Instruments Incorporated Product Folder Links: TPS2459 TPS2459 www.ti.com SLUS917E – FEBRUARY 2009 – REVISED MAY 2013 ELECTRICAL CHARACTERISTICS over –40°C ≤ TJ ≤ 85°C, VIN3 =VVDD3 = 3.3 V, VIN12 = VSENP = VSENM = VSETP = 12 V, VEN3=VEN12=logic 1 or open, VAGND = VGNDA = VGNDB = 0 V, VSUM12 = 6.8 kΩ to GND, , VSUM3 = 3.3 kΩ to GND. All other pins OPEN, all I2C™ bits at different values, all voltages referenced to GND. (unless otherwise noted) PARAMETER CONDITIONS MIN TYP MAX UNITS 1.2 1.3 1.4 V 20 50 80 mV 5 8 15 VEN12 =VOREN = 17 V 6 15 VEN3 = 5 V 1 ENABLE INPUTS Threshold voltage, falling edge Hysteresis Pullup current Input bias current VEN =VOREN = 0 V µA 5 3.3-V Turn off time EN3 deasserts to VVOUT3 < 1.0 V, COUT = 0 μF 10 12-V Turn off time EN12 deasserts to VVOUT12 < 1.0 V, COUT = 0 μF, CQGATE = 35 nF 20 µs POWER GOOD COMPARATORS Threshold voltage Hysteresis PG12, falling OUT12 PG3, falling OUT3 10.2 10.5 10.8 2.7 2.8 2.9 PG12, measured at OUT12 130 PG3, measured at OUT3 V mV 50 INTERNAL 2.35-V RAIL Output voltage 0 V < IVINT < 50 μA 2.0 2.3 0.70% 0.77% 2.8 V FAULT TIMER Fault time bit weight 3xFT[4:0] = 12xFT[4:0] = 00001B Retry duty cycle D = tFAULT/tDELAY 0.45 ms 0.80% 12-V SUMMING NODE Input referred offset 10.8 V ≤ VSENM ≤ 13.2 V, VSENP = (VSENM + 50 mV), measure VSET– VSENM –1.5 Summing threshold 12CL[3:0] = 1111B, VPASS = 15 V 0.66 Leakage current VSET =(VSENM – 10 mV) 1.5 0.675 mV 0.69 V 1 µA 50 52.5 mV 40 µA 100 120 mV 12-V CURRENT LIMIT Current limit threshold RSUM = 6.8 kΩ, RSET = 422 Ω, increase ILOAD and measure VSENP – VSENM when VPASS = 15 V Sink current in current limit IPASS measured at VSUM = 1 V and VPASS = 12 V 20 Fast trip threshold Measure VSENP – VSENM 80 Fast turn-off delay 20 mV overdrive, CPASS = 0 pF, tp50-50 Bleed-down resistance VOUT = 6 V Bleed-down threshold Timer start threshold VPASS - VIN when timer starts, while VPASS falling due to overcurrent 47.5 200 300 ns 1.1 1.6 2.1 kΩ 75 100 130 mV 5 6 7 Submit Documentation Feedback Copyright © 2009–2013, Texas Instruments Incorporated Product Folder Links: TPS2459 V 3 TPS2459 SLUS917E – FEBRUARY 2009 – REVISED MAY 2013 www.ti.com ELECTRICAL CHARACTERISTICS (continued) over –40°C ≤ TJ ≤ 85°C, VIN3 =VVDD3 = 3.3 V, VIN12 = VSENP = VSENM = VSETP = 12 V, VEN3=VEN12=logic 1 or open, VAGND = VGNDA = VGNDB = 0 V, VSUM12 = 6.8 kΩ to GND, , VSUM3 = 3.3 kΩ to GND. All other pins OPEN, all I2C™ bits at different values, all voltages referenced to GND. (unless otherwise noted) PARAMETER CONDITIONS MIN TYP MAX UNITS 12-V UVLO UVLO rising IN12 rising 8.1 8.5 8.9 UVLO hysteresis IN12 falling 0.44 0.5 0.59 V 12-V BLOCKING Turn-on threshold Measure VSENP – VVOUT 5 10 15 Turn-off threshold Measure VSENP – VVOUT –6 –3 0 Turn-off delay 20-mV overdrive, CBLK = 0 pF, tP50-50 200 300 ns 21.5 23 24.5 V 40 µA mV 12-V GATE DRIVERS (PASS, BLK) Output voltage VVIN12 = VVOUT12 = 10 V Sourcing current VVIN12 = VVOUT12 = 10 V, VPASS= VBLK = 17 V 20 30 Fast turnoff, VPASS = VBLK = 14 V 0.5 1 6 14 25 mA 14 20 26 kΩ 5 10 15 μs 0.25 ms 675 695 mV 290 500 mΩ 170 195 225 240 300 400 750 1300 280 400 500 Ω 75 100 130 mV Sinking current 4 V ≤ VPASS = VBLK ≤ 25 V Pulldown resistance In OTSD ( at 150°C ) Fast turn-off duration Startup time IN12 rising to PASS and BLK sourcing A 3.3-V SUMMING NODE Summing threshold 655 3.3-V CURRENT LIMIT On-resistance IOUT3 = 150 mA Current limit RSUM3 = 3.3 kΩ , VVOUT3 = 0 V Fast trip threshold Fast turn-off delay IOUT3= 400 mA, tP50-50 Bleed-down resistance VOUT3= 1.65 V Bleed-down threshold mA ns 3.3-V UVLO UVLO rising IN3 rising 2.65 2.75 2.85 V UVLO hysteresis IN3 falling 200 240 300 mV 3.3-V BLOCKING Turn-on threshold Measure VIN3 – VOUT3 5 10 15 mV Turn-off threshold Measure VIN3 – VOUT3 –5 –3 0 mV ORing turn-on delay time VIN3 = 3.3 V, VOUT3 = 3.5 V, ROUT3 = 100 Ω to GND, VORON = 1. Remove 3.5 V from OUT3. Measure time from VOUT3 decreasing thru 2.9 V to VOUT3 = 3.2 V 300 350 μs 20 mV overdrive, tP50-50 250 350 ns 15 mA Fast turnoff delay time Safety gate pulldown current (1) Slew IN3x, Out3x, 5-V in 1 μs SUPPLY CURRENTS (IIN+ISENP+ISENM+ISET+IVDD) Both channels enabled IOUT3A = IOUT3B= 0 Both channels disabled 3.1 4 2.0 2.8 mA THERMAL SHUTDOWN Whole-chip shutdown temperature TJ rising, IOUT3A = IOUT3B= 0 A 140 150 3.3-V channel shutdown temperature TJ rising, IOUT3A or IOUT3B in current limit 130 140 Hysteresis Whole chip or 3.3-V channel (1) 4 °C 10 When setting an address bit to a logic 1 the pin should be connected to VINT. Submit Documentation Feedback Copyright © 2009–2013, Texas Instruments Incorporated Product Folder Links: TPS2459 TPS2459 www.ti.com SLUS917E – FEBRUARY 2009 – REVISED MAY 2013 ELECTRICAL CHARACTERISTICS (continued) over –40°C ≤ TJ ≤ 85°C, VIN3 =VVDD3 = 3.3 V, VIN12 = VSENP = VSENM = VSETP = 12 V, VEN3=VEN12=logic 1 or open, VAGND = VGNDA = VGNDB = 0 V, VSUM12 = 6.8 kΩ to GND, , VSUM3 = 3.3 kΩ to GND. All other pins OPEN, all I2C™ bits at different values, all voltages referenced to GND. (unless otherwise noted) PARAMETER CONDITIONS MIN TYP MAX UNITS 0.37 V I2C™ SERIAL INTERFACE (SDA, SCL, A0, A1, A2) Lower logic threshold A0, A1, A2 0.33 0.35 Upper logic threshold A0, A1, A2 1.32 1.35 1.38 V Input pullup resistance A0, A1, A2, (VAx – 0 V) 400 700 1000 kΩ Input pulldown resistance A0, A1, A2, (VAx – VVINT) (2) 200 350 550 kΩ Input open-circuit voltage IA = 0 V 0.5 0.8 1.0 V Threshold voltage, rising SDA, SCL 2.3 V Threshold voltage, falling SDA, SCL 1.0 V Hysteresis SDA, SCL 165 mV Leakage SDA, SCL 1 μA Input clock frequency SCL 400 kHz Low-level output voltage ISDA = 3 mA 0.4 V Input clock low duration SCL 1.3 μs Input clock high duration SCL 0.6 μs Data setup time SDA 100 ns Data hold time SDA Output fall time 300 900 SDA, 2.3 V–1.0 V, CBUS = 10 pF 21 250 SDA, 2.3 V–1.0 V, CBUS = 400 pF 60 250 0 50 ns 10 pF Deglitch time SDA, pulse width suppressed Capacitance CSDA, CSCL (2) ns ns When setting an address bit to a logic 1 the pin should be connected to VINT. Submit Documentation Feedback Copyright © 2009–2013, Texas Instruments Incorporated Product Folder Links: TPS2459 5 TPS2459 SLUS917E – FEBRUARY 2009 – REVISED MAY 2013 www.ti.com TPS2459 FUNCTIONAL BLOCK DIAGRAMS 12-V Channel Circuitry 12V IN RSENSE RSET SENP 100 W SET SENM PASS 100 W BLK OUT12 pgat\ 100 mv 12dis + 30 uA ogat 30 uA Q Pump 10 us + IN12 10 us Fault Timer Vcp ~25 V Vcp FLT12 to I2C EN12 PG3\ 675 mV x (12xCL/1111) RSUM + SUM12 to I2C 10 mv OUT + 6810 out12 pgat\ R S -3 mv + Q + ogat 100 us PG12 vpg Q 12OR [R3:7] OREN Optional Oring FET for Redundant Power Feed Systems 6 Submit Documentation Feedback Copyright © 2009–2013, Texas Instruments Incorporated Product Folder Links: TPS2459 TPS2459 www.ti.com SLUS917E – FEBRUARY 2009 – REVISED MAY 2013 3.3-V Channel Circuitry 0.1 W IN3 OUT3 2.8 V 96 W + gat en 30 mV 30 ms + PG3 12dis Q Pump 30 mA + VDD3 Fault Timer vcpx ~25 V PG3 to I2C vcpx FLT3 30 ms EN3 Control Logic SUM3 FLT3 to I2C + RSUM vthoc - [ 675 mV nominal ] 3300 Circuitry Common to Both Channels VINT por en IN12 PREREG Control Logic POR OUT12 2.2 V IN3 OUT3 AGND GND GND GND GND GND GND GND Submit Documentation Feedback Copyright © 2009–2013, Texas Instruments Incorporated Product Folder Links: TPS2459 7 TPS2459 SLUS917E – FEBRUARY 2009 – REVISED MAY 2013 www.ti.com DEVICE INFORMATION GNDN A0 GNDA EN12 GNDE EN3 32 31 30 29 28 27 26 A2 NC TPS2459 (Top View) VINT 1 25 24 GNDS SDA 2 23 AGND SCL 3 22 VDD3 PG12 4 12-V Inputs SUM12 5 21 SUM3 20 PG3 19 FLT3 18 A1 17 OUT3 PowerPADTM BLK 6 9 10 11 12 13 14 15 16 OREN PASS SENM SET SENP IN12 IN3 OUT12 8 GNDB FLT12 7 3-V Inputs 12-V Inputs Figure 1. TERMINAL FUNCTIONS PIN NO. I/O A0 30 I I2C™ address programming bit, LSB A1 18 I I2C™ address programming bit, LSB+1 A2 25 I I2C™ address programming bit, LSB+2 AGND 23 — Analog ground. Ground pin for the analog circuitry insideBypass capacitor connection point for internal supply the TPS2459. BLK 6 O 12-V blocking transistor gate drive. Gate drive pin for the 12-V channel BLK FET. This pin sources 30 μA to turn the FET on. An internal clam prevents this pin from rising more than 14.5 V above OUT12. Setting the OREN pin high holds the BLK pin low. EN12 28 I 12-V enable. (active high). Pulling this pin low turns off the 12-V channel by pulling both BLK and PASS low. An internal 200-kΩ resistor pulls this pin up to VINT when disconnected. EN3 26 I 3-V enable. (active high) Pulling this pin low turns off the 3-V channel by pulling the gate of the internal pass FET to GND. An internal 200-kΩ resistor pulls this pin up to VINT when disconnected. FLT12 7 O 12-V fault output (active low) Open-drain output indicating that channel 12 has remained in current limit long enough to time out the fault timer and shut the channel down. asserted when 12-V fault timer runs out FLT3 19 O 3-V fault output (active low) Open-drain output indicating that channel 3 has remained in current limit long enough to time out the fault timer and shut the channel down. asserted when 3-V fault timer runs out GNDA 29 GNDB 9 — 12-V power ground. GNDE 27 GNDN 31 — Ground. GNDS 24 IN3 16 IN12 NC NAME 8 DESCRIPTION I 3-V input. Supply pin for the 3-V channel internal pass FET. 15 I 12-V input. Supply pin for 12-V channel internal circuitry. 32 — No connection. Submit Documentation Feedback Copyright © 2009–2013, Texas Instruments Incorporated Product Folder Links: TPS2459 TPS2459 www.ti.com SLUS917E – FEBRUARY 2009 – REVISED MAY 2013 TERMINAL FUNCTIONS (continued) PIN NO. I/O 10 I OUT12 8 I/O 12-V output. Senses the output voltage of the 12-V channel. OUT3 17 I/O 3-V output. Output of the 3-V channel internal pass FET. PASS 11 O 12-V pass transistor gate drive. This pin sources 30 μA to turn the FET on. An internal clamp prevents this pin from rising more than 14.5 V above IN12. PG12 4 O 12-V power good output,asserts when VOUT12 > V PG12 ( active low) . Open-drain output indicating that channel 12 output voltage has dropped below the PG threshold, which nominally equals 10.5 V. PG3 20 O 3-V power good output, asserts when VOUT3 > 2.8 V ( active low) . Open-drain output indicating that channel 3 output voltage has dropped below the PG threshold, which nominally equals 2.85 V. SCL 3 I Serial clock input for the I2C™ data line. (See TPS2459 I2C™ Interface section for details.) SDA 2 I/O SENM 12 I 12-V current limit sense. Senses the voltage on the low side of the 12-V channel current sense resistor. SENP 14 I 12-V input sense. Senses the voltage on the high side of the 12-V channel current sense resistor. SET 13 I 12-V current limit set. A resistor connected from this pin to SENP sets the current limit level in conjunction with the current sense resistor and the resistor connected to the SUM12 pin, as described in 12-V thresholds, setting current limit and fast overcurrent trip section. SUM12 5 I/O 12-V summing node. A resistor connected from this pin to ground forms part of the channel x current limit. As the current delivered to the load increases, so does the voltage on this pin. When the voltage on this pin reaches 675 mV, the current limit amplifier acts to prevent the current from further increasing. SUM3 21 I/O 3-V summing node. A resistor connected from this pin to ground forms part of the channel x current limit. As the current delivered to the load increases, so does the voltage on this pin. When the voltage on this pin reaches 675 mV, the current limit amplifier acts to prevent the current from further increasing. VDD3 22 I VINT 1 I/O NAME OREN DESCRIPTION 12-V blocking transistor enable. (active high). Pulling this pin high (or allowing it to float high) allows the 12-V channel ORing function to operate normally. Pulling this pin low disables the 12-V ORing function by pulling the BLK pin low. An internal 200-kΩ resistor pulls this pin up to VINT when disconnected. Bidirectional I2C™ data line. (See TPS2459 I2C™ Interface section for details.) 3-V charge pump input Bypass capacitor connection point for internal supply. This pin connects to the internal 2.35-V rail. A 0.1-μF capacitor must be connected from this pin to ground. Do not connect other external circuitry to this pin except the address programming pins, as required. Submit Documentation Feedback Copyright © 2009–2013, Texas Instruments Incorporated Product Folder Links: TPS2459 9 TPS2459 SLUS917E – FEBRUARY 2009 – REVISED MAY 2013 www.ti.com TYPICAL CHARACTERISTICS ORING TURN-OFF THRESHOLD vs JUNCTION TEMPERATURE ORING TURN-ON THRESHOLD vs JUNCTION TEMPERATURE 0 VTURNOFF – ORing Turn-on Threshold – mV VTURNON – ORing Turn-on Threshold – mV 12 11 10 9 8 -50 0 50 100 –1 –2 –3 –4 –5 -50 150 TJ – Junction Temperature – °C 100 Figure 2. Figure 3. 12-V TURN OFF VOLTAGE THRESHOLD vs JUNCTION TEMPERATURE 12-V TURN ON THRESHOLD vs JUNCTION TEMPERATURE 150 12.0 VTURNON12 –Turn On Threshold – mV VTURNOFF12 –Turn Off Threshold – mV 50 TJ – Junction Temperature – °C 0 -1 -2 -3 -4 -5 11.5 11.0 10.5 10.0 9.5 9.0 8.5 8.0 -50 0 50 100 150 -50 TJ – Junction Temperature – °C Figure 4. 10 0 0 50 100 150 TJ – Junction Temperature – °C Figure 5. Submit Documentation Feedback Copyright © 2009–2013, Texas Instruments Incorporated Product Folder Links: TPS2459 TPS2459 www.ti.com SLUS917E – FEBRUARY 2009 – REVISED MAY 2013 TYPICAL CHARACTERISTICS (continued) 12-V INPUT CURRENT vs JUNCTION TEMPERATURE 3-V INPUT CURRENT vs JUNCTION TEMPERATURE 2.4 0.26 VIN = 12 V 2.3 IDD_3V – Input Current – mA IDD_12V – Input Current – mA 0.25 2.2 2.1 0.24 0.23 0.22 0.21 2.0 0.20 -50 0 50 100 150 -50 TJ – Junction Temperature – °C 50 100 Figure 6. Figure 7. 12-V INPUT CURRENT vs INPUT VOLTAGE 12-V CURRENT LIMIT THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE 150 51.0 VILIM – Current Limit Threshold Voltage – mV 2.45 2.40 IDD – Input Current – mA 0 TJ – Junction Temperature – °C 2.35 2.30 2.25 2.20 2.15 2.10 VIN = 12 V 50.8 50.6 50.4 50.2 50.0 10 11 12 13 14 -50 0 50 100 150 TJ – Junction Temperature – °C VIN – Input Voltage – V Figure 8. Figure 9. Submit Documentation Feedback Copyright © 2009–2013, Texas Instruments Incorporated Product Folder Links: TPS2459 11 TPS2459 SLUS917E – FEBRUARY 2009 – REVISED MAY 2013 www.ti.com TYPICAL WAVEFORMS 12 Figure 10. OUT3 Startup Into 22-Ω, (150 mA), 150-μF Load . . Figure 11. OUT3 Load Stepped from 165 mA to 240 mA . . Figure 12. OUT3 Short Circuit Under Full Load, (165 mA), Zoom View . . Figure 13. OUT3 Short Circuit Under Full Load, (165 mA), Wide View . . Submit Documentation Feedback Copyright © 2009–2013, Texas Instruments Incorporated Product Folder Links: TPS2459 TPS2459 www.ti.com SLUS917E – FEBRUARY 2009 – REVISED MAY 2013 TYPICAL WAVEFORMS (continued) Figure 14. OUT3 Startup Into Short Circuit . . Figure 15. OUT12 Startup Into 500-Ω, 830-μF Load . . Figure 16. OUT12 Startup Into 80-W, 830-μF Load . . Figure 17. OUT12 Short Circuit Under Full Load, (6.7 A), Wide View . . Submit Documentation Feedback Copyright © 2009–2013, Texas Instruments Incorporated Product Folder Links: TPS2459 13 TPS2459 SLUS917E – FEBRUARY 2009 – REVISED MAY 2013 www.ti.com TYPICAL WAVEFORMS (continued) Figure 18. OUT12 Short Circuit Under Full Load, (6.7 A), Zoom View . . Figure 19. OUT12 Startup Into Short Circuit . . Figure 20. OUT12 Overloaded While Supplying 6.7 A . . 14 Submit Documentation Feedback Copyright © 2009–2013, Texas Instruments Incorporated Product Folder Links: TPS2459 TPS2459 www.ti.com SLUS917E – FEBRUARY 2009 – REVISED MAY 2013 Control and Status Registers Seven 8-bit registers are used to control and read the status of the TPS2459. Registers 3 and 4 control the 12-V channel. Rregister 5 controls the 3-V channel. Register 6 contains eight general configuration bits. Read-only registers 7, 8, and 9 report back system status to the I2C™ controller. All ten registers use the I2C™ protocol and are organized as follows shown in Table 1. Table 1. Top Level Register Functions FUNCTION REGISTE R READ WRITE 3 √ √ 4 √ √ VOLTAGE (V) 3.3 DESCRIPTION 12 √ Set 12-V current limit, power good level, and OR functions Set 12-V fault time, enable, and bleed-down functions √ √ √ √ √ System configuration controls 7 √ √ √ Fault and PG outputs 8 √ √ Overcurrent and fast trip indicators are latched 9 √ √ Channel status indicators 5 6 √ √ Set 3-V fault time, enable, and bleed-down functions Submit Documentation Feedback Copyright © 2009–2013, Texas Instruments Incorporated Product Folder Links: TPS2459 15 TPS2459 SLUS917E – FEBRUARY 2009 – REVISED MAY 2013 www.ti.com Summary of Registers Table 2. Summary of Registers BIT NAME DEFAULT DESCRIPTION REGISTER 3 READ/WRITE 12-V CHANNEL CONFIGURATION 0 12CL0 1 Clearing bit reduces 12-V current limit and fast threshold by 5%. 1 12CL1 1 Clearing bit reduces 12-V current limit and fast threshold by 10%. 2 12CL2 1 Clearing bit reduces 12-V current limit and fast threshold by 20%. 3 12CL3 1 Clearing bit reduces 12-V current limit and fast threshold by 40%. 4 12PG0 1 Clearing bit reduces 12-V power good threshold by 600 mV. 5 12PG1 1 Clearing bit reduces 12-V power good threshold by 1.2 V. 6 12HP 0 Setting bit shifts 12 OR VTURNOFF from –3 mV to +3 mV nominal. 7 12OR 1 Clearing bit turns off 12-V ORing FET by pulling BLK low. REGISTER 4 READ/WRITE 12-V CHANNEL CONFIGURATION 0 12FT0 1 Setting bit increases 12-V fault time by 0.45 ms. 1 12FT1 0 Setting bit increases 12-V fault time by 0.9 ms. 2 12FT2 0 Setting bit increases 12-V fault time by 1.8 ms. 3 12FT3 0 Setting bit increases 12-V fault time by 3.6 ms. 4 12FT4 0 Setting bit increases 12-V fault time by 7.2 ms. 5 12EN 0 Clearing bit disables 12-V by pulling PASSB and BLKB to 0 V. 6 12UV 0 Setting bit prevents enabling unless OUT12 < bleed-down threshold. 7 12DS 0 Clearing bit disconnects OUT12 bleed-down resistor. REGISTER 5 READ/WRITE 3.3-V CHANNEL CONFIGURATION 0 3FT0 1 Setting bit increases 3 V fault time by 0.45 ms. 1 3FT1 0 Setting bit increases 3 V fault time by 0.9 ms. 2 3FT2 0 Setting bit increases 3 V fault time by 1.8 ms. 3 3FT3 0 Setting bit increases 3 V fault time by 3.6 ms. 4 3FT4 0 Setting bit increases 3 V fault time by 7.2 ms. 5 3EN 0 Clearing bit disables 3 V. 6 3UV 0 Setting bit prevents enabling unless OUT3B < bleed-down threshold. 7 3DS 0 Clearing bit disconnects OUT3B bleed-down resistor. REGISTER 6 READ/WRITE 16 SYSTEM CONFIGURATION 0 PPTEST 0 12-V pulldown test pin. Setting pin pulls the PASS and BLK pins to 0 V. 1 FLTMODE 0 Clearing bit latchs off channels after over-current fault. Setting bit allows channels to automatically attempt restart after fault. 2 ENPOL 0 This bit must be 0. 3 3ORON 0 Setting bit enables 3-V channel to prevent reverse current flow. 4 12VNRS 0 Non Redundant System in rush control bit. Setting bit allows increased inrush current in 12-V channel . 5 DISA 0 This bit must be set to 1 6 spare 0 7 DCC 0 Setting bit allows the 12-V channels to operate despite loss of 3.3-V. This bit should be low for μTCA and AMC applications Submit Documentation Feedback Copyright © 2009–2013, Texas Instruments Incorporated Product Folder Links: TPS2459 TPS2459 www.ti.com SLUS917E – FEBRUARY 2009 – REVISED MAY 2013 Table 2. Summary of Registers (continued) BIT NAME DEFAULT DESCRIPTION REGISTER 7 READ ONLY LATCHED CHANNEL STATUS INDICATORS, CLEARED ON READ 0 1 spare — 4 12PG 0 Latches high when OUT12 goes from above VTH_PG to below VTH_PG. 5 12FLT 0 Latches high when 12 fault timer has run out. 6 3PG 0 Latches high when OUT3 goes from above VTH_PG to below VTH_PG. 7 3FLT 0 Latches high when 3-V fault timer has run out. 2 3 REGISTER 8 READ ONLY LATCHED OVERCURRENT INDICATORS, CLEARED ON READ 0 1 spare — 4 12OC 0 Latches high when 12-V channel goes into over-current. 5 12FTR 0 Latches high if 12-V fast trip threshold exceeded. 6 3OC 0 Latches high when 3-V enters over-current. 7 3FTR 0 Latches high if 3-V fast trip threshold exceeded. 2 3 REGISTER 9 READ ONLY UNLATCHED FET STATUS INDICATORS 0 spare 1 spare 2 spare 3 12BS – High indicates BLK commanded high. 4 12PS – Low indicates (VPASS > VOUT + 6 V). 5 3BS – Low indicates VIN3 > VOUT3. 6 spare 7 3GS – Low indicates 3 V channel gate is driven on VGATE > ( VIN + 1.75 V ). – Submit Documentation Feedback Copyright © 2009–2013, Texas Instruments Incorporated Product Folder Links: TPS2459 17 TPS2459 SLUS917E – FEBRUARY 2009 – REVISED MAY 2013 www.ti.com DETAILED DESCRIPTION OF REGISTERS Table 3. Register 3: 12-V Channel Configuration (Read/Write) BIT NAME DEFAULT 0 12CL0 1 Clearing bit reduces 12-V current limit and fast threshold by 5%. DESCRIPTION 1 12CL1 1 Clearing bit reduces 12-V current limit and fast threshold by 10%. 2 12CL2 1 Clearing bit reduces 12-V current limit and fast threshold by 20%. 3 12CL3 1 Clearing bit reduces 12-V current limit and fast threshold by 40%. 4 12PG0 1 Clearing bit reduces 12-V power good threshold by 600 mV. 5 12PG1 1 Clearing bit reduces 12-V power good threshold by 1.2 V. 6 12HP 0 Setting bit shifts 12-V OR VTURNOFF from –3 mV to +3 mV nominal. 7 12OR 1 Clearing bit turns off 12-V ORing FET by pulling BLK low. 12CL[3:0] These four bits adjust the 12-V current limit and fast trip threshold using the I2CTM interface. Setting the bits to 1111B places the 12-V current limit at its maximum level, corresponding to 675 mV at SUM12. The fast trip threshold then equals 100 mV. Clearing all bits reduces the current limit and fast trip threshold to 25% of these maximums. 12PG[1:0] These two bits adjust the 12-V power good threshold. Setting the bits to 11B places the power good threshold at its maximum level of 10.5 V . Setting the bits to 00B places the threshold at its minimum level of 8.7 V. The lower thresholds may prove desirable in systems that routinely experience large voltage droops. 12HP Setting this bit moves the 12-V ORing turn off threshold from –3 mV to +3 mV. A positive threshold prevents reverse current from flowing through the channel, but it may cause the ORing FET to repeatedly cycle on-and-off if the load is too light to maintain the required positive voltage drop across the combined resistance of the external FETs and the sense resistor. For further information, see Adjusting ORing Turn Off Threshold For High Power Loads section. 12OR Clearing this bit forces the BLK pin low, keeping the 12-V ORing FET off. Clearing this bit does not prevent current from flowing through the FET’s body diode. . Table 4. Register 4: 12-V Channel Configuration (Read/Write) BIT NAME DEFAULT DESCRIPTION 0 12FT0 1 Setting bit increases 12-V fault time by 0.45 ms. 1 12FT1 0 Setting bit increases 12-V fault time by 0.90 ms. 2 12FT2 0 Setting bit increases 12-V fault time by 1.80 ms. 3 12FT3 0 Setting bit increases 12-V fault time by 3.60 ms. 4 12FT4 0 Setting bit increases 12-V fault time by 7.20 ms. 5 12EN 0 Clearing bit disables 12-V by pulling PASS and BLK to 0 V. 6 12UV 0 Setting bit prevents enabling unless OUT12 < bleed-down threshold. 7 12DS 0 Clearing bit disconnects OUT12 bleed-down resistor. 12FT[4:0] These five bits adjust the 12-V channel fault time. The least-significant bit has a nominal weight of 0.45 ms, so fault times ranging from 0.45 ms (for code 00001B) to 13.95 ms (for code 11111B) can be programmed. The code xFT = 00000B should not be used. In general the shortest fault time that fully charges downstream bulk capacitors without generating a fault should be used. Once the load capacitors have fully charged, the fault time can be reduced to provide faster short circuit protection. See Setting Fault Time section. 12EN This bit serves as a master enable for the 12-V channel. Setting the bit allows the 12-V channel to operate normally. Clearing the bit disables the channel by pulling PASS and BLK low. 12UV Setting this bit prevents 12-V channel from turning on until VOUT12 falls below the bleed-down threshold of 100 mV. This feature ensures that downstream devices reset by requiring their supply voltage to fall to nearly zero before the channel can enable them. 12DS Clearing this bit disconnects the bleed-down resistor that otherwise connects from OUT12 to ground. Systems using redundant power supplies should clear 12DS to prevent the bleed-down resistor from continuously sinking current. . 18 Submit Documentation Feedback Copyright © 2009–2013, Texas Instruments Incorporated Product Folder Links: TPS2459 TPS2459 www.ti.com SLUS917E – FEBRUARY 2009 – REVISED MAY 2013 Table 5. Register 5: 3.3-V Channel Configuration (Read/Write) BIT NAME DEFAULT 0 3FT0 1 Setting bit increases 3-V fault time by 0.45 ms. DESCRIPTION 1 3FT1 0 Setting bit increases 3-V fault time by 0.9 ms. 2 3FT2 0 Setting bit increases 3-V fault time by 1.8 ms. 3 3FT3 0 Setting bit increases 3-V fault time by 3.6 ms. 4 3FT4 0 Setting bit increases 3-V fault time by 7.2 ms. 5 3EN 0 Clearing bit disables 3-V. 6 3UV 0 Setting bit prevents enabling unless OUT3 < bleed-down threshold. 7 3DS 0 Clearing bit disconnects OUT3 bleed-down resistor. 3FT[4:0] These five bits adjust the 3-V channel fault time. The least-significant bit has a nominal weight of 0.45 ms, so fault times ranging from 0.45 ms (for code 00001B) to 13.95 ms (for code 11111B) can be programmed. The code xFT = 00000B should not be used. In general the shortest fault time that fully charges downstream bulk capacitors without generating a fault should be used. See the Setting Fault Time section. 3EN This bit serves as a master enable for the 3-V channel. Setting this bit allows the 3-V channel to operate normally, provided the EN3 pin is also asserted. Clearing this bit disables the channel by removing gate drive to the internal pass FET, regardless of the state of the EN3 pin. 3UV Setting this bit prevents the 3-V channel from turning on until VOUT3 falls below the bleed-down threshold of 100 mV. This feature ensures that downstream devices reset by requiring their supply voltage to fall to nearly zero before the channel can enable them. 3DS Clearing this bit disconnects the bleed-down resistor that otherwise connects from OUT3 to ground. Systems using redundant power supplies should clear 3DS to prevent the bleed-down resistor from continuously sinking current. . Submit Documentation Feedback Copyright © 2009–2013, Texas Instruments Incorporated Product Folder Links: TPS2459 19 TPS2459 SLUS917E – FEBRUARY 2009 – REVISED MAY 2013 www.ti.com Table 6. Register 6: System Configuration (Read/Write) BIT NAME DEFAULT 0 PPTEST 0 12V pulldown test pin. Asserting this pulls the PASS and BLK pins to 0 V. DESCRIPTION 1 FLTMODE 0 Clearing bit forces channels to latch off after over-current fault. Setting bit allows channels to automatically attempt restart after fault. 2 ENPOL ENP 0 This bit must be 0. 3 3ORON 0 Setting bit enables 3.3-V channel to prevent reverse current flow. Clearing bit disables 3A and 3B ORing. 4 12VNRS 0 Non-redundant system inrush control bit. Setting bit allows increased inrush current in 12-V channel 5 DISA 0 This bit must be set to 1. 6 spare 0 7 DCC 0 Setting bit allows the 12-V channel to operate despite loss of 3.3 V. For μTCA and AMC applications this bit should be low. PPTEST This bit is used for testing the fast turnoff feature of the PASS and BLK pins. Setting this bit enables the fast turnoff drivers for all four pins. Clearing this bit restores normal operation. PPTEST allows the fast turnoff drivers to operate at full current indefinitely, whereas they would normally operate for only approximately 15 μs. While using PPTEST the energy dissipated in the fast turnoff drivers must be externally limited to 1 mJ per driver to prevent damage to the TPS2459. FLTMODE Setting this bit allows a channel to attempt an automatic restart after an overcurrent condition has caused it to time out and shut off. The retry period equals approximately 100 times the programmed fault time. The FLTMODE bit affects all four channels. If cross-connection is enabled (DCC = 0), a fault on the 3.3-V channel turns off the 12-V channel. If the 3.3-V channel automatically restarts because FLTMODE = 1, the 12-V channel remains disabled until its enable bit (12EN) is cycled off and on. ENPOL This bit must be 0. 3ORON Setting this bit allows the 3.3-V ORing function to operate normally. Clearing this bit prevents a VOUT3 > VIN3 condition from turning off the 3 V channel and forces 3A / 3B ORing to behave as if IN3A >> OUT3A, and IN3B >> OUT3B... This bit is typically cleared for non-redundant systems. 12VNRS Setting this bit increases the current limit for the 12-V channel to its maximum value during the initial inrush period that immediately follows the enabling of the channel. During inrush, the current limit behaves as if 12CL[3:0] = 1111B. After the current drops below this limit, signifying the end of the inrush period, the current limit returns to normal operation. This function is intended for use in non-redundant systems with capacitive loads. Setting this bit forces the 12-V current limiters to behave as though the current limit adjust bits R0[3:0], R3[3:0] are set to 1111 right after EN asserts and will persist until the channel comes out of current limit or the fault timer times out, whichever comes first. DISA This bit must be set to 1. DCC Setting this bit disables cross-connection. If DCC = 0, when the 3.3-V channel experiences a fault, both it and the 12-V channel turn off. If DCC = 1, then the 12-V channel continues to operate even if the 3.3-V channel experiences a fault. X 20 Submit Documentation Feedback Copyright © 2009–2013, Texas Instruments Incorporated Product Folder Links: TPS2459 TPS2459 www.ti.com SLUS917E – FEBRUARY 2009 – REVISED MAY 2013 Table 7. Register 7: Latched Channel Status Indicators (Read-only, cleared on read) BIT NAME 0 spare DEFAULT DESCRIPTION 1 spare 2 spare 3 spare 4 12PG 0 Latches high when OUT12 goes from above VTH_PG to below VTH_PG. This bit is set each time channel is turned on. A second read cycle will indicate true status. 5 12FLT 0 Latches high when 12-V fault timer has run out. 6 3PG 0 Latches high when OUT3 goes from above VTH_PG to below VTH_PG. This bit is set each time channel is turned on. A second read cycle will indicate true status. 7 3FLT 0 Latches high when 3 V fault timer has run out. – 12PG This bit is set if the voltage on OUT12 drops below the power-good threshold set by the 12PG[1:0] bits, and it remains set until Register 7 is read. 12FLT This bit is set if the fault timer on the 12-V channel has run out, and it remains set until Register 7 is read. 3PG This bit is set if the voltage on OUT3 drops below the power-good threshold, and it remains set until Register 7 is read. 3FLT This bit is set if the fault timer on the 3.3-V channel runs out, and it remains set until Register 7 is read. Table 8. Register 8: Latched Status Indicators (Read-only, cleared on read) BIT NAME 0 spare 1 spare 2 spare DEFAULT DESCRIPTION – 3 spare 4 12OC 0 Latches high when 12-V channel enters overcurrent. 5 12FTR 0 Latches high if 12-V fast trip threshold exceeded. 6 3BOC 0 Latches high when 3 V channel enters over-current. 7 3BFTR 0 Latches high if 3 fV ast trip threshold exceeded. 12OC This bit is set if the voltage on the PASS pin drops below the timer start threshold, signifying a current limit condition. This bit remains set until Register 8 is read. This bit is set each time channel is turned on. A second read cycle after turn on is required to determine true status. 12FTR This bit is set if the voltage across the sense resistor for the 12-V channel exceeds the fast trip threshold. This bit remains set until Register 8 is read. This bit remains set until Register 8 is read. This bit is set each time channel is turned on. A second read cycle after turn on is required to determine true status. 3OC This bit is set if the gate-to-source voltage on the 3 V channel pass FET drops low enough to start the fault timer. This bit remains set until Register 8 is read. This bit remains set until Register 8 is read. This bit is set each time channel is turned on. A second read cycle after turn on is required to determine true status. 3FTR This bit is set if the current through the 3 V channel exceeds the fast trip threshold. This bit remains set until Register 8 is read. X Submit Documentation Feedback Copyright © 2009–2013, Texas Instruments Incorporated Product Folder Links: TPS2459 21 TPS2459 SLUS917E – FEBRUARY 2009 – REVISED MAY 2013 www.ti.com Table 9. Register 9: Unlatched Status Indicators (Read-only) BIT NAME 0 spare DEFAULT DESCRIPTION 1 spare 2 spare 3 12BS – High indicates BLK commanded high. 4 12PS – Low indicates VPASS > VOUT + 6 V. 5 3BS – Low indicates VIN3 > VOUT3. 6 spare 7 3GS – Low indicates channel 3 gate is driven on (VGATE > VIN + 1.75 V). – 12BS This bit goes high when the 12-V ORing logic commands the BLK pin high ( 25 V ) and the BLK FET should be on. 12PS This bit goes low when the 12-V PASS pin is above the timer start threshold (OUT12 + 7 V), indicating that the 12-V PASS FET should be on. 3BS This bit goes low when the 3 V ORing logic commands the 3 V pass FET on, indicating that a reverse blocking condition does not exist. 3GS This bit goes low when the 3 V FET gate-to-source voltage exceeds 1.75 V, indicating that the 3 V FET should be on. X 22 Submit Documentation Feedback Copyright © 2009–2013, Texas Instruments Incorporated Product Folder Links: TPS2459 TPS2459 www.ti.com SLUS917E – FEBRUARY 2009 – REVISED MAY 2013 APPLICATION INFORMATION The TPS2459 has been designed to simplify compliance with the PICMG-AMC.R2.0 and PICMG-MTCA.0 specifications. These specifications were developed by the PCI Industrial Computer Manufacturers Group (PICMG). These two specifications are derivations of the PICMG-ATCA (Advanced Telecommunication Computing Architecture) specification originally released in December, 2002. PICMG-AMC Highlights • AMC – Advanced Mezzanine Cards • Designed to Plug into ATCA Carrier Boards • AdvancedMC™ Focuses on Low Cost • 1 to 8 AdvancedMC™ per ATCA Carrier Board • 3.3-V Management Power – Maximum Current Draw of 150 mA • 12-V Payload Power – Converted to Required Voltages on AMC • Maximum 80 W Dissipation per AdvancedMC™ • Hotswap and Current Limiting and must be Present on Carrier Board • For details, see www.picmg.org/ PICMG-MTCA Highlights • MTCA – MicroTelecommunications Computing Architecture • Architecture for Using AMCs without an ATCA Carrier Board • Up to 12 AMCs per System, plus Two MicroTCA Carrier Hub (MCH)s, plus Two Cooling Units (CU)s • Focuses on Low Cost – Commoditizes the Hardware • All Functions of ATCA Carrier Board must be Provided • MicroTCA is also known as MTCA, mTCA, μTCA or uTCA • For details, see www.picmg.org/ Introduction The TPS2459 controls a 12-V power path and a 3.3-V power path in a 32-pin QFN package. An I2C™ interface enables the implementation using one small integrated circuit, but it also provides many opportunities for design customization. The following sections describe the main functions of the TPS2459 and provide guidance for designing systems around this device. Control Logic and Power-On Reset The TPS2459 circuitry, including the I2C™ interface, draws power from an internal bus fed by a preregulator. A capacitor attached to the VINT pin provides decoupling and output filtering for this preregulator. It can draw power from either of the two inputs (IN12, IN3) or from either of two outputs (OUT12, OUT3). This feature allows the internal circuitry to function regardless of which channels receive power, or from what source. The two external FET drive pins (PASS, BLK) are held low during startup to ensure that the 12-V channel remains off. The internal 3.3-V channel is also held off. When the voltage on the internal VINT rail exceeds approximately 1 V, the power-on reset circuit loads the internal registers with the default values listed in Detailed Description of Registers section. Submit Documentation Feedback Copyright © 2009–2013, Texas Instruments Incorporated Product Folder Links: TPS2459 23 TPS2459 SLUS917E – FEBRUARY 2009 – REVISED MAY 2013 www.ti.com Enable Functions Table 10 lists the specific conditions required to enable the two channels of the TPS2459. The 3.3-V channel has an active-high enable pin with a 200-kΩ internal pullup resistor. The enable pin must be pulled high, or allowed to float high, to enable the channel. The I2C™ interface includes an enable bit for each of the two channels. The bit corresponding to a channel must be set to enable the channel. Both channels also include bleed-down threshold comparators. Setting the bleed-down control bit ensures that a channel cannot turn on until its output voltage drops below about 100 mV. This feature supports applications in which removal and restoration of power reinitializes the state of downstream loads. The 12-V channel also includes a cross-connection feature to support PICMG.AMC™ and MicroTCA™ requirements. When enabled, this feature ensures that when the 3.3-V output drops below 2.85 V, the 12-V channel automatically shuts off. This feature can be disabled by setting the DCC bit in Register 6. Table 10. Enable Requirements CHANNEL (V) ENABLE PINS ENABLE BITS BLEED DOWN CROSS CONNECTION 3.3 EN3 > 1.4 V 3EN = 1 OUT3 > 0.1 V or 3UV = 0 12 EN12 > 1.4 V 12EN = 1 OUT12 > 0.1 V or 12UV = 0 3PG = 0 or DCC = 1 Fault, Powergood, Overcurrent and FET Status Bits The TPS2459 I2C™ interface includes six status bits for each channel, for a total of 12 bits. These status bits occupy registers 7, 8, and 9. Table 11 summarizes the locations of these bits. Table 11. Location REGISTER[BIT] NAME FUNCTION 12-V CHANNEL 3-V CHANNEL PG Powergood R7[4] R7[6] FLT Overcurrent time-out fault R7[5] R7[7] OC Momentary overcurrent R8[4] R8[6] FTR Overcurrent fast trip R8[5] R8[7] 12BS 12-V block FET status R9[3] 12PS 12-V pass FET status R9[4] 3BS 3-V block status – 3GS 3-V gate status R9[7] – R9[5] Current Limit and Fast Trip Thresholds Both channels monitor current by sensing the voltage across a resistor. The 3.3-V channel uses an internal sense resistor with a nominal value of 290 mΩ. The 12-V channel uses an external sense resistor that typically lies in the range of 4 mΩ to 10 mΩ. Each channel features two distinct thresholds: a current limit threshold and a fast trip threshold. The current limit threshold sets the regulation point of a feedback loop. If the current flowing through the channel exceeds the current limit threshold, then this feedback loop reduces the gate-to-source voltage imposed on the pass FET. This causes the current flowing through the channel to settle to the value determined by the current limit threshold. For example, when a module first powers up, it draws an inrush current to charge its load capacitance. The current limit feedback loop ensures that this inrush current does not exceed the current limit threshold. The current limit feedback loop has a finite response time. Serious faults such as shorted loads require a faster response in order to prevent damage to the pass FETs or voltage sags on the supply rails. A comparator monitors the current flowing through the sense resistor, and if it ever exceeds the fast trip threshold it immediately shuts off the channel. Then it will immediately attempt a normal turn on which allows the current limit feedback loop time to respond. The fast trip threshold is normally set 2 to 5 times higher than the current limit. 24 Submit Documentation Feedback Copyright © 2009–2013, Texas Instruments Incorporated Product Folder Links: TPS2459 TPS2459 www.ti.com SLUS917E – FEBRUARY 2009 – REVISED MAY 2013 3.3-V Current Limiting The 3.3-V management power channel includes an internal pass FET and current sense resistor. The onresistance of the management channel (including pass FET, sense resistor, metallization resistance, and bond wires) typically equals 290 mΩ and never exceeds 500 mΩ. The AdvancedMC™ specification allows a total of 1 Ω between the power source and the load. The TPS2459 never consumes more than half of this requirement. 3.3-V Fast Trip Function The 3.3-V fast trip function protects the channel against short-circuit events. If the current through the channel exceeds a nominal value of 300 mA, then the TPS2459 immediately disables the internal pass transistor and then allows it to slowly turn back on into current limiting. 3.3-V Current Limit Function The 3.3-V current limit function internally limits the current to comply with the AdvancedMC™ and MicroTCA™ specifications. External resistor RSUM3 allows the user to adjust the current limit threshold. The nominal current limit threshold ILIMIT is shown in Equation 1. ILIMIT = 650 V RSUM3 (1) A 3320-Ω resistor gives a nominal current limit of ILIMIT = 195 mA which complies with AdvancedMC™ and MicroTCA™ specifications. This resistance corresponds to an EIA 1% value. Alternatively, a 3.3-kΩ resistor also suffices. Whenever the 3.3-V channel enters current limit, its fault timer begins to operate (see Fault Timer Programming section). 3.3-V Over-Temperature Shutdown The 3.3-V over-temperature shutdown is enabled if the 3.3 V channel remains in current limit while the die temperature exceeds approximately 140°C. When this occurs, the channel operating in current limit turns off until the chip cools by approximately 10°C. 3.3-V ORing The 3.3-V channel limits reverse current flow by sensing the input-to-output voltage differential and turning off the internal pass FET when this differential drops below –3 mV. This corresponds to a nominal reverse current flow of 10 mA. The pass FET turns back on when the differential exceeds +10 mV. These thresholds provide a nominal 13 mV of hysteresis to help prevent false triggering. This feature allows the implementation of redundant power supplies (also known as supply ORing). If the 3.3-V channel does not use redundant supplies, the 3ORON bit can be cleared to disable the ORing circuitry. This precaution eliminates the chance that transients might trigger the ORing circuitry and upset system operation. Submit Documentation Feedback Copyright © 2009–2013, Texas Instruments Incorporated Product Folder Links: TPS2459 25 TPS2459 SLUS917E – FEBRUARY 2009 – REVISED MAY 2013 www.ti.com 12-V Fast Trip and Current Limiting Figure 21 shows a simplified block diagram of the circuitry associated with the fast trip and current limit circuitry in the 12-V channel, which requires an external N-channel pass FET and three external resistors. These resistors allow the user to independently set the fast trip threshold and the current limit threshold, as described below. RSENSE 12 V VIN 100 W RSET SET SENP 13 SENM 14 PASS 12 OUT12 11 8 100 mV + 30 mA + + Fast Trip Comparator A1 SUM12 5 675 mV + A2 RSUM TPS2459 UDG-09040 Figure 21. 12-V Channel Threshold Circuitry 12-V Fast Trip Function The 12-V fast trip function protects the channel against short-circuit events. If the voltage across external resistor RSENSE exceeds the fast trip threshold, then the TPS2459 immediately disables the pass transistor. The 12CL bits set the magnitude of the fast trip threshold. When 12CL = 1111B, the fast trip threshold nominally equals 100 mV. The fast trip current IFT corresponding to this threshold is shown in Equation 2. IFT = 100mV RSENSE (2) The recommended value of (RSENSE = 5 mΩ) sets the fast trip threshold at 20 A for 12CL = 1111B. This choice of sense resistor corresponds to the maximum 19.4 A inrush current allowed by the MicroTCA™ specification. 12-V Current Limit Function The 12-V current limit function regulates the PASS pin voltage to prevent the current through the channel from exceeding ILIMIT. The current limit circuitry includes two amplifiers, A1 and A2, as shown in Figure 21. Amplifier A1 forces the voltage across external resistor RSET to equal the voltage across external resistor RSENSE. The current that flows through RSET also flows through external resistor RSUM, generating a voltage on the 12SUM pin is shown in Equation 3. æR ´ RSUM ö V12SUM = ç SENSE ÷ ´ ISENSE RSET è ø (3) Amplifier A2 senses the voltage on the 12SUM pin. As long as this voltage is less than the reference voltage on its positive input (nominally 0.675 V for 12CL = 1111B), the amplifier sources current to PASS. When the voltage on the 12SUM pin exceeds the reference voltage, amplifier A2 begins to sink current from PASS. The gate-tosource voltage of pass FET MPASS drops until the voltages on the two inputs of amplifier A2 balance. The current flowing through the channel then nominally is shown in Equation 4. 26 Submit Documentation Feedback Copyright © 2009–2013, Texas Instruments Incorporated Product Folder Links: TPS2459 TPS2459 www.ti.com SLUS917E – FEBRUARY 2009 – REVISED MAY 2013 æ ö RSET ILIMIT = ç ÷ ´ 0.675 V è RSUM ´ RSENSE ø (4) The recommended value of RSUM is 6810 Ω. This resistor should never equal less than 675 Ω to prevent excessive currents from flowing through the internal circuitry. Using the recommended values of RSENSE = 5 mΩ and RSUM = 6810 Ω gives Equation 5. æ 0.0198 A ö ILIMIT = ç ÷ ´ R SET W è ø (5) A system capable of powering an 80-W AdvancedMC™ module consumes a maximum of 8.25 A according to MicroTCA™ specifications. The above equation suggests RSET = 417 Ω. The nearest 1% EIA value equals 422 Ω. The selection of RSET for MicroTCA™ power modules is described in the Redundant vs. Non-redundant Inrush Current Limiting section. 12-V Inrush Slew Rate Control Although it is possible to slow the gate slew rate, it is very unlikely that would be necessary since the TPS2459 limits inrush current at turn on. The limit level is programmed by the user. As normally configured, the turn-on slew rate of the 12-V channel output voltage VOUT is shown in Equation 6. DVOUT ISRC @ Dt Cg where • • ISRC equals the current sourced by the PASS pin (nominally 30 μA) Cg equals the effective gate capacitance (6) For purposes of this computation, the effective gate capacitance approximately equals the reverse transfer capacitance, CRSS. To reduce the slew rate, increase Cg by connecting additional capacitance from PASS to ground. Place a resistor of at least 1000 Ω in series with the additional capacitance to prevent it from interfering with the fast turn off of the FET. RSENSE IN12 OUT12 100 W R > 1 kW C 11 PASS TPS2459 UDG-09033 Figure 22. RC Slew Rate Control Submit Documentation Feedback Copyright © 2009–2013, Texas Instruments Incorporated Product Folder Links: TPS2459 27 TPS2459 SLUS917E – FEBRUARY 2009 – REVISED MAY 2013 www.ti.com Redundant vs. Non-Redundant Inrush Current Limiting The TPS2459 can support redundant and non-redundant systems. Redundant systems generally use a single fixed current limit, as described above. Non-redundant systems often allow a higher current limit during inrush to compensate for the lack of a redundant supply. The MicroTCA™ standard allows up to 19.4 A for up to 200 ms in non-redundant systems, while limiting individual supplies in redundant systems to 9.1 A at all times. Designers can optimize the performance of the system for either application by properly setting the 12VNRS bit that controls inrush limiting. The ability to change the inrush profile using 12VNRS makes it possible to reconfigure a controller for redundant or non-redundant operation with a single bit. This is particularly useful for MicroTCA Power Modules which may be deployed in redundant or non-redundamnt systems. The 12VNRS bit affects the value of the 12CL bits during inrush. Setting 12VNRS causes the current limit threshold and fast trip threshold to behave as if 12CL = 1111B during inrush. Once the current flowing through the channel falls below the current limit threshold, the current limit threshold and fast trip threshold correspond to the actual values of the 12CL bits. ILIMIT – Current Limit – A Figure 23 illustrates the behavior of the 12VNRS bit. Figure A shows that setting the 12CL bits to 1111B results in a current limit equal to IMAX. Figure 6B shows how the 12CL bits affect the current limit when the 12VNRS bit is cleared. Setting 12CL = 0111B reduces the current limit to 60% of IMAX. Figure C shows how the 12CL bits affect the current limit when the 12VNRS bit is set. The current limit initially equals IMAX, but as soon as the current drops below this level, the current limit resets to 60% of IMAX and remains there so long as the channel remains enabled. IMAX If 12xCL[3:0] = 1111B, 12VNRS has no effect 60% IMAX tFAULT tFAULT tFAULT 12 VNRS = x 12 VNRS = 0 12 VNRS = 1 0 0 t – Time (A) t – Time (B) t – Time (C) A. 12xCL[3:0] = 111B B. The characteristics shown represent the current limit level versus time. It is not a representation of current versus time. Figure 23. Current Limits in Redundant and Non-Redundant Systems Current Limiting Design Examples Example One Set up a 12-V channel input voltage to start into an 80-W load and charge a 1600-μF capacitor in less than 3 ms. Set an operational ILIMIT of 8.25 A ±10%. Equation 7 calculate how much current is needed for capacitor charging and powering the load. ISTARTUP = ICHARGE + ILOAD = 6.4 A + 6.67 A = 13.7 A where ICHARGE = • 28 C ´ V 1600 mF ´ 12 V = = 6.4 A t 0.003 s Submit Documentation Feedback Copyright © 2009–2013, Texas Instruments Incorporated Product Folder Links: TPS2459 TPS2459 www.ti.com SLUS917E – FEBRUARY 2009 – REVISED MAY 2013 ILOAD = • PLOAD 80 W = = 6.67 A VLOAD 12 V (7) Next, use Equation 8 to calculate RSET for an ILIMIT of 13.7 A. RSET = (ILIMIT ´ RSENSE ´ RSUM ) = 691 W 0.675 where • • RSUM = 6810 Ω RSENSE = 5 Ω (8) The closest 1% value is 698 Ω. The ILIMIT can be calculated in Equation 9. ILIMIT = 0.675 ´ R SET = 13.83 A R SENSE ´ R SUM (9) If R3[3:0] are set to 0111 and R6[4] = 1 the current limit drops to 60% of the programmed maximum after dropping out of current limit following inrush. The operational current limit is calculated in Equation 10. ILIMIT = 0.6 ´ IINRUSH = 0.6 ´ 13.83 A = 8.3 A (10) The new 8.38-A current limit is within the specification of 8.25 A ±10 %. Note. These calculations use all nominal values and neglect di/dt rates at turn on. Example Two Set up 12-A to startup into an 80-W load and charge a 1600 μF at not more than 17-A nominal. Then drop to an operational ILIMIT of 8.25 A ±10%. ISTARTUP = 17 A The correct RSET must be found to set maximum ILIMIT to less than 17 A. R SET = (ILIMIT ´ R SENSE ´ R SUM ) = 857 W 0.675 where • • RSUM = 6810 Ω RSENSE = 5 Ω (11) The closest 1% value is 845 Ω. ILIMIT = 0.675 ´ RSET = 16.75 A RSENSE ´ RSUM (12) Neglecting the current slew time, charge the 1600-μF capacitor in 1.9 ms. If R3[3:0] are set to 0101 and R6[4] = 1 the current limit drops to 50% of the programmed maximum after dropping out of current limit following inrush. The operational current limit is calculated in Equation 13. ILIMIT = 0.5 ´ IINRUSH = 0.5 ´ 16.75 A = 8.38 A (13) The new 8.38-A current limit is within the specification of 8.25 A ±10 %. Note. These calculations use all nominal values. Table 12. Configuring 12-V Current Limits in Non-Redundant Systems RSET 12CLx [3:0] 412 1111 ILIMIT (A) – INRUSH 12VNRS R6[4]=0 R6[4]=1 ILIMIT (A) OPERATIONAL 12VNRS = 1 8.17 8.17 8.17 PLOAD (W) 80 CBULK CHARGE TIME (ms) FAULT TIME (ms) 800 μF 1600 μF 800 μF 1600 μF 6.4 12.8 8.5 17 Submit Documentation Feedback Copyright © 2009–2013, Texas Instruments Incorporated Product Folder Links: TPS2459 29 TPS2459 SLUS917E – FEBRUARY 2009 – REVISED MAY 2013 www.ti.com Table 12. Configuring 12-V Current Limits in Non-Redundant Systems (continued) ILIMIT (A) – INRUSH 12VNRS RSET 12CLx [3:0] R6[4]=0 698 111 13.84 845 101 16.75 CBULK CHARGE TIME (ms) FAULT TIME (ms) R6[4]=1 ILIMIT (A) OPERATIONAL 12VNRS = 1 PLOAD (W) 800 μF 1600 μF 800 μF 1600 μF 8.3 8.3 80 1.34 2.68 2 3.5 8.38 8.38 80 0.95 1.9 1.5 3 12-V ORing Operation for Redundant Systems The 12-V channels use external pass FETs to provide reverse blocking. The TPS2459 pulls the BLK pin high when the input-to-output differential voltage VIN12–OUT12 exceeds a nominal value of 10 mV, and it pulls the pin low when this differential falls below a nominal value of –3 mV. These thresholds provide a nominal 13 mV of hysteresis to help prevent false triggering. The source of the blocking FET connects to the source of the pass FET, and the drain of the blocking FET connects to the load. This orients the body diode of the blocking FET such that it conducts forward current and blocks reverse current. The body diode of the blocking FET does not normally conduct current because the FET turns on when the voltage differential across it exceeds 10 mV. Applications that do not use the blocking FET should clear the associated 12OR bit to turn off the internal circuitry that drives the BLK pin. (See Figure 24). RSENSE 12 V VIN RSET 100 W 100 W 14 13 12 11 6 8 SENP SET SENM PASS BLK OUT12 TPS2459 UDG-09035 Figure 24. 12-V Path 30 Submit Documentation Feedback Copyright © 2009–2013, Texas Instruments Incorporated Product Folder Links: TPS2459 TPS2459 www.ti.com SLUS917E – FEBRUARY 2009 – REVISED MAY 2013 12-V ORing for High-Power Loads The 12HP bit adjusts the ORing turn-off threshold of the 12-V channel. Clearing the bit sets the ORing turn-off threshold to the default nominal value of -3 mV. Setting the bit shifts the threshold up by 6 mV to a nominal value of +3 mV (Figure 8). Shifting the turn-off threshold to a positive value ensures that the blocking FET shuts off before any reverse current flows. A light load may not draw sufficient current to keep the input-to-output differential VIN12-OUT12 above 3 mV. When this happens, the blocking FET shuts off and then the differential voltage increases until it turns back on. This process endlessly repeats, wasting power and generating noise. Therefore 12HP should only be set for high-power loads that satisfy the relationship. ILOAD > 10 mV R SENSE + R DS (on )PASS + R DS (on )BLK where • • • • ILOAD is the current drawn by the load RSENSE is the value of the sense resistor RDS(on)PASS is the maximum on-resistance of the pass FET RDS(on)BLK equals the maximum on-resistance of the blocking FET (14) For example, if RSENSE = RHSFET = RORFET = 5 mΩ, then a high-power load must always draw at least 667 mA. Most, although not all, AdvancedMC™ loads can benefit from using the high-power bit 12HP. VGATE VGATE Figure 25 shows the different ORing thresholds in high power and low power applications. 25 V GND VOR 3 mV 10 mV –3 mV VOR 12 HP = 0 10 mV GND 25 V 12 HP = 1 UDG-09034 Figure 25. ORing Thresholds High Power vs. Low Power Submit Documentation Feedback Copyright © 2009–2013, Texas Instruments Incorporated Product Folder Links: TPS2459 31 TPS2459 SLUS917E – FEBRUARY 2009 – REVISED MAY 2013 www.ti.com Internal Bleed-Down Resistors and Bleed-Down Thresholds The TPS2459 includes two features intended to support downstream loads that require removal and reapplication of power to properly reset their internal circuitry. Disabling and re-enabling a channel of the TPS2459 does not necessarily reset such a load because the capacitance attached to the output bus may not fully discharge. The TPS2459 includes two bleed-down comparators that monitor the OUT12 and OUT3 pins. The I2C™ interface includes two bits (3DS and 12DS) that enable these comparators. Enabling a bleed-down comparator prevents the corresponding channel from turning on until the output voltage drops below about 100 mV. This precaution ensures that the output rail drops so low that all downstream loads properly reset. In case the downstream load cannot quickly bleed-off charge from the output capacitance, the TPS2459 also includes bleed-down resistors connected to each output rail through pins OUT12 and OUT3. Internal switches connect these resistors from their corresponding rails to ground when the channels are disabled, providing that one sets the appropriate bit in the I2C™ interface. These bits are named 12UV and 3UV. Clearing these bits ensures that the corresponding resistors never connect to their buses. If redundant supplies connect to an output, clear the corresponding bleed-down threshold and bleed-down resistor bits. Failing to clear the bleed-down threshold bit prevents the channel from enabling, while the redundant supply continues to hold up the output rail. Failing to clear the bleed-down resistor bit causes current to continually flow through the resistor when the TPS2459 is disabled and the redundant supply holds up the output bus. 32 Submit Documentation Feedback Copyright © 2009–2013, Texas Instruments Incorporated Product Folder Links: TPS2459 TPS2459 www.ti.com SLUS917E – FEBRUARY 2009 – REVISED MAY 2013 Multiswap Operation in Redundant Systems TheTPS2459 features an additional mode of operation called Multiswap redundancy. This technique does not require a microcontroller, making it simpler and faster than the redundancy schemes described in the MicroTCA™standard. Multiswap is especially attractive for AdvancedMC™ applications that require redundancy but need not comply with the MicroTCA™ power module standard. To implement Multiswap redundancy, connect the SUM pins of the redundant channels together and tie a single RSUM resistor from this node to ground. The current limit thresholds now apply to the sum of the currents delivered by the redundant supplies. When implementing Multiswap redundancy on 12-V channels, all of the channels must use the same values of resistors for RSENSE and RSET. Figure 26 and Figure 27 compare the redundancy technique advocated by the MicroTCA™ specification with Multiswap redundancy. MicroTCA™ redundancy independently limits the current delivered by each power source. The current drawn by the load cannot exceed the sum of the current limits of the individual power sources. Multiswap redundancy limits the current drawn by the load to a fixed value regardless of the number of operational power sources. Removing or inserting power sources within a Multiswap system does not affect the current limit seen by the load. Power Source 1 TPS2459 7 RSUM12 TPS2459 SUM3 SUM12 RSUM3 Power Source 2 TPS2459 TPS2459 SUM12 SUM3 SUM12 SUM3 SUM12 7 21 5 21 5 21 mC Power Source 1 Power Source 2 RSUM12 mC SUM3 21 RSUM3 RSUM12 Backplane RSUM3 Backplane UDG-09036 UDG-09036 Figure 26. μTCA Redundancy Figure 27. Multiswap Redundancy Submit Documentation Feedback Copyright © 2009–2013, Texas Instruments Incorporated Product Folder Links: TPS2459 33 TPS2459 SLUS917E – FEBRUARY 2009 – REVISED MAY 2013 www.ti.com Fault Timer Programming Both of the TPS2459 channels include a fault timer. The timer begins operating whenever the channel enters current limit. If the channel remains in current limit so long that the fault timer runs out, then the channel turns off the pass FET and reports a fault condition by means of the xFLT bit in the I2C™ interface. The fault timers are independently programmable from 0.45 to 13.95 ms in steps of 0.45 ms using the appropriate xFT bits. A code of xFT = 00001B corresponds to a time of 0.45 ms. The code xFT = 00000B should not be used. The locations of the fault timer programming bits are shown in Table 13. Table 13. Fault Time Control Bits FAULT TIME (ms) CHANNEL VOLTAGE (V) 7.2 3.6 1.8 0.9 0.45 12 R4[4] R4[3] R4[2] R4[1] R4[0] 3.3 R5[4] R5[3] R5[2] R5[1] R5[0] REGISTER [BIT] Select the shortest fault times sufficient to allow down-stream loads and bulk capacitors to charge. Shorter fault times reduce the stresses imposed on the pass FETs under fault conditions. This consideration may allow the use of smaller and less expensive pass FETs for the 12-V channels. The TPS2459 supports two modes of fault timer operation. Clearing the FLTMODE bit causes a channel to latch off whenever its fault timer runs out. The channel remains off until it has been disabled and re-enabled (see Enable Functions section). The TPS2459 operates in this manner by default. Setting the FLTMODE bit causes a faulted channel to automatically attempt to turn back on after a delay roughly one hundred times the fault time. This process repeats until either the fault disappears or the user disables the channel. The pass FET for a 12-V channel with a shorted output must therefore continuously dissipate the following power; PFAULT @ 0.01´ VIN12 ´ ICL where • • VIN12 equals the voltage present at the input of the 12-V channel ICL equals the current limit setting for this channel (the inrush current if 12VNRS is set) (15) When used in MicroTCA Power Modules it is very important to protect the OUT12 pin by connecting a Schottky diode from the OUT12 pin to GND. The relatively long and uncontrolled load line lengths to the AdvancedMC modules make it quite likely that shutting off while under load causes an inductive transient to pull the OUT12 pin below -0.3 V. Pulling OUT12 below this level can disrupt proper device operation. 34 Submit Documentation Feedback Copyright © 2009–2013, Texas Instruments Incorporated Product Folder Links: TPS2459 TPS2459 www.ti.com SLUS917E – FEBRUARY 2009 – REVISED MAY 2013 TPS2459 I2C™ Interface The TPS2459 digital interface meets the specifications for an I2C™ bus operating in the high-speed mode. The interface to recognize any one of 27 separate I2C™ addresses can be configured using the A0, A1, and A2 pins (Table 14 I2C™ Addressing). These pins accept any of three distinct voltage levels. Connecting a pin to ground generates a low level (L). Connecting a pin to VINT generates a high level (H). Leaving a pin floating generates a no-connect level (NC). Table 14. I2C™ Addressing I2C™ (DEVICE) ADDRESS EXTERNAL PINS A2 A1 A0 DEC HEX BINARY L L L L 8 8 1000 L NC 9 9 1001 L L H 10 0A 1010 L NC L 11 0B 1011 L NC NC 12 0C 1100 L NC H 13 0D 1101 L H L 14 0E 1110 L H NC 15 0F 1111 L H H 16 10 10000 NC L L 17 11 10001 NC L NC 18 12 10010 NC L H 19 13 10011 NC NC L 20 14 10100 NC NC NC 21 15 10101 NC NC H 22 16 10110 NC H L 23 17 10111 NC H NC 24 18 11000 NC H H 25 19 11001 H L L 26 1A 11010 H L NC 27 1B 11011 H L H 28 1C 11100 H NC L 29 1D 11101 H NC NC 30 1E 11110 H NC H 31 1F 11111 H H L 32 20 100000 H H NC 33 21 100001 H H H 34 22 100010 The I2C™ hardware interface consists of two wires known as serial data (SDA) and serial clock (SCL). The interface is designed to operate from a nominal 3.3-V supply. SDA is a bidirectional wired-OR bus that requires an external pullup resistor, typically a 2.2-kΩ resistor connected from SDA to the 3.3-V supply. The I2C™ protocol assumes one device on the bus acts as a master and another device acts as a slave. The TPS2459 supports only slave operation with two basic functions called register write and register read. Submit Documentation Feedback Copyright © 2009–2013, Texas Instruments Incorporated Product Folder Links: TPS2459 35 TPS2459 SLUS917E – FEBRUARY 2009 – REVISED MAY 2013 www.ti.com Register Write DATA ACK REGISTER NUMBER STOP 0 ACK ADDRESS ACK START Figure 28 shows the format of a register write. First, the master issues a start condition, followed by a seven-bit I2C™ address. Next, the master writes a zero to signify that it wishes to conduct a write operation. Upon receiving an acknowledge from the slave, the master writes the eight-bit register number across the bus. Following a second acknowledge, the master writes the eight-bit data value for the register across the bus. Upon receiving a third acknowledge, the master issues a stop condition. This action concludes the register write. Figure 28. Register Write Format Register Read DATA ACK 1 STOP I2CTM ADDRESS ACK REGISTER NUMBER ACK 0 START I2CTM ADDRESS ACK START Figure 29 shows the format of a register read. First, the master issues a start condition followed by a seven-bit I2C™ address. Next, the master writes a zero to signify that it conducts a write operation. Upon receiving an acknowledge from the slave, the master writes the eight-bit register number across the bus. Following a second acknowledge, the master issues a repeat start condition. Then the master issues a seven-bit I2C™ address followed by a one to signify that it conducts a read operation. Upon receiving a third acknowledge, the master releases the bus to the TPS2459. The TPS2459 then writes the eight-bit data value from the register across the bus. The master acknowledges receiving this byte and issues a stop condition. This action concludes the register read. Figure 29. Register Read Format 36 Submit Documentation Feedback Copyright © 2009–2013, Texas Instruments Incorporated Product Folder Links: TPS2459 TPS2459 www.ti.com SLUS917E – FEBRUARY 2009 – REVISED MAY 2013 Using the TPS2459 to Control an AdvancedMC™ Slot The TPS2459 has been designed for use in systems under I2C™ control. Figure 30 shows the TPS2459 in a typical system implementing redundant power sources. A non-redundant application would omit the blocking FET and leave the BLK pin unconnected. RSENSE 0.005 W CSD16406Q3 CSD16406Q3 12 V VIN 12 V RSET 422 W 0.01 mF 100 W 100 W 14 13 12 11 6 SENP SET SENM PASS BLK AdvancedMCTM 8 OUT12 OUT3 17 3.3 V 15 IN12 PG12 4 FLT12 7 16 IN3 0.01 mF 22 VDD3 PG3 20 28 EN12 { From IMPC { 3.3 V To IMPC FLT3 19 TPS2459 26 EN3 6810 W SUM12 5 10 OREN 3320 W SUM3 21 { 2 SDA 0.1 mF To I2C VINT 3 1 SCL A0 A1 A2 AGND 30 18 25 27 GND GND GND GND GND 9 24 27 29 31 UDG-09037 Figure 30. TPS2459 Redundant System Schematic Submit Documentation Feedback Copyright © 2009–2013, Texas Instruments Incorporated Product Folder Links: TPS2459 37 TPS2459 SLUS917E – FEBRUARY 2009 – REVISED MAY 2013 www.ti.com Layout Considerations TPS2459 applications require careful attention to layout to ensure proper performance and minimize susceptibility to transients and noise. IImportant points to consider include: • Connect AGND and all GND pins to a ground plane. • Place a 0.01-μF or larger ceramic bypass capacitors on IN12 and VDD3. • Minimize the loop area created by the leads running to these devices. • Minimize the loop area between the SENM and SENP leads by running them side-by-side. • Use Kelvin connections at the points of contact with RSENSE Figure 31 • Minimize the loop area between the SET and SENP leads. • Connect the SET leads to the same Kelvin points as the SENP leads, or as close to these points as possible. • Size the following runs to carry at least 20 A: – Runs on both sides of RSENSE – Runs from the drains and sources of the external FETs • Minimize the loop area between the OUT12 and SENP leads. • Size the runs to IN3 and OUT3 to carry at least 1 A. • Soldering the powerpad of the TPS2459 to the board will improve thermal performance. Load Current Path Load Current Path Sense Resistor RSET RSET 14 13 14 13 12 12 TPS2459 TPS2459 (a) (b) *Additional details ommoted for clarity. Figure 31. Recommended RSENSE Layout 38 Submit Documentation Feedback Copyright © 2009–2013, Texas Instruments Incorporated Product Folder Links: TPS2459 TPS2459 www.ti.com SLUS917E – FEBRUARY 2009 – REVISED MAY 2013 Transient Protection The need for transient protection in conjunction with hot-swap controllers should always be considered. When the TPS2459 interrupts current flow, input inductance generates a positive voltage spike on the input and output inductance generates a negative voltage spike on the output. Such transients can easily exceed twice the supply voltage if steps are not taken to address the issue. Typical methods for addressing transients include : • minimizing lead length/inductance into and out of the device • transient voltage suppressors (TVS) on the input to absorb inductive spikes • Shottky diode and/or capacitors across the output to absorb negative spikes • a combination of ceramic and electrolytic capacitors on the input and output to absorb energy. Equation 16 estimates the magnitude of these voltage spikes. VSPIKE = VNOM + ILOAD ´ L C where • • • • VNOM is the nominal voltage at terminal being analyzed L is the combined inductance of feed to RTN lines. C is the capacitance at point of disconnect. ILOAD is the current through terminal at TDISCONNECT (16) The inductance due to a straight length of wire is described in Equation 17. æ æ æ 4 ´ length ö öö - 0.75 ÷ ÷ LSTRAIGHTWIRE @ ç 0.2 ´ length ´ ç ln ç ÷ ç ÷ è è diameter ø øø è where • • L is the length of the wire D is the diameter (17) If sufficient capacitance to prevent transients from exceeding the absolute ratings of the TPS2459 cannot be included the application requires the addition of transient protectors. Submit Documentation Feedback Copyright © 2009–2013, Texas Instruments Incorporated Product Folder Links: TPS2459 39 TPS2459 SLUS917E – FEBRUARY 2009 – REVISED MAY 2013 www.ti.com Output Protection Considerations for MicroTCA Power Systems MicroTCA Power systems have particular transient protection requirements because of the basic power architecture. Traditional protection methods must be adjusted to accommodate these systems where the supplies are OR’ed together after the inrush control and current limit circuits. However, minor changes to some standard techniques will yield very good results. Unlike systems which have hotswap/inrush control at the load, uTCA power modules and their hot-swap circuitry are often a significant distance ( up to 1 m of trace length, two way ) from the load module. Even with the best designed backplanes this distance results in stray inductance which will store energy while current is being delivered to the load. The inductive energy can cause large negative voltage spikes at the power module output when the current is switched off under load. The spikes become especially severe when the channel shuts off due to a short circuit, which drives the current well above normal levels just before shut off. The lowest voltage allowed on the device pins is -0.3 V. If a transient makes a pin more negative than -0.3 V the internal ESD Zener diode attached to the pin will become forward biased and current will be conducted across the substrate to the ground pins. This current may disrupt normal operation or, if large enough, damage the silicon. Typical protection solutions involve capacitors, TVSs ( Transient Voltage Suppressors ) and/or a Schottky diode to absorb the energy which appears at the power module output in the form of a large negative voltage spike. The Risk With Output Capacitors Putting transient filter capacitors at the output of a uTCA power module can cause nuisance trips when that power module is plugged into an active bus. If there is no series resistance with the capacitor and the bus is low impedance an inrush surge can cause the active supply to “detect” a short circuit and shut down. One possible solution is to put a few Ohms of resistance in series with the cap to limit inrush below the fast trip level. A better solution is to put a Schottky diode across the output to clamp the transient energy and shunt it to ground as shown in Figure 32. Although the Schottky diode will absorb most of the energy, the extremely fast di/dt at shutoff allows some of the leading edge energy to couple through the parasitic capacitances of the hotswap FET and the ORing FET, ( CDS, CGS, CGD ) and into the BLK and GATE pins. Protection for these pins is provided by 100-Ω GATE resistors which have little effect on normal operation but provide good isolation during transient events. Simplified PASS FET Simplified BLK FET CDS CDS OUT12 LP RP L P +L EMI_FILTER IN12 CGD 100 SENP ESD Diode C GD CGS C GS E=LI 2 /2 1k 100 PASS BLK ESD Diode OUT12 ESD Diode ESD Diode RP LP LP E=LI 2 /2 TPS2359 POWER MODULE BACKPLANE AMC Figure 32. Parasitic Inductance and Transient Protection Output Bleed Down Resistance When the TPS2359 commands the 12-V channel off there is a small leakage current sourced by the OUT12 pin. If this leakage is ignored it can eventually charge any external capacitance to approximately 6 V. In some systems this may be acceptable but, if not, the leakage can be bled to GND by commanding the internal bleed down resistor on by setting 12xDS high. • 12ADS = R1[7] • 12DSB = R4[7] If a hardware solution is preferred then a 1k resistor from OUT12 to GND will suffice. Maximum leakage is around 23 µA and can be modeled as a 6-V source in series with a 280-kΩ resistor. 40 Submit Documentation Feedback Copyright © 2009–2013, Texas Instruments Incorporated Product Folder Links: TPS2459 TPS2459 www.ti.com SLUS917E – FEBRUARY 2009 – REVISED MAY 2013 REVISION HISTORY Changes from Revision A (August 2009) to Revision B Page • Added New Typical Application Diagram .............................................................................................................................. 1 • Changed pin EN12 From 0 to 5 V To: 0 to 17 V .................................................................................................................. 2 • Changed the Input bias current From:mµ To: µA ................................................................................................................. 3 • Changed the Leakage current From:mµ To: µA ................................................................................................................... 3 • Changed the Sink current From: mµ To: µA ......................................................................................................................... 3 • Added New Block Diagram ................................................................................................................................................... 6 • Changed 3.3-V Channel Circuitry Block Diagram ................................................................................................................ 7 • Deleted Setting bit makes EN3 and EN12 pins active low. ................................................................................................ 16 • Added This bit must be 0 to ENPOL. ................................................................................................................................. 16 • Deleted the ENPOL ENP Description From: Setting bit makes EN3 and EN12 pins active low.Setting bit makes external ENx pins active low; clearing bit makes pins active high. (Actually, setting this bit reverses polarity of ENPOL R14[5] which will nominally be set as active low). To: This bit must be 0 ............................................................ 20 • Deleted Changed ENPOL From: Setting this bit makes the EN12 and EN3 pins active low. To: This bit must be 0. ....... 20 • Deleted Latches high when OUT12 goes from above VTH_PG to below VTH_PG. ......................................................... 21 • Added This bit is set each time channel is turned on. A second read cycle will indicate true status. ................................ 21 • Deleted Latches high when OUT3 goes from above VTH_PG to below VTH_PG. ........................................................... 21 • Added This bit is set each time channel is turned on. A second read cycle will indicate true status. ................................ 21 • Added This bit remains set until Register 8 is read. This bit is set each time channel is turned on. A second read cycle after turn on is required to determine true status. ..................................................................................................... 21 • Added This bit remains set until Register 8 is read. This bit is set each time channel is turned on. A second read cycle after turn on is required to determine true status. ..................................................................................................... 21 • Added This bit remains set until Register 8 is read. This bit is set each time channel is turned on. A second read cycle after turn on is required to determine true status. ..................................................................................................... 21 • Added New 12-V Channel Threshold Circuitry Diagram .................................................................................................... 26 • Added New RC Slew Rate Control Diagram ...................................................................................................................... 27 • Added New 12-V Path Diagram, replaced ORing Thresholds Diagram ............................................................................. 30 • Added image title: ORing Thresholds High Power vs. Low Power ..................................................................................... 31 • Changed From: programmable from 0.5 to 32 ms in steps of 0.5 To: programmable from 0.5 to 15.5 ms in steps of 0.5 ms ................................................................................................................................................................................. 34 • Added text "the following power" to the Fault Timer Programming section ........................................................................ 34 • Added New TPS3459 Redundant System Schematic Diagram ......................................................................................... 37 Submit Documentation Feedback Copyright © 2009–2013, Texas Instruments Incorporated Product Folder Links: TPS2459 41 TPS2459 SLUS917E – FEBRUARY 2009 – REVISED MAY 2013 www.ti.com Changes from Revision B (February 2010) to Revision C Page • Added Latches high when OUT12 goes from above VTH_PG to below VTH_PG. ........................................................... 21 • Added Latches high when OUT3 goes from above VTH_PG to below VTH_PG. ............................................................. 21 Changes from Revision C (March 2010) to Revision D Page • Changed the Turn off time From: µS To: µs ......................................................................................................................... 3 • Changed the Sourcing current From: mµ To: µA ................................................................................................................. 4 Changes from Revision D (May 2010) to Revision E Page • Changed the FAULT TIMER section of the ELECTRICAL CHARACTERISTICS table ....................................................... 3 • Changed Table 2: REGISTER 4 and REGISTER 5 From: fault time by 0.5, 1, 2, 4, 8 ms To: fault time by 0.45, 0.9, 1.80, 3.6, 7.2 ms ................................................................................................................................................................. 16 • Changed Table 4: Register 4 From: fault time by 0.5, 1, 2, 4, 8 ms To: fault time by 0.45, 0.9, 1.80, 3.6, 7.2 ms ........... 18 • Changed the 12FT[4:0] description From: The least-significant bit has a nominal weight of 0.5 ms, so fault times ranging from 0.5 ms (for code 00001B) to 15.5 ms (for code 11111B) can be programmed. To: The least-significant bit has a nominal weight of 0.45 ms, so fault times ranging from 0.45 ms (for code 00001B) to 13.95 ms (for code 11111B) can be programmed. ............................................................................................................................................ 18 • Changed Table 5: Register 5 From: fault time by 0.5, 1, 2, 4, 8 ms To: fault time by 0.45, 0.9, 1.80, 3.6, 7.2 ms ........... 19 • Changed the 3FT[4:0] description From: The least-significant bit has a nominal weight of 0.5 ms, so fault times ranging from 0.5 ms (for code 00001B) to 15.5 ms (for code 11111B) can be programmed. To: The least-significant bit has a nominal weight of 0.45 ms, so fault times ranging from 0.45 ms (for code 00001B) to 13.95 ms (for code 11111B) can be programmed. ............................................................................................................................................ 19 • Changed the Fault Timer Programming section and Table 13 ........................................................................................... 34 42 Submit Documentation Feedback Copyright © 2009–2013, Texas Instruments Incorporated Product Folder Links: TPS2459 PACKAGE MATERIALS INFORMATION www.ti.com 3-Jun-2022 TAPE AND REEL INFORMATION REEL DIMENSIONS TAPE DIMENSIONS K0 P1 B0 W Reel Diameter Cavity A0 B0 K0 W P1 A0 Dimension designed to accommodate the component width Dimension designed to accommodate the component length Dimension designed to accommodate the component thickness Overall width of the carrier tape Pitch between successive cavity centers Reel Width (W1) QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Sprocket Holes Q1 Q2 Q1 Q2 Q3 Q4 Q3 Q4 User Direction of Feed Pocket Quadrants *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TPS2459RHBR VQFN RHB 32 3000 330.0 12.4 5.3 5.3 1.5 8.0 12.0 Q2 TPS2459RHBT VQFN RHB 32 250 180.0 12.4 5.3 5.3 1.5 8.0 12.0 Q2 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 3-Jun-2022 TAPE AND REEL BOX DIMENSIONS Width (mm) W L H *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS2459RHBR VQFN RHB 32 3000 356.0 356.0 35.0 TPS2459RHBT VQFN RHB 32 250 210.0 185.0 35.0 Pack Materials-Page 2 GENERIC PACKAGE VIEW RHB 32 VQFN - 1 mm max height PLASTIC QUAD FLATPACK - NO LEAD 5 x 5, 0.5 mm pitch Images above are just a representation of the package family, actual package may vary. Refer to the product data sheet for package details. 4224745/A www.ti.com PACKAGE OUTLINE RHB0032E VQFN - 1 mm max height SCALE 3.000 PLASTIC QUAD FLATPACK - NO LEAD 5.1 4.9 A B PIN 1 INDEX AREA (0.1) 5.1 4.9 SIDE WALL DETAIL OPTIONAL METAL THICKNESS 20.000 C 1 MAX SEATING PLANE 0.05 0.00 0.08 C 2X 3.5 (0.2) TYP 3.45 0.1 9 EXPOSED THERMAL PAD 16 28X 0.5 8 17 2X 3.5 SEE SIDE WALL DETAIL SYMM 33 32X 24 1 PIN 1 ID (OPTIONAL) 32 0.3 0.2 0.1 0.05 C A B C 25 SYMM 32X 0.5 0.3 4223442/B 08/2019 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. www.ti.com EXAMPLE BOARD LAYOUT RHB0032E VQFN - 1 mm max height PLASTIC QUAD FLATPACK - NO LEAD ( 3.45) SYMM 32 25 32X (0.6) 1 24 32X (0.25) (1.475) 28X (0.5) 33 SYMM (4.8) ( 0.2) TYP VIA 8 17 (R0.05) TYP 9 (1.475) 16 (4.8) LAND PATTERN EXAMPLE SCALE:18X 0.07 MIN ALL AROUND 0.07 MAX ALL AROUND SOLDER MASK OPENING METAL SOLDER MASK OPENING METAL UNDER SOLDER MASK NON SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED SOLDER MASK DETAILS 4223442/B 08/2019 NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. www.ti.com EXAMPLE STENCIL DESIGN RHB0032E VQFN - 1 mm max height PLASTIC QUAD FLATPACK - NO LEAD 4X ( 1.49) (0.845) (R0.05) TYP 32 25 32X (0.6) 1 24 32X (0.25) 28X (0.5) (0.845) SYMM 33 (4.8) 17 8 METAL TYP 16 9 SYMM (4.8) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL EXPOSED PAD 33: 75% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE SCALE:20X 4223442/B 08/2019 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. www.ti.com IMPORTANT NOTICE AND DISCLAIMER TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, regulatory or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources. TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. TI objects to and rejects any additional or different terms you may have proposed. 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