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TPS24710, TPS24711
TPS24712, TPS24713
SLVSAL2G – JANUARY 2011 – REVISED NOVEMBER 2015
TPS2471x 2.5-V to 18-V High-Efficiency Power-Limiting Hot-Swap Controller
1 Features
3 Description
•
•
•
•
•
•
•
•
•
The TPS24710/11/12/13 is an easy-to-use, 2.5 V to
18 V, hot-swap controller that safely drives an
external N-channel MOSFET. The programmable
current limit and fault time protect the supply and load
from excessive current at startup. After startup,
currents above the user-selected limit will be allowed
to flow until programmed timeout – except in extreme
overload events when the load is immediately
disconnected from source. The low, 25mV current
sense threshold is highly accurate and allows use of
smaller, more efficient sense resistors yielding lower
power loss and smaller footprint.
1
•
•
2.5-V to 18-V Operation
Accurate Current Limiting for Startup
Programmable FET SOA Protection
Accurate 25-mV Current-Sense Threshold
Power-Good Output
Fast Breaker for Short-Circuit Protection
Programmable Fault Timer
Programmable UV Threshold
Drop-In Upgrade for LTC4211 – No Layout
Changes
PG, FLT Active-High and Active-Low Versions
MSOP-10 Package
Programmable power limiting ensures the external
MOSFET operates inside its safe operating area
(SOA) at all times. This allows the use of smaller
MOSFETS while improving system reliability. Power
good and fault outputs are provided for status
monitoring and downstream load control.
2 Applications
•
•
•
•
•
Server Backplanes
Storage Area Networks (SAN)
Medical Systems
Plug-In Modules
Base Stations
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
TPS24710
TPS24711
SSOP (10)
TPS24712
3.00 mm × 3.00 mm
TPS24713
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Typical Application (12 V at 10 A)
RSENSE
2 mΩ
VIN
M1
CSD16403Q5
VOUT
COUT
470 μF
C1
0.1 μF
RGATE
10 Ω
R1
130 kΩ
VCC
SENSE
3V
GATE
EN
R2
18.7 kΩ
OUT
R4
3.01 kΩ
R5
3.01 kΩ
PGb (PG)
TPS2471x
FLTb (FLT)
TIMER
PROG
CT
56 nF
RPROG
44.2 kΩ
GND
VUVLO = 10.8 V
ILMT = 12 A
tFAULT = 7.56 ms
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS24710, TPS24711
TPS24712, TPS24713
SLVSAL2G – JANUARY 2011 – REVISED NOVEMBER 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
4
4
5
7.1
7.2
7.3
7.4
7.5
7.6
7.7
5
5
5
5
6
7
9
Absolute Maximum Ratings ......................................
ESD Ratings ............................................................
Recommended Operating Conditions.......................
Thermal Information .................................................
Electrical Characteristics...........................................
Timing Requirements ................................................
Typical Characteristics ..............................................
Detailed Description ............................................ 13
8.1 Overview ................................................................. 13
8.2 Functional Block Diagram ....................................... 13
8.3 Feature Description................................................. 14
8.4 Device Functional Modes........................................ 17
9
Application and Implementation ........................ 24
9.1 Application Information............................................ 24
9.2 Typical Application ................................................. 24
10 Power Supply Recommendations ..................... 30
11 Layout................................................................... 31
11.1 Layout Guidelines ................................................. 31
11.2 Layout Example .................................................... 31
12 Device and Documentation Support ................. 32
12.1
12.2
12.3
12.4
12.5
12.6
Documentation Support .......................................
Related Links ........................................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
32
32
32
32
32
32
13 Mechanical, Packaging, and Orderable
Information ........................................................... 32
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision F (February 2015) to Revision G
Page
•
Changed the values of the Power limit threshold in Electrical Characteristics for VOUT = 7 V and VOUT = 2 V From:
10, 12.5, 15 mV To: 10.1, 11.6, 13.1 mV ............................................................................................................................... 7
•
Changed the title of Figure 8 From: MOSFET Gate Current vs Voltage Across RSENSE During Inrush Power Limiting
To: Gate Current vs Voltage Across RSENSE ........................................................................................................................... 9
•
Added Figure 9 ...................................................................................................................................................................... 9
•
Changed V(VCC–SENSE) To: V(SENSE–VCC) in Figure 10 and Figure 11 ........................................................................................ 9
•
Added Equation 1 ................................................................................................................................................................ 15
•
Added text to the PROG section: "To compute the Power limit based on an existing RPROG..." ......................................... 15
•
Changed Equation 2 ............................................................................................................................................................ 15
•
Changed text in STEP 3. Choose Power-Limit Value, PLIM, and RPROG From: "a 53.6-kΩ, 1% resistor is selected for
RPROG" To: a 44.2-kΩ, 1% resistor is selected for RPROG" .................................................................................................... 27
•
Changed Equation 9 ............................................................................................................................................................ 27
•
Added the Using Soft Start with TPS2471x section ............................................................................................................ 30
Changes from Revision E (November 2013) to Revision F
Page
•
Added ESD Rating table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section. ................................................................................................ 1
•
Changed the Input voltage range, PROG - MAX value in the Absolute Maximum Ratings table From: 0.3 To: 3.6 ............ 5
•
Deleted External capacitance - GATE from the Recommended Operating Conditions ......................................................... 5
•
Deleted text from the last paragraph in the GATE section "If used, any capacitor connecting GATE and GND should
not exceed 1 μF and it should be connected in series with a resistor of no less than 1 kΩ.".............................................. 15
•
Deleted section: Alternative Design Example: GATE Capacitor (dV/dt) Control in Inrush Mode......................................... 29
•
Deleted text from the High-Gate-Capacitance Applications section "When gate capacitor dV/dt control is used, ...
then a Zener diode is not necessary." .................................................................................................................................. 29
2
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TPS24712, TPS24713
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SLVSAL2G – JANUARY 2011 – REVISED NOVEMBER 2015
Changes from Revision D (November 2013) to Revision E
Page
•
Reverted Equation 2 in rev E back to rev C ......................................................................................................................... 15
•
Reverted Equation 9 in rev E back to rev C ......................................................................................................................... 27
Changes from Revision C (May 2011) to Revision D
Page
•
Added Note 1 to the Supply Current Conditions statement ................................................................................................... 6
•
Added Note 1 to Fast-turnoff delay ....................................................................................................................................... 7
•
Changed the Functional Block Diagram From: VCC = 6 V to VCC = 5.9 V at the Gate Comparator ..................................... 13
•
Changed text in the GATE section From: "Timer Activation Voltage (6 V for VVCC = 12 V)." To: "Timer Activation
Voltage (5.9 V for VVCC = 12 V).".......................................................................................................................................... 14
•
Changed the first paragraph of the Inrush Operation section .............................................................................................. 18
•
Added text and new Equation 10 ......................................................................................................................................... 27
•
Changed text prior to Equation 12 From: "6 V (for VVCC = 12 V)" To: "5.9 V (for VVCC = 12 V)".......................................... 28
•
Changed the text following Equation 12............................................................................................................................... 28
•
Changed text following Alternative Design Example: GATE Capacitor (dV/dt) Control in Inrush Mode From: "Set PLIM
to a value greater than VVCC × ICHG" To: "Choose ICHG < PLIM / VVCC" .................................................................................. 29
•
Changed Equation 15 From: – CISS To: – CRS (this equation deleted by Revision F).......................................................... 29
Changes from Revision B (April 2011) to Revision C
Page
•
Changed in PGb: from: 140V/340mV, to:170mV / 240mV .................................................................................................. 15
•
Changed in Equation 8: rDS(on) to RSENSE .............................................................................................................................. 27
Changes from Revision A (March 2011) to Revision B
•
Page
Corrected voltage values shown in Figure 26 ...................................................................................................................... 13
Copyright © 2011–2015, Texas Instruments Incorporated
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TPS24712, TPS24713
SLVSAL2G – JANUARY 2011 – REVISED NOVEMBER 2015
www.ti.com
5 Device Comparison Table
TPS2471
0
Latch Off
TPS2471
1
TPS24712
X
TPS24713
X
Retry
X
X
PG
L
L
H
H
FLT
L
L
H
H
6 Pin Configuration and Functions
DGS Package
(10 Pins)
Top View
PGb (PG)
1
10
EN
2
9
FLTb (FLT)
VCC
PROG
3
8
SENSE
TIMER
4
7
GATE
GND
5
6
OUT
Pin Functions
PINS
NAME
TPS24710/11 TPS24712/13
I/O
I
DESCRIPTION
EN
2
2
FLT
–
10
FLTb
10
–
GATE
7
7
O
Gate driver output for external MOSFET
GND
5
5
–
Ground
OUT
6
6
I
Output voltage sensor for monitoring MOSFET power.
PG
–
1
PGb
1
–
PROG
3
3
SENSE
8
TIMER
4
VCC
9
O
O
4
Active-high enable input. Logic input. Connects to resistor divider.
Active-high, open-drain output indicates overload fault timer has turned MOSFET off.
Active-low, open-drain output indicates overload fault timer has turned MOSFET off.
Active-high, open-drain power good indicator. Status is determined by the voltage
across the MOSFET.
Active-low, open-drain power good indicator. Status is determined by the voltage
across the MOSFET.
I
Power-limiting programming pin. A resistor from this pin to GND sets the maximum
power dissipation for the FET.
8
I
Current sensing input for resistor shunt from VCC to SENSE.
4
I/O
9
I
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A capacitor connected from this pin to GND provides a fault timing function.
Input-voltage sense and power supply
Copyright © 2011–2015, Texas Instruments Incorporated
Product Folder Links: TPS24710 TPS24711 TPS24712 TPS24713
TPS24710, TPS24711
TPS24712, TPS24713
www.ti.com
SLVSAL2G – JANUARY 2011 – REVISED NOVEMBER 2015
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range, all voltages referred to GND (unless otherwise noted)
Input voltage
range
(1)
MIN
MAX
EN, FLT (2) (3), FLTb (2) (4), GATE, OUT, PG (2) (3), PGb (2) (4), SENSE, VCC
–0.3
30
PROG (2)
–0.3
3.6
SENSE to VCC
–0.3
0.3
TIMER
–0.3
5
V
Sink current
FLT, PG, FLTb, PGb
Source current
PROG
Internally limited
Temperature
Maximum junction, TJ
Internally limited
(1)
(2)
(3)
(4)
UNIT
5
mA
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Do not apply voltages directly to these pins.
for TPS24712/13
for TPS24710/11
7.2 ESD Ratings
V(ESD)
Electrostatic
discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS- All pins except PG
001 (1)
and PGb
PG, PGb
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
(1)
(2)
VALUE
UNIT
±2000
V
±500
V
±500
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
2.5
18
EN, FLT, FLTb, PG, PGb, OUT
0
18
Sink current
FLT, FLTb, PG, PGb
0
2
mA
Resistance
PROG
4.99
500
kΩ
External capacitance
TIMER
1
Input voltage range
SENSE, VCC
NOM
Operating junction temperature range, TJ
V
nF
–40
125
°C
7.4 Thermal Information
TPS2471/x
THERMAL METRIC (1)
MSOP (10) PINS
RθJA
Junction-to-ambient thermal resistance
166.5
RθJC(top)
Junction-to-case (top) thermal resistance
41.8
RθJB
Junction-to-board thermal resistance
86.1
ψJT
Junction-to-top characterization parameter
1.5
ψJB
Junction-to-board characterization parameter
84.7
RθJC(bot)
Junction-to-case (bottom) thermal resistance
n/a
(1)
UNIT
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
Copyright © 2011–2015, Texas Instruments Incorporated
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7.5 Electrical Characteristics
–40°C ≤ TJ ≤ 125°C, VCC = 12 V, VEN = 3 V, and RPROG = 50 kΩ to GND.
All voltages referenced to GND, unless otherwise noted.
PARAMETER
CONDITIONS
MIN
NOM
MAX
UNIT
UVLO threshold, rising
2.2
2.32
2.45
V
UVLO threshold, falling
2.1
2.22
2.35
V
VCC
UVLO hysteresis (1)
Supply current
0.1
Enabled ― IOUT + IVCC + ISENSE
1
Disabled (1) ― EN = 0 V, IOUT + IVCC + ISENSE
V
1.4
0.45
mA
mA
EN
Threshold voltage, falling
1.2
Hysteresis (1)
Input leakage current
1.3
1.4
50
0 V ≤ VEN ≤ 30 V
–1
V
mV
0
1
µA
0.11
0.25
V
–1
0
1
µA
140
240
340
mV
FLT, FLTb
Output low voltage
Input leakage current
Sinking 2 mA
VFLT = 0 V, 30 V
VFLTb = 0 V, 30 V
PG, PGb
Threshold
Hysteresis (1)
Output low voltage
Input leakage current
V(SENSE – OUT) rising, PG going low
V(SENSE – OUT) rising, PGb going high
Measured V(SENSE – OUT) falling, PG going high
70
Measured V(SENSE – OUT) falling, PGb going low
Sinking 2 mA
VPG = 0 V, 30 V
VPGb = 0 V, 30 V
mV
0.11
0.25
V
–1
0
1
µA
PROG
Bias voltage
Sourcing 10 µA
0.65
0.678
0.7
V
Input leakage current
VPROG = 1.5 V
–0.2
0
0.2
µA
VTIMER = 0 V
8
10
12
µA
VTIMER = 2 V
8
10
12
µA
VEN = 0 V, VTIMER = 2 V
2
4.5
7
mA
1.30
1.35
1.40
V
0.33
0.35
0.37
V
5
5.9
7
V
70
104
130
kΩ
16
30
µA
23.5
25.8
28
V
TIMER
Sourcing current
Sinking current
Upper threshold voltage
Lower threshold voltage
Timer activation voltage
Raise GATE until ITIMER sinking, measure V(GATE – VCC), VCC = 12 V
Bleed-down resistance
VENSD = 0 V, VTIMER = 2 V
OUT
Input bias current
VOUT = 12 V
GATE
Output voltage
VOUT = 12 V
Clamp voltage
Inject 10 µA into GATE, measure V(GATE – VCC)
12
13.9
15.5
V
Sourcing current
VGATE = 12 V
20
30
40
µA
Fast turnoff, VGATE = 14 V
0.5
1
1.4
A
Sinking current
Pulldown resistance
(1)
6
Sustained, VGATE = 4 V to 23 V
6
11
20
mA
In inrush current limit, VGATE = 4 V to 23 V
20
30
40
µA
Thermal shutdown
14
20
26
kΩ
Parameters are for reference only, and do not constitute part of TI’s published specifications for purposes of TI’s product warranty.
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SLVSAL2G – JANUARY 2011 – REVISED NOVEMBER 2015
Electrical Characteristics (continued)
–40°C ≤ TJ ≤ 125°C, VCC = 12 V, VEN = 3 V, and RPROG = 50 kΩ to GND.
All voltages referenced to GND, unless otherwise noted.
PARAMETER
CONDITIONS
MIN
NOM
MAX
UNIT
SENSE
Input bias current
VSENSE = 12 V, sinking current
30
40
µA
Current limit threshold
VOUT = 12 V
22.5
25
27.5
mV
VOUT = 7 V, RPROG = 50 kΩ
10.1
11.6
13.1
VOUT = 2 V, RPROG = 25 kΩ
10.1
11.6
13.1
52
60
68
130
140
°C
10
°C
Power limit threshold
Fast-trip threshold
mV
mV
OTSD
Threshold, rising
Hysteresis (1)
7.6 Timing Requirements
MIN
NOM
MAX
UNIT
20
60
150
µs
8
14
18
µs
0.1
0.4
1
µs
2
3.4
6
ms
8
13.5
18
µs
100
250
µs
13.5
18
µs
EN
Turnoff time
EN ↓ to VGATE < 1 V, CGATE = 33 nF
Deglitch time
EN ↑
Disable delay
EN ↓ to GATE ↓, CGATE = 0, tpff50–90, See
Figure 1
PG, PGb
Delay (deglitch) time
Rising or falling edge
GATE
Fast-turnoff duration
VCC rising to GATE sourcing, tprr50-50, See
Figure 2
Turn on delay
SENSE
Fast-turnoff duration
Fast-turnoff delay
(1)
(1)
8
V(VCC – SENSE) = 80 mV, CGATE = 0 pF,
tprf50–50, See Figure 3
200
ns
Parameters are for reference only, and do not constitute part of TI’s published specifications for purposes of TI’s product warranty.
VGATE
90%
VEN
50%
0
Time
t(pff50-90)
T0492-01
Figure 1. tpff50–90 Timing Definition
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IGATE
50%
VVCC
50%
0
Time
t(prr50-50)
T0494-01
Figure 2. tprr50–50 Timing Definition
VGATE
50%
VVCC – VSENSE
50%
0
Time
t(prf50-50)
T0495-01
Figure 3. tprf50–50 Timing Definition
8
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SLVSAL2G – JANUARY 2011 – REVISED NOVEMBER 2015
7.7 Typical Characteristics
1200
5
4
T = 25°C
Supply Current (µA)
Supply Current (µA)
T = 125°C
1000
T = 125°C
800
T = –40°C
T = 25°C
3
2
T = –40°C
600
1
400
0
4
2
6
8
10
12
14
Input Voltage, VVCC (V)
16
18
0
20
EN = High
0
4
2
6
8
10
12
14
Input Voltage, VVCC (V)
16
18
20
EN = 0 V
Figure 4. Supply Current vs Input Voltage at Normal
Operation
Figure 5. Supply Current vs Input Voltage at Shutdown
32
26.5
28
Voltage ,V(VCC – SENSE) (mV)
Voltage, V(VCC – SENSE) (V)
VCC Voltage = 12 V
VVCC = 12 V
26
VVCC = 2.5 V
25.5
25
24.5
VVCC = 18 V
24
T = 125°C
T = 25°C
20
16
T = –40°C
12
8
23.5
–50
–20
10
40
70
Temperature (°C)
100
4
130
Figure 6. Voltage Across RSENSE in Inrush Current Limiting
vs Temperature
0
2
4
6
8
10
Voltage, V(SENSE – OUT) (V)
12
14
Figure 7. Voltage Across RSENSE in Inrush Power Limiting vs
VDS of Pass MOSFET
40
30
Gate Current at Current Limiting
32
TJ = 25°C
TJ = -40°C
TJ = 125°C
20
24
16
Gate Current (PA)
Gate Current (μA)
24
T = 25°C
8
0
T = 125°C
–8
–16
10
0
-10
T = –40°C
–24
-20
–32
–40
0
5
10
15 20 25 30 35 40
Voltage, V(VCC – SENSE) (mV)
45
50
55
VVCC = 12 V = VOUT
-30
1
2
3
4
5
6
7
Voltage, V(VCC-SENSE) (mV)
VVCC = 12 V
VGATE = 3 V
Figure 8. Gate Current vs Voltage Across R(SENSE)
Copyright © 2011–2015, Texas Instruments Incorporated
VOUT = 0 V
8
9
10
D001
RPROG = 50 kΩ
Figure 9. Gate Current vs V(VCC_SENSE)
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Typical Characteristics (continued)
T = 25°C
Gate Current (A)
1.2
0.9
0.2
0.7
0.15
0.6
0.1
1
0.05
V(SENSE – VCC)
0.8
0
T = 125°C
0.6
–0.05
0.4
–0.1
0.2
–0.15
0.25
0.2
T = –40°C
0.1
0.05
0.4
0.3
–0.1
0
–0.15
–0.1
–0.2
–10
–0.25
–0.2
–10
20
40
30
–0.2
VVCC = 3.3 V
0
10
7
32
TIMER Activation Voltage Threshold (V)
Gate Voltage Referenced to GND, VGATE (V)
–0.25
Figure 11. Gate Current During Fast Trip
T = 25°C
28
T = 125°C
24
20
T = –40°C
16
12
4
0
8
12
Input Voltage, VVCC (V)
16
T = 25°C
6
T = –40°C
5
4
4
0
8
12
Input Voltage, VVCC (V)
16
20
Figure 13. TIMER Activation Voltage Threshold vs Input
Voltage at Various Temperatures
2
2
VVCC = 12 V
CT = 10 nF
1.2
CT = 4.7 nF
0.8
CT = 1 nF
0.4
–20
10
40
70
Temperature (°C)
100
130
Figure 14. Fault-Timer Period vs Temperature With Various
TIMER Capacitors
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VVCC = 12 V
EN Threshold Voltage (V)
1.6
0
–50
T = 125°C
3
20
Figure 12. Gate Voltage With Zero Gate Current vs Input
Voltage
Fault-Timer Period (ms)
40
30
VVCC = VGATE = 3.3 V
Figure 10. Gate Current During Fast Trip
10
20
Time (μs)
Time (μs)
VVCC = VGATE = 12 V
8
–0.05
0.1
–0.2
10
0
V(SENSE – VCC)
T = 125°C
0.2
0
0
0.15
T = 25°C
0.5
Voltage, V(SENSE – VCC) (V)
T = –40°C
1.4
0.25
Gate Current (A)
VVCC = 12 V
Voltage, V(SENSE – VCC) (V)
1.8
1.6
EN Upper Threshold
1.6
1.2
0.8
0.4
0
–50
–20
–10
10
30
50
70
Temperature (°C)
90
110
130
Figure 15. EN Threshold Voltage vs Temperature
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Typical Characteristics (continued)
240
UVLO Threshold Voltage (V)
VVCC = 12 V
V(SENSE – OUT) Threshold Voltage (mV)
2.36
UVLO Upper Threshold
2.32
2.28
UVLO Lower Threshold
2.24
2.20
–50
–20
10
40
70
Temperature (°C)
100
Low-State Open-Drain Output Voltage (mV)
Fast-Trip Threshold Voltage (mV)
VVCC = 12 V
63
VVCC = 2.5 V
62.5
62
61.5
61
VVCC = 18 V
60.5
60
–50
–20
10
40
70
Temperature (°C)
100
130
PG Rising and PGb Falling
160
10
–20
40
70
Temperature (°C)
100
130
160
140
120
VVCC = 18 V
VVCC = 2.5 V
100
80
VVCC = 12 V
60
–50
10
–20
40
70
Temperature (°C)
100
130
Figure 19. PG and PGb Open-Drain Output Voltage in Low
State
Figure 18. Fast-Trip Threshold Voltage vs Temperature
160
0.7
VEN = 0 V
140
T = 125°C
0.6
Supply Current (µA)
Low-State Open-Drain Output Voltage (mV)
180
Figure 17. Threshold Voltage of VDS vs Temperature, PGb
and PG Rising and Falling
Figure 16. UVLO Threshold Voltage vs Temperature
63.5
200
140
–50
130
64
PG Falling and PGb Rising
220
120
VVCC = 2.5 V
VVCC = 18 V
100
80
T = 25°C
0.5
0.4
T = –40°C
0.3
VVCC = 12 V
60
–50
–20
10
40
70
Temperature (°C)
100
130
Figure 20. FLT and FLTb Open-Drain Output Voltage in Low
State
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0.2
0
4
8
12
Input Voltage, VVCC (V)
16
20
Figure 21. Supply Current vs Input Voltage at Various
Temperatures When EN Pulled Low
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Typical Characteristics (continued)
0.365
Timer Lower Threshold Voltage (V)
Timer Upper Threshold Voltage (V)
1.344
1.342
VVCC = 18 V
VVCC = 12 V
1.34
1.338
VVCC = 2.5 V
1.336
1.334
–50
–20
10
40
70
Temperature (°C)
100
Figure 22. Timer Upper Threshold Voltage vs Temperature
at Various Input Voltages
Timer Sinking Current (µA)
Timer Sourcing Current (µA)
–20
10
40
70
Temperature (°C)
10.3
VVCC = 18 V
VVCC = 12 V
9.9
9.8
9.7
VVCC = 2.5 V
9.6
100
130
VVCC = 18 V
VVCC = 12 V
10.2
10.1
10
VVCC = 2.5 V
9.9
9.8
–20
10
40
70
Temperature (°C)
100
130
Figure 24. Timer Sourcing Current vs Temperature at
Various Input Voltages
12
VVCC = 2.5 V
10.4
10.1
9.5
–50
0.36
Figure 23. Timer Lower Threshold Voltage vs Temperature
at Various Input Voltages
10.2
10
VVCC = 12 V
0.357
–50
130
VVCC = 18 V
0.362
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9.7
–50
–20
10
40
70
Temperature (°C)
100
130
Figure 25. Timer Sinking Current vs Temperature at Various
Input Voltages
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8 Detailed Description
8.1 Overview
The following description relies on the Typical Application (12 V at 10 A), as well as the functional block diagram
in Figure 26.
8.2 Functional Block Diagram
M1
VIN
RSENSE
SENSE
RGATE
GATE
8
OUT
7
6
60 mV
DC
+
Charge
Pump
–
RSET
Servo
Amplifier
RIMON
= 27
RSET
Inrush
Latch
+
30 µA
+
9
–
VCC
Fast
Comparator
–
S
Q
R
Q
+
VCC
5.9 V
11 mA
1-shot
Gate
Comparator
–
0~60 µA
RIMON
+
A
–
æ KpA
ö
, 675 mV ÷
è B
ø Main Opamp in Inrush
Min ç
+
PROG
Becomes Comparator
After Inrush Limit
Complete
20 kΩ
–
3
RPROG
UVLO
+
2.32 V
2.22 V
EN
B
–
OUT
DC
240 mV
170 mV
–
1
2 ms
+
PGb (PG)
PG
Comparator
+
2
1.35 V
1.3 V
–
14 µs
10 µA
10 FLTb (FLT)
Fault Logic
+
1.5 V
–
POR
+
TSD
1.35 V
0.35 V
10 µA
5
GND
4
TIMER
CT
B0438-02
NOTE: Pins 1 and 10 are PG and FLT, respectively, for TPS24712/13
Figure 26. Block Diagram of the TPS24710/11
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8.3 Feature Description
8.3.1 DETAILED PIN DESCRIPTIONS
8.3.1.1 EN
Applying a voltage of 1.35 V or more to this pin enables the gate driver. The addition of an external resistor
divider allows the EN pin to serve as an undervoltage monitor. Cycling EN low and then back high resets the
TPS24710/11/12/13 that has latched off due to a fault condition. This pin should not be left floating.
8.3.1.2 FLT
FLT is assigned for TPS24712/13. This active-high open-drain output assumes high-impedance when
TPS24712/13 has remained in current limit long enough for the fault timer to expire. The behavior of the FLT pin
depends on the version of the IC. The TPS24712 operates in latch mode and the TPS24713 operates in retry
mode. In latch mode, a fault timeout disables the external MOSFET and holds FLT in open drain condition. The
latched mode of operation is reset by cycling EN or VCC. In retry mode, a fault timeout first disables the external
MOSFET, next waits sixteen cycles of TIMER charging and discharging, and finally attempts a restart. This
process repeats as long as the fault persists. In retry mode, the FLT pin goes open-drain whenever the external
MOSFET is disabled by the fault timer. In a sustained fault, the FLT waveform becomes a train of pulses. The
FLT pin does not assert if the external MOSFET is disabled by EN, overtemperature shutdown, or UVLO. This
pin can be left floating when not used.
8.3.1.3 FLTb
FLTb is assigned for TPS24710/11. This active-low open-drain output pulls low when TPS24710/11/12/13 has
remained in current limit long enough for the fault timer to expire. The behavior of the FLTb pin depends on the
version of the IC. The TPS24710 operates in latch mode and the TPS24711 operates in retry mode. In latch
mode, a fault timeout disables the external MOSFET and holds FLTb low. The latched mode of operation is reset
by cycling EN or VCC. In retry mode, a fault timeout first disables the external MOSFET, next waits sixteen
cycles of TIMER charging and discharging, and finally attempts a restart. This process repeats as long as the
fault persists. In retry mode, the FLTb pin is pulled low whenever the external MOSFET is disabled by the fault
timer. In a sustained fault, the FLTb waveform becomes a train of pulses. The FLTb pin does not assert if the
external MOSFET is disabled by EN, overtemperature shutdown, or UVLO. This pin can be left floating when not
used.
8.3.1.4 GATE
This pin provides gate drive to the external MOSFET. A charge pump sources 30 µA to enhance the external
MOSFET. A 13.9-V clamp between GATE and VCC limits the gate-to-source voltage, because VVCC is very close
to VOUT in normal operation. During start-up, a transconductance amplifier regulates the gate voltage of M1 to
provide inrush current limiting. The TIMER pin charges timer capacitor CT during the inrush. Inrush current
limiting continues until the V(GATE – VCC) exceeds the Timer Activation Voltage (5.9 V for VVCC = 12 V). Then the
TPS24710/11/12/13 enters into circuit-breaker mode. The Timer Activation Voltage is defined as a threshold
voltage. When V(GATE-VCC) exceeds this threshold voltage, the inrush operation is finished and the TIMER stops
sourcing current and begins sinking current. In the circuit-breaker mode, the current flowing in RSENSE is
compared with the current-limit threshold derived from the MOSFET power-limit scheme (see PROG). If the
current flowing in RSENSE exceeds the current limit threshold, then MOSFET M1 is turned off. The GATE pin is
disabled by the following three conditions:
1. GATE is pulled down by an 11-mA current source when
– The fault timer expires during an overload current fault (VSENSE > 25 mV)
– VEN is below its falling threshold
– VVCC drops below the UVLO threshold
2. GATE is pulled down by a 1 A current source for 13.5 µs when a hard output short circuit occurs and
V(VCC – SENSE) is greater than 60 mV, i.e., the fast-trip shutdown threshold. After fast-trip shutdown is
complete, an 11-mA sustaining current ensures that the external MOSFET remains off.
3. GATE is discharged by a 20 kΩ resistor to GND if the chip die temperature exceeds the OTSD rising
threshold.
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Feature Description (continued)
GATE remains low in latch mode (TPS24710/12) and attempts a restart periodically in retry mode
(TPS24711/13).
No external resistor should be directly connected from GATE to GND or from GATE to OUT.
8.3.1.5 GND
This pin is connected to system ground.
8.3.1.6 OUT
This pin allows the controller to measure the drain-to-source voltage across the external MOSFET M1. The
power-good indicator (PG/PGb) relies on this information, as does the power limiting engine. The OUT pin should
be protected from negative voltage transients by a clamping diode or sufficient capacitors. A Schottky diode of
3 A / 40 V in a SMC package is recommended as a clamping diode for high-power applications. The OUT pin
should be bypassed to GND with a low-impedance ceramic capacitor in the range of 10 nF to 1 μF.
8.3.1.7 PG
PG is assigned for TPS24712/13. This active-high, open-drain output is intended to interface to downstream
dc/dc converters or monitoring circuits. PG assumes high-impedance after the drain-to-source voltage of the FET
has fallen below 170 mV and a 3.4-ms deglitch delay has elapsed. It pulls low when VDS exceeds 240 mV. PG
assumes low-impedance status after a 3.4-ms deglitch delay once VDS of M1 rises up, resulting from GATE being
pulled to GND at any of the following conditions:
• An overload current fault occurs (VSENSE > 25 mV).
• A hard output short circuit occurs, leading to V(VCC – SENSE) greater than 60 mV, i.e., the fast-trip shutdown
threshold has been exceeded.
• VEN is below its falling threshold.
• VVCC drops below the UVLO threshold.
• Die temperature exceeds the OTSD threshold.
This pin can be left floating when not used.
8.3.1.8 PGb
PGb is assigned for TPS24710/11. This active-low, open-drain output is intended to interface to downstream
dc/dc converters or monitoring circuits. PGb pulls low after the drain-to-source voltage of the FET has fallen
below 170 mV and a 3.4-ms deglitch delay has elapsed. It goes open-drain when VDS exceeds 240 mV. PGb
assumes high-impedance status after a 3.4-ms deglitch delay once VDS of M1 rises up, resulting from GATE
being pulled to GND at any of the following conditions:
• An overload current fault occurs (VSENSE > 25 mV).
• A hard output short circuit occurs, leading to V(VCC – SENSE) greater than 60 mV, i.e., the fast-trip shutdown
threshold has been exceeded.
• VEN is below its falling threshold.
• VVCC drops below the UVLO threshold.
• Die temperature exceeds the OTSD threshold.
This pin can be left floating when not used.
8.3.1.9 PROG
A resistor from this pin to GND sets the maximum power permitted in the external MOSFET M1 during inrush. Do
not apply a voltage to this pin. If the constant power limit is not desired, use a PROG resistor of 4.99 kΩ. To set
the maximum power, use Equation 1.
3125
RPROG =
PLIM ´ RSENSE + 0.9 mV ´ VVCC
(1)
To compute the Power limit based on an existing RPROG use Equation 2.
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Feature Description (continued)
PLIM =
0.9 mV ´ V(VCC-OUT)
3125
RPROG ´ RSNS
RSNS
(2)
where PLIM is the allowed power limit of MOSFET M1. RSENSE is the load-current-monitoring resistor connected
between the VCC pin and the SENSE pin. RPROG is the resistor connected from the PROG pin to GND. Both
RPROG and RSENSE are in ohms and PLIM is in watts. PLIM is determined by the maximum allowed thermal stress of
MOSFET M1, given by Equation 3,
TJ(MAX) - TC(MAX)
PLIM <
RθJC(MAX)
(3)
where TJ(MAX) is the maximum desired transient junction temperature and TC(MAX) is the maximum case
temperature prior to a start or restart. RӨJC(MAX) is the junction-to-case thermal impedance of the pass MOSFET
M1 in units of °C/W. Both TJ(MAX) and TC(MAX) are in °C.
8.3.1.10 SENSE
This pin connects to the negative terminal of RSENSE. It provides a means of sensing the voltage across this
resistor, as well as a way to monitor the drain-to-source voltage across the external FET. The current limit ILIM is
set by Equation 4.
ILIM = 25 mV
RSENSE
(4)
A fast trip shutdown occurs when V(VCC – VSENSE) exceeds 60 mV.
8.3.1.11 TIMER
A capacitor CT connected from the TIMER pin to GND determines the overload fault timing. TIMER sources 10
µA when an overload is present, and discharges CT at 10 µA otherwise. M1 is turned off when VTIMER reaches
1.35 V. In an application implementing auto-retry after a fault, this capacitor also determines the period before
the external MOSFET is re-enabled. A minimum timing capacitance of 1 nF is recommended to ensure proper
operation of the fault timer. The value of CT can be calculated from the desired fault time tFLT, using Equation 5.
10 μA
CT =
´ tFLT
1.35 V
(5)
The latch mode (TPS24710/12) or the retry mode (TPS24711/13) occurs if the load current exceeds the current
limit threshold or the fast-trip shutdown threshold, While in latch mode, the TIMER pin continues to charge and
discharge the attached capacitor periodically. In retry mode, the external MOSFET is disabled for sixteen cycles
of TIMER charging and discharging. The TIMER pin is pulled to GND by a 2-mA current source at the end of the
16th cycle of charging and discharging. The external MOSFET is then re-enabled. The TIMER pin capacitor, CT,
can also be discharged to GND during latch mode or retry mode by a 2-mA current source whenever any of the
following occurs:
• VEN is below its falling threshold.
• VVCC drops below the UVLO threshold.
8.3.1.12 VCC
This pin performs three functions. First, it provides biasing power to the integrated circuit. Second, it serves as an
input to the power-on reset (POR) and undervoltage lockout (UVLO) functions. The VCC trace from the
integrated circuit should connect directly to the positive terminal of RSENSE to minimize the voltage sensing error.
Bypass capacitor C1, shown in the typical application diagram on the front page, should be connected to the
positive terminal of RSENSE. A capacitance of at least 10 nF is recommended.
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8.4 Device Functional Modes
The TPS24710/11/12/13 provides all the features needed for a positive hot-swap controller. These features
include:
• Undervoltage lockout
• Adjustable (system-level) enable
• turn-on inrush limiting
• High-side gate drive for an external N-channel MOSFET
• MOSFET protection by power limiting
• Adjustable overload timeout — also called an electronic circuit breaker
• Charge-complete indicator for downstream converter coordination
• A choice of latch (TPS24710/12) or automatic restart mode (TPS24711/13)
The Typical Application (12 V at 10 A), and oscilloscope plots shown in Figure 27 through Figure 29 and
Figure 31 through Figure 34, demonstrate many of the functions described previously.
8.4.1 Board Plug In
Figure 27 and Figure 28 illustrate the inrush current that flows when a hot swap board under the control of the
TPS24710/11/12/13 is plugged into a system bus. Only the bypass capacitor charge current and small bias
currents are evident when a board is first plugged in. The TPS24710/11/12/13 is held inactive, for a short period
while internal voltages stabilize. During this period GATE, PROG, TIMER are held low and PG, FLT, PGb, and
FLTb are held open drain. When the voltage on the internal VCC rail exceeds approximately 1.5 V, the power-on
reset (POR) circuit initializes the TPS24710/11/12/13 and a start-up cycle is ready to take place.
GATE, PROG, TIMER, PG, FLT, PGb, and FLTb are released after the internal voltages have stabilized and the
external EN (enable) thresholds have been exceeded. The part begins sourcing current from the GATE pin to
turn on MOSFET M1. The TPS24710/11/12/13 monitors both the drain-to-source voltage across MOSFET M1
and the drain current passing through it. Based on these measurements, the TPS24710/11/12/13 limits the drain
current by controlling the gate voltage so that the power dissipation within the MOSFET does not exceed the
power limit programmed by the user. The current increases as the voltage across the MOSFET decreases until
finally the current reaches the current limit ILIM.
Figure 27. Inrush Mode at Hot-Swap Circuit Insertion
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Device Functional Modes (continued)
8.4.2 Inrush Operation
After TPS24710/11/12/13 initialization is complete (as described in the Board Plug-In section) and EN is active,
GATE is enabled (VGATE starts increasing). When VGATE reaches the MOSFET M1 gate threshold, a current flows
into the downstream bulk storage capacitors. When this current exceeds the limit set by the power limit engine,
the gate of the MOSFET is regulated by a feedback loop to make the MOSFET current rise in a controlled
manner. This not only limits the inrush current charging capacitance but it also limits the power dissipation of the
MOSFET to safe levels. A more complete explanation of the power limiting scheme is given in the section
entitled Action of the Constant Power Engine. When Gate is enabled, the TIMER pin begins to charge the timing
capacitor CT with a current of approximately 10 μA. The TIMER pin continues to charge CT until V(GATE – VCC)
reaches the timer activation voltage (5.9 V for VVCC = 12 V). The TIMER then begins to discharge CT with a
current of approximately 10 μA. This indicates that the inrush mode is finished. If the TIMER exceeds its upper
threshold of 1.35 V before V(GATE – VCC) reaches the timer activation voltage, the GATE pin is pulled to GND and
the hot-swap circuit enters either latch mode (TPS24710/12) or auto-retry mode (TPS24711/13).
The power limit feature is disabled once the inrush operation is finished and the hotswap circuit becomes a
circuit breaker. The TPS24710/11/12/13 will turn off the MOSFET, M1, after a fault timer period once the load
exceeds the current limit threshold.
8.4.3 Action of the Constant-Power Engine
Figure 28 illustrates the operation of the constant-power engine during start-up. The circuit used to generate the
waveforms of Figure 28 was programmed to a power limit of 29.3 W by means of the resistor connected between
PROG and GND. At the moment current begins to flow through the MOSFET, a voltage of 12 V appears across
it (input voltage VVCC = 12 V), and the constant-power engine therefore allows a current of 2.44 A (equal to 29.3
W divided by 12 V) to flow. This current increases in inverse ratio as the drain-to-source voltage diminishes, so
as to maintain a constant dissipation of 29.3 W. The constant-power engine adjusts the current by altering the
reference signal fed to the current limit amplifier. The lower part of Figure 29 shows the measured power
dissipated within the MOSFET, labeled FET PWR, remaining substantially constant during this period of
operation, which ends when the current through the MOSFET reaches the current limit ILIM. This behavior can be
considered a form of foldback limiting, but unlike the standard linear form of foldback limiting, it allows the power
device to operate near its maximum capability, thus reducing the start-up time and minimizing the size of the
required MOSFET.
I_IN: Input Current, 2 A/div
GAT: Voltage on GATE Pin, 5 V/div
V_DS: Drain-to-Source Voltage of M1, 5 V/div
TIMER: Voltage on TIMER Pin, 500 mV/div
FET_PWR: Power on M1 (product of V_DS and I_IN), 19 W/div
Time: 10 ms/div
C002
Figure 28. Computation of M1 Power Stress During Start-Up
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Device Functional Modes (continued)
8.4.4 Circuit Breaker and Fast Trip
The TPS24710/11/12/13 monitors load current by sensing the voltage across RSENSE. The TPS24710/11/12/13
incorporates two distinct thresholds: a current-limit threshold and a fast-trip threshold.
The functions of circuit breaker and fast-trip turn off are shown in Figure 29 through Figure 32.
Figure 29 shows the behavior of the TPS24710/11 when a fault in the output load causes the current passing
through RSENSE to increase to a value above the current limit but less than the fast-trip threshold. When the
current exceeds the current-limit threshold, a current of approximately 10 μA begins to charge timing capacitor
CT. If the voltage on CT reaches 1.35 V, then the external MOSFET is turned off. The TPS24710 latches off and
the TPS24711 commences a restart cycle. In either event, fault pin FLTb pulls low to signal a fault condition.
Overload between the current limit and the fast trip threshold is permitted for this period. This shutdown scheme
is sometimes called an electronic circuit breaker.
The fast-trip threshold protects the system against a severe overload or a dead short circuit. When the voltage
across the sense resistor RSENSE exceeds the 60 mV fast-trip threshold, the GATE pin immediately pulls the
external MOSFET gate to ground with approximately 1 A of current. This extremely rapid shutdown may
generate disruptive transients in the system, in which case a low-value resistor inserted between the GATE pin
and the MOSFET gate can be used to moderate the turn off current. The fast-trip circuit holds the MOSFET off
for only a few microseconds, after which the TPS24710/11/12/13 turns back on slowly, allowing the current-limit
feedback loop to take over the gate control of M1. Then the hot-swap circuit goes into either latch mode
(TPS24710/12) or auto-retry mode (TPS24711/13). Figure 31 and Figure 32 illustrate the behavior of the system
implementing TPS24710/11 when the current exceeds the fast-trip threshold.
Figure 29. Circuit Breaker Mode During Over Load Condition
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Device Functional Modes (continued)
ILIMIT
M1
RSENSE
RGATE
VCC
9
RSET
SENSE
GATE
8
7
OUT
6
+
60 mV
+
Server
Amplifier
–
–
Fast Trip
Comparator
A1
60 μA
+
675 mV
PROG
RIMON
VCP
–
Current
Limit Amp
3
RPROG
A2
30 μA
+
B0439-02
Figure 30. Partial Diagram of the TPS24710/11/12/13 With Selected External Components
Figure 31. Current Limit During Output Load Short Circuit
Condition (Overview)
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Figure 32. Current Limit During Output-Load Short-Circuit
Condition (Onset)
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Device Functional Modes (continued)
8.4.5 Automatic Restart
The TPS24711/13 automatically initiates a restart after a fault has caused it to turn off the external MOSFET M1.
Internal control circuits use CT to count 16 cycles before re-enabling M1 as shown in Figure 33 (TPS24711). This
sequence repeats if the fault persists. The timer has a 1 : 1 charge-to-discharge current ratio. For the very first
cycle, the TIMER pin starts from 0 V and rises to the upper threshold of 1.35 V and subsequently falls to 0.35 V
before restarting. For the following 16 cycles, 0.35 V is used as the lower threshold. This small duty cycle often
reduces the average short-circuit power dissipation to levels associated with normal operation and eliminates
special thermal considerations for surviving a prolonged output short.
Figure 33. Auto-Restart Cycle Timing
Figure 34. Latch After Overload Fault
8.4.6 PG, FLT, PGb, FLTb, and Timer Operations
The open-drain PG/PGb (PG is for TPS24712/13 and PGb is for TPS24710/11) output provides a deglitched
end-of-inrush indication based on the voltage across M1. PG/PGb is useful for preventing a downstream dc/dc
converter from starting while its input capacitor COUT is still charging. PG goes active-high and PGb goes activelow about 3.4 ms after COUT is charged. This delay allows M1 to fully turn on and any transients in the power
circuits to end before the converter starts up. This type of sequencing prevents the downstream converter from
demanding full current before the power-limiting engine allows the MOSFET to conduct the full current set by the
current limit ILIM. Failure to observe this precaution may prevent the system from starting. The pullup resistor
shown on the PG/PGb pin in the typical application diagram on the front page is illustrative only; the actual
connection to the converter depends on the application. The PG/PGb pin may indicate that inrush has ended
before the MOSFET is fully enhanced, but the downstream capacitor will have been charged to substantially its
full operating voltage. Care should be taken to ensure that the MOSFET on-resistance is sufficiently small to
ensure that the voltage drop across this transistor is less than the minimum power-good threshold of 140 mV.
After the hot-swap circuit successfully starts up, the PG pin can return to a low-impedance status and PGb to
high-impedance status whenever the drain-to-source voltage of MOSFET M1 exceeds its upper threshold of
340 mV, which presents the downstream converters a warning flag. This flag may occur as a result of overload
fault, output short fault, input overvoltage, higher die temperature, or the GATE shutdown by UVLO and EN.
FLT/FLTb (FLT is for TPS24712/13 and FLTb is for TPS24710/11) is an indicator that the allowed fault-timer
period during which the load current can exceed the programmed current limit (but not the fast-trip threshold) has
expired. The fault timer starts when a current of approximately 10 μA begins to flow into the external capacitor,
CT, and ends when the voltage of CT reaches TIMER upper threshold, i.e., 1.35 V. FLT goes high and FLTb pulls
low at the end of the fault timer. Otherwise, FLT assumes a low-impedance state and FLTb a high-impedance
state.
The fault-timer state requires an external capacitor CT connected between the TIMER pin and GND pin. The
length of the fault timer is the charging time of CT from 0 V to its upper threshold of 1.35 V. The fault timer begins
to count under any of the following three conditions:
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Device Functional Modes (continued)
1. In the inrush mode, TIMER begins to source current to the timer capacitor, CT, when MOSFET M1 is
enabled. TIMER begins to sink current from the timer capacitor, CT when V(GATE – VCC) exceeds the timer
activation voltage (see the Inrush Operation section). If V(GATE – VCC) does not reach the timer activation
voltage before TIMER reaches 1.35 V, then the TPS24710/11/12/13 disables the external MOSFET M1. After
the MOSFET turns off, the timer goes into either latch mode (TPS24710/12) or retry mode (TPS24711/13).
2. In an overload fault, TIMER begins to source current to the timer capacitor, CT, when the load current
exceeds the programmed current limits. When the timer capacitor voltage reaches its upper threshold of
1.35 V, TIMER begins to sink current from the timer capacitor, CT, and the GATE pin is pulled to ground.
After the fault timer period, TIMER may go into latch mode (TPS24710/12) or retry mode (TPS24711/13).
3. In output short-circuit fault, TIMER begins to source current to the timer capacitor, CT, when the load current
exceeds the programmed current limits following a fast-trip shutdown of M1. When the timer capacitor voltage
reaches its upper threshold of 1.35 V, TIMER begins to sink current from the timer capacitor, CT, and the
GATE pin is pulled to ground. After the fault timer period, TIMER may go into latch mode (TPS24710/12) or
retry mode (TPS24711/13).
If the fault current drops below the programmed current limit within the fault timer period, VTIMER decreases and
the pass MOSFET remains enabled.
The behaviors of TIMER are different in the latch mode (TPS24710/12) and retry mode (TPS24711/13). If the
timer capacitor reaches the upper threshold of 1.35 V, then:
• In latch mode, the GATE remains low and the TIMER pin continues to charge and discharge the attached
capacitor periodically until TPS24710/12 is disabled by UVLO or EN as shown in Figure 34.
• In retry mode, TIMER charges and discharges CT between the lower threshold of 0.35 V and the upper
threshold of 1.35 V for sixteen cycles before the TPS24711/13 attempts to re-start. The TIMER pin is pulled
to GND at the end of the 16th cycle of charging and discharging and then ramps from 0 V to 1.35 V for the
initial half-cycle in which the GATE pin sources current. This periodic pattern is stopped once the overload
fault is removed or the TPS24711/13 is disabled by UVLO or EN.
8.4.7 Overtemperature Shutdown
The TPS24710/11/12/13 includes a built-in overtemperature shutdown circuit designed to disable the gate driver
if the die temperature exceeds approximately 140°C. An overtemperature condition also causes the FLT, PG,
FLTb and PGb pins to go to high-impedance states. Normal operation resumes once the die temperature has
fallen approximately 10°C.
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Device Functional Modes (continued)
8.4.8 Start-Up of Hot-Swap Circuit by VCC or EN
The connection and disconnection between a load and the system bus are controlled by turning on and turning
off the MOSFET, M1.
The TPS24710/11/12/13 has two ways to turn on MOSFET M1:
1. Increasing VVCC above UVLO upper threshold while EN is already higher than its upper threshold sources
current to the GATE pin. After an inrush period, TPS24710/11/12/13 fully turns on MOSFET M1.
2. Increasing EN above its upper threshold while VVCC is already higher than UVLO upper threshold sources
current to the GATE pin. After an inrush period, TPS24710/11/12/13 fully turns on MOSFET M1.
The EN pin can be used to start up the TPS24710/11/12/13 at a selected input voltage VVCC.
To isolate the load from the system bus, the GATE pin sinks current and pulls the gate of MOSFET M1 low. The
MOSFET can be disabled by any of the following conditions: UVLO, EN, load current above current limit
threshold, hard short at load, or OTSD. Three separate conditions pull down the GATE pin:
1. GATE is pulled down by an 11-mA current source when any of the following occurs.
– The fault timer expires during an overload current fault (VSENSE > 25 mV).
– VEN is below its falling threshold.
– VVCC drops below the UVLO threshold.
2. GATE is pulled down by a 1-A current source for 13.5 µs when a hard output short circuit occurs and V(VCC –
SENSE) is greater than 60 mV, i.e., the fast-trip shutdown threshold. After fast-trip shutdown is complete, an
11-mA sustaining current ensures that the external MOSFET remains off.
3. GATE is discharged by a 20-kΩ resistor to GND if the chip die temperature exceeds the OTSD rising
threshold.
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The TPS2471x is a hotswap used to manage inrush current and provide load fault protection. When designing a
hotswap, three key scenarios should be considered:
• Start-up
• Output of a hotswap is shorted to ground when the hotswap is on. This is often referred to as a hot-short.
• Powering-up a board when the output and ground are shorted. This is usually called a start-into-short.
Each of these scenarios place stress on the hotswap MOSFET. Take special care when designing the hotswap
circuit to keep the MOSFET within its SOA. The following design example is provided as a guide. Use the
TPS24710 Design Calculator (SLVC566) to assist with the detailed design equation calculations.
9.2 Typical Application
This section provides an application example utilizing power limited start-up and MOSFET SOA protection. The
design parameters are listed in the Design Requirements section and represent a more moderate level of fault
current. For more stringent current levels, refer to either the TPS2471xEVM (SLUU459) (25 A design) or the
calculator tool (SLVC566) (50 A design).
RSENSE
2 mΩ
VIN
M1
CSD16403Q5
VOUT
COUT
470 μF
C1
0.1 μF
RGATE
10 Ω
R1
130 kΩ
VCC
SENSE
3V
GATE
EN
R2
18.7 kΩ
OUT
R4
3.01 kΩ
R5
3.01 kΩ
PGb (PG)
TPS2471x
FLTb (FLT)
TIMER
PROG
CT
56 nF
RPROG
44.2 kΩ
GND
VUVLO = 10.8 V
ILMT = 12 A
tFAULT = 7.56 ms
Figure 35. Typical Application (12 V at 10 A)
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Typical Application (continued)
9.2.1 Design Requirements
For this design example, use the parameters shown in Table 1.
Table 1. Design Parameters
PARAMETER
VALUE
Input voltage
12 V ±2V
Maximum operating load current
10 A
Operating temperature
20°C —50°C
Fault trip current
12 A
Load capacitance
470 µF
9.2.2 Detailed Design Procedure
9.2.2.1 Power-Limited Start-Up
This design example assumes a 12-V system voltage with an operating tolerance of ±2 V. The rated load current
is 10 A, corresponding to a dc load of 1.2 Ω. If the current exceeds 12 A, then the controller should shut down
and then attempt to restart. Ambient temperatures may range from 20°C to 50°C. The load has a minimum input
capacitance of 470 μF. Figure 36 shows a simplified system block diagram of the proposed application.
This design procedure seeks to control the junction temperature of MOSFET M1 under both static and transient
conditions by proper selection of package, cooling, rDS(on), current limit, fault timeout, and power limit. The design
procedure further assumes that a unit running at full load and maximum ambient temperature experiences a brief
input-power interruption sufficient to discharge COUT, but short enough to keep M1 from cooling. A full COUT
recharge then takes place. Adjust this procedure to fit your application and design criteria.
PROTECTION
RSENSE
LOAD
M1
0.1 μF
0.1 μF
RGATE
Specifications (at Output):
Peak Current Limit = 12 A
Nominal Current = 10 A
COUT
470 μF
OUT
GATE
SENSE
VCC
12-V Main Bus Supply
RLOAD
1.2 W
GND
TPS2471x
TIMER
CT
B0440-02
Figure 36. Simplified Block Diagram of the System Constructed in the Design Example
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9.2.2.1.1 STEP 1. Choose RSENSE
From the TPS24710/11/12/13 electrical specifications, the current-limit threshold voltage, V(VCC – SENSE), is around
25 mV. A resistance of 2 mΩ is selected for the peak current limit of 12 A, while dissipating only 200 mW at the
rated 10-A current (see Equation 6). This represents a 0.17% power loss.
V(VCC - SENSE )
RSENSE =
,
ILIM
therefore,
RSENSE =
25 mV
» 2 mW
12 A
(6)
9.2.2.1.2 STEP 2. Choose MOSFET M1
The next design step is to select M1. The TPS24710/11/12/13 is designed to use an N-channel MOSFET with a
gate-to-source voltage rating of 20 V.
Devices with lower gate-to-source voltage ratings can be used if a Zener diode is connected so as to limit the
maximum gate-to-source voltage across the transistor.
The next factor to consider is the drain-to-source voltage rating, VDS(MAX), of the MOSFET. Although the
MOSFET only sees 12 V DC, it may experience much higher transient voltages during extreme conditions, such
as the abrupt shutoff that occurs during a fast trip. A TVS may be required to limit inductive transients under such
conditions. A transistor with a VDS(MAX) rating of at least twice the nominal input power-supply voltage is
recommended regardless of whether a TVS is used or not.
Next select the on resistance of the transistor, rDS(on). The maximum on-resistance must not generate a voltage
greater then the minimum power-good threshold voltage of 140 mV. Assuming a current limit of 12 A, a
maximum rDS(on) of 11.67 mΩ is required. Also consider the effect of rDS(on) upon the maximum operating
temperature TJ(MAX) of the MOSFET. Equation 7 computes the value of rDS(on)(MAX) at a junction temperature of
TJ(MAX). Most manufacturers list rDS(on)(MAX) at 25°C and provide a derating curve from which values at other
temperatures can be derived. Compute the maximum allowable on-resistance, rDS(on)(MAX), using Equation 7.
TJ(MAX) - TA(MAX)
rDS(on)(MAX) =
,
IMAX2 ´ RqJA
therefore,
rDS(on)(MAX) =
150°C - 50°C
(12 A )2 ´ 51°C / W
= 13.6 mW
(7)
Taking these factors into consideration, the TI CSD16403Q5 was selected for this example. This transistor has a
VGS(MAX) rating of 16 V, a VDS(MAX) rating of 25 V, and a maximum rDS(on) of 2.8 mΩ at room temperature. During
normal circuit operation, the MOSFET can have up to 10 A flowing through it. The power dissipation of the
MOSFET equates to 0.24 W and a 9.6°C rise in junction temperature. This is well within the data sheet limits for
the MOSFET. The power dissipated during a fault (e.g., output short) is far larger than the steady-state power.
The power handling capability of the MOSFET must be checked during fault conditions.
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9.2.2.1.3 STEP 3. Choose Power-Limit Value, PLIM, and RPROG
MOSFET M1 dissipates large amounts of power during inrush. The power limit PLIM of the TPS24710/11/12/13
should be set to prevent the die temperature from exceeding a short-term maximum temperature, TJ(MAX)2. The
short-term TJ(MAX)2 could be set as high as 130°C while still leaving ample margin to the usual manufacturer’s
rating of 150°C. Equation 8 is an expression for calculating PLIM,
TJ(MAX)2 - é IMAX2 ´ r DS(on) ´ RqCA + TA(MAX) ù
ë
û,
PLIM £ 0.8 ´
RqJC
(
)
therefore,
PLIM £ 0.8 ´
130°C - é
ëê
((12 A ) ´ 0.002 W ´ (51°C / W - 1.8°C / W )) + 50°Cûúù = 29.3 W
2
1.8°C / W
(8)
where RθJC is the junction-to-case thermal resistance of the MOSFET, rDS(on) is the resistance at the maximum
operating temperature, and the factor of 0.8 represents the tolerance of the constant-power engine. For an
ambient temperature of 50°C, the calculated maximum PLIM is 29.3 W. From Equation 2, a 44.2-kΩ, 1% resistor
is selected for RPROG (see Equation 9).
3125
RPROG =
PLIM ´ RSENSE + 0.9 mV x VVCC(MAX)
therefore,
RPROG =
3125
= 43.89 kΩ
29.3 ´ 0.002 Ω + 0.0009 V x 14 V
(9)
VSNS-PL_MIN is the minimum sense voltage during power limit operation. Due to offsets of internal amplifiers,
programmed power limit (PLIM) accuracy degrades at low VSNS-PL_MIN and could cause start-up issues. To ensure
reliable operation, verify that VSNS,PL,MIN > 3 mV using Equation 10.
P ´ RSENSE 29.3 W ´ 2 mW
=
= 4.19 mV (> 3 mV)
VSNS -PL _ MIN = LIM
VIN _ MAX
14 V
(10)
9.2.2.1.4 STEP 4. Choose Output Voltage Rising Time, tON, CT
The maximum output voltage rise time, tON, set by the timer capacitor CT must suffice to fully charge the load
capacitance COUT without triggering the fault circuitry. Equation 11 defines tON for two possible inrush cases.
Assuming that only the load capacitance draws current during start-up,
COUT ´ PLIM
2 ´ ILIM2
+
COUT ´ VVCC(MAX)2
2 ´ PLIM
-
COUT ´ VVCC(MAX)
ILIM
if
PLIM < ILIM ´ VVCC(MAX)
t ON =
COUT ´ VVCC(MAX)
ILIM
if
PLIM > ILIM ´ VVCC(MAX)
therefore,
t ON =
470 μF ´ 29.3 W
2
2 ´ (12 A )
2
+
470 μF ´ (12 V )
2 ´ 29.3 W
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-
470 μF ´ 12 V
= 0.614 ms
12 A
(11)
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The next step is to determine the minimum fault-timer period. In Equation 11, the output rise time is tON. This is
the amount of time it takes to charge the output capacitor up to the final output voltage. However, the fault timer
uses the difference between the input voltage and the gate voltage to determine if the TPS24710/11/12/13 is still
in inrush limit. The fault timer continues to run until VGS rises 5.9 V (for VVCC = 12 V) above the input voltage.
Some additional time must be added to the charge time to account for this additional gate voltage rise. The
minimum fault time can be calculated using Equation 12,
5.9 V ´ CISS
tFLT = t ON +
,
IGATE
therefore,
tFLT = 0.614 ms +
5.9 V ´ 2040 pF
= 1.22 ms
20 μA
(12)
where CISS is the MOSFET input capacitance and IGATE is the minimum gate sourcing current of
TPS24710/11/12/13, or 20 μA. Using the example parameters in Equation 12 and the CSD16403Q5 data sheet
(SLPS201) leads to a minimum fault time of 1.22 ms. This time is derived considering the tolerances of COUT,
CISS, ILIM, PLIM, IGATE, and VVCC(MAX). The fault timer must be set to a value higher than 1.22 ms to avoid turning
off during start-up, but lower than any maximum fault time limit determined by the SOA curve (see Figure 38)
derated for operating junction temperature.
For this example, select 7 ms to allow for variation of system parameters such as temperature, load, component
tolerance, and input voltage. The timing capacitor is calculated in Equation 5 as 52 nF. Selecting the next-highest
standard value, 56 nF, yields a 7.56-ms fault time (see Equation 13).
10 μA
CT =
´ tFLT ,
1.35 V
therefore,
CT =
10 μA
´ 7 ms = 52 nF
1.35 V
(13)
9.2.2.1.5 STEP 5. Calculate the Retry-Mode Duty Ratio
In retry mode, the TPS24711/13 is on for one charging cycle and off for 16 charge/discharge cycles, as can be
seen in Figure 33. The first CT charging cycle is from 0 V to 1.35 V, which gives 7.56 ms. The first CT discharging
cycle is from 1.35 V to 0.35 V, which gives 5.6 ms. Therefore, the total time is 7.56 ms + 33 × 5.6 ms = 192.36
ms. As a result, the retry mode duty ratio is 7.56 ms/192.36 ms = 3.93%.
9.2.2.1.6 STEP 6. Select R1 and R2 for UV
Next, select the values of the UV resistors, R1 and R2, as shown in the typical application diagram on the front
page. From the TPS24710/11/12/13 electrical specifications, VENTHRESH = 1.35 V. The VUV is the undervoltage
trip voltage, which for this example equals 10.7 V.
R2
VENTHRESH =
´ VVCC
R1 + R2
(14)
Assume R1 is 130 kΩ and use Equation 14 to solve for the R2 value of 18.7 kΩ.
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9.2.2.1.7 STEP 7. Choose RGATE, R4, R5 and C1
In the typical application diagram on the front page, the gate resistor, RGATE, is intended to suppress highfrequency oscillations. A resistor of 10 Ω will serve for most applications, but if M1 has a CISS below 200 pF, then
33 Ω is recommended. Applications with larger MOSFETs and very short wiring may not require RGATE. R4 and
R5 are required only if PGb and FLTb are used; these resistors serve as pullups for the open-drain output
drivers. The current sunk by each of these pins should not exceed 2 mA (see the RECOMMENDED
OPERATING CONDITIONS table). C1 is a bypass capacitor to help control transient voltages, unit emissions,
and local supply noise while in the disabled state. Where acceptable, a value in the range of 0.001 μF to 0.1 μF
is recommended.
9.2.2.2 Additional Design Considerations
9.2.2.2.1 Use of PG/PGb
Use the PG/PGb pin to control and coordinate a downstream dc/dc converter. If this is not done, then a long time
delay is needed to allow COUT to fully charge before the converter starts. An undesirable latch-up condition can
be created between the TPS24710/11/12/13 output characteristic and the dc/dc converter input characteristic if
the converter starts while COUT is still charging; the PG/PGb pin is one way to avoid this
9.2.2.2.2 Output Clamp Diode
Inductive loads on the output may drive the OUT pin below GND when the circuit is unplugged or during a
current-limit event. The OUT pin ratings can be satisfied by connecting a diode from OUT to GND. The diode
should be selected to control the negative voltage at the full short-circuit current. Schottky diodes are generally
recommended for this application.
9.2.2.2.3 Gate Clamp Diode
The TPS24710/11/12/13 has a relatively well-regulated gate voltage of 12 V to 15.5 V with a supply voltage VVCC
higher than 4 V. A small clamp Zener from GATE to source of M1 is recommended if VGS of M1 is rated below 12
V. A series resistance of several hundred ohms or a series silicon diode is recommended to prevent the output
capacitance from discharging through the gate driver to ground.
9.2.2.2.4 High-Gate-Capacitance Applications
Gate voltage overstress and abnormally large fault current spikes can be caused by large gate capacitance. An
external gate clamp Zener diode is recommended to assist the internal Zener if the total gate capacitance of M1
exceeds about 4000 pF.
9.2.2.2.5 Bypass Capacitors
It is a good practice to provide low-impedance ceramic capacitor bypassing of the VCC and OUT pins. Values in
the range of 10 nF to 1 µF are recommended. Some system topologies are insensitive to the values of these
capacitors; however, some are not and require minimization of the value of the bypass capacitor. Input
capacitance on a plug-in board may cause a large inrush current as the capacitor charges through the lowimpedance power bus when inserted. This stresses the connector contacts and causes a short voltage sag on
the input bus. Small amounts of capacitance (e.g., 10 nF to 0.1 µF) are often tolerable in these systems.
9.2.2.2.6 Output Short-Circuit Measurements
Repeatable short-circuit testing results are difficult to obtain. The many details of source bypassing, input leads,
circuit layout and component selection, output shorting method, relative location of the short, and instrumentation
all contribute to variation in results. The actual short itself exhibits a certain degree of randomness as it
microscopically bounces and arcs. Care in configuration and methods must be used to obtain realistic results. Do
not expect to see waveforms exactly like those in this data sheet; every setup differs.
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9.2.2.2.7 Using Soft Start with TPS2471x
In some applications, it may be desired to have a constant dv/dt ramp on the output of the TPS2471x to ensure a
constant inrush current. This is often accomplished by adding a capacitor from GATE to GND as shown in
Figure 37. This limits the gate ramp speed, which in turn limits the ramp of the output.
VOUT
VIN
RGATE =10Q
GATE
CSS
TPS2471x
GND
Figure 37. Simplified Diagram for Using Soft Start
Due to the nature of the timer and the gate driver, there are several considerations that must be taken into
account when using this type of a design. For a further discussion of this topic, refer to the following Application
Note: (SLVA749).
9.2.3 Application Curve
IDS – Drain-to-Source Current – A
1k
100
1ms
10
10ms
100ms
Area Limited
by RDS(on)
1
1s
0.1
Single Pulse
RθJA = 94ºC/W (min Cu)
0.01
0.01
0.1
DC
1
10
100
VDS – Drain-to-Source Voltage – V
G009
Figure 38. CSD16403Q5 SOA Curve
10 Power Supply Recommendations
Use a 10-nF to 1-μF ceramic capacitor to bypass the VCC pin to GND. When the input bus power feed is
inductive, then a transient voltage suppressor (TVS) may also be required.
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11 Layout
11.1 Layout Guidelines
TPS24710/11/12/13 applications require careful attention to layout to ensure proper performance and to minimize
susceptibility to transients and noise. In general, all traces should be as short as possible, but the following list
deserves first consideration:
• Decoupling capacitors on VCC pin should have minimal trace lengths to the pin and to GND.
• Traces to VCC and SENSE must be short and run side-by-side to maximize common-mode rejection. Kelvin
connections should be used at the points of contact with RSENSE. (see Figure 39).
• Power path connections should be as short as possible and sized to carry at least twice the full load current,
more if possible.
• Protection devices such as snubbers, TVS, capacitors, or diodes should be placed physically close to the
device they are intended to protect, and routed with short traces to reduce inductance. For example, the
protection Schottky diode shown in the typical application diagram on the front page of this data sheet should
be physically close to the OUT pin.
11.2 Layout Example
LOAD CURRENT
PATH
LOAD CURRENT
PATH
SENSE
VCC
SENSE
VCC
RSENSE
TPS2471x
TPS2471x
Method 1
Method 2
M0217-02
Figure 39. Recommended RSENSE Layout
Copyright © 2011–2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TPS24710 TPS24711 TPS24712 TPS24713
31
TPS24710, TPS24711
TPS24712, TPS24713
SLVSAL2G – JANUARY 2011 – REVISED NOVEMBER 2015
www.ti.com
12 Device and Documentation Support
12.1 Documentation Support
Using the TPS24700EVM, TPS24701EVM, TPS24710EVM and the TPS24711EVM, SLUU459.
TPS24710 Design Calculator, SLVC566
Using Soft Start with TPS2471x and TPS24720, SLVA749
12.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 2. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
TPS24710
Click here
Click here
Click here
Click here
Click here
TPS24711
Click here
Click here
Click here
Click here
Click here
TPS24712
Click here
Click here
Click here
Click here
Click here
TPS24713
Click here
Click here
Click here
Click here
Click here
12.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
32
Submit Documentation Feedback
Copyright © 2011–2015, Texas Instruments Incorporated
Product Folder Links: TPS24710 TPS24711 TPS24712 TPS24713
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
SN24710DGS
ACTIVE
VSSOP
DGS
10
80
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
24710
SN24710DGSR
ACTIVE
VSSOP
DGS
10
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
24710
TPS24710DGS
ACTIVE
VSSOP
DGS
10
80
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
24710
TPS24710DGSR
ACTIVE
VSSOP
DGS
10
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
24710
TPS24711DGS
ACTIVE
VSSOP
DGS
10
80
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
24711
TPS24711DGSR
ACTIVE
VSSOP
DGS
10
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
24711
TPS24712DGS
ACTIVE
VSSOP
DGS
10
80
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
24712
TPS24712DGSR
ACTIVE
VSSOP
DGS
10
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
24712
TPS24713DGS
ACTIVE
VSSOP
DGS
10
80
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
24713
TPS24713DGSR
ACTIVE
VSSOP
DGS
10
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
24713
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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