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TPS2543-Q1
SLVSBW2A – MARCH 2013 – REVISED OCTOBER 2016
USB Charging Port Controller and Power Switch with Load Detection
1 Features
2 Applications
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Qualified for Automotive Application
AEC-Q100 Qualified With the Following Results:
– Device Temperature Grade 1: –40°C to 125°C
Ambient Operating Temperature Range
– Device HBM ESD Classification Level H2
– Device CDM ESD Classification Level C5
D+/D– CDP/DCP Modes per USB Battery
Charging Specification 1.2
D+/D– Shorted Mode per Chinese
Telecommunication Industry Standard YD/T 15912009
Supports non-BC1.2 Charging Modes by
Automatic Selection
– D+/D– Divider Modes 2V/2.7V and 2.7/2V
Supports Sleep-Mode Charging and Low Speed
Mouse/Keyboard Wake Up
Load Detection for Power Supply Control in S4/S5
Charging and Port Power Management in all
Charge Modes
Compatible with USB 2.0 and 3.0 Power Switch
requirements
Integrated 73-mΩ (typ) High-Side MOSFET
Adjustable Current-Limit up to 3 A (Typical)
Operating Range: 4.5 V to 5.5 V
Max Device Current
– 2 µA When Device Disabled
– 260 µA When Device Enabled
Drop-In and BOM Compatible with TPS2543
Available in 16-Pin QFN (3x3) Package
USB Ports (Host and Hubs)
Notebook and Desktop PCs
Automotive Infotainment System
3 Description
The TPS2543-Q1 is a USB charging port controller
and power switch with an integrated USB 2.0 highspeed data line (D+/D–) switch. TPS2543-Q1
provides the electrical signatures on D+/D– lines to
support charging schemes listed under device feature
section. TI tests charging of popular mobile phones,
tablets and media devices with the TPS2543-Q1 to
ensure compatibility with both BC1.2 compliant and
non-BC1.2 compliant devices.
In addition to charging popular devices, the TPS2543Q1 also supports two distinct power management
features, namely, power wake and port power
management (PPM) via the STATUS pin. Power
wake allows for power supply control in S4/S5
charging and PPM the ability to manage port power in
a multi-port applications. Additionally, system wake
up (from S3) with a mouse/keyboard (low speed only)
is also supported in the TPS2543-Q1.
The TPS2543-Q1 73-mΩ power-distribution switch is
intended for applications where heavy capacitive
loads and short-circuits are likely to be encountered.
Two programmable current thresholds provide
flexibility for setting current limits and load detect
thresholds.
Device Information(1)
PART NUMBER
TPS2543-Q1
PACKAGE
WQFN (16)
BODY SIZE (NOM)
3.00 mm x 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Typical Application Diagram
To Portable Device
Power Bus
4.5 V – 5.5 V
R STATUS
(10 kW)
STATUS Signal
0.1 uF
IN
OUT
TPS2543-Q1
ILIM _LO
ILIM _HI
R FAULT
(10 kW)
STATUS
Fault Signal
FAULT
ILIM Select
ILIM _SEL
EN
Power Switch EN
Mode Select I/O
VBUS
DD+
GND
C USB
CTL 1
CTL 2
CTL 3
R ILIM_HI
R ILIM_LO
GND
USB
Connector
DM_IN
DP_IN
DM _OUT
DP_ OUT
To Host Controller
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS2543-Q1
SLVSBW2A – MARCH 2013 – REVISED OCTOBER 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
7
8
1
1
1
2
3
4
Absolute Maximum Ratings ...................................... 4
ESD Ratings.............................................................. 4
Recommended Operating Conditions....................... 4
Thermal Information .................................................. 5
Electrical Characteristics.......................................... 5
Electrical Characteristics, High-Bandwidth Switch.... 7
Electrical Characteristics, Charging Controller ......... 8
Typical Characteristics .............................................. 9
Parameter Measurement Information ................ 13
Detailed Description ............................................ 14
8.1 Overview ................................................................. 14
8.2 Functional Block Diagram ....................................... 15
8.3 Feature Description................................................. 15
8.4 Device Functional Modes........................................ 26
9
Application and Implementation ........................ 29
9.1 Application Information............................................ 29
9.2 Typical Application ................................................. 30
10 Power Supply Recommendations ..................... 32
11 Layout................................................................... 33
11.1 Layout Guidelines ................................................. 33
11.2 Layout Example .................................................... 33
12 Device and Documentation Support ................. 34
12.1
12.2
12.3
12.4
12.5
12.6
Documentation Support .......................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
34
34
34
34
34
34
13 Mechanical, Packaging, and Orderable
Information ........................................................... 34
4 Revision History
Changes from Original (March 2013) to Revision A
Page
•
Added Device Information table, ESD Ratings table, Feature Description section, Device Functional Modes,
Application and Implementation section, Power Supply Recommendations section, Layout section, Device and
Documentation Support section, and Mechanical, Packaging, and Orderable Information section ..................................... 1
•
Deleted Feature : "UL Listed and CB File No. E169910"....................................................................................................... 1
•
Changed ILIM_LO+60mA for 200 ms To: ILIM_LO + 75 mA for 200 ms and ILIM_LO+10mA for 3s To: ILIM_LO +
25 mA for 3s in section PPM Details .................................................................................................................................... 24
•
Changed text From: "it switches to Divider2 scheme" To: "it discharges and then switches to Divider2 scheme." in
section DCP Auto Mode ....................................................................................................................................................... 26
•
Changed text From: "it will revert to Divider1 scheme" To: "it performs OUT discharge and will revert to Divider1
scheme" in section DCP Auto Mode .................................................................................................................................... 26
•
Changed the description of S0 and S3 From: ILIM_LO + 60 mA thresholds To: ILIM_LO + 75 mA thresholds in Table 2 27
2
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SLVSBW2A – MARCH 2013 – REVISED OCTOBER 2016
5 Pin Configuration and Functions
GND
FAULT
13
3
10
DP_IN
4
9
7
8
CTL3
ILIM_SEL
14
DM_IN
CTL2
DP_OUT
ILIM_LO
11
PowerPAD
6
2
15
OUT
CTL1
DM_OUT
ILIM_HI
12
5
1
EN
IN
16
RTE Package
16 Pin (WQFN)
Top View
STATUS
Not to scale
Pin Functions
NO.
(1)
NAME
TYPE (1)
DESCRIPTION
P
Input voltage and supply voltage; connect 0.1 μF or greater ceramic capacitor from IN to GND as close
to the device as possible
1
IN
2
DM_OUT
I/O
D– data line to USB host controller
3
DP_OUT
I/O
D+ data line to USB host controller
4
ILIM_SEL
I
Logic-level input signal used to control the charging mode, current limit threshold, and load detection;
see the control truth table. Can be tied directly to IN or GND without pull-up or pull-down resistor.
5
EN
I
Logic-level input for turning the power switch and the signal switches on/off; logic low turns off the
signal and power switches and holds OUT in discharge. Can be tied directly to IN or GND without pullup or pull-down resistor.
6
CTL1
I
7
CTL2
I
8
CTL3
I
Logic-level inputs used to control the charging mode and the signal switches; see the control truth
table. Can be tied directly to IN or GND without pull-up or pull-down resistor.
9
STATUS
O
Active-low open-drain output, asserted in load detection conditions
10
DP_IN
I/O
D+ data line to downstream connector
11
DM_IN
I/O
D– data line to downstream connector
12
OUT
P
Power-switch output
13
FAULT
O
Active-low open-drain output, asserted during over-temperature or current limit conditions
14
GND
P
Ground connection
15
ILIM_LO
I
External resistor connection used to set the low current-limit threshold and the load detection current
threshold. A resistor to ILIM_LO is optional; see the Current-Limit Settings section.
16
ILIM_HI
I
External resistor connection used to set the high current-limit threshold
NA
PowerPAD™
Internally connected to GND; used to heat-sink the part to the circuit board traces. Connect to GND
plane.
G = Ground, I = Input, O = Output, P = Power
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
–0.3
7
–7
7
DP_IN, DM_IN, DP_OUT, DM_OUT
–0.3 to (IN + 0.3)
5.7
Input clamp current
DP_IN, DM_IN, DP_OUT, DM_OUT
–20
20
mA
Continuous current in SDP
or CDP mode
DP_IN to DP_OUT or DM_IN to DM_OUT
–100
100
mA
Continuous current in
BC1.2 DCP mode
DP_IN to DM_IN
–50
50
mA
Continuous output current
OUT
Continuous output sink
current
FAULT, STATUS
25
mA
Continuous output source
current
ILIM_LO, ILIM_HI
IN, EN, ILIM_LO, ILIM_HI, FAULT, STATUS, ILIM_SEL,
CTL1, CTL2, CTL3, OUT
Voltage range
IN to OUT
UNIT
V
Internally limited
Internally limited
mA
Operating junction temperature, TJ
–40
Internally
limited
°C
Storage temperature, Tstg
–65
150
°C
(1)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
(3)
Electrostatic discharge
Human-body model (HBM), per AEC Q100-002 (1)
±2000 (2)
Charged-device model (CDM), per AEC Q100-011
±500 (3)
UNIT
V
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
The passing level per AEC-Q100 Classification H2.
The passing level per AEC-Q100 Classification C5.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
VIN
Input voltage, IN
NOM
MAX
UNIT
4.5
5.5
V
Input voltage, logic-level inputs, EN, CTL1, CTL2, CTL3, ILIM_SEL
0
5.5
V
Input voltage, data line inputs, DP_IN, DM_IN, DP_OUT, DM_OUT
0
VIN
V
VIH
High-level input voltage, EN, CTL1, CTL2, CTL3, ILIM_SEL
VIL
Low-level input voltage, EN, CTL1, CTL2, CTL3, ILIM_SEL
0.8
V
Continuous current, data line inputs, SDP or CDP mode, DP_IN to
DP_OUT, DM_IN to DM_OUT
±30
mA
Continuous current, data line inputs, BC1.2 DCP mode, DP_IN to
DM_IN
±15
mA
2.5
A
IOUT
Continuous output current, OUT
1.8
0
Continuous output sink current, FAULT, STATUS
V
0
10
mA
RILIM_XX
Current-limit set resistors
16.9
750
kΩ
TJ
Operating virtual junction temperature
–40
125
°C
4
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6.4 Thermal Information
TPS2543-Q1
THERMAL METRIC (1)
RTE (WQFN)
UNIT
16 PINS
RθJA
Junction-to-ambient thermal resistance
53.4
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
51.4
°C/W
RθJB
Junction-to-board thermal resistance
17.2
°C/W
ψJT
Junction-to-top characterization parameter
3.7
°C/W
ψJB
Junction-to-board characterization parameter
20.7
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
3.9
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5
Electrical Characteristics
Unless otherwise noted: –40 ≤ TJ ≤ 125°C, 4.5V ≤ VIN ≤ 5.5 V, VEN = VIN, VILIM_SEL = VIN, VCTL1 = VCTL2 = VCTL3 = VIN. R FAULT =
R STATUS = 10 kΩ, RILIM_HI = 20 kΩ, RILIM_LO = 80.6 kΩ. Positive currents are into pins. Typical values are at 25°C. All voltages
are with respect to GND.
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT
POWER SWITCH
RDS(on)
On resistance (1)
tr
OUT voltage rise time
tf
OUT voltage fall time
ton
OUT voltage turn-on time
toff
OUT voltage turn-off time
IREV
Reverse leakage current
TJ = 25°C, IOUT = 2 A
73
84
–40°C ≤ TJ ≤ 85°C, IOUT = 2 A
73
105
–40°C ≤ TJ ≤ 125°C, IOUT = 2 A
VIN = 5 V, CL = 1 µF, RL = 100 Ω (see Figure 23 and
Figure 24)
73
120
0.7
1.0
1.60
0.2
0.35
0.5
2.7
4
1.7
3
VIN = 5V, CL = 1 µF, RL = 100 Ω (see Figure 23 and
Figure 25)
VOUT = 5.5 V, VIN = VEN = 0 V, –40 ≤ TJ ≤ 85°C,
Measure IOUT
mΩ
ms
ms
2
µA
DISCHARGE
RDCHG
OUT discharge resistance
VOUT = 4 V, VEN = 0 V
400
500
630
Ω
tDCHG
OUT discharge hold time
Time VOUT < 0.7 V (see Figure 26)
205
310
450
ms
Input pin rising logic threshold
voltage
1
1.35
1.70
V
Input pin falling logic threshold
voltage
0.85
1.15
1.45
EN, ILIMSEL, CTL1, CTL2, CTL3 INPUTS
Hysteresis (2)
Input current
200
Pin voltage = 0 V or 5.5 V
–0.5
VILIM_SEL = 0 V, RILIM_LO = 210 kΩ
205
mV
0.5
µA
ILIMSEL CURRENT LIMIT
IOS
tIOS
(1)
(2)
OUT short circuit current limit (1)
Response time to OUT shortcircuit (2)
240
275
625
680
VILIM_SEL = 0 V, RILIM_LO = 80.6 kΩ
575
VILIM_SEL = 0 V, RILIM_LO = 22.1 kΩ
2120
2275 2430
VILIM_SEL = VIN, RILIM_HI= 20 kΩ
2340
2510 2685
VILIM_SEL = VIN, RILIM_HI = 16.9 kΩ
2770
2970 3170
VIN = 5.0 V, R = 0.1Ω, lead length = 2 inches (see
Figure 27)
1.5
mA
µs
Pulse-testing techniques maintain junction temperature close to ambient temperature; Thermal effects must be taken into account
separately.
These parameters are provided for reference only and do not constitute part of TI's published device specifications for purposes of TI's
product warranty.
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Electrical Characteristics (continued)
Unless otherwise noted: –40 ≤ TJ ≤ 125°C, 4.5V ≤ VIN ≤ 5.5 V, VEN = VIN, VILIM_SEL = VIN, VCTL1 = VCTL2 = VCTL3 = VIN. R FAULT =
R STATUS = 10 kΩ, RILIM_HI = 20 kΩ, RILIM_LO = 80.6 kΩ. Positive currents are into pins. Typical values are at 25°C. All voltages
are with respect to GND.
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT
SUPPLY CURRENT
IIN_OFF
Disabled IN supply current
IIN_ON
Enabled IN supply current
VEN = 0 V, VOUT = 0 V, –40 ≤ TJ ≤ 85°C
0.1
2
VCTL1 = VCTL2 = VIN, VCTL3 = 0 V or VIN, VILIM_SEL = 0 V
155
210
VCTL1 = VCTL2 = VIN, VCTL3 = 0V, VILIM_SEL = VIN
175
230
VCTL1 = VCTL2 = VIN, VCTL3 = VIN, VILIM_SEL = VIN
185
240
VCTL1 = 0V, VCTL2 = VCTL3 = VIN
205
260
4.1
4.3
µA
µA
UNDERVOLTAGE LOCKOUT
VUVLO
IN rising UVLO threshold voltage
Hysteresis
3.9
(2)
100
V
mV
FAULT
Output low voltage
I FAULT = 1 mA
Off-state leakage
V FAULT = 5.5 V
Over current FAULT rising and
falling deglitch
5
8.2
100
mV
1
µA
12
ms
100
mV
1
µA
STATUS
Output low voltage
I STATUS = 1 mA
Off-state leakage
V STATUS = 5.5 V
THERMAL SHUTDOWN
Thermal shutdown threshold
155
Thermal shutdown threshold in
current-limit
135
Hysteresis (2)
6
°C
20
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6.6 Electrical Characteristics, High-Bandwidth Switch
Unless otherwise noted: –40 ≤ TJ ≤ 125°C, 4.5 V ≤ VIN ≤ 5.5 V, VEN = VIN, VILIM_SEL = VIN, VCTL1 = VCTL2 = VCTL3 = VIN. R FAULT =
R STATUS = 10 kΩ, RILIM_HI = 20 kΩ, RILIM_LO = 80.6 kΩ, Positive currents are into pins. Typical values are at 25°C. All voltages
are with respect to GND.
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT
HIGH-BANDWIDTH ANALOG SWITCH
DP/DM switch on resistance
Switch resistance mismatch between
DP / DM channels
DP/DM switch off-state capacitance (1),
DP/DM switch on-state capacitance
(2)
(3) (2)
2
4
VDP/DM_OUT = 2.4 V, IDP/DM_IN = –15 mA
3
6
VDP/DM_OUT = 0 V, IDP/DM_IN = 30 mA
0.05
0.15
VDP/DM_OUT = 2.4 V, IDP/DM_IN = –15 mA
0.05
0.15
VEN = 0 V, VDP/DM_IN = 0.3 V, Vac = 0.6 Vpk-pk,
f = 1 MHz
3
Ω
Ω
pF
VDP/DM_IN = 0.3 V, Vac = 0.6 Vpk-pk, f = 1 MHz
5.4
pF
OIRR
Off-state isolation (2)
VEN = 0 V, f = 250 MHz
33
dB
XTALK
On-state cross channel isolation (2)
f = 250 MHz
52
dB
Off state leakage current
VEN = 0 V, VDP/DM_IN = 3.6 V, VDP/DM_OUT = 0 V,
measure IDP/DM_OUT
0.1
BW
Bandwidth (–3dB) (2)
RL = 50 Ω
tpd
Propagation delay (2)
tSK
Skew between opposite transitions of the
same port (tPHL – tPLH) (2)
(1)
(2)
(3)
,
VDP/DM_OUT = 0 V, IDP/DM_IN = 30 mA
1.5
µA
2.6
GHz
0.25
ns
0.1
ns
The resistance in series with the parasitic capacitance to GND is typically 250 Ω.
These parameters are provided for reference only and do not constitute part of TI's published device specifications for purposes of TI's
product warranty.
The resistance in series with the parasitic capacitance to GND is typically 150 Ω
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6.7 Electrical Characteristics, Charging Controller
Unless otherwise noted: –40 ≤ TJ ≤ 125°C, 4.5 V ≤ VIN ≤ 5.5 V, VEN = VIN, VILIM_SEL = VIN, VCTL1 = 0 V, VCTL2 = VCTL3 = VIN. R
FAULT = R STATUS = 10 kΩ, RILIM_HI = 20 kΩ, RILIM_LO = 80.6 kΩ, Positive currents are into pins. Typical values are at 25°C. All
voltages are with respect to GND.
PARAMETER
TEST CONDITIONS
SHORTED MODE (BC1.2 DCP)
MIN
TYP
MAX
UNIT
125
200
Ω
VCTL1 = VIN, VCTL2 = VCTL3 = 0V
DP_IN / DM_IN shorting resistance
DIVIDER1 MODE
DP_IN Divider1 output voltage
1.9
2.0
2.1
V
DM_IN Divider1 output voltage
2.57
2.7
2.84
V
DP_IN output impedance
8
10.5
12.5
kΩ
DM_IN output impedance
8
10.5
12.5
kΩ
DP_IN Divider2 output voltage
2.57
2.7
2.84
V
DM_IN Divider2 output voltage
DIVIDER2 MODE
IOUT = 1A
1.9
2.0
2.1
V
DP_IN output impedance
8
10.5
12.5
kΩ
DM_IN output impedance
8
10.5
12.5
kΩ
0.5
0.6
0.7
V
0.4
V
CHARGING DOWNSTREAM PORT
VCTL1 = VCTL2 = VCTL3 = VIN
VDP_IN = 0.6 V,
–250 µA < IDM_IN < 0 µA
VDM_SRC
DM_IN CDP output voltage
VDAT_REF
DP_IN rising lower window threshold for
VDM_SRC activation
Hysteresis
VLGC_SRC
0.25
(1)
50
DP_IN rising upper window threshold for
VDM_SRC de-activation
0.8
hysteresis (1)
IDP_SINK
VDP_IN = 0.6 V
70
100
µA
635
700
765
mA
50
Load detect set time
200
275
ms
1.9
3
4.2
s
Power wake short circuit current limit
32
55
78
mA
IOUT falling power wake reset current
detection threshold
23
45
67
mA
10.7
15
Load detect reset time
Reset current hysteresis
VCTL1 = VCTL2 = 0V, VCTL3 = VIN
(1)
5
Power wake reset time
8
mA
140
LOAD DETECT – POWER WAKE
(1)
mV
40
hysteresis (1)
IOS_PW
V
VCTL1 = VCTL2 = VCTL3 = VIN
IOUT rising load detect current threshold
tLD_SET
1
100
DP_IN sink current
LOAD DETECT – NON POWER WAKE
ILD
mV
mA
20.6
s
These parameters are provided for reference only and do not constitute part of TI's published device specifications for purposes of TI's
product warranty.
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6.8 Typical Characteristics
0.3
100
0.25
Reverse Leakage Current (µA)
On Resistance (mΩ)
90
80
70
60
0.2
0.15
0.1
0.05
50
−40 −25 −10
5
20 35 50 65 80
Junction Temperature (°C)
95
0
−40 −25 −10
110 125
5
20 35 50 65 80
Junction Temperature (°C)
95
110 125
G001
Figure 1. Power Switch On Resistance vs Temperature
G002
Figure 2. Reverse Leakage Current vs Temperature
580
3000
OUT Short Circuit Current Limit (mA)
OUT Discharge Resistance (Ω)
560
3500
VIN = 4.5 V
VIN = 5 V
VIN = 5.5 V
540
520
500
480
2500
2000
1500
RILIM_LO = 210 kΩ
RILIM_LO = 80.6 kΩ
RILIM_HI = 20 kΩ
RILIM_HI = 16.9 kΩ
1000
500
460
−40 −25 −10
5
20 35 50 65 80
Junction Temperature (°C)
95
0
−40 −25 −10
110 125
5
20 35 50 65 80
Junction Temperature (°C)
95
110 125
G003
Figure 3. Out Discharge Resistance vs Temperature
G004
Figure 4. Out Short Circuit Current Limit vs Temperature
1.2
190
VIN = 5.5 V
180
Enabled IN Supply Current (µA)
Disabled IN Supply Current (µA)
1
0.8
0.6
0.4
0.2
0
−40
VIN = 4.5 V
VIN = 5 V
VIN = 5.5 V
170
160
150
Device configured for SDP
VILIMSEL = 0 V
140
−20
0
20
40
60
Junction Temperature (°C)
80
100
130
−40 −25 −10
G005
Figure 5. Disabled In Supply Current vs Temperature
5
20 35 50 65 80
Junction Temperature (°C)
95
110 125
G006
Figure 6. Enabled In Supply Current - SDP vs Temperature
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Typical Characteristics (continued)
220
240
VIN = 4.5 V
VIN = 5 V
VIN = 5.5 V
230
Enabled IN Supply Current (µA)
Enabled IN Supply Current (µA)
210
200
190
180
170
VIN = 4.5 V
VIN = 5 V
VIN = 5.5 V
220
210
200
190
Device configured for CDP
160
−40 −25 −10
5
20 35 50 65 80
Junction Temperature (°C)
95
Device configured for DCP AUTO
180
−40 −25 −10
110 125
5
20 35 50 65 80
Junction Temperature (°C)
G007
95
110 125
G008
Figure 7. Enabled In Supply Current - CDP vs Temperature
Figure 8. Enabled In Supply Current - DCP Auto vs
Temperature
0
700
TJ = −40°C
TJ = 25°C
TJ = 125°C
600
Transmission Gain - dB
Output Low Voltage (mV)
-5
500
400
300
200
-10
-15
-20
100
VIN = 4.5 V
0
0
1
2
3
4
5
6
7
Sinking Current (mA)
8
9
10
-20
0.01
G009
Figure 9. STATUS and FAULT Output Low Voltage vs
Sinking Current
10
Figure 10. Data Transmission Characteristics vs Frequency
XTALK - ON State Cross-Channel Isolation - dB
80
50
OIRR - Off State Isolation - dB
1
Frequency - GHz
60
40
30
20
10
70
60
50
40
30
20
10
0
0
0.01
0.1
1
10
0.01
0.1
1
10
Frequency - GHz
Frequency - GHz
Figure 11. Off State Data Switch Isolation vs Frequency
10
0.1
Figure 12. On State Cross-Channel Isolation vs Frequency
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0.5
0.5
0.4
0.4
0.3
0.3
0.2
0.2
Differential Signal (V)
Differential Signal (V)
Typical Characteristics (continued)
0.1
0
–0.1
–0.2
0.1
0
–0.1
–0.2
–0.3
–0.3
–0.4
–0.4
–0.5
–0.5
0
0.2
0.4
0.6
0.8
1 1.2
Time (ns)
1.4
1.6
1.8
0
2
0.2
0.4
G013
Figure 13. Eye Diagram Using USB Compliance Test Pattern
(with no switch)
0.6
0.8
1 1.2
Time (ns)
1.4
1.6
1.8
2
G014
Figure 14. Eye Diagram Using USB Compliance Test Pattern
(with data switch)
230
740
RILIM_LO = 80.6 kΩ
720
225
Load Detect Set Time (ms)
Current (mA)
700
680
660
640
220
215
210
205
620
IOS - OUT Short Circuit Current Limit
ILD - IOUT Rising Load Detect Threshold
600
−40 −25 −10
5
20 35 50 65 80
Junction Temperature (°C)
95
110 125
200
−40 −25 −10
5
20 35 50 65 80
Junction Temperature (°C)
95
110 125
G015
Figure 15. IOUT Rising Load Detect Threshold
and Out Short Circuit Current Limit vs Temperature
G016
Figure 16. Load Detect Set Time vs Temperature
59
Power Wake Current Limit (mA)
58
57
VOUT
2 V/div
56
VEN
5 V/div
55
54
IIN
500 mA/div
53
52
−40 −25 −10
RLOAD = 5 Ω
CLOAD = 150 µF
t - Time - 1 ms/div
5
20 35 50 65 80
Junction Temperature (°C)
95
110 125
G021
Figure 18. Turn-On Response
G017
Figure 17. Power Wake Current Limit vs Temperature
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Typical Characteristics (continued)
V/FAULT
5 V/div
VOUT
2 V/div
VEN
5 V/div
VEN
5 V/div
RLOAD = 5 Ω
CLOAD = 150 µF
IIN
500 mA/div
IIN
500 mA/div
t - Time - 1 ms/div
t - Time - 2 ms/div
G022
G023
Figure 20. Device Enabled Into Short Circuit
Figure 19. Turn-Off Response
RILM_HI = 20 kΩ
V/FAULT
5 V/div
RILM_LO = 80.6 kΩ
V/FAULT
5 V/div
VEN
5 V/div
VOUT
2 V/div
IIN
1 A/div
IIN
2 A/div
t - Time - 5 ms/div
t - Time - 2 ms/div
G024
Figure 21. Device Enabled Into Short Circuit - Thermal
Cycling
12
RILIM_HI = 20 kΩ
RLOAD = 5 Ω
CLOAD = 150 µF
G025
Figure 22. Short Circuit to Full Load Recovery
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7 Parameter Measurement Information
OUT
RL
CL
VOUT
tr
tf
90%
10%
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Figure 23. OUT Rise/Fall Test Load
VEN
50 %
Figure 24. Power-On and Off Timing
50 %
5V
ton
toff
tDCHG
VOUT
90 %
VOUT
10 %
0V
Figure 25. Enable Timing, Active High Enable
Figure 26. OUT Discharge During Mode Change
IOS
IOUT
tIOS
Figure 27. Output Short Circuit Parameters
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8 Detailed Description
8.1 Overview
The following overview references various industry standards. It is always recommended to consult the most upto-date standard to ensure the most recent and accurate information. Rechargeable portable equipment requires
an external power source to charge its batteries. USB ports are a convenient location for charging because of an
available 5-V power source. Universally accepted standards are required to make sure host and client-side
devices operate together in a system to ensure power management requirements are met. Traditionally, host
ports following the USB 2.0 specification must provide at least 500 mA to downstream client-side devices.
Because multiple USB devices can be attached to a single USB port through a bus-powered hub, it is the
responsibility of the client-side device to negotiate its power allotment from the host to ensure the total current
draw does not exceed 500 mA. In general, each USB device is granted 100 mA and may request more current in
100 mA unit steps up to 500 mA. The host may grant or deny based on the available current. A USB 3.0 host
port not only provides higher data rate than USB 2.0 port but also raises the unit load from 100 mA to 150 mA. It
is also required to provide a minimum current of 900 mA to downstream client-side devices.
Additionally, the success of USB has made the mini-USB connector a popular choice for wall adapter cables.
This allows a portable device to charge from both a wall adapter and USB port with only one connector. As USB
charging has gained popularity, the 500 mA minimum defined by USB 2.0 or 900 mA for USB 3.0 has become
insufficient for many handset and personal media players which need a higher charging rate. Wall adapters can
provide much more current than 500 mA/900 mA. Several new standards have been introduced defining protocol
handshaking methods that allow host and client devices to acknowledge and draw additional current beyond the
500 mA/900 mA minimum defined by USB 2.0/3.0 while still using a single micro-USB input connector.
The TPS2543-Q1 supports three of the most common USB charging schemes found in popular hand-held media
and cellular devices:
• USB Battery Charging Specification BC1.2
• Chinese Telecommunications Industry Standard YD/T 1591-2009
• Divider Mode
YD/T 1591-2009 is a subset of BC1.2 spec. supported by vast majority of devices that implement USB changing.
Divider charging scheme is supported in devices from specific yet popular device maker.
BC1.2 lists three different port types as listed below.
• Standard Downstream Port (SDP)
• Charging Downstream Port (CDP)
• Dedicated Charging Port (DCP)
BC1.2 defines a charging port as a downstream facing USB port that provides power for charging portable
equipment, under this definition CDP and DCP are defined as charging ports
14
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8.2 Functional Block Diagram
Current
Sense
IN
CS
OUT
Disable +UVLO +Discharge
ILIM _HI
Current
Limit
Select
Current
Limit
Charge
Pump
ILIM _LO
GND
OC
8-ms Deglitch
OTSD
UVLO
ILIM _SEL
Thermal
Sense
Driver
LD cur set
EN
FAULT
8- ms Deglitch
(falling edge)
discharge
DM _OUT
DM _IN
DP _OUT
DP _IN
ILIM _SEL
OC
CTL 1
CTL 2
Logic
control
CDP
Detection
DCP
Detection
Divider
Mode
Auto - Detection
LD cur set
Discharge
STATUS
CTL 3
Discharge
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8.3 Feature Description
8.3.1 Standard Downstream Port (SDP) USB 2.0/USB 3.0
An SDP is a traditional USB port that follows USB 2.0/3.0 protocol and supplies a minimum of 500mA/900mA per
port. USB 2.0/3.0 communications is supported, and the host controller must be active to allow charging.
TPS2543-Q1 supports SDP mode in system power state S0 when system is completely powered ON and fully
operational. For more details on control pin (CTL1-CTL3) settings to program this state please refer to device
truth table.
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Feature Description (continued)
8.3.2 Charging Downstream Port (CDP)
A CDP is a USB port that follows USB BC1.2 and supplies a minimum of 1.5 A per port. It provides power and
meets USB 2.0 requirements for device enumeration. USB 2.0 communications is supported, and the host
controller must be active to allow charging. What separates a CDP from an SDP is the host-charge handshaking
logic that identifies this port as a CDP. A CDP is identifiable by a compliant BC1.2 client device and allows for
additional current draw by the client device.
The CDP hand-shaking process is done in two steps. During step one the portable equipment outputs a nominal
0.6 V output on its D+ line and reads the voltage input on its D- line. The portable device concludes it is
connected to an SDP if the voltage is less than the nominal data detect voltage of 0.3 V. The portable device
concludes that it is connected to a Charging Port if the D- voltage is greater than the nominal data detect voltage
of 0.3V and optionally less than 0.8 V.
The second step is necessary for portable equipment to determine if it is connected to CDP or DCP. The
portable device outputs a nominal 0.6 V output on its D- line and reads the voltage input on its D+ line. The
portable device concludes it is connected to a CDP if the data line being read remains less than the nominal data
detect voltage of 0.3V. The portable device concludes it is connected to a DCP if the data line being read is
greater than the nominal data detect voltage of 0.3 V.
TPS2543-Q1 supports CDP mode in system power state S0 when system is completely powered ON and fully
operational. For more details on control pin (CTL1-CTL3) settings to program this state please refer to device
truth table.
8.3.3 Dedicated Charging Port (DCP)
A DCP only provides power but does not support data connection to an upstream port. As shown in following
sections, a DCP is identified by the electrical characteristics of its data lines. The TPS2543-Q1 emulates DCP in
two charging states, namely DCP Forced and DCP Auto as shown in Figure 28. In DCP Forced state the device
will support one of the two DCP charging schemes, namely Divider1 or Shorted. In the DCP Auto state, the
device charge detection state machine is activated to selectively implement charging schemes involved with the
Shorted, Divider1 and Divider2 modes. Shorted DCP mode complies with BC1.2 and Chinese
Telecommunications Industry Standard YD/T 1591-2009, while the Divider mode is employed to charge devices
that do not comply with BC1.2 DCP standard.
8.3.3.1 DCP BC1.2 and YD/T 1591-2009
Both standards define that the D+ and D- data lines should be shorted together with a maximum series
impedance of 200 Ω. This is shown in Figure 28.
TPS2543-Q1
D- Out
VBUS
2.0V
USB
CDP
Detect
Auto
Detect
Connector
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