Product
Folder
Sample &
Buy
Support &
Community
Tools &
Software
Technical
Documents
TPS2549
SLUSCP2 – SEPTEMBER 2016
TPS2549 USB Charging Port Controller and Power Switch With Cable Compensation
1 Features
•
•
•
•
•
1
•
•
•
•
•
•
•
heavy charging currents. This is important in systems
with long USB cables where significant voltage drops
can occur while fast-charging portable devices.
4.5-V to 6.5-V Operating Range
47-mΩ (typical) High-Side MOSFET
3-A Maximum Continuous Output Current
±5% CS Output for Cable Compensation
CDP Mode per USB Battery Charging
Specification 1.2
Automatic DCP Modes Selection:
– Shorted Mode per BC1.2 and YD/T 1591-2009
– 2.7-V Divider 3 Mode
– 1.2-V Mode
D+ and D– Client Mode for System Update
D+ and D– Short-to-VBUS Protection
D+ and D– ±8-kV Contact and ±15-kV Air
Discharge ESD Rating (IEC 61000-4-2)
UL Recognition and CB Certification Pending
–40°C to 125°C Junction Operating Temperature
16-Pin QFN (3-mm × 3-mm) Package
The TP2549 47-mΩ power switch has two selectable,
programmable current limits that support port power
management by providing a lower current limit that
can be used when adjacent ports are experiencing
heavy loads. This is important in systems with
multiple ports and an upstream supply unable to
provide full current to all ports simultaneously.
The DCP_Auto scheme detects and selects the
proper D+ and D– settings to communicate with the
attached device, so that it can fast-charge at full
current. The integrated CDP detection enables up to
1.5-A fast charging of most portable devices with
simultaneous data communication.
The unique client-mode feature allows software
updates to client devices, but avoids power conflicts
by turning off the internal power switch while keeping
the data line connection.
Additionally, the TPS2549 device integrates short-toVBUS protection for D+ and D– to prevent damage
when D+ and/or D– unexpectedly short to VBUS. To
save space in the application, the TPS2549 device
also integrates ESD protection to pass IEC61000-4-2
without external circuitry on D+ and D–.
2 Applications
•
•
•
USB Ports (Host and Hubs)
Wall Charging Adapters
Aftermarket Automotive Chargers
Device Information(1)
3 Description
PART NUMBER
The TPS2549 device is a USB charging port
controller and power switch with a current-sense
output that is able to control an upstream supply. This
allows it to maintain 5 V at the USB port even with
heavy
TPS2549
PACKAGE
BODY SIZE (NOM)
WQFN (16)
3.00 mm × 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematic
Voltage
Regulator
C(COMP)
LMR14030
LM53603
LM25117
TPS54340
R(CABLE1)
0.1 µF
IN
5V
R(FA)
R(STATUS)
DM_IN
FAULT
STATUS
FB
R(G)
C(OUT)
TPS2549
R(FAULT)
STATUS
Power S witch EN
Mode Select I/O
R(CABLE2)
DP_IN
GND
CS
EN
CTL1
GND
OUT
FAULT
R(FB)
USB Port
4.5 V to 6.5 V
V(BAT)
CTL2
CTL3
ILIM_LO
ILIM_HI
DM_OUT
DP_OUT
R_HI
To Host
Controller
R_LO
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS2549
SLUSCP2 – SEPTEMBER 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
4
4
4
5
5
8
8
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Switching Characteristics ..........................................
Typical Characteristics ..............................................
8.3 Feature Description................................................. 17
8.4 Device Functional Modes........................................ 24
9
Application and Implementation ........................ 28
9.1 Application Information............................................ 28
9.2 Typical Application ................................................. 28
10 Power Supply Recommendations ..................... 33
11 Layout................................................................... 33
11.1 Layout Guidelines ................................................. 33
11.2 Layout Example .................................................... 34
12 Device and Documentation Support ................. 35
12.1
12.2
12.3
12.4
12.5
12.6
Parameter Measurement Information ................ 14
Detailed Description ............................................ 15
8.1 Overview ................................................................. 15
8.2 Functional Block Diagram ....................................... 16
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
35
35
35
35
35
35
13 Mechanical, Packaging, and Orderable
Information ........................................................... 36
4 Revision History
2
DATE
REVISION
NOTES
September 2016
*
Initial release.
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: TPS2549
TPS2549
www.ti.com
SLUSCP2 – SEPTEMBER 2016
5 Pin Configuration and Functions
ILIM_HI
ILIM_LO
GND
FAULT
16
15
14
13
RTE Package
16-Pin WQFN
Top View
IN
1
12
OUT
DM_OUT
2
11
DM_IN
10
DP_IN
9
STATUS
Thermal
7
8
CTL3
EN
CTL2
4
6
CS
Pad
CTL1
3
5
DP_OUT
Pin Functions
PIN
NAME
NO.
TYPE (1)
DESCRIPTION
Provide sink current proportional to output current. For cable compensation, connect to the
feedback divider of the up-stream voltage regulator.
CS
4
O
CTL1
6
I
CTL2
7
I
CTL3
8
I
DM_IN
11
I/O
D– data line to downstream connector
DM_OUT
2
I/O
D– data line to upstream USB host controller
DP_IN
10
I/O
D+ data line to downstream connector
DP_OUT
3
I/O
D+ data line to upstream USB host controller
EN
5
I
Logic-level control input for turning the power switch and the signal switches on/off. When
EN is low, the device is disabled, the signal and power switches are OFF.
FAULT
13
O
Active-low open-drain output, asserted during overtemperature, overcurrent, and DP_IN and
DM_IN overvoltage conditions. See Table 1.
GND
14
—
Ground connection; should be connected externally to the thermal pad.
ILIM_HI
16
I
Connect external resistor to ground to set the high current-limit threshold.
ILIM_LO
15
I
Connect external resistor to ground to set the low current-limit threshold and the loaddetection current threshold.
IN
1
PWR
Input supply voltage; connect a 0.1 µF or greater ceramic capacitor from IN to GND as close
to the IC as possible.
OUT
12
PWR
Power-switch output
STATUS
9
O
Active-low open-drain output, asserted when the load exceeds the load-detection threshold
Thermal pad
—
—
Thermal pad on bottom of package. The thermal pad is internally connected to GND and is
used to heat-sink the device to the circuit board. Connect the thermal pad to the GND plane.
(1)
Logic-level control inputs for controlling the charging mode and the signal switches; (see
Table 2). These pins tie directly to IN or GND without a pullup or pulldown resistor.
I = Input, O = Output, I/O = Input and output, PWR = Power
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: TPS2549
3
TPS2549
SLUSCP2 – SEPTEMBER 2016
www.ti.com
6 Specifications
6.1 Absolute Maximum Ratings
Voltages are with respect to GND unless otherwise noted (1)
Voltage range
MIN
MAX
UNIT
CS, CTL1, CTL2, CTL3, EN, FAULT, ILIM_HI,
ILIM_LO, IN, OUT, STATUS
–0.3
7
V
DM_IN, DM_OUT, DP_IN, DP_OUT
–0.3
5.7
V
7
V
–100
100
mA
–35
35
mA
IN to OUT
–7
Continuous current in SDP,
CDP or client mode
DP_IN to DP_OUT or DM_IN to DM_OUT
Continuous current in BC1.2
DCP mode
DP_IN to DM_IN
Continuous output current
OUT
Internally limited
A
I(SRC)
Continuous output source
current
ILIM_HI, ILIM_LO
Internally limited
A
I(SNK)
Continuous output sink current
TJ
Operating junction temperature
–40
Internally limited
°C
Tstg
Storage temperature
–65
150
°C
(1)
FAULT, STATUS
25
CS
mA
Internally limited
A
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
Electrostatic
discharge
V(ESD)
Charged-device model (CDM),per JEDEC specification JESD22-C101 (2)
IEC
(1)
(2)
(3)
(3)
UNIT
±2,000
±750
V
IEC61000-4-2 contact discharge, DP_IN and DM_IN
±8,000
IEC61000-4-2 air discharge, DP_IN and DM_IN
±15,000
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
Surges per IEC61000-4-2, 1999 applied between DP_IN/DM_IN and output ground of the TPS2549Q1EVM-729 (SLVUAK6) evaluation
module.
6.3 Recommended Operating Conditions
Voltages are with respect to GND unless otherwise noted.
MIN
V(IN)
Supply voltage
Input voltage
I(OUT)
IN
NOM
MAX
UNIT
4.5
6.5
V
CTL1, CTL2, CTL3, EN
0
6.5
V
DM_IN, DM_OUT, DP_IN, DP_OUT
0
3.6
V
3
A
Output continuous current
OUT (–40°C ≤ TA ≤ 85°C)
Continuous current in SDP, CDP or
client mode
DP_IN to DP_OUT or DM_IN to DM_OUT
–30
30
mA
Continuous current in BC1.2 DCP
mode
DP_IN to DM_IN
–15
15
mA
Continuous output sink current
FAULT, STATUS
10
mA
R(ILIM_xx)
Current limit-set resistors
15.4
1000
kΩ
TJ
Operating junction temperature
–40
125
°C
4
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: TPS2549
TPS2549
www.ti.com
SLUSCP2 – SEPTEMBER 2016
6.4 Thermal Information
TPS2549
THERMAL METRIC (1)
RTE (WQFN)
UNIT
16 PINS
RθJA
Junction-to-ambient thermal resistance
44.9
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
53.3
°C/W
RθJB
Junction-to-board thermal resistance
17.6
°C/W
ψJT
Junction-to-top characterization parameter
1
°C/W
ψJB
Junction-to-board characterization parameter
17.6
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
4.1
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.5 Electrical Characteristics
Unless otherwise noted, –40°C ≤ TJ ≤ 125°C and 4.5 V ≤ V(IN) ≤ 6.5 V, V(EN) = V(IN), V(CTL1) = V(CTL2) = V(CTL3) = V(IN). R(FAULT) =
R(STATUS) = 10 kΩ, R(ILIM_HI) = 19.1 kΩ, R(ILIM_LO) = 80.6 kΩ. Positive currents are into pins. Typical values are at 25°C. All
voltages are with respect to GND.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
TJ = 25°C
47
57
–40°C ≤ TJ ≤ 85°C
47
72
–40°C ≤TJ ≤ 125°C
47
80
UNIT
OUT – POWER SWITCH
rDS(on)
On-resistance (1)
Ilkg(OUT)
Reverse leakage current on VOUT = 6.5 V, VIN = VEN = 0 V, –40°C ≤ TJ ≤ 85°C,
OUT pin
measure I(OUT)
mΩ
2
µA
OUT - DISCHARGE
R(DCHG)
OUT discharge resistance
400
500
630
Ω
Input pin rising logic
threshold voltage
1
1.35
2
V
Input pin falling logic
threshold voltage
0.85
1.15
1.65
V
EN, CTL1, CTL2, CTL3 INPUTS
Hysteresis (2)
Input current
200
Pin voltage = 0 V or 6.5 V
–1
mV
1
µA
CURRENT LIMIT
R(ILIM_LO) = 210 kΩ
OUT short-circuit current
limit
IOS
205
255
305
R(ILIM_LO) = 80.6 kΩ
600
660
720
R(ILIM_LO) = 23.2 kΩ
2145
2300
2455
R(ILIM_HI) = 20 kΩ
2500
2670
2840
R(ILIM_HI) = 19.1 kΩ
2620
2800
2975
R(ILIM_HI) = 15.4 kΩ
3255
3470
3685
R(ILIM_HI) shorted to GND
5500
7000
8000
mA
SUPPLY CURRENT
I(IN_OFF)
I(IN_ON)
(1)
(2)
Disabled IN supply current
Enabled IN supply current
V(EN) = 0 V, V(OUT) = 0 V, –40°C ≤ TJ ≤ 85°C
0.1
5
V(CTL)1 = V(CTL2) = V(CTL3) = V(IN)
220
300
V(CTL1) = V(CTL2) = 0 V, V(CTL3) = V(IN)
226
300
V(CTL2) = V(IN), V(CTL1) = V(CTL3) = 0 V
150
220
V(CTL1) = V(IN), V(CTL2) = V(CTL3) = 0 V
115
190
µA
µA
Pulse-testing techniques maintain junction temperature close to ambient temperature. Thermal effects must be taken into account
separately.
These parameters are provided for reference only and do not constitute part of TI's published device specifications for purposes of TI's
product warranty.
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: TPS2549
5
TPS2549
SLUSCP2 – SEPTEMBER 2016
www.ti.com
Electrical Characteristics (continued)
Unless otherwise noted, –40°C ≤ TJ ≤ 125°C and 4.5 V ≤ V(IN) ≤ 6.5 V, V(EN) = V(IN), V(CTL1) = V(CTL2) = V(CTL3) = V(IN). R(FAULT) =
R(STATUS) = 10 kΩ, R(ILIM_HI) = 19.1 kΩ, R(ILIM_LO) = 80.6 kΩ. Positive currents are into pins. Typical values are at 25°C. All
voltages are with respect to GND.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
3.9
4.1
4.3
UNIT
UNDERVOLTAGE LOCKOUT, IN
IN rising UVLO threshold
voltage
V(UVLO)
Hysteresis
(3)
TJ = 25°C
100
V
mV
FAULT
Output low voltage
I(FAULT) = 1 mA
100
mV
Off-state leakage
V(FAULT) = 6.5 V
2
µA
Output low voltage
I(STATUS) = 1 mA
100
mV
Off-state leakage
V(STATUS) = 6.5 V
2
µA
STATUS
THERMAL SHUTDOWN
T(OTSD2)
Thermal shutdown
threshold
155
°C
T(OTSD1)
Thermal shutdown
threshold in current-limit
135
°C
Hysteresis (3)
20
°C
LOAD DETECT (VCTL1 = VCTL2 = VCTL3 = VIN)
IOUT load detection
threshold
I(LD)
R(ILIM_LO) = 80.6 kΩ, rising load current
630
Hysteresis (3)
700
770
50
mA
mA
DP_IN AND DM_IN SHORT-TO-VBUS PROTECTION
Overvoltage protection trip
threshold
V(OV)
DP_IN and DM_IN rising
3.7
Hysteresis (3)
R(DCHG_Data)
Discharge resistance after
OVP
3.9
4.15
100
V
mV
V(DP_IN) = V(DM_IN) = 5 V
160
210
240
Load = 3 A, 2.5 V ≤ V(CS) ≤ 6.5 V
214
225
236
Load = 2.4 A, 2.5 V ≤ V(CS) ≤ 6.5 V
171
180
189
Load = 2.1 A, 2.5 V ≤ V(CS) ≤ 6.5 V
149
158
166
70
75
80
kΩ
CABLE COMPENSATION
I(CS)
Sink current
Load = 1 A, 2.5 V ≤ V(CS) ≤ 6.5 V
(3)
6
µA
These parameters are provided for reference only and do not constitute part of TI's published device specifications for purposes of TI's
product warranty.
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: TPS2549
TPS2549
www.ti.com
SLUSCP2 – SEPTEMBER 2016
Electrical Characteristics (continued)
Unless otherwise noted, –40°C ≤ TJ ≤ 125°C and 4.5 V ≤ V(IN) ≤ 6.5 V, V(EN) = V(IN), V(CTL1) = V(CTL2) = V(CTL3) = V(IN). R(FAULT) =
R(STATUS) = 10 kΩ, R(ILIM_HI) = 19.1 kΩ, R(ILIM_LO) = 80.6 kΩ. Positive currents are into pins. Typical values are at 25°C. All
voltages are with respect to GND.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
2
4
2.9
6
0.05
0.15
0.05
0.15
UNIT
HIGH-BANDWIDTH ANALOG SWITCH
R(HS_ON)
|ΔR(HS_ON)|
DP and DM switch onresistance
V(DP_OUT) = V(DM_OUT) = 0 V, I(DP_IN) = I(DM_IN) =
30 mA
Ω
V(DP_OUT) = V(DM_OUT) = 2.4 V, I(DP_IN) = I(DM_IN) =
–15 mA
V(DP_OUT) = V(DM_OUT) = 0 V, I(DP_IN) = I(DM_IN) =
Switch resistance mismatch 30 mA
between DP and DM
V(DP_OUT) = V(DM_OUT) = 2.4 V, I(DP_IN) = I(DM_IN) =
channels
–15 mA
Ω
C(IO_OFF)
DP/DM switch off-state
capacitance (4)
VEN = 0 V, V(DP_IN) = V(DM_IN) = 0.3 V,
Vac = 0.03 VPP , f = 1 MHz
6.7
pF
C(IO_ON)
DP/DM switch on-state
capacitance (4)
V(DP_IN) = V(DM_IN) = 0.3 V,
Vac = 0.03 VPP, f = 1 MHz
10
pF
Off-state isolation (4)
VEN = 0 V, f = 250 MHz
27
dB
On-state cross-channel
isolation (4)
f = 250 MHz
23
dB
Off-state leakage current,
DP_OUT and DM_OUT
VEN = 0 V, V(DP_IN) = V
= V(DM_OUT) = 0 V
Ilkg(OFF)
BW
Bandwidth (–3 dB)
(4)
(DM_IN)
= 3.6 V, V(DP_OUT)
0.1
R(L) = 50 Ω
1.5
925
µA
MHz
CHARGING DOWNSTREAM PORT DETECT
V(DM_SRC)
DM_IN CDP output voltage
V(DAT_REF)
DP_IN rising lower window
threshold for VDM_SRC
activation
V(DP_IN) = 0.6 V, –250 µA < I(DM_IN) < 0 µA
0.5
0.36
Hysteresis (4)
V(LGC_SRC)
DP_IN rising upper window
threshold for VDM_SRC
de-activation
V(LGC_SRC_HYS)
Hysteresis (4)
I(DP_SINK)
DP_IN sink current
0.6
0.7
V
0.4
V
50
0.8
mV
0.88
100
V(DP_IN) = 0.6 V
40
V
mV
75
100
µA
125
200
Ω
V
BC1.2 DCP MODE
R(DPM_SHORT)
DP_IN and DM_IN shorting
resistance
DIVIDER3 MODE
V(DP_DIV3)
DP_IN output voltage
2.57
2.7
2.84
V(DM_DIV3)
DM_IN output voltage
2.57
2.7
2.84
V
R(DP_DIV3)
DP_IN output impedance
I(DP_IN) = –5 µA
24
30
36
kΩ
R(DM_DIV3)
DM_IN output impedance
I(DM_IN) = –5 µA
24
30
36
kΩ
1.2-V MODE
V(DP_1.2V)
DP_IN output voltage
1.12
1.2
1.26
V
V(DM_1.2V)
DM_IN output voltage
1.12
1.2
1.26
V
R(DP_1.2V)
DP_IN output impedance
I(DP_IN) = –5 µA
84
100
126
R(DM_1.2V)
DM_IN output impedance
I(DM_IN = –5 µA
84
100
126
(4)
kΩ
These parameters are provided for reference only and do not constitute part of TI's published device specifications for purposes of TI's
product warranty.
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: TPS2549
7
TPS2549
SLUSCP2 – SEPTEMBER 2016
www.ti.com
6.6 Switching Characteristics
Unless otherwise noted –40°C ≤ TJ ≤ 125°C and 4.5 V ≤ V(IN) ≤ 6.5 V, V(EN) = V(IN), V(CTL1) = V(CTL2) = V(CTL3) = V(IN). R(FAULT) =
R(STATUS) = 10 kΩ, R(ILIM_HI) = 19.1 kΩ, R(ILIM_LO) = 80.6 kΩ. Positive current is into pins. Typical value is at 25°C. All voltages
are with respect to GND.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
0.7
1.14
2
UNIT
ms
0.2
0.35
0.6
ms
4.15
6
ms
1.8
3
ms
1.1
2
2.9
s
186
320
450
ms
tr
OUT voltage rise time
tf
OUT voltage fall time
ton
OUT voltage turnon time
toff
OUT voltage turnoff time
t(DCHG_L)
Long OUT discharge hold
time (SDP, CDP, or client
mode to DCP_Auto)
Time V(OUT) < 0.7 V (see Figure 34)
t(DCHG_S)
Short OUT discharge hold
time (DCP_Auto to SDP,
CDP, or client mode)
Time V(OUT) < 0.7 V (see Figure 34)
t(IOS)
OUT short-circuit response
time (1)
V(IN) = 5 V, R(SHORT) = 50 mΩ (see Figure 25)
t(OC_OUT_FAULT)
OUT FAULT deglitch time
Bidirectional deglitch applicable to current limit
condition only (no deglitch assertion for OTSD)
tpd
Analog switch propagation
delay (1)
V(IN) = 5 V
0.14
ns
t(SK)
Analog switch skew
between opposite
transitions of the same port
(tPHL – tPLH) (1)
V(IN) = 5 V
0.02
ns
t(LD_SET)
Load-detect set time
V(IN) = 5 V (See Figure 27)
120
210
280
ms
t(LD_RESET)
Load-detect reset time
V(IN) = 5 V (See Figure 28)
1.8
3
4.2
s
t(OV_D)
DP_IN and DM_IN overvoltage protection response V(OUT) = 5 V (See Figure 29)
time
t(OV_D_FAULT)
DP_IN and DM_IN FAULT
degltich time
(1)
V(IN) = 5 V, C(L) = 1 µF, R(L) = 100 Ω (see
Figure 32 and Figure 33)
V(IN) = 5 V, C(L) = 1 µF, R(L) = 100 Ω (see
Figure 32 andFigure 35)
2
5.5
8
µs
11.5
2
V(OUT) = 5 V (See Figure 30)
11
ms
µs
16
23
ms
These parameters are provided for reference only and do not constitute part of TI's published device specifications for purposes of TI's
product warranty.
6.7 Typical Characteristics
0.6
OUT Reverse Leakage Current (µA)
Power Switch On-Resistance (m:)
70
65
60
55
50
45
40
35
30
-40
-25
-10
5
20 35 50 65 80
Junction Temperature (ºC)
95
110 125
0.4
0.3
0.2
0.1
0
-0.1
-40
-25
-10
D001
VIN = 5 V
5
20 35 50 65 80
Junction Temperature (ºC)
95
110 125
D002
VIN = 5 V
Figure 1. Power Switch On-Resistance vs Temperature
8
0.5
Figure 2. Reverse Leakage Current vs Temperature
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: TPS2549
TPS2549
www.ti.com
SLUSCP2 – SEPTEMBER 2016
Typical Characteristics (continued)
4000
V(IN) = 4.5 V
V(IN) = 5 V
V(IN) = 6.5 V
540
OUT Short-Circuit Current Limit (mA)
OUT Discharge Resistance (:)
550
530
520
510
500
490
480
470
-40
-25
-10
5
20 35 50 65 80
Junction Temperature (ºC)
95
3500
3000
2500
1500
1000
500
0
-40
110 125
Figure 3. OUT Discharge Resistance vs Temperature
6
4
2
0
-25
-10
5
20 35 50 65 80
Junction Temperature (ºC)
CTL1 = 1
95
110 125
D004
95
V(IN) = 4.5 V
V(IN) = 5 V
V(IN) = 6.5 V
260
240
220
200
180
-40
110 125
-25
-10
5
D005
CTL2 = 1
CTL3 = 1
20 35 50 65 80
Junction Temperature (ºC)
CTL1 = 1
Figure 5. Disabled IN Supply Current vs Temperature
95
110 125
D006
CTL2 = 1
CTL3 = 1
Figure 6. Enabled IN Supply Current – CDP (111) vs
Temperature
220
290
V(IN) = 4.5 V
V(IN) = 5 V
V(IN) = 6.5 V
IN Supply Current, Enabled (µA)
IN Supply Current, Enabled (µA)
20 35 50 65 80
Junction Temperature (ºC)
Figure 4. OUT Short-Circuit Current Limit vs Temperature
IN Supply Current, Enabled (µA)
IN Supply Current, Disabled (µA)
V(IN) = 4.5 V
V(IN) = 5 V
V(IN) = 6.5 V
8
250
230
210
190
-40
5
280
10
270
-10
VIN = 5 V
14
-2
-40
-25
D003
A
12
R(ILIM_LO) = 210 k:
R(ILIM_LO) = 80.6 k:
R(ILIM_HI) = 20 k:
R(ILIM_HI) = 19.1 k:
R(ILIM_HI) = 15.4 k:
2000
-25
-10
CTL1 = 0
5
20 35 50 65 80
Junction Temperature (ºC)
CTL2 = 0
95
110 125
V(IN) = 4.5 V
V(IN) = 5 V
V(IN) = 6.5 V
200
180
160
140
120
-40
-25
-10
D007
CTL3 = 1
Figure 7. Enabled IN Supply Current – DCP_Auto (001) vs
Temperature
CTL1 = 0
5
20 35 50 65 80
Junction Temperature (ºC)
CTL2 = 1
95
110 125
D008
CTL3 = 0
Figure 8. Enabled IN Supply Current – SDP (010) vs
Temperature
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: TPS2549
9
TPS2549
SLUSCP2 – SEPTEMBER 2016
www.ti.com
Typical Characteristics (continued)
160
720
V(IN) = 4.5 V
V(IN) = 5 V
V(IN) = 6.5 V
710
700
Current (µA)
IN Supply Current, Enabled (µA)
180
140
120
680
670
660
100
650
80
-40
-25
-10
5
CTL1 = 1
20 35 50 65 80
Junction Temperature (ºC)
95
110 125
CTL2 = 0
CTL3 = 0
20 35 50 65 80
Junction Temperature (ºC)
95
110 125
D010
Figure 10. IOUT Rising Load-Detect Threshold and OUT
Short-Circuit Current Limit vs Temperature
DM_IN OV Protection Threshold (V)
4
3.9
3.8
3.7
-25
-10
5
20 35 50 65 80
Junction Temperature (ºC)
95
4.1
4
3.9
3.8
3.7
3.6
-40
110 125
-25
-10
5
D011
20 35 50 65 80
Junction Temperature (ºC)
95
110 125
D012
VIN = 5 V
Figure 11. DP_IN Overvoltage Protection Threshold vs
Temperature
Figure 12. DM_IN Overvoltage Protection Threshold vs
Temperature
250
250
200
200
Sink Current (µA)
Sink Current (µA)
5
R(ILIM_LO) = 80.6 kΩ
VIN = 5 V
150
100
50
150
100
50
I(OUT) = 1 A
I(OUT) = 2.1 A
-25
-10
5
VIN = 5 V
20 35 50 65 80
Junction Temperature (ºC)
I(OUT) = 2.4 A
I(OUT) = 3 A
95
VCS = 2. 5 V
I(OUT) = 1 A
I(OUT) = 2.1 A
110 125
0
2.5
3
D013
3.5
4
4.5
5
CS Voltage (V)
I(OUT) = 2.4 A
I(OUT) = 3 A
5.5
6
6.5
D014
VIN = 6.5 V
Figure 13. ICS vs Temperature
10
-10
4.2
4.1
0
-40
-25
D009
4.2
3.6
-40
I(LD), OUT Rising Load-Detect Threshold
IOS, OUT Short-Circuit Current
640
-40
Figure 9. Enabled IN Supply Current – Client Mode (100) vs
Temperature
DP_IN OV Protection Threshold (V)
690
Figure 14. ICS vs VCS Voltage
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: TPS2549
TPS2549
www.ti.com
SLUSCP2 – SEPTEMBER 2016
Typical Characteristics (continued)
Figure 15. Data Transmission Characteristics vs Frequency
Figure 16. Off-State Data-Switch Isolation vs Frequency
Figure 17. On-State Cross-Channel Isolation vs Frequency
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: TPS2549
11
TPS2549
SLUSCP2 – SEPTEMBER 2016
www.ti.com
Typical Characteristics (continued)
Forcing a page break between ImageMatrices
Figure 18. Eye Diagram Using USB Compliance Test
Pattern, Bypassing the TPS2549 Data Switch
Figure 19. Eye Diagram Using USB Compliance Test
Pattern, Through the TPS2549 Data Switch
V(EN)
5 V/div
V(EN)
5 V/div
V(OUT)
V(OUT)
2.5 V/div
2.5 V/div
I(IN)
0.5 A/div
I(IN)
0.5 A/div
R(LOAD) = 5 Ω
C(LOAD) = 150 µF
t = 1 ms/div
R(LOAD) = 5 Ω
Figure 20. Turnon Response
V(EN)
5 V/div
V(FAULT)
5 V/div
I(IN)
0.5 A/div
V(FAULT)
5 V/div
I(IN)
1 A/div
t = 2 ms/div
Figure 22. Enable Into Short
12
t = 1 ms/div
Figure 21. Turnoff Response
V(EN)
5 V/div
R(ILIM_HI) = 80.6 kΩ
C(LOAD) = 150 µF
R(ILIM_HI) = 19.1 kΩ
t = 4 ms/div
Figure 23. Enable Into Short – Thermal Cycling
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: TPS2549
TPS2549
www.ti.com
SLUSCP2 – SEPTEMBER 2016
Typical Characteristics (continued)
V(FAULT)
5 V/div
V(OUT)
2.5 V/div
V(OUT)
2.5 V/div
I(IN)
2 A/div
R(ILIM_HI) = 19.1 kΩ
I(OUT)
10 A/div
R(SHORT) = 50 mΩ
t = 4 ms/div
t = 1 µs/div
Figure 25. Hot-Short Response Time
Figure 24. Short-Circuit to Full-Load Recovery
V(EN)
2.5 V/div
V(OUT)
2.5 V/div
V(STATUS)
5 V/div
I(OUT)
0.5 A/div
I(OUT)
2 A/div
R(ILIM_HI) = 19.1 kΩ
R(SHORT) = 50 mΩ
t = 1 ms/div
R(ILIM_LO) = 80.6 kΩ
t = 100 ms/div
Figure 27. Load-Detection Set Time
Figure 26. Hot Short
V(STATUS)
5 V/div
V(DM_IN)
2.5 V/div
V(OUT)
2.5 V/div
V(DM_OUT)
2.5 V/div
I(OUT)
0.5 A/div
R(ILIM_LO) = 80.6 kΩ
t = 1 s/div
R(DM_OUT) = 15 kΩ
Figure 28. Load Detection Reset Time
t = 1 µs/div
Figure 29. DM_IN Short to VBUS Response Time
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: TPS2549
13
TPS2549
SLUSCP2 – SEPTEMBER 2016
www.ti.com
Typical Characteristics (continued)
V(FAULT)
5 V/div
V(FAULT)
5 V/div
V(DM_IN)
2.5 V/div
V(DM_IN)
2.5 V/div
V(DM_OUT)
2.5 V/div
V(DM_OUT)
2.5 V/div
R(DM_OUT) = 15 kΩ
t = 4 ms/div
R(DM_OUT) = 15 kΩ
Figure 30. DM_IN Short to VBUS
t = 1 µs/div
Figure 31. DM_IN Short-to-VBUS Recovery
7 Parameter Measurement Information
OUT
R(L)
C(L)
V(OUT)
tf
90%
10%
Figure 33. Power-On and -Off Timing
Figure 32. OUT Rise-Fall Test Load Figure
V(EN)
5V
tr
50%
toff
ton
t(DCHG)
V(OU T)
50%
90%
V(OUT)
10%
Figure 35. Enable Timing, Active-High Enable
0V
Figure 34. OUT Discharge During Mode Change
IOS
I(OUT)
t(IO S)
Figure 36. Output Short-Circuit Parameters
14
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: TPS2549
TPS2549
www.ti.com
SLUSCP2 – SEPTEMBER 2016
8 Detailed Description
8.1 Overview
The TPS2549 device is a USB charging controller and power switch which integrates D+ and D– short to VBUS
protection, cable compensation and IEC ESD protection, and is suitable for USB charging and USB portprotection applications.
The TPS2549 device integrates a current-limited, power-distribution switch using N-channel MOSFETs for
applications where short circuits or heavy capacitive loads can be encountered. The device allows the user to
program the current-limit threshold via an external resistor. The device enters constant-current mode when the
load exceeds the current limit threshold.
The TPS2549 device also integrates CDP mode, defined in the BC1.2 specification, to enable up to 1.5-A fast
charging of most of portable devices, meanwhile supporting data communication. In addition, the device
integrates the DCP-auto feature to enable fast-charging of most portable devices including pads, tablets, and
smart phones.
The TPS2549 device integrates a cable compensation (CS) feature to compensate the voltage drop in long
cables and keep the remote USB port output voltage constant.
Additionally, the device integrates an IEC ESD cell to provide ESD protection up to ±8 kV (contact discharge)
and ±15 kV (air discharge) per IEC 61000-4-2 on DP_IN and DM_IN, and integrates short-to-VBUS overvoltage
protection on DP_IN and DM_IN to protect the upstream USB transceiver.
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: TPS2549
15
TPS2549
SLUSCP2 – SEPTEMBER 2016
www.ti.com
8.2 Functional Block Diagram
Current
Sense
CS
IN
ILIM_HI
ILIM_LO
OUT
Disable + UVLO
+ Discharge
Current
Limit
Charge
Pump
8-ms
Deglitch
GND
OC
Driver
EN
FAULT
UVLO
CS
I(CS) = I(OUT) × 75 µA /A
Thermal
Sense
16-ms
Deglitch
OTSD
OVP2
OVP1
DM_OUT
DM_IN
DP_OUT
DP_IN
CDP
Detection
CTL1
CTL2
DCP
(Auto-Detection)
STATUS
Logic
Control
CTL3
Discharge
Copyright © 2016, Texas Instruments Incorporated
16
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: TPS2549
TPS2549
www.ti.com
SLUSCP2 – SEPTEMBER 2016
8.3 Feature Description
8.3.1 FAULT Response
The device features an active-low, open-drain fault output. FAULT goes low when there is a fault condition. Fault
detection includes overtemperature, overcurrent, or DP_IN, DM_IN overvoltage. Connect a 10-kΩ pullup resistor
from FAULT to IN.
Table 1 summarizes the conditions that generate a fault and actions taken by the device.
Table 1. Fault Conditions
EVENT
Overcurrent on V(OUT)
CONDITION
ACTION
The device regulates switch current at IOS until thermal
cycling occurs. The fault indicator asserts and de-asserts
with an 8-ms deglitch (The device does not assert FAULT on
overcurrent in SDP1 and DCP1 modes).
I(OUT) > IOS
The device immediately shuts off the USB data switches.
The fault indicator asserts with a 16-ms deglitch, and deasserts without deglitch.
Overvoltage on the data lines DP_IN or DM_IN > 3.9 V
Overtemperature
The device immediately shuts off the internal power switch
and the USB data switches. The fault indicator asserts
immediately when the junction temperature exceeds OTSD2
or OTSD1 while in a current-limiting condition. The device
has a thermal hysteresis of 20°C.
TJ > OTSD2 in non-current-limited or
TJ > OTSD1 in current-limited mode.
8.3.2 Cable Compensation
V(OUT) (V)
When a load draws current through a long or thin wire, there is an IR drop that reduces the voltage delivered to
the load. In the vehicle from the voltage regulator 5-V output to the VPD_IN (input voltage of portable device), the
total resistance of power switch rDS(on) and cable resistance causes an IR drop at the PD input.. So the charging
current of most portable devices is less than their expected maximum charging current.
V(OUT) With Compensation
5.x
V(DROP)
VBUS With Compensation
VBUS Without Compensation
0
0.5
1
1.5
2
2.5
3
I(OUT) (A)
Figure 37. Voltage Drop
TPS2549 device detects the load current and generates a proportional sink current that can be used to adjust
output voltage of the upstream regulator to compensate the IR drop in the charging path. The gain G(CS) of the
sink current proportional to load current is 75 µA/A.
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: TPS2549
17
TPS2549
SLUSCP2 – SEPTEMBER 2016
www.ti.com
rDS(on)
R(FA)
To Regulator OUT
IN
OUT
R3
V(OUT)
C(COMP)
R1
R2
To Load
VBUS
R(WIRE)
R(LOAD)
C(OUT)
R(FB)
FB
To Regulator
Resistor Divider
CS
R(G)
Copyright © 2016, Texas Instruments Incorporated
Figure 38. Cable Compensation Equivalent Circuit
8.3.2.1 Design Procedure
To start the procedure, the total resistance, including power switch rDS(on) and wire resistance R(WIRE), must to be
known.
1. Choose R(G) following the voltage-regulator feedback resistor-divider design guideline.
2. Calculate R(FA) according to Equation 1.
R FA = (r DS(on) + R (WIRE) ) / G (CS)
(1)
3. Calculate R(FB) according to Equation 2.
V(OUT)
R (FB) =
- R (G) - R (FA)
V(FB) / R (G)
(2)
4. C(COMP) in parallel with R(FA) is needed to stablilize V(OUT) when C(OUT) is large. Start with C(COMP) ≥ 3 × G(CS)
× C(OUT), then adjust C(COMP) to optimize the load transient of the voltage regulator output. V(OUT) stability
should always be verified in the end application circuit.
8.3.3 D+ and D– Protection
D+ and D– protection consists of ESD and OVP (overvoltage protection). The DP_IN and DM_IN pins integrate
an IEC ESD cell to provide ESD protection up to ±15 kV air discharge and ±8 kV contact discharge per IEC
61000-4-2 (See the ESD Ratings section for test conditions). Overvoltage protection (OVP) is provided for shortto-VBUS conditions in the vehicle harness to prevent damaging the upstream USB transceiver. Short-to-GND
protection for D+ and D– is provided by the upstream USB transceiver.
The ESD stress seen at DP_IN and DM_IN is impacted by many external factors like the parasitic resistance and
inductance between ESD test points and the DP_IN and DM_IN pins. For air discharge, the temperature and
humidity of the environment can cause some difference, so the IEC performance should always be verified in the
end-application circuit.
8.3.4 Output and D+ or D– Discharge
To allow a charging port to renegotiate current with a portable device, the TPS2549 device uses the OUT
discharge function. This function turns off the power switch while discharging OUT with a 500-Ω resistance, then
turns the power switches to back on reassert the OUT voltage.
For DP_IN and DM_IN, when OVP is triggered, the device turns on an internal discharge path with 210-Ω
resistance. On removal of OVP, this path can discharge the remnant charges to automatically turn on analog
switch and turn off this discharge path, thus back into normal mode.
18
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: TPS2549
TPS2549
www.ti.com
SLUSCP2 – SEPTEMBER 2016
8.3.5 Port Power Management (PPM)
PPM is the intelligent and dynamic allocation of power. PPM is for systems that have multiple charging ports but
cannot power them all simultaneously.
8.3.5.1 Benefits of PPM
The benefits of PPM include the following:
• Delivers better user experience
• Prevents overloading of system power supply
• Allows for dynamic power limits based on system state
• Allows every port to potentially be a high-power charging port
• Allows for smaller power-supply capacity because loading is controlled
8.3.5.2 PPM Details
All ports are allowed to broadcast high-current charging. The current-limit is based on ILIM_HI. The system
monitors the STATUS pin to see when high-current loads are present. Once the allowed number of ports asserts
STATUS, the remaining ports are toggled to a non-charging port. The non-charging port current-limit is based on
the ILIM_LO setting. The non-charging ports are automatically toggled back to charging ports when a charging
port de-asserts STATUS.
STATUS asserts in a charging port when the load current is above ILIM_LO + 40 mA for 210 ms (typical).
STATUS de-asserts in a charging-port when the load current is below ILIM_LO – 10 mA for 3 seconds (typical).
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: TPS2549
19
TPS2549
SLUSCP2 – SEPTEMBER 2016
www.ti.com
8.3.5.3 Implementing PPM in a System With Two Charging Ports (CDP and SDP1)
Figure 39 shows the implementation of the two charging ports with data communication, each with a TPS2549
device and configured in CDP mode. In this example, the 5-V power supply for the two charging ports is rated at
less than 3.5 A. Both TPS2549 devices have ILIM_LO of 1 A and ILIM_HI of 2.4 A. In this implementation, the
system can support only one of the two ports at 2.4-A charging current, whereas the other port is set to SDP1
mode and I(LIMIT) corresponds to 1 A. In SDP1 mode, FAULT does not assert for overcurrent.
TPS2549 Port 1
5V
USB Charging
Port 1
IN
OUT
EN1
EN
DM_IN
FAULT1
DP_IN
FAULT
STATUS
ILIM _LO
ILIM_HI
CTL1
CTL2
R_HI
R_LO
GND
100 kW
CTL3
TPS2549 Port 2
USB Charging
Port 2
IN
OUT
EN2
EN
FAULT2
DM_IN
DP_IN
FAULT
STATUS
ILIM _LO
ILIM_HI
CTL1
CTL2
R_HI
R_LO
GND
100 kW
CTL3
Copyright © 2016, Texas Instruments Incorporated
Figure 39. PPM With CDP and SDP1
20
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: TPS2549
TPS2549
www.ti.com
SLUSCP2 – SEPTEMBER 2016
8.3.5.4 Implementing PPM in a System With Two Charging Ports (DCP and DCP1)
Figure 40 shows the implementation of the two charging-only ports, each with a TPS2549 device and configured
in DCP mode. In this example, the 5-V power supply for the two charging ports is rated at less than 3.5 A. Both
TPS2549 devices have ILIM_LO of 1 A and ILIM_HI of 2.4 A. In this implementation, the system can support
only one of the two ports at 2.4-A charging current, whereas the other port is set to DCP1 mode and I(LIMIT)
corresponds to 1 A. In DCP1 mode, FAULT does not assert for overcurrent.
TPS2549 Port 1
5V
USB Charging
Port 1
IN
OUT
EN1
EN
DM_IN
FAULT1
DP_IN
FAULT
STATUS
ILIM _LO
ILIM_HI
CTL1
CTL2
R_HI
R_LO
GND
100 kW
CTL3
TPS2549 Port 2
USB Charging
Port 2
IN
OUT
EN2
EN
FAULT2
DM_IN
DP_IN
FAULT
STATUS
ILIM _LO
ILIM_HI
CTL1
CTL2
R_HI
R_LO
GND
100 kW
CTL3
Copyright © 2016, Texas Instruments Incorporated
Figure 40. PPM With DCP and DCP1
8.3.6 CDP and SDP Auto Switch
The TPS2549 device is equipped with a CDP and SDP auto-switch feature to support some popular phones in
the market. These popular phones do not comply with the BC1.2 specification because they fail to establish a
data connection in CDP mode. These phones use primary detection (used to distinguish between an SDP and
different types of charging ports) to only identify ports as SDP (data, no charge) or DCP (no data, charge). These
phones do not recognize CDP (data, charge) ports. When connected to a CDP port, these phones classify the
port as a DCP and only charge the battery. Because the charging ports are configured as CDP, users do not
receive the expected data connection.
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: TPS2549
21
TPS2549
SLUSCP2 – SEPTEMBER 2016
www.ti.com
Primary Detection
D+
Device never signals
connection and enumerates.
Data connection is lost.
D–
VBUS
VBUS Current
Figure 41. CDP and SDP Auto-Switch
To remedy this problem, the TPS2549 device employs a CDP and SDP auto-switch scheme to ensure these
BC1.2 noncompliant phones establish data connection using the following steps.
1. The TPS2549 device determines when a noncompliant phone has wrongly classified a CDP port as a DCP
port and has not made a data connection.
2. The TPS2549 device automatically completes an OUT (VBUS) discharge and reconfigures the port as an
SDP.
3. When reconfigured as an SDP, the phone detects a connection to an SDP and establishes a data
connection.
4. The TPS2549 device then switches automatically back to a CDP without doing an OUT (VBUS) discharge.
5. The phone continues to operate as if connected to an SDP because OUT (VBUS) was not interrupted. The
port is now ready in CDP if a new device is attached.
8.3.7 Overcurrent Protection
When an overcurrent condition is detected, the device maintains a constant output current and reduces the
output voltage accordingly. Two possible overload conditions can occur. In the first condition, the output is
shorted before the device enables or before the application of V(IN). The TPS2549 device senses the short and
immediately switches into a constant-current output. In the second condition, a short or an overload occurs while
the device is enabled. At the instant the overload occurs, high currents flow for 2 μs (typical) before the currentlimit circuit reacts. The device operates in constant-current mode after the current-limit circuit has responded.
Complete shutdown occurs only if the fault is presented long enough to activate overtemperature protection. The
device remains off until the junction temperature cools to approximately 20°C and then restarts. The device
continues to cycle on and off until the overcurrent condition is removed.
8.3.8 Undervoltage Lockout
The undervoltage-lockout (UVLO) circuit disables the device until the input voltage reaches the UVLO turnon
threshold. Built-in hysteresis prevents unwanted oscillations on the output due to input voltage drop from large
current surges.
8.3.9 Thermal Sensing
Two independent thermal-sensing circuits protect the TPS2549 device if the temperature exceeds recommended
operating conditions. These circuits monitor the operating temperature of the power-distribution switch and
disable operation. The device operates in constant-current mode during an overcurrent condition, which
increases the voltage drop across power switch. The power dissipation in the package is proportional to the
voltage drop across the power switch, so the junction temperature rises during an overcurrent condition. When
the device is in a current-limiting condition, the first thermal sensor turns off the power switch when the die
22
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: TPS2549
TPS2549
www.ti.com
SLUSCP2 – SEPTEMBER 2016
temperature exceeds OTSD1. If the device is not in a current-limiting condition, the second thermal sensor turns
off the power switch when the die temperature exceeds OTSD2. Hysteresis is built into both thermal sensors,
and the switch turns on after the device has cooled by approximately 20°C. The switch continues to cycle off and
then on until the fault is removed. The open-drain false-reporting output, FAULT, is asserted (low) during an
overtemperature shutdown condition.
8.3.10 Current Limit Setting
The TPS2549 has two independent current-limit settings that are each programmed externally with a resistor.
The ILIM_HI setting is programmed with R(ILIM_HI) connected between ILIM_HI and GND. The ILIM_LO setting is
programmed with R(ILIM_LO) connected between ILIM_LO and GND. Consult the device truth table (Table 2) to
see when each current limit is used. Both settings have the same relation between the current limit and the
programming resistor.
R(ILIM_LO) is optional and the ILIM_LO pin may be left unconnected if the following conditions are met:
• The TPS2549 device is configured as DCP(001) or CDP(111).
• Load detection is not used.
The following equation calculates the value of resistor for programming the typical current limit:
53 762 (V)
I(OSnom) (mA) =
R (ILIM _ xx)1.0021 (kW)
(3)
R(ILIM_xx) corresponds to either R(ILIM_HI) or R(ILIM_LO), as appropriate.
Many applications require that the current limit meet specific tolerance limits. When designing to these tolerance
limits, both the tolerance of the TPS2549 current limit and the tolerance of the external programming resistor
must be taken into account. The following equations approximate the TPS2549 minimum and maximum current
limits to within a few milliamperes and are appropriate for design purposes. The equations do not constitute part
of TI’s published device specifications for purposes of TI’s product warranty. These equations assume an
ideal—no variation—external programming resistor. To take resistor tolerance into account, first determine the
minimum and maximum resistor values based on its tolerance specifications and use these values in the
equations. Because of the inverse relation between the current limit and the programming resistor, use the
maximum resistor value in the I(OS_min) equation and the minimum resistor value in the I(OS_max) equation.
50 409 (V)
I(OSmin) (mA) =
- 35
R (ILIM _ xx)0.9982 (kW)
(4)
I(OSmax) (mA) =
57 813 (V)
R (ILIM _ xx)1.0107 (kW)
+ 41
(5)
700
4000
Current Limit Threshold (mA)
3500
Current Limit Threshold (mA)
I(OSmin)
I(OStyp)
I(OSmax)
3000
2500
2000
1500
1000
I(OSmin)
I(OStyp)
I(OSmax)
600
500
400
300
200
100
500
0
10
20
30
40
50
60
70
Current Limit Resistor (k:)
80
90
100
0
100
D019
Figure 42. Current Limit Setting vs Programming
Resistor I
200
300
400 500 600 700 800
Current Limit Resistor (k:)
900
1000
D020
Figure 43. Current Limit Setting vs Programming
Resistor II
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: TPS2549
23
TPS2549
SLUSCP2 – SEPTEMBER 2016
www.ti.com
The routing of the traces to the R(ILIM_xx) resistors should have a sufficiently low resistance so as to not affect the
current-limit accuracy. The ground connection for the R(ILIM_xx) resistors is also very important. The resistors must
reference back to the TPS2549 GND pin. Follow normal board layout practices to ensure that current flow from
other parts of the board does not impact the ground potential between the resistors and the TPS2549 GND pin.
8.4 Device Functional Modes
8.4.1 Device Truth Table (TT)
The device truth table (Table 2) lists all valid combinations for the three control pins (CTL1 through CTL3), and
the corresponding charging mode of each pin combination. The TPS2549 device monitors the CTL inputs and
transitions to whichever charging mode it is commanded to go to. For example, if the USB port is a charging-only
port, then the user must set the CTL pins of the TPS2549 device to correspond to the DCP-auto charging mode.
However, when the USB port requires data communication, then the user must set control pins to correspond to
the SDP or CDP mode, and so on.
Table 2. Truth Table
CTL1
CTL2
CTL3
CURRENT
LIMIT
SETTING
MODE
STATUS
OUTPUT
(ACTIVELOW)
FAULT
OUTPUT
(ACTIVELOW)
CS FOR CABLE
COMPENSATION
0
0
0
Lo
DCP1 (1)
OFF
ON (2)
ON
DCP includes divider 3,
1.2-V mode, and
BC1.2 mode
0
0
1
Hi
DCP (1)
ON
ON
ON
DCP includes divider 3,
1.2-V mode, and
BC1.2 mode
0
1
X
Lo
SDP
OFF
ON
ON
Standard SDP port
1
0
X
NA
Client mode
OFF
OFF
OFF
No current limit, power
switch disabled, data
switch bypassed
1
1
0
Lo
SDP1 (3)
OFF
ON (2)
ON
Standard SDP port
ON
ON
ON
CDP-SDP auto switch
mode
1
(1)
(2)
(3)
1
1
Hi
CDP
(3)
NOTES
No OUT discharge when changing between 000 and 001
FAULT not asserted on overcurrent
No OUT discharge when changing between 110 and 111
8.4.2 USB Specification Overview
The following overview references various industry standards. TI recommends consulting the most up-to-date
standards to ensure the most recent and accurate information. Rechargeable portable equipment requires an
external power source to charge batteries. USB ports are a convenient location for charging because of an
available 5-V power source. Universally accepted standards are required to ensure host and client-side devices
operate together in a system to ensure power-management requirements are met. Traditionally, host ports
following the USB-2.0 specification must provide at least 500 mA to downstream client-side devices. Because
multiple USB devices can be attached to a single USB port through a bus-powered hub, the client-side device
sets the power allotment from the host to ensure the total current draw does not exceed 500 mA. In general,
each USB device is granted 100 mA and can request more current in 100-mA unit steps up to 500 mA. The host
grants or denies additional current based on the available current. A USB-3.0 host port not only provides higher
data rate than a USB-2.0 port but also raises the unit load from 100 mA to 150 mA. Providing a minimum current
of 900 mA to downstream client-side devices is required.
Additionally, the success of USB has made the micro-USB and mini-USB connectors a popular choice for walladapter cables. A micro-USB or mini-USB allows a portable device to charge from both a wall adapter and USB
port with only one connector. As USB charging has gained popularity, the 500-mA minimum defined by USB 2.0,
or 900 mA for USB 3.0, has become insufficient for many handset and personal media players, which require a
higher charging rate. Wall adapters provide much more current than 500 or 900 mA. Several new standards have
been introduced defining protocol handshaking methods that allow host and client devices to acknowledge and
draw additional current beyond the 500-mA and 900-mA minimum defined by USB 2.0 and USB 3.0,
respectively, while still using a single micro-USB or mini-USB input connector.
24
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: TPS2549
TPS2549
www.ti.com
SLUSCP2 – SEPTEMBER 2016
The TPS2549 device supports four of the most-common USB-charging schemes found in popular hand-held
media and cellular devices.
• USB Battery Charging Specification BC1.2
• Chinese Telecommunications Industry Standard YD/T 1591-2009
• Divider 3 mode
• 1.2-V mode
The BC1.2 specification includes three different port types:
• Standard downstream port (SDP)
• Charging downstream port (CDP)
• Dedicated charging port (DCP)
BC1.2 defines a charging port as a downstream-facing USB port that provides power for charging portable
equipment. Under this definition, CDP and DCP are defined as charging ports.
Table 3 lists the difference between these port types.
Table 3. Operating Modes Table
PORT TYPE
SUPPORTS USB2.0 COMMUNICATION
MAXIMUM ALLOWABLE CURRENT
DRAWN BY PORTABLE EQUIPMENT (A)
SDP (USB 2.0)
YES
0.5
SDP (USB 3.0)
YES
0.9
CDP
YES
1.5
DCP
NO
1.5
8.4.3 Standard Downstream Port (SDP) Mode — USB 2.0 and USB 3.0
An SDP is a traditional USB port that follows USB 2.0 or USB 3.0 protocol. A USB 2.0 SDP supplies a minimum
of 500 mA per port and supports USB 2.0 communications. A USB 3.0 SDP supplies a minimum of 900 mA per
port and supports USB 3.0 communications. For both types, the host controller must be active to allow charging.
8.4.4 Charging Downstream Port (CDP) Mode
A CDP is a USB port that follows USB BC1.2 and supplies a minimum of 1.5 A per port. A CDP provides power
and meets the USB 2.0 requirements for device enumeration. USB-2.0 communication is supported, and the host
controller must be active to allow charging. The difference between CDP and SDP is the host-charge
handshaking logic that identifies this port as a CDP. A CDP is identifiable by a compliant BC1.2 client device and
allows for additional current draw by the client device.
The CDP handshaking process occurs in two steps. During step one, the portable equipment outputs a nominal
0.6-V output on the D+ line and reads the voltage input on the D– line. The portable device detects the
connection to an SDP if the voltage is less than the nominal data-detect voltage of 0.3 V. The portable device
detects the connection to a CDP if the D– voltage is greater than the nominal data detect voltage of 0.3 V and
optionally less than 0.8 V.
The second step is necessary for portable equipment to determine whether the equipment is connected to a CDP
or a DCP. The portable device outputs a nominal 0.6-V output on the D– line and reads the voltage input on the
D+ line. The portable device concludes the equipment is connected to a CDP if the data line being read remains
less than the nominal data detects voltage of 0.3 V. The portable device concludes it is connected to a DCP if
the data line being read is greater than the nominal data detect voltage of 0.3 V.
8.4.5 Dedicated Charging Port (DCP) Mode
A DCP only provides power and does not support data connection to an upstream port. As shown in the following
sections, a DCP is identified by the electrical characteristics of the data lines. The TPS2549 only emulates one
state, DCP-auto state. In the DCP-auto state, the device charge-detection state machine is activated to
selectively implement charging schemes involved with the shorted, divider3 and 1.2 v modes. The shorted DCP
mode complies with BC1.2 and Chinese Telecommunications Industry Standard YD/T 1591-2009, whereas the
divider3 and 1.2 V modes are employed to charge devices that do not comply with the BC1.2 DCP standard.
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: TPS2549
25
TPS2549
SLUSCP2 – SEPTEMBER 2016
www.ti.com
8.4.5.1 DCP BC1.2 and YD/T 1591-2009
Both standards specify that the D+ and D– data lines must be connected together with a maximum series
impedance of 200 Ω, as shown in Figure 44.
D–
200 Ω
(m a x.)
D+
GND
USB Connector
VBUS
5V
Figure 44. DCP Supporting BC1.2 and YD/T 1591-2009
8.4.5.2 DCP Divider-Charging Scheme
The device supports divider3, as shown in Figure 45. In the Divider3 charging scheme the device applies 2.7 V
and 2.7 V to D+ and D– data lines.
VBUS
USB Connector
5V
D–
2.7 V
2.7 V
D+
GND
Figure 45. Divider 3 Mode
8.4.5.3 DCP 1.2-V Charging Scheme
The DCP 1.2-V charging scheme is used by some hand-held devices to enable fast charging at 2 A. The
TPS2549 device supports this scheme in DCP-auto state before the device enters BC1.2 shorted mode. To
simulate this charging scheme, the D+ and D– lines are shorted and pulled up to 1.2 V for a fixed duration. Then
the device moves to DCP shorted mode as defined in the BC1.2 specification and as shown in Figure 46.
200 Ω (m a x.)
D–
D+
1.2 V
GND
USB Connector
VBUS
5V
Figure 46. 1.2-V Mode
8.4.6 DCP Auto Mode
As previously discussed, the TPS2549 device integrates an auto-detect state machine that supports all the DCP
charging schemes. The auto-detect state machine starts in the Divider3 scheme. However, if a BC1.2 or YD/T
1591-2009 compliant device is attached, the TPS2549 device responds by turning the power switch back on
without output discharge and operating in 1.2-V mode briefly before entering BC1.2 DCP mode. Then the autodetect state machine stays in that mode until the device releases the data line, in which case the auto-detect
state machine goes back to the Divider3 scheme. When a Divider3-compliant device is attached, the TPS2549
device stays in the Divider3 state.
26
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: TPS2549
TPS2549
www.ti.com
SLUSCP2 – SEPTEMBER 2016
5V
S1
S2
S4
S3
2.7 V
2.7 V
DM_IN
D–
DP_IN
D+
GND
GND
USB Connector
VBUS
1.2 V
Divider 3 Mode
S1, S2: ON
S3, S4: OFF
Shorted Mode
S4 ON
S1, S2, S3: OFF
1.2-V Mode
S1, S2: OFF
S3, S4: ON
Figure 47. DCP Auto Mode
8.4.7 Client Mode
The TPS2549 device integrates client mode as shown in Figure 48. The internal power switch is OFF and only
the data analog switch is ON to block OUT power. This mode can be used for some software programming via
the USB port.
IN
OUT
DP_OUT
DM_OUT
OFF
DP_IN
DM_IN
Figure 48. Client-Mode Equivalent Circuit
8.4.8 High-Bandwidth Data-Line Switches
The TPS2549 device passes the D+ and D– data lines through the device to enable monitoring and handshaking
while supporting the charging operation. A wide-bandwidth signal switch allows data to pass through the device
without corrupting signal integrity. The data-line switches are turned on in any of the CDP, SDP, or client
operating modes. The EN input must be at logic high for the data line switches to be enabled.
•
•
•
•
NOTE
While in CDP mode, the data switches are ON, even during CDP handshaking.
The data line switches are OFF if EN is low, or if in DCP mode. The switches are not
automatically turned off if the power switch (IN to OUT) is in current-limit.
The data switches are only for a USB-2.0 differential pair. In the case of a USB-3.0
host, the super-speed differential pairs must be routed directly to the USB connector
without passing through the TPS2549 device.
Data switches are OFF during OUT (VBUS) discharge.
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: TPS2549
27
TPS2549
SLUSCP2 – SEPTEMBER 2016
www.ti.com
9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The TPS2549 device is a USB charging-port controller and power switch with cable compensation. It is typically
used for USB port protection and as a USB charging controller. The following design procedure can be used to
select components for the TPS2549 device. This section presents a simplified discussion of how to design cable
compensation.
9.2 Typical Application
USB port charging requires a voltage regulator to convert battery voltage to 5-V VBUS output. Because the VBUS,
D+, and D– pins of a USB port are exposed, there is a need for a protection device that has VBUS overcurrent
and D+ and D– ESD protection. An additional need is a charging controller with integrated CDP and DCP
charging protocols on D+ and D– to support fast charging. A schematic of an application circuit with cable
compensation is shown in Figure 49. An LMR14030 device is used as the voltage regulator, and the TPS2549
device is used as the charging controller with protection features.
28
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: TPS2549
TPS2549
www.ti.com
SLUSCP2 – SEPTEMBER 2016
Typical Application (continued)
0.1 µF
10 µH
22 nF
5.6 kW
LMR14030
47 µF
0.1 µF
2.2 µF
2.2 µF
Bulk
Capacitor
VIN
47 µF
SW
B350A-13-F
BOOT
12 V
GND
33 kW
EN
60.4 kW
0.75 V
FB
6.8 kW
RT/SYNC
V(DC)
SS
0.018 µF
To Portable Device
47 mΩ
OUT
R(BUS)
2 × 47 µF
USB Port
IN
10 k W
10 k W
10 k W
0.1µF
TPS2549
FAULT
FAULT
DM_IN
R(GN D)
DP_IN
1.5-m USB Cable
VBUS
STATUS
GND
STATUS
CS
EN
I/O
ILIM_LO
ILIM _HI
CTL1
CTL2
DM_OUT
CTL3
DP_OUT
20 k W
80.6 k W
To Host
Controller
Copyright © 2016, Texas Instruments Incorporated
Figure 49. Typical Application Schematic: USB Port Charging With Cable Compensation
9.2.1 Design Requirements
For this design example, use the following as the input parameters.
DESIGN PARAMETER
EXAMPLE VALUE
Input voltage, V(IN)
12 V
Output voltage, V(DC)
5V
Total parasitic resistance including TPS2549 rDS(on)
420 mΩ
Maximum continuous output current, I(OUT)
2.4 A
Current limit, I(LIM)
2.5 A to 2.9 A
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: TPS2549
29
TPS2549
SLUSCP2 – SEPTEMBER 2016
www.ti.com
9.2.2 Detailed Design Procedure
To begin the design process, a few parameters must be decided upon. The designer needs to know the
following:
• Total resistance including power switch rDS(on), cable resistance, and the contact resistance of connectors
• The maximum continuous output current for the charging port. The minimum current-limit setting of TPS2549
device must be higher than this current.
• The maximum output current of the upstream dc-dc converter. The maximum current-limit setting of TPS2549
device must be lower than this current.
9.2.2.1 Input and Output Capacitance
Input and output capacitance improves the performance of the device; the actual capacitance should be
optimized for the particular application. All protection circuits including the TPS2549 device have the potential for
input voltage droop, overshoot, and output-voltage undershoot.
For all applications, TI recommends a 0.1-µF or greater ceramic bypass capacitor between IN and GND, placed
as close as possible to the device for the local noise decoupling.
The TPS2549 device is used for 5-V power rail protection when a hot-short occurs on the output or when
plugging in a capacitive load. Due to the limited response time of the upstream power supply, a large load
transient can deplete the charge on the output capacitor of the power supply, causing a voltage droop. If the
power supply is shared with other loads, ensure that voltage droop from current surges of the other loads do not
force the TPS2549 device into UVLO. Increasing the upstream power supply output capacitor can reduce this
droop. Shortening the connection impedance (resistance and inductance) between the TPS2549 device and the
upstream power supply can also help reduce the voltage droop and overshoot on the TPS2549 input power bus.
Input voltage overshoots can be caused by either of two effects. The first cause is an abrupt application of input
voltage in conjunction with input power-bus inductance and input capacitance when the IN terminal is in the highimpedance state (before turnon). Theoretically, the peak voltage is 2 times the applied voltage. The second
cause is due to the abrupt reduction of output short-circuit current when the TPS2549 device turns off and
energy stored in the input inductance drives the input voltage high. Applications with large input inductance (for
example, connecting the evaluation board to the bench power supply through long cables) may require large
input capacitance to prevent the voltage overshoot from exceeding the absolute maximum voltage of the device.
For output capacitance, consider the following three application situations.
The first, output voltage undershoot is caused by the inductance of the output power bus just after a short has
occurred and the TPS2549 has abruptly reduced OUT current. Energy stored in the inductance will drive the
OUT voltage down and potentially negative as it discharges. Applications with large output inductance (such as
from a cable) benefit from use of a high-value output capacitor to control the voltage undershoot. Second, for
USB-port application, because the OUT pin is exposed to the air, the application must withstand ESD stress
without damage. Because there is no internal IEC ESD cell as on DP_IN and DM_IN, using a low-ESR
capacitance can make this pin robust. Third, when plugging in apacitive load such as the input capacitor of any
portable device, having a large output capacitance can help reduce the peak current and up-stream power
supply output voltage droop. So for TPS2549 output capacitance, recommended practice is typically adding two
47-µF ceramic capacitors.
9.2.2.2 Cable Compensation Calculation
Based on the known total resistance, Table 4 shows the calculation.
30
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: TPS2549
TPS2549
www.ti.com
SLUSCP2 – SEPTEMBER 2016
Table 4. Cable Compensation Calculation
CALCULATION EQUATION (1)
CALCULATED VALUE
V(DC) (V) without load
R(G) (kΩ)
6.8
R(total) (Ω)
0.42
G(CS) (mA/A)
R(FA) (kΩ)
5.6
R(FB) = [V(DC) / (V(FB) / R(G))] –
R(G) – R(FA)
32.93
V(CS) (V) (2)
VCS = (V(FB) / R(G)) × (R(G) +
R(FB))
4.39
Maximum IOS (A) at 20 kΩ
33
2.84
V(DC,max) = 5 + I(OS,max) ×
G(CS,max) × R(FA)
6.25
C(OUT) (µF)
(1)
(2)
(3)
(4)
5.6
0.75
R(FB) (kΩ)
C(COMP) (nF) (4)
6.8
0.075
R(FA) = R(total) / G(CS)
V(FB) (V)
V(DC,max) output (V) (3)
ASSEMBLY VALUE
5
2 × 47
C(COMP) ≥ 3 × G(CS) × C(OUT)
≥21.15
22
See Figure 38 and Design Procedure .
Ensure that VCS exceeds 2.5 V.
Ensure that the maximum dc-dc output voltage is lower than 6.5 V when considering I(OS,max) and G(CS,max).
CCOMP impacts load-transient performance, so the output performance should always be verified in the end application circuit.
9.2.2.3 Power Dissipation and Junction Temperature
The low on-resistance of the N-channel MOSFET allows small surface-mount packages to pass large currents. It
is good design practice to estimate power dissipation and junction temperature. The following analysis gives an
approximation for calculating junction temperature based on the power dissipation in the package. However, it is
important to note that thermal analysis is strongly dependent on additional system-level factors. Such factors
include air flow, board layout, copper thickness and surface area, and proximity to other devices dissipating
power. Good thermal design practice must include all system-level factors in addition to individual component
analysis. Begin by determining the rDS(on) of the N-channel MOSFET relative to the input voltage and operating
temperature. As an initial estimate, use the highest operating ambient temperature of interest and read rDS(on)
from the typical characteristics graph. Using this value, the power dissipation can be calculated by:
PD = r DS(on) ´ I OUT 2
(6)
where:
PD = Total power dissipation (W)
rDS(on) = Power-switch on-resistance (Ω)
IOUT = Maximum current-limit threshold (A)
This step calculates the total power dissipation of the N-channel MOSFET.
Finally, calculate the junction temperature:
TJ = PD ´ R qJA + TA
(7)
where:
TA = Ambient temperature (°C)
RθJA = Thermal resistance (°C/W)
PD = Total power dissipation (W)
Compare the calculated junction temperature with the initial estimate. If they are not within a few degrees, repeat
the calculation using the refined rDS(on) from the previous calculation as the new estimate. Two or three iterations
are generally sufficient to achieve the desired result. The final junction temperature is highly dependent on
thermal resistance RθJA, and thermal resistance is highly dependent on the individual package and board layout.
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: TPS2549
31
TPS2549
SLUSCP2 – SEPTEMBER 2016
www.ti.com
9.2.3 Application Curves
6.2
VBUS
V(DC)
6
Voltage (V)
5.8
5.6
5.4
V(DC) at 5-V Offset
100 mV/div
5.2
I(OUT)
200 mA/div
5
4.8
0
0.5
1
1.5
I(LOAD) (A)
2
2.5
D018
Figure 50. V(DC) and VBUS vs I(LOAD) Output
t = 20 ms/div
Figure 51. Plugging In a Portable Device, V(DC)
VBUS at 5-V Offset
10 mV/div
V(DC) at 5-V Offset
100 mV/div
I(OUT)
200 mA/div
I(OUT)
200 mA/div
t = 20 ms/div
t = 20 ms/div
Figure 52. Unplugging a Portable Device, V(DC)
Figure 53. Plugging In Portable Device, VBUS
V(DC) at 5-V Offset
200 mV/div
I(OUT)
200 mA/div
VBUS at 5-V Offset
100 mV/div
I(OUT)
1 A/div
t = 20 ms/div
t = 200 µs/div
Figure 54. Unplugging Portable Device, VBUS
32
Figure 55. 0.5-A ↔ 2.4-A Load Transient With 100-mA/µs
Slew Rate, V(DC)
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: TPS2549
TPS2549
www.ti.com
SLUSCP2 – SEPTEMBER 2016
V(DC)
1 V/div
VBUS at 5-V Offset
200 mV/div
I(OUT)
1 A/div
I(OUT)
2 A/div
t = 200 µs/div
t = 200 µs/div
Figure 56. 0.5-A ↔ 2.4-A Load Transient With 100-mA/µs
Slew Rate, VBUS
Figure 57. VBUS Shorted to GND, V(DC)
10 Power Supply Recommendations
The TPS2549 device is designed for a supply-voltage range of 4.5 V ≤ VIN ≤ 6.5 V. If the input supply is located
more than a few inches from the device, an input ceramic bypass capacitor higher than 0.1 μF is recommended.
The power supply should be rated higher than the TPS2549 current-limit setting to avoid voltage droops during
overcurrent and short-circuit conditions.
11 Layout
11.1 Layout Guidelines
•
•
•
•
•
For the trace routing of DP_IN, DM_IN, DP_OUT, and DM_OUT: Route these traces as micro-strips with
nominal differential impedance of 90 Ω. Minimize the use of vias in the high-speed data lines. Keep the
reference GND plane devoid from cuts or splits above the differential pairs to prevent impedance
discontinuities. For more information, see the High Speed USB Platform Design Guideline from Intel.
The trace routing from the upstream regulator to the TPS2549 IN pin should as short as possible to reduce
the voltage drop and parasitic inductance.
The traces routing from the RILIM_HI and RILIM_LO resistors to the device should be as short as possible to
reduce parasitic effects on the current-limit accuracy.
The thermal pad should be directly connected to the PCB ground plane using a wide and short copper trace.
The trace routing from the CS pin to the feedback divider of the upstream regulator should not be routed near
any noise sources that can capacitively couple to the feedback divider.
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: TPS2549
33
TPS2549
SLUSCP2 – SEPTEMBER 2016
www.ti.com
11.2 Layout Example
Top Layer Signal Trace
Top Layer Signal Ground Plane
Bottom Layer Signal Trace
Via to Bottom Layer Signal Ground Plane
16
15
FAULT
GND
ILIM_HI
ILIMI_LO
Via to Bottom Layer Signal
14
13
DM_OUT
2
11
DM_IN
DP_OUT
3
10
DP_IN
4
9
STATUS
CS
5
6
7
8
CTL3
OUT
CTL2
12
CLT1
1
EN
IN
Figure 58. TPS2549 Layout Diagram
34
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: TPS2549
TPS2549
www.ti.com
SLUSCP2 – SEPTEMBER 2016
12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
High Speed USB Platform Design Guidelines, Intel
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: TPS2549
35
TPS2549
SLUSCP2 – SEPTEMBER 2016
www.ti.com
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
36
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: TPS2549
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS2549RTER
ACTIVE
WQFN
RTE
16
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
2549
TPS2549RTET
ACTIVE
WQFN
RTE
16
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
2549
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
工商网监
湘ICP备2023018690号
