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TPS25810A-Q1
SLVSE37 – APRIL 2017
TPS25810A-Q1 USB Type-C DFP Controller and Power Switch With Digital Cable
Compensation
1 Features
•
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1
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•
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Qualified for Automotive Applications
AEC-Q100 Qualified With the Following Results:
– Device Temperature Grade T: –40°C to 105°C
Ambient Operating Temperature Range
– Device HBM ESD Classification Level 2
– Device CDM ESD Classification Level C4B
USB Type-C Rev. 1.2 Compliant DFP Controller
Connector Attach or Detach Detection
STD, 1.5-A, or 3-A Capability Advertisement on
CC
Super-Speed Polarity Determination
VBUS Application and Discharge
VCONN Application to Electronically Marked Cable
Audio and Debug Accessory Identification
0.7-µA (typ) IDDQ When Port Is Unattached
Three Input Supply Options
– IN1: USB Charging Supply
– IN2: VCONN Supply
– AUX: Device Power Supply
Power Wake Supports Low Power in System
Hibernate (S4) and OFF (S5) Power States
34-mΩ (typ) High-Side MOSFET
Fixed 3.4-A ILIM (±7.1%)
Digital Cable Compensation, IOUT ≥ 1.95 A
Package: 20-Pin WQFN (3 mm × 4 mm) (1)
2 Applications
•
•
Automotive Infotainment Systems
Automotive Back-seat USB Charging
3 Description
The TPS25810A-Q1 device is a USB Type-C
downstream-facing port (DFP) controller with an
integrated 3-A rated USB power switch. The device
monitors the Type-C configuration channel (CC) lines
to determine when a USB device is attached. If an
upstream-facing port (UFP) device is attached, it
applies power to VBUS and communicate the
selectable VBUS current-sourcing capability to the
UFP via the pass-through CC line. If the UFP is
attached using an electronically marked cable, it also
applies VCONN power to the cable CC pin. The
TPS25810A-Q1 can identify and report when Type-C
audio or debug accessories are attached.
Device Information(1)
PART NUMBER
PACKAGE
TPS25810A-Q1
WQFN (20)
BODY SIZE (NOM)
3.00 mm x 4.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
(1)
CC pins are IEC-61000-4-2 rated
Simplified Schematic
6 ´ 100 kW
(optional)
4.5 V– 6.5 V
CC Power
4.5 V– 5.5 V
Auxiliary Power
2.9 V– 5.5 V
IN1
OUT
IN2
FAULT
AUX
CS
120 µF
Control Signals
Power-Switch
Status Signals
CC1
EN
CC2
CHG
UFP
CHG_HI
POL
AUDIO
REF
100 kW (1%)
VBUS
REF_RTN
DEBUG
GND
Thermal Pad
USB Type-C
Connector
TPS25810A-Q1
Bus Power
10 µF
Type-C DFP
Status Signals
Copyright © 2017, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS25810A-Q1
SLVSE37 – APRIL 2017
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Description (Continued) ........................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
2
3
4
7.1
7.2
7.3
7.4
7.5
7.6
7.7
4
4
4
5
5
7
9
Absolute Maximum Ratings ......................................
ESD Ratings ............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Switching Characteristics ..........................................
Typical Characteristics ..............................................
8.4 Device Functional Modes........................................ 21
9
Application and Implementation ........................ 23
9.1 Application Information............................................ 23
9.2 Typical Applications ................................................ 23
10 Power Supply Recommendations ..................... 28
11 Layout................................................................... 29
11.1 Layout Guidelines ................................................. 29
11.2 Layout Example .................................................... 30
12 Device and Documentation Support ................. 31
12.1
12.2
12.3
12.4
12.5
12.6
12.7
Detailed Description ............................................ 11
8.1 Overview ................................................................. 11
8.2 Functional Block Diagram ....................................... 13
8.3 Feature Description................................................. 13
Device Support ....................................................
Documentation Support .......................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
31
31
31
31
31
31
31
13 Mechanical, Packaging, and Orderable
Information ........................................................... 32
4 Revision History
DATE
REVISION
NOTE
April 2017
*
Initial release
5 Description (Continued)
The TPS25810A-Q1 device draws less than 0.7 µA (typical) from the AUX pin when no USB load is connected.
Additional system power saving is achievable in the S4 and S5 system power states by using the UFP output to
disable the high-power 5-V supply when no UFP is attached. In this mode, the device is capable of running from
an auxiliary supply (AUX), which can be a lower-voltage supply (3.3 V), typically powering the system
microcontroller in low-power states (S4 and S5).
The TPS25810A-Q1 device integrates a 34-mΩ power switch with a fixed 3.4-A current limit independent of the
Type-C current advertisement level. The FAULT output signals when the switch is in an overcurrent or
overtemperature condition. The CS output is used for implementing digital cable compensation for load currents
greater than 1.95 A. Cable compensation, also known as line drop compensation, is a means of offsetting
voltage droop from the USB power supply to the UFP load.
2
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6 Pin Configuration and Functions
CS
UFP
POL
AUDIO
20
19
18
17
TPS25810A-Q1 RVC Package
20-Pin WQFN With Exposed Thermal Pad
Top View
FAULT
1
16
DEBUG
IN1
2
15
OUT
IN1
3
14
OUT
IN2
4
13
CC2
AUX
5
12
GND
EN
6
11
CC1
Thermal
10
REF
8
9
REF_RTN
CHG
CHG_HI
7
Pad
Not to scale
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
AUDIO
17
O
Open-drain logic output that asserts when a Type-C audio accessory is identified on
the CC lines
AUX
5
I
Auxiliary input supply. Connect to an always-alive system rail to use the power-wake
feature. Short to IN1 and IN2 if only one supply is used.
CC1
11
I/O
Analog input/output that connects to the Type-C receptacle CC1 pin
CC2
13
I/O
Analog input/output that connects to the Type-C receptacle CC2 pin.
CHG
7
I
Charge-logic input to select between standard USB (500 mA for a Type-C receptacle
supporting only USB 2.0, and 900 mA for Type-C receptacle supporting USB 3.1) or a
Type-C current-sourcing ability.
CHG_HI
8
I
High-charge logic input to select between 1.5-A and 3-A Type-C current sourcing
capability. Valid when CHG is set to Type-C current.
CS
20
O
Open-drain output enabling digital cable compensation when load current is greater
than 1.95 A, nominal.
DEBUG
16
O
Open-drain logic output that asserts when a Type-C debug accessory is identified on
the CC lines
EN
6
I
Enable logic input. Turns the device on and off
FAULT
1
O
Fault event indicator. Open-drain logic output that asserts low to indicate a currentlimit or thermal-shutdown event due to overtemperature.
GND
12
—
Power ground
IN1
2, 3
I
VBUS input supply. Internal power switch connects IN1 to OUT.
IN2
4
I
VCONN input supply. Internal power switch connects IN2 to CC1 or CC2. Short to IN1 if
only one supply is used.
OUT
14, 15
O
Power switch output
POL
18
O
Polarity open-drain logic output that signals which Type-C CC pin is connected to the
CC line. This gives the information needed to multiplex the super-speed lines.
Asserted when the CC2 pin is connected to the CC line in the cable.
REF
10
I
Analog input used to generate the internal current reference. Connect a 1% or better,
100-ppm, 100-kΩ resistor between this pin and REF_RTN.
REF_RTN
9
I
Precision signal-reference return. Connect to the REF pin via a 100-kΩ, 1% resistor.
UFP
19
O
Open-drain logic output that asserts when a Type-C UFP is identified on the CC lines.
Thermal
pad
—
—
Thermal pad on the bottom of the package. The thermal pad is internally connected to
GND and is used to heat-sink the device to the circuit board. Connect the thermal pad
to the GND plane.
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7 Specifications
7.1 Absolute Maximum Ratings
over operating ambient temperature range, voltages are with respect to GND (unless otherwise noted)
MIN
MAX
UNIT
–0.3
7
V
REF_RTN
Internally
connected
to GND
V
CC1, CC2, OUT, REF
Internally
limited
A
5
A
AUDIO, AUX, CC1, CC2, CHG, CHG_HI, CS, DEBUG, EN,
FAULT, IN1, IN2, OUT, POL, REF, UFP,
Pin voltage, V
Pin positive source current, ISRC
(1)
OUT (while applying VBUS)
CC1, CC2 (while applying VCONN)
Pin positive sink current, ISNK
AUDIO, CS, DEBUG, FAULT, POL, UFP
1
A
Internally
limited
mA
Operating junction temperature, TJ
–40
180
°C
Storage temperature range, Tstg
–65
150
°C
(1)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 ESD Ratings
VALUE
Human-body model (HBM), per per AEC Q100-002 (2)
V(ESD) (1)
(1)
(2)
(3)
Electrostatic
discharge
UNIT
±2 000
Charged-device model (CDM), per per AEC Q100-011
±500
V
61000-4-2 contact discharge, CC1 and CC2 (3) IEC
±8 000
IEC 61000-4-2 air discharge, CC1 and CC2 (3)
±15 000
Electrostatic discharge (ESD) to measure device sensitivity and immunity to damage caused by assembly line electrostatic discharges
into the device.
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
Surges per IEC61000-402, 1999 applied between CC1, CC2 and output ground of the TPS25810EVM-745.
7.3 Recommended Operating Conditions
Voltages are with respect to GND (unless otherwise noted)
MIN
VIN
Supply voltage
NOM
MAX
IN1
4.5
6.5
IN2
4.5
5.5
AUX
2.9
5.5
5.5
VI
Input voltage
CHG, CHG_HI, EN
0
VIH
High-level input voltage
CHG, CHG_HI, EN
1.17
VIL
Low-level voltage
CHG, CHG_HI, EN
VPU
Pullup voltage
Used on AUDIO, CS, DEBUG, FAULT, POL, UFP,
ISRC
Positive source current
ISNK
Positive sink current (10 ms moving
average)
UNIT
V
V
V
0
OUT
0.63
V
5.5
V
3
A
250
mA
AUDIO, CS, DEBUG, FAULT, POL, UFP
10
mA
ISNK_PULSE Positive repetitive pulse sink current AUDIO, CS, DEBUG, FAULT, POL, UFP
Internally
limited
mA
102
kΩ
125
°C
RREF
Reference resistor
TJ
Operating junction temperature
4
CC1 or CC2 when supplying VCONN
98
–40
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7.4 Thermal Information
TPS25810A-Q1
THERMAL METRIC (1)
RVC (WQFN)
UNIT
20 PINS
RθJA
Junction-to-ambient thermal resistance
39.3
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
43.4
°C/W
RθJB
Junction-to-board thermal resistance
13
°C/W
ψJT
Junction-to-top characterization parameter
0.7
°C/W
ψJB
Junction-to-board characterization parameter
13
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
4.2
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
7.5 Electrical Characteristics
–40°C ≤ TJ ≤ 125°C, 4.5 V ≤ VIN1 ≤ 6.5 V, 4.5 V ≤ VIN2 ≤ 5.5 V, 2.9 V ≤ VAUX ≤ 5.5 V; VEN = VCHG = VCHG_HI = VAUX, RREF =
100 kΩ. Typical values are at 25°C. All voltages are with respect to GND. IOUT and IOS defined as positive out of the indicated
pin (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
TJ = 25°C, IOUT = 3 A
34
37
–40°C ≤ TJ ≤ 85°C, IOUT = 3 A
34
46
–40°C ≤ TJ ≤ 125°C, IOUT = 3 A
34
55
VOUT = 6.5 V, VIN1 = VEN = 0 V,
OUT to IN reverse leakage current –40°C ≤ TJ ≤ 85°C,
IREV is current out of IN1 pin
0
3
3.4
3.64
UNIT
OUT – POWER SWITCH
rDS(on)
IREV
On-resistance (1)
mΩ
µA
OUT – CURRENT LIMIT
IOS
Short-circuit current limit
3.16
(1)
RREF = 10 Ω
7
A
OUT – DISCHARGE
Discharge resistance
VOUT = 4 V, UFP signature removed from
CC lines, time < tw_DCHG
400
500
600
Ω
Bleed discharge resistance
VOUT = 4 V, No UFP signature on CC lines,
time > tw_DCHG
100
150
250
kΩ
0.78
0.8
0.82
V
15.3
µA
350
mV
1
µA
350
mV
1
µA
2.1
A
REF
VO
Output voltage
IOS
Short circuit current
RREF = 10 Ω
VOL
Output low voltage
IFAULT = 1 mA
IOFF
Off-state leakage
VFAULT = 5.5 V
VOL
Output low voltage
ICS = 1 mA
IOFF
Off-state leakage
VCS = 5.5 V
ITH
OUT sourcing, rising threshold
current for load detect
9.5
FAULT
CS
1.8
Hysteresis (2)
(1)
(2)
1.95
125
mA
Pulse-testing techniques maintain junction temperature close to ambient temperature; thermal effects must be taken into account
separately.
These parameters are provided for reference only and do not constitute part of TI’s published specifications for purposes of TI’s product
warranty.
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Electrical Characteristics (continued)
–40°C ≤ TJ ≤ 125°C, 4.5 V ≤ VIN1 ≤ 6.5 V, 4.5 V ≤ VIN2 ≤ 5.5 V, 2.9 V ≤ VAUX ≤ 5.5 V; VEN = VCHG = VCHG_HI = VAUX, RREF =
100 kΩ. Typical values are at 25°C. All voltages are with respect to GND. IOUT and IOS defined as positive out of the indicated
pin (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
TJ = 25°C, IOUT = 250 mA
365
420
–40°C ≤ TJ ≤ 85°C, IOUT = 250 mA
365
530
–40°C ≤ TJ ≤ 125°C, IOUT = 250 mA
365
600
355
410
UNIT
CC1, CC2 – VCONN POWER SWITCH
rDS(on)
On-resistance
mΩ
CC1, CC2 – VCONN POWER SWITCH – CURRENT LIMIT
300
Short-circuit current limit (1)
IOS
RREF = 10 Ω
800
mA
CC1, CC2 – CONNECT MANAGEMENT – DANGLING ELECTRONICALLY MARKED CABLE MODE
ISRC
Sourcing current on the passthrough CC Line
0 V ≤ VCCx ≤ 1.5 V
64
80
96
Sourcing current on the Ra CC
line
0 V ≤ VCCx ≤ 1.5 V
64
80
96
64
80
96
µA
CC1, CC2 – CONNECT MANAGEMENT – ACCESSORY MODE
CCx sourcing current
(CC2 – audio, CC1-debug)
ISRC
CCx sourcing current
(CC1 – audio, CC2-debug)
0 V ≤ VCCx ≤ 1.5 V
µA
(2)
0 V ≤ VCCx ≤ 1.5 V
0
CC1, CC2 – CONNECT MANAGEMENT – UFP MODE
Sourcing current with either IN1 or 0 V ≤ VCCx ≤ 1.5 V
IN2 in UVLO
VIN1 < VTH_UVLO_IN1 or VIN2 < VTH_UVLO_IN2
ISRC
64
80
96
75
80
85
VCHG = VAUX and VCHG_HI = 0 V
0 V ≤ VCCx ≤ 1.5 V
170
180
190
VCHG = VAUX and VCHG_HI = VAUX
0 V ≤ VCCx ≤ 2.45 V
312
330
348
VCHG = 0 V and VCHG_HI = 0 V
0 V ≤ VCCx ≤ 1.5 V
ISRC
Sourcing current
µA
µA
UFP, POL, AUDIO, DEBUG
VOL
Output low voltage
ISNK_PIN = 1 mA
IOFF
Off-state leakage
VPIN = 5.5 V
250
mV
1
µA
1.15
V
EN, CHG, CHG_HI – LOGIC INPUTS
VTH
Rising threshold voltage
VTH
Falling threshold voltage
0.925
0.65
Hysteresis (2)
IIN
Input current
0.875
V
50
VEN = 0 V or 6.5 V
–0.5
mV
0.5
µA
OVERTEMPERATURE SHUTDOWN
TTH_OTSD2
Rising threshold temperature for
device shutdown
155
Hysteresis (2)
TTH_OTSD1
°C
20
Rising threshold temperature for
OUT/ VCONN switch shutdown in
current limit
°C
135
Hysteresis (2)
°C
20
°C
IN1
VTH_UVLO_IN1
Rising threshold voltage for UVLO
3.9
Hysteresis (2)
4.1
4.3
100
V
mV
IIN1(DIS)
Disabled supply current
VEN = 0 V, –40°C ≤ TJ ≤ 85°C
1
µA
IIN1(CC_OPEN)
Enabled supply current with CC
lines open
–40°C ≤ TJ ≤ 85°C
1
µA
6
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Electrical Characteristics (continued)
–40°C ≤ TJ ≤ 125°C, 4.5 V ≤ VIN1 ≤ 6.5 V, 4.5 V ≤ VIN2 ≤ 5.5 V, 2.9 V ≤ VAUX ≤ 5.5 V; VEN = VCHG = VCHG_HI = VAUX, RREF =
100 kΩ. Typical values are at 25°C. All voltages are with respect to GND. IOUT and IOS defined as positive out of the indicated
pin (unless otherwise noted)
PARAMETER
IIN1(Ra)
Enabled supply current with
accessory or dangling
electronically marked cable
signature on CC lines
IIN1(Rd)
Enabled supply current with UFP
attached
TEST CONDITIONS
MIN
TYP
MAX
UNIT
2
VCHG = 0 V, or VCHG = VAUX and VCHG_HI =
0V
75
100
85
110
4.1
4.3
µA
µA
IN2
VTH_UVLO_IN2
Rising threshold voltage for UVLO
Hysteresis
3.9
(2)
V
100
mV
IIN2(DIS)
Disabled supply current
VEN = 0 V, –40°C ≤ TJ ≤ 85°C
1
µA
IIN2(CC_OPEN)
Enabled supply current with CC
lines open
–40°C ≤ TJ ≤ 85°C
1
µA
IIN2(Ra)
Enabled supply current with
accessory or dangling
electronically marked cable
signature on CC lines
2
µA
IIN2(Rd)
Enabled supply current with UFP
signature on CC lines
(Includes IN current that provides
the CC output current to the UFP
Rd resistor)
VCHG = 0 V, 0 V ≤ VCCx ≤ 1.5 V
98
110
VCHG = VIN and VCHG_HI = 0 V, 0 V ≤ VCCx ≤
1.5 V
198
215
0 V ≤ VCCx ≤ 2.45 V
348
373
2.75
2.85
µA
AUX
VTH_UVLO_AUX Rising threshold voltage for UVLO
Hysteresis
2.65
(2)
V
100
IAUX(DIS)
Disabled supply current
VEN = 0 V, –40°C ≤ TJ ≤ 85°C
IAUX(CC_OPEN)
Enabled internal supply current
with CC lines open
–40°C ≤ TJ ≤ 85°C
IAUX(Ra)
Enabled supply current with
accessory or dangling active cable
signature on CC lines
IAUX(Rd_noIN)
Enabled supply current with UFP
termination on CC lines and with
either IN1 or IN2 in UVLO
IAUX(Rd)
Enabled supply current with UFP
termination on CC lines
VIN1 < VTH_UVLO_IN1 or VIN2 < VTH_UVLO_IN2
mV
1
µA
0.7
3
µA
140
185
µA
145
190
µA
55
82
µA
7.6 Switching Characteristics
–40°C ≤ TJ ≤ 125°C, 4.5 V ≤ VIN1 ≤ 6.5 V, 4.5 V ≤ VIN2 ≤ 5.5 V, 2.9 V ≤ VAUX ≤ 5.5 V; VEN = VCHG = VCHG_HI = VAUX, RREF =
100 kΩ. Typical values are at 25°C. All voltages are with respect to GND. IOUT and IOS defined as positive out of the indicated
pin (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VIN1 = 5 V, CL = 1 µF, RL = 100 Ω
(measured from 10% to 90% of final
value)
1.2
1.8
2.5
ms
0.35
0.55
0.75
ms
2.5
3.5
5
ms
2
3
4.5
ms
1.5
4
µs
OUT – POWER SWITCH
tr
Output-voltage rise time
tf
Output-voltage fall time
ton
Output-voltage turnon time
toff
Output-voltage turnoff time
VIN1 = 5 V, CL = 1 µF, RL = 100 Ω
OUT – CURRENT LIMIT
tios
Current-limit response time to short
circuit
VIN1 – VOUT = 1 V, RL = 10 mΩ, see
Figure 1
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Switching Characteristics (continued)
–40°C ≤ TJ ≤ 125°C, 4.5 V ≤ VIN1 ≤ 6.5 V, 4.5 V ≤ VIN2 ≤ 5.5 V, 2.9 V ≤ VAUX ≤ 5.5 V; VEN = VCHG = VCHG_HI = VAUX, RREF =
100 kΩ. Typical values are at 25°C. All voltages are with respect to GND. IOUT and IOS defined as positive out of the indicated
pin (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
5.5
8.2
10.7
ms
FAULT
tDEGA
Asserting deglitch time due to
overcurrent
tDEGA(OC)
Asserting deglitch time due to
overtemperature in current limit (1)
tDEGA(OT)
Deasserting deglitch time
5.5
8.2
10.7
ms
tDEGA
Asserting deglitch time
5.5
8.2
10.7
ms
tDEGD
Deasserting deglitch time
5.5
8.2
10.7
ms
39
65
96
ms
0.15
0.25
0.35
ms
0.18
0.22
0.26
ms
1
1.5
2
ms
0.3
0.4
0.55
ms
1
3
µs
0
ms
CS
OUT – DISCHARGE
VOUT = 1 V, time ISNK_OUT > 1 mA
after UFP signature removed from
CC lines
RDCHG discharge time
CC1, CC2 - VCONN POWER SWITCH
tr
Output-voltage rise time
VIN2 = 5 V, CL = 1 µF, RL = 100 Ω
(measured from 10% to 90% of final
value)
tf
Output-voltage fall time
ton
Output-voltage turnon time
toff
Output-voltage turnoff time
VIN2 = 5 V, CL = 1 µF, RL = 100 Ω
CC1, CC2 – VCONN POWER SWITCH – CURRENT LIMIT
Current-limit response time to short
circuit
tres
VIN2 – VCONN = 1 V, R = 10 mΩ, see
Figure 1
UFP, POL, AUDIO, DEBUG
tDEGR
Asserting deglitch time
100
150
200
ms
tDEGF
Deasserting deglitch time
7.9
12.5
17.7
ms
(1)
These parameters are provided for reference only and do not constitute part of TI’s published specifications for purposes of TI’s product
warranty.
IOS
IOUT
tios
Figure 1. Output Short-Circuit Timing Diagram
8
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7.7 Typical Characteristics
500
RDS(ON) - On Resistance (m:)
RDS(ON) - On Resistance (m:)
50
40
30
20
10
0
-40
-25
-10
5
20 35 50 65 80
TJ - Junction Temperature (oC)
95
400
350
300
250
-40
110 125
-10
5
20 35 50 65 80
TJ - Junction Temperature (oC)
95
110 125
D001
Figure 3. VCONN Current-Limiting Switch On-Resistance vs
Temperature
0.25
4000
3500
ILIM - Limit Current (mA)
0.2
0.15
0.1
3000
VBUS ILIM 3 A
VBUS ILIM 1.5 A
VCONN_ILIM
2500
2000
1500
1000
0.05
500
0
-40
-25
-10
Device disabled
5
20 35 50 65 80
TJ - Junction Temperature (oC)
95
0
-40
110 125
-10
5
20 35 50 65 80
TJ - Junction Temperature (oC)
95
110 125
D001
(VOUT – VIN) = 6.5
V
Figure 5. ILIM for VBUS and VCONN vs Temperature
350
CS Threshold, Rising
CS Threshold, Falling
300
Sourcing Current (PA)
2010
1990
1970
1950
1930
1910
1890
1870
1850
1830
1810
1790
1770
1750
-40
-25
D001
Figure 4. OUT Reverse Leakage Current vs Temperature
CS Threshold (mA)
-25
D001
Figure 2. VBUS Current-Limiting Switch On-Resistance vs
Temperature
IREV - Reverse Leakage Current (µA)
450
250
UFP 3 A
UFP 1.5 A
UFP 0.5 A/0.9 A
200
150
100
-25
-10
5
20 35 50 65 80
Junction Temperature (qC)
95
110 125
50
-40
-25
D005
Figure 6. CS Threshold vs Temperature
-10
5
20 35 50 65 80
TJ - Junction Temperature (oC)
95
110 125
D001
Figure 7. CC Sourcing Current to UFP vs Temperature
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Typical Characteristics (continued)
95
400
IN1 UFP 3 A
IN1 UFP 0.5 A/1.5 A
IIN_ON - Enabled IN Supply Current (PA)
IIN_ON - Enabled IN Supply Current (PA)
100
90
85
80
75
70
-40
-25
-10
5
20 35 50 65 80
TJ - Junction Temperature (oC)
95
110 125
350
300
IN2 UFP 3 A
IN2 UFP 1.5 A
IN2 UFP 0.5 A
250
200
150
100
50
-40
-25
-10
D001
Figure 8. IN1 Current With UFP vs Temperature
5
20 35 50 65 80
TJ - Junction Temperature (oC)
95
110 125
D001
Figure 9. IN2 Current With UFP vs Temperature
IIN_ON - Enabled IN Supply Current (µA)
70
65
60
55
50
45
40
-40
-25
-10
5
20 35 50 65 80
TJ - Junction Temperature (oC)
95
110 125
D001
VAUX = 5 V
Figure 10. AUX Current With UFP vs Temperature
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8 Detailed Description
8.1 Overview
The TPS25810A-Q1 device is a highly integrated USB Type-C™ downstream-facing port (DFP) controller,
developed with a built-in power switch for the new USB Type-C connector and cable. The device provides all of
the functionality needed to support a USB Type-C DFP in a system where USB power delivery (PD) source
capabilities (for example, VBUS > 5 V) are not implemented. It is designed to be compliant with the Type‑C
specification, revision 1.2.
8.1.1 USB Type-C Basic
For a detailed description of the Type-C specification, see the USB-IF Web site to download the latest released
version. Some of the basic concepts of the Type-C specification that pertain to understanding the operation of
the TPS25810A-Q1 (DFP device) are described as follows.
USB Type-C removes the need for different plug and receptacle types for host and device functionality. The
Type-C receptacle replaces both Type-A and Type-B receptacles because the Type-C cable is pluggable in
either direction between host and device. A host-to-device logical relationship is maintained via the configuration
channel (CC). Optionally, hosts and devices can be either providers or consumers of power when USB PD
communication is used to swap roles.
All
•
•
•
USB Type-C ports operate in one of the following three data modes:
Host mode: the port can only be host (provider of power).
Device mode: the port can only be device (consumer of power).
Dual-role mode: the port can be either host or device.
Port types:
• DFP (downstream facing port): Host
• UFP (upstream facing port): Device
• DRP (dual-role port): Host or device
Valid DFP-to-UFP connections:
• Table 1 describes valid DFP-to-UFP connections.
• Host-to-host and device-to-device have no functions.
Table 1. DFP-to-UFP Connections
HOST-MODE PORT
(1)
DEVICE-MODE
PORT
DUAL-ROLE PORT
Works
Host-mode port
No function
Works
Device-mode port
Works
No function
Works
Dual-role port
Works
Works
Works (1)
This may be automatic or manually driven.
8.1.2 Configuration Channel
The function of the configuration channel (CC) is to detect connections and configure the interface across the
USB Type-C cables and connectors.
Functionally, the configuration channel serves the following purposes:
• Detect connection to the USB ports
• Resolve cable orientation and twist connections to establish USB data-bus routing
• Establish DFP and UFP roles between two connected ports
• Discover and configure power: USB Type-C current modes or USB power delivery
• Discover and configure optional alternate and accessory modes
• Enhance flexibility and ease of use
Typical flow of DFP-to-UFP configuration is shown in Figure 11:
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Detect Valid
Connection
Establish USB
Power Method
USB Device
Enumeration
Figure 11. Flow of DFP-to-UFP Configuration
8.1.3 Detecting a Connection
DFPs and DRPs fulfill the role of detecting a valid connection over USB Type-C. Figure 12 shows a DFP-to-UFP
connection made with Type-C cable. As shown in Figure 12, the detection concept is based on being able to
detect terminations in the product that has been attached. A pullup and pulldown termination model is used. A
pullup termination can be replaced by a current source.
• In the DFP-to-UFP connection, the DFP monitors both CC pins for a voltage lower than the unterminated
voltage.
• A UFP advertises Rd on both of its CC pins (CC1 and CC2).
• A powered cable advertises Ra on only one of the CC pins of the plug. Ra is used to inform the source to
apply VCONN.
• An analog audio device advertises Ra on both CC pins of the plug, which identifies it as an analog audio
device. VCONN is not applied on either CC pin in this case.
UFP monitors for
connection
DFP monitors for
connection
Cable
CC
Rp
Rp
Ra
Rds
Ra
DFP monitors for
connection
Rds
UFP monitors for
connection
Figure 12. DFP-to-UFP Connection
12
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8.2 Functional Block Diagram
Current Sense
OUT
IN1
UVLO
Current Sense
CC1
IN2
UVLO
Current Sense
CC2
AUX
CC
Monitor
CS
UVLO
Charge
Pump
Current
Limit
FAULT
Gate
Control
OTSD
Thermal
Sense
POL
UFP
EN
Control
Logic
CHG
DEBUG
CHG_HI
REF
AUDIO
REF_RTN
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8.3 Feature Description
TheTPS25810A-Q1 device is a DFP Type-C port controller with integrated power switches for VCONN and VBUS. It
does not support BC 1.2 charging modes inherently, because it does not interact with USB D+ and D– data lines.
The TPS25810A-Q1 device can be used in conjunction with a BC 1.2 controller like the TPS2514A-Q1 device to
support BC1.2 and Type-C charging modes in a single Type-C DFP port. See the TPS25810 EVM User's Guide
and Application and Implementation section of this data sheet for more details. The TPS25810A-Q1 device can
be used in a USB 2.0 only or in a USB 3.1 port implementation. When used in a USB 3.1 port, the POL pin can
control an external super-speed MUX to handle the Type-C flippable feature.
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Feature Description (continued)
8.3.1 Configuration Channel Pins CC1 and CC2
Each device has two pins, CC1 and CC2, that serve to detect an attachment to the port and to resolve cable
orientation. These pins are also used to establish the current broadcast to a valid UFP, configure VCONN, and
detect attachment of a debug or audio-adapter accessory.
Table 2 lists the response to various attachments to its port.
Table 2. TPS25810A-Q1 Response
TPS25810A-Q1 RESPONSE (1)
TPS25810A-Q1 TYPE-C
PORT
OUT
VCONN
on CC1 or
CC2
POL
OPEN
OPEN
NO
OPEN
IN1
NO
OPEN
Rd
IN1
OPEN
Ra
Ra
CC1
CC2
OPEN
Rd
UFP
AUDIO
DEBUG
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
LOW
Hi-Z
Hi-Z
NO
LOW
LOW
Hi-Z
Hi-Z
OPEN
NO
Hi-Z
Hi-Z
Hi-Z
Hi-Z
OPEN
OPEN
NO
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Powered cable, UFP
connected
Rd
Ra
IN1
CC2
Hi-Z
LOW
Hi-Z
Hi-Z
Ra
Rd
IN1
CC1
LOW
LOW
Hi-Z
Hi-Z
Debug accessory connected
Rd
Rd
OPEN
NO
Hi-Z
Hi-Z
Hi-Z
LOW
Audio-adapter accessory
connected
Ra
Ra
OPEN
NO
Hi-Z
Hi-Z
LOW
Hi-Z
Nothing attached
UFP connected
Powered cable, no UFP
connected
(1)
POL, UFP, AUDIO, and DEBUG are open-drain outputs; pull high with 100 kΩ to AUX when used. Tie to GND or leave open when not
used.
8.3.2 Current Capability Advertisement and Overload Protection
The TPS25810A-Q1 device supports all three Type-C current advertisements as defined by the USB Type-C
standard. Current broadcast to a connected UFP is controlled by the CHG and CHG_HI pins. For each broadcast
level, the device protects itself from a UFP that draws current in excess of the USB Type-C current
advertisement of that port by setting the current limit as shown in Table 3.
Table 3. USB Type-C Current Advertisement
CHG
CHG_HI
CC CAPABILITY
BROADCAST
CURRENT LIMIT (TYP)
CS THRESHOLD (TYP)
0
0
STD
3.4 A
1.95 A
0
1
STD
3.4 A
1.95 A
1
0
1.5 A
3.4 A
1.95 A
1
1
3A
3.4 A
1.95 A
Under OUT overload conditions, an internal OUT current-limit regulator limits the output current to the selected
ILIM based on CHG and CHG_HI selection. In applications where VCONN is supplied via CC1 or CC2, separate
fixed current-limit regulators protect these pins from overload at the level indicated in the Electrical
Characteristics table. When an overload condition is present, the device maintains a constant output current, with
the output voltage determined by (IOS × RLOAD). Two possible overload conditions can occur. The first overload
condition occurs when either: 1) input voltage is first applied, enable is true, and a short circuit is present (load
which draws IOUT > IOS), or 2) input voltage is present and the TPS25810A-Q1 device is enabled into a short
circuit. The output voltage is held near zero potential with respect to ground and the TPS25810A-Q1 device
ramps the output current to IOS. Both limit the current to IOS until the overload condition is removed or the device
begins to thermal cycle. This is demonstrated in Figure 23 where the device was enabled into a short, and
subsequently cycles current off and on as the thermal protection engages.
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The second condition is when an overload occurs while the device is enabled and fully turned on. The device
responds to the overload condition within time tios (see Figure 1) when the specified overload (per Electrical
Characteristics) is applied. The response speed and shape vary with the overload level, input circuit, and rate of
application. The current-limit response can be either simply settling to IOS or turnoff and controlled return to IOS.
Similar to the previous case, the TPS25810A-Q1 device limits the current to IOS until the overload condition is
removed or the device begins to thermal cycle.
The TPS25810A-Q1 device thermal cycles if an overload condition is present long enough to activate thermal
limiting in any of the above cases. This is due to the relatively large power dissipation [(VIN – VOUT) × IOS] driving
the junction temperature up. The device turns off when the junction temperature exceeds 135°C (minimum) while
in current limit. The device remains off until the junction temperature cools 20°C and then restarts. The currentlimit profile is shown in Figure 13.
VOUT
Slope = -r DS( on )
0V
0A
IOUT
IOS
Figure 13. Current-Limit Profile
8.3.3 Undervoltage Lockout (UVLO)
The undervoltage lockout (UVLO) circuit disables the power switch until the input voltage reaches the UVLO
turnon threshold. Built-in hysteresis prevents unwanted on-off cycling due to input voltage droop during turnon.
8.3.3.1 Device Power Pins (IN1, IN2, AUX, OUT, and GND)
The device has multiple input power pins: IN1, IN2 and AUX. IN1 is connected to OUT by the internal power FET
and serves as the supply for the Type-C charging current. IN2 is the supply for VCONN and ties directly between
the VCONN power switch on its input and CC1 or CC2 on its output. AUX, the auxiliary input supply, provides
power to the device. See the Functional Block Diagram.
In the simplest implementation where multiple supplies are not available, IN1, IN2, and AUX can be tied together.
However, in mobile systems (battery powered) where system power savings is paramount, IN1 and IN2 can be
powered by the high-power dc-dc supply (>3-A capability), and AUX can be connected to the low-power supply
that typically powers the system microcontroller when the system is in the hibernate or sleep power state. Unlike
IN1 and IN2, AUX can operate directly from a 3.3-V supply commonly used to power the microcontroller when
the system is put in low-power mode. Ceramic bypass capacitors close to the device from the INx and AUX pins
to GND are recommended to alleviate bus transients.
The recommended operating voltage range for IN1 and IN2 is 4.5 V to 5.5 V, whereas AUX can be operated
from 2.9 V to 5.5 V. However IN1, the high-power supply, can operate up to 6.5 V. This higher input voltage
affords a larger IR loss budget in systems where a long cable harness is used, and results in high IR losses with
3-A charging current. Increasing IN1 beyond 5.5 V enables longer cable and board trace lengths between the
device and the Type-C receptacle while meeting the USB specification for VBUS ≥ 4.75 V at the connector.
Figure 14 illustrates the point. In this example IN1 is at 5 V, which restricts the IR loss budget from the dc-dc
converter to the connector to 250 mV.
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Total IR Drop Budget = 250 mV
Trace IR Drop Budget at 3 A
= 250 – 165 = 85 mV
V_Trace1
V_Trace2
V_TPS25810A-Q1
Type C
V_DC-DC = 5 V
OUT
IN1
5-V DC-DC
V_Connector
= 4.75 V (MIN)
MaxRds_On = 55 mΩ
165-mV Drop at 3 A
82.5-mV Drop at 1.5 A
Figure 14. Total IR Loss Budget
8.3.3.2 FAULT Response
The FAULT pin is an open-drain output asserted low when the device OUT current exceeds its programmed
value and the overtemperature threshold (TTH_OTSD1) is crossed. See the Electrical Characteristics for overcurrent
and overtemperature values. The FAULT signal remains asserted until the fault condition is removed and the
device resumes normal operation. An internal deglitch circuit eliminates false overcurrent-fault reporting.
Connect FAULT with a pullup resistor to AUX. FAULT can be left open or tied to GND when not used.
8.3.3.3 Thermal Shutdown
The device has two internal overtemperature shutdown thresholds, TTH_OTSD1 and TTH_OTSD2, to protect the
internal FET from damage and assist with overall safety of the system. TTH_OTSD2 is greater than TTH_OTSD1.
FAULT is asserted low to signal a fault condition when the device temperature exceeds TTH_OTSD1 and the
current-limit switch is disabled. However, when TTH_OTSD2 is exceeded, all open-drain outputs are left open and
the device is disabled such that minimum power is dissipated. The device attempts to power up when the die
temperature decreases by 20°C.
8.3.3.4 REF
A 100-kΩ (1% or better recommended) resistor is connected from this pin to REF_RTN. The REF pin sets the
reference current required to bias the internal circuitry of the device. The overload current-limit tolerance and CC
currents depend upon the accuracy of this resistor. Using a ±1% or better low-temperature-coefficient resistor
yields the best current-limit accuracy and overall device performance.
8.3.3.5 Audio Accessory Detection
The USB Type-C specification defines an audio-adapter decode state which allows implementation of an analog
USB Type-C to 3.5-mm headset adapter. An audio accessory device is detected when both CC1 and CC2 pins
detect VRa voltage (when pulled to ground by an Ra resistor). The open-drain AUDIO pin is asserted low to
indicate the detection of such a device.
Table 4. Audio Accessory Detection
16
CC1
CC2
AUDIO
STATE
Ra
Ra
Asserted (pulled low)
Audio-adapter accessory connected
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Platforms supporting the audio accessory function can be triggered by the AUDIO pin to enable accessory mode
circuits to support the audio function. When the Ra pulldown is removed from the CC2 pin, AUDIO is deasserted
or pulled high. The TPS25810A-Q1 device monitors the CC2 pin for audio device detach. When this function is
not needed (for example in a data-less port), AUDIO can be tied to GND or left open.
8.3.3.6 Debug Accessory Detection
The Type-C spec supports an optional debug-accessory mode, used for debug only and not to be used for
communicating with commercial products. When the TPS25810A-Q1 device detects VRd voltage on both CC1
and CC2 pins (when pulled to ground by an Rd resistor), it asserts DEBUG low. With DEBUG asserted, the
system can enter debug mode for factory testing or a similar functional mode. DEBUG deasserts or pulls high
when Rd is removed from CC1. The CC1 pin is monitored for debug-accessory detach.
If the debug-accessory mode is not used, tie DEBUG to GND or leave it open.
Table 5. Debug Accessory Detection
CC1
CC2
POL
STATE
Rd
Rd
Asserted (pulled low)
Debug accessory connected
8.3.3.7 Plug Polarity Detection
Reversible Type-C plug orientation is reported by the POL pin when a UFP is connected. However, when no
UFP is attached POL remains deasserted, irrespective of cable plug orientation. Table 6 describes the POL state
based on which of the device CC pins detects VRd from an attached UFP pulldown.
Table 6. Plug Polarity Detection
CC1
CC2
POL
STATE
Rd
Open
Hi-Z
UFP connected
Open
Rd
Asserted (pulled low)
UFP connected with reverse plug orientation
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Figure 15 shows an example implementation which uses the POL terminal to control the SEL terminal on the
HD3SS3212 device. The HD3SS3212 device provides switching on the differential channels between Port B and
Port C to Port A, depending on cable orientation. For details on the HD3SS3212 device, see HD3SS3212x TwoChannel Differential 2:1/1:2 USB3.1 Mux/Demux.
3.3 V
HD3SS3212
USB Host
VCC
USB C
B0+
B0–
SSTXp
A0+
SSTXn
A0–
SSRXp
A1+
Dp
Dm
Dm
0.1 µF
0.1 µF
0.1 µF
C0–
SSTXp2
Dp1
SSTXn2
Dp2
SSTXp1
Dm1
SSTXn1
Dm2
B1+
SSRXp2
B1–
SSRXn2
OEn
C1+
SSRXp1
GND
SEL
C1–
SSRXn1
GND
A1–
SSRXn
Dp
C0+
0.1 µF
Dp
Dm
GND
GND
CC2
VBUS
GND
GND
GND
CC1
3.3 V
TPS25810A-Q1
5V
POL
UFP
IN1
IN1
OUT
OUT
CC1
CC2
5V
IN2
AUX
EN
REF
REF_RTN
GND
Thermal Pad
CHG
CHG HI
_
FAULT
CS
AUDIO
DEBUG
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Figure 15. Example Implementation
8.3.3.8 Device Enable Control
The logic enable pin (EN) controls the power switch and device supply current. The supply current is reduced to
less than 1 μA when a logic low is present on EN. The EN pin provides a convenient way to turn on or turn off
the device while it is powered. The enable input threshold has built-in hysteresis. When this pin is pulled high, the
device is turned on or enabled. When the device is disabled (EN pulled low) the internal FETs tied to IN1 and
IN2 are disconnected, all open-drain outputs are left open (Hi-Z), and the monitor block for CC1 and CC2 is
turned off. The EN terminal should not be left floating.
8.3.3.9 Cable Compensation (CS)
The TPS25810A-Q1 device monitors the current to a UFP, and if the load current exceeds 1.95 A (typ), the CS
pin asserts. This can be useful for implementing a digital droop-compensation scheme by altering the feedback
resistor ratio of the IN1 power source.
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Figure 16 shows a USB charging design using the TPS25810A-Q1 device. The 5-V (typical) nominal output of
the USB power supply, designated 5 VOUT herein, is often a dc-dc converter in automotive applications. VUFP_IN
refers to the voltage across the inside contacts of the USB connector of a UFP device. Official USB
specifications should be consulted for the most up-to-date requirements. For illustration purposes, it is assumed
the minimum and maximum voltages allowed for VUFP_IN are 4 V and 5.25 V, respectively. In general, when
VUFP_IN is 5 V, the UFP draws optimum current and requires the minimum amount of time to recharge its battery.
TPS25810A-Q1
5-V
LDO
CC Power 4.5 V– 5.5 V
Auxiliary Power 2.9 V– 5.5 V
R1
DC-DC
Converter
VBUS
IN1
OUT
IN2
FAULT
AUX
CS
CC1
EN
CC2
CHG
UFP
CHG_HI
POL
IOUT
USB Type-C
Connector
5V
Bus Power 4.5 V– 6.5 V
5 VOUT
VUFP_IN
R4
COUT
R2
Control Signals
FB
R3
REF
Portable UFP Device
5 ´ 100 kW
(optional)
Cable
10 µF
AUDIO
100 kW (1%)
REF_RTN
GND
GND
DEBUG
Thermal Pad
Type-C DFP
Status Signals
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Figure 16. TPS25810A-Q1 Charging System Schematic
In a practical system, there are voltage drops from the dc-dc output, 5 VOUT, to VUFP_IN which include the onresistance of the TPS25810A-Q1 device power switch, USB cabling and connector contact resistances.
Under rated UFP load current, these drops can be several hundred millivolts, decreasing VUFP_IN below the
optimal 5-V level. In addition, as VUFP_IN decreases below 5 V, most modern UFPs decrease their load
current to prevent possible overload conditions and to maintain VUFP_IN above 4 V. Lower-than-optimum load
current increases the time required to recharge the UFP battery. For example, in Figure 16, assuming that
the loss resistance is 113 mΩ (includes 79 mΩ of USB cable resistance and 34 mΩ of power switch
resistance) and 5 VOUT is 5 V, the input voltage of UFP (VUFP_IN) is about 4.66 V at 3 A. The TPS25810A-Q1
device provides the CS pin to report high-charging-current conditions and increase the 5 VOUT voltage as
shown in Figure 17
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Output Voltage (V)
5.25
5.00
4.75
4.50
5 VOUT with compensation
VUFP_IN with compensation
5 VOUT without compensation
VUFP_IN without compensation
1
2
3
Output Current (A)
Figure 17. TPS25810A-Q1 CS Function
Equation 1 through Equation 4 refer to Figure 16
The power supply output voltage is calculated in Equation 1.
(R1 + R 2 + R 3 )´ VFB
5 VOUT =
R3
(1)
5 VOUT and VFB are known. If R3 is given and R1 is fixed, R2 can be calculated. The 5 VOUT voltage change with
compensation is shown in Equation 2 and Equation 3.
(R 2 + R 3 )´ R1 ´ VFB
DV =
R3 ´ R4
(2)
æ 5V
R öR ´V
ΔV = ç OUT - 1 ÷ 1 FB
R3 ø R4
è VFB
(3)
If R1 is less than R3, then Equation 3 can be simplified as Equation 4.
5VOUT ´ R1
DV »
R4
8.3.3.10
(4)
Power Wake
The power-wake feature offers the mobile-systems designer a way to save on system power when no UFP is
attached to the Type-C port. See Figure 18. To enable power wake, the UFP pins from any combination of two
TPS25810A-Q1 devices are tied together (each with its own 100-kΩ pullup) to the enable pin of a 5-V, 6-A dc-dc
buck converter. When no UFP is detected on both Type-C ports, the EN pin of the dc-dc converter is pulled high,
thereby disabling it. Because the TPS25810A-Q1 device is powered by an always-on 3.3-V LDO, turning off the
supply to IN1 and IN2 does not affect its operation in the detach state. Anytime a UFP is detected on either port,
the corresponding UFP pin is pulled low, enabling the dc-dc converter to provide charging current to the attached
UFP. Turning off the high-power dc-dc converter when ports are unattached saves on system power. This
method can save a significant amount of power, because the TPS25810A-Q1 device requires only 0.7 µA
(typical) via the AUX pin when no UFP device is connected.
20
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I
EN
CC1
IN2
AUX
CHG
TPS25810A-Q1
No. 1
CC2
USB Type-C
Connector
OUT
IN1
TPS54620
Buck
Converter
No UFP
Attached
USB Type-C
Connector
Both UFP High
Converters
Disabled
No UFP
Attached
UFP_1
CHG_HI
12 V
UFP_1
(High)
UFP_2
(High)
OUT
IN1
CC1
IN2
AUX
LP2950-33
LDO
CHG
TPS25810A-Q1
No. 2
CC2
UFP_2
One UFP Low
Converter
Enabled
OUT
IN1
TPS54620
Buck
Converter
CC1
IN2
AUX
EN
CHG
TPS25810A-Q1
No. 1
CC2
USB Type-C
Connector
CHG_HI
UFP
Attached
UFP_1
-
CHG_HI
12 V
UFP_2
(High)
IN1
OUT
CC1
IN2
AUX
LP2950-33
LDO
CHG
TPS25810A-Q1
No. 2
CC2
USB Type-C
Connector
UFP_1
(High)
No UFP
Attached
UFP_2
CHG_HI
Copyright © 2017, Texas Instruments Incorporated
Figure 18. Power-Wake Implementation
8.4 Device Functional Modes
The TPS25810A-Q1 device is a Type-C controller with integrated power switches that supports all Type-C
functions in a downstream facing port. The device manages current advertisement and protection for a
connected UFP and active cable. Each device starts its operation by monitoring the AUX bus. When VAUX
exceeds the undervoltage-lockout threshold, the device samples the EN pin. A high level on this pin enables the
device, and normal operation begins. Having successfully completed its start-up sequence, the device now
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Device Functional Modes (continued)
actively monitors its CC1 and CC2 pins for attachment to a UFP. When a UFP is detected on either the CC1 or
CC2 pin, the internal MOSFET starts to turn on after the required deglitch time is met. The internal MOSFET
starts conducting and allows current to flow from IN1 to OUT. If Ra is detected on the other CC pin (not
connected to the UFP), VCONN is applied to allow current to flow from IN2 to the CC pin connected to Ra. For a
complete listing of various device operational modes, see Table 2.
22
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The TPS25810A-Q1 device is a Type-C DFP controller that supports all Type-C DFP required functions. It
applies power to VBUS when a UFP attach is detected and removes power when it detects the UFP is detached.
The device exposes its identity via its CC pin, advertising its current capability based on the CHG and CHG_HI
pin settings. The TPS25810A-Q1 device also limits its advertised current internally and provides robust protection
to a fault on the system VBUS power rail.
After a connection is established, either device is capable of providing VCONN to power circuits in the cable plug
on the CC pin that is not connected to the CC wire in the cable. VCONN is internally current-limited and has its
own supply pin, IN2. Apart from providing charging current to a UFP, the TPS25810A-Q1 device also supports
audio and debug accessory modes.
The following design procedure can be used to implement a full-featured Type-C DFP.
NOTE
BC 1.2 is not supported in the TPS25810A-Q1 device. To support BC 1.2 with Type-C
charging modes in a single Type-C connector, a dedicated charging port (DCP) controller
something like a TPS2514A-Q1 device must be used.
9.2 Typical Applications
9.2.1 Type-C DFP Port Implementation Without BC 1.2 Support
Figure 19 shows a minimal Type-C DFP implementation capable of supporting 5-V and 3-A charging.
5V
2
0.1 µF
47 µF
47 µF
47 µF
3
4
5
6
7
8
IN1
IN1
IN2
AUX
EN
CHG
CHG_HI
OUT
OUT
CC2
CC1
FAULT
CS
UFP
POL
10
AUDIO
REF
100 kW
(1%)
DEBUG
GND
9
VBUS
14
USB Type-C
Receptacle
15
13
11
1
20
10 µF
19
18
17
16
12
REF_RTN
Copyright © 2017, Texas Instruments Incorporated
Figure 19. Type-C DFP Port Implementation Without BC 1.2 Support
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Typical Applications (continued)
9.2.1.1 Design Requirements
9.2.1.1.1 Input and Output Capacitance
Input and output capacitance improves the performance of the device. The actual capacitance should be
optimized for the particular application. For all applications, a 0.1-μF or greater ceramic bypass capacitor
between INx and GND is recommended as close to the device as possible for local noise decoupling.
All protection circuits, including those of the TPS25810A-Q1 device, have the potential for input voltage
overshoots and output voltage undershoots. Input voltage overshoots can be caused by either of two effects. The
first cause is an abrupt application of input voltage in conjunction with input power-bus inductance and input
capacitance when the INx pin is high-impedance (before turnon). Theoretically, the peak voltage is 2 times the
applied voltage. The second cause is due to the abrupt reduction of output short-circuit current when the device
turns off and energy stored in the input inductance drives the input voltage high. Input voltage droops may also
occur with large load steps and as the output is shorted. Applications with large input inductance (for instance,
connecting the evaluation board to the bench power supply through long cables) may require large input
capacitance to prevent the voltage overshoot from exceeding the absolute maximum voltage of the device.
The fast current-limit speed of the TPS25810A-Q1 device to hard output short circuits isolates the input bus from
faults. However, ceramic input capacitance in the range of 1 μF to 22 μF adjacent to the input aids in both
response time and limiting the transient seen on the input power bus. Momentary input transients to 6.5 V are
permitted. Output voltage undershoot is caused by the inductance of the output power bus just after a short has
occurred and the device has abruptly reduced the OUT current. Energy stored in the inductance drives the OUT
voltage down, and potentially negative, as it discharges. An application with large output inductance (such as
from a cable) benefits from the use of a high-value output capacitor to control voltage undershoot.
When implementing a USB-standard application, 120-μF minimum output capacitance is required. Typically, a
150-μF electrolytic capacitor is used, which is sufficient to control voltage undershoots. Because in Type-C
applications, DFP is a cold socket when no UFP is attached, the output capacitance should be placed at the INx
pin versus the OUT pin, as is done in USB Type-A ports. It is also recommended to put a 10-μF ceramic
capacitor on the OUT pin for better voltage bypass.
9.2.1.2 Detailed Design Procedure
The TPS25810A-Q1 device supports up to three different input voltages, based on the application. In the
simplest implementation, all input pins are tied to a single voltage source set to 5 V, as shown in Figure 19.
However, it is recommended to set a slightly higher (100 mV to 200 mV) input voltage, when possible, to
compensate for IR loss from the source to the Type-C connector.
Other design considerations are listed as follows:
• Place at least 120 µF of bypass capacitance close to the INx pins rather than the OUT pin, as Type-C is a
cold-socket connector.
• A 10-µF bypass capacitor is recommended to be placed near a Type-C receptacle VBUS pin to handle load
transients.
• Depending on the maximum current-level advertisement supported by the Type-C port in the system, set the
CHG and CHG_HI levels accordingly. Advertisement of 3 A is shown in Figure 19.
• The EN, CHG, and CHG_HI pins can be tied directly to GND or VAUX without a pullup resistor.
– CHG and CHG_HI can also be dynamically controlled by a microcontroller to change the current
advertisement level to the UFP.
• When an open-drain output of the TPS25810A-Q1 device is not used, it can be left open or tied to GND.
• Use a 1% 100-kΩ resistor to connect between the REF and REF_RTN pins, placing it close to the device pin
and keeping it isolated from switching noise on the board.
24
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Typical Applications (continued)
VIN
2 V/div
VBUS
2 V/div
2 V/div
9.2.1.3 Application Curves
2 V/div
2 V/div
CC1
VIN
VBUS
CC1
Time 20 ms/div
Time 50 ms/div
Basic start-up: IN1 = IN2 = AUX = EN = CHG = CHG_HI = 5 V
CC1 = Rd
CC2 = open
IN1 = IN2 = AUX = EN = CHG = CHG_HI = 5 V
CC1 = open
CC2 = open → Rd
2 V/div
VBUS VIN
2 V/div
IN
500 mA/div
CC1
VIN
VBUS
2 V/div
2 V/div
Figure 21. Start-Up
CC1
2 A/div
2 V/div
Figure 20. Basic Start-Up
2 V/div
2 V/div
2 V/div
2 A/div
CC2
IN
IN
Time 50 ms/div
Time 200 ms/div
IN1 = IN2 = AUX = EN = 5 V; CHG = CHG_HI = 0 V
CC1 = open
CC2 = Rd
OUT = open → 5
Ω
IN1 = IN2 = AUX = EN = CHG = CHG_HI = 5 V
CC1 = Rd
CC2 = open
OUT = shorted
Figure 23. Hot-Plug to Short
2 V/div
VIN
IN
2 V/div
VOUT
CC1
2 V/div
2 V/div
CC1
2 A/div
VIN
2 V/div
VBUS
2 V/div
2 V/div
Figure 22. Load Step
CC2
Time 20 ms/div
Time 20 ms/div
IN1 = IN2 = AUX = EN = CHG = CHG_HI = 5 V
CC1 = short
CC2 = Rd
IN1 = IN2 = AUX = EN = CHG = CHG_HI = 5 V
CC1 = Rd → open
CC2 = open
Figure 24. Short On CC1
Figure 25. Remove Rd
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VIN
VBUS
CC2
2 V/div
CC1
2 V/div
2 V/div
2 V/div
Typical Applications (continued)
Time 50 ms/div
VIN 5 V → 3.5 V (100 ms) → 5 V (1 V/ms)
IN1 = IN2 = AUX = EN = CHG = CHG_HI = 5 V
CC1 = Rd
CC2 = Ra
Figure 26. Brown-Out Test
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Typical Applications (continued)
9.2.2 Type-C DFP Port Implementation With BC 1.2 (DCP Mode) Support
Figure 27 shows a Type-C DFP implementation capable of supporting 5-V, 3-A charging in a Type-C port that is
also able to support charging of legacy devices when used with a Type-C µB cable assembly for charging
phones and handheld devices equipped with a µB connector.
This implementation requires the use of a TPS2514A-Q1 device, a USB dedicated charging-port (DCP) controller
with auto-detect feature to charge not only BC 1.2-compliant handheld devices but also popular phones and
tablets that incorporate their own propriety charging algorithm. See TPS2513A-Q1, TPS2514A-Q1 USB
Dedicated Charging Port Controller for more details.
TPS2514A-Q1
IN
DM1
DP1
NC
GND NC
0.1 µF
TPS 25810A-Q1
5V
2
0.1 µF
47 µF
47 µF
47 µF
3
4
5
6
7
8
10
IN1
IN1
IN2
OUT
OUT
CC2
AUX
EN
CC1
FAULT
CHG
CS
CHG_HI
UFP
REF
POL
AUDIO
100 kW
(1%)
DEBUG
9
REF_RTN
GND
VBUS
14
15
USB Type-C
Receptacle
D–
13
D+
11
1
20
10 µF
19
18
17
16
12
Copyright © 2017, Texas Instruments Incorporated
Figure 27. Type-C DFP Port Implementation With BC 1.2 (DCP Mode) Support
9.2.2.1 Design Requirements
See Design Requirements for the design requirements.
9.2.2.2 Detailed Design Procedure
See Detailed Design Procedure for the detailed design procedure.
9.2.2.3 Application Curves
See Application Curves for the application curves.
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10 Power Supply Recommendations
The device has three power supply inputs. IN1, which is directly connected to OUT via the power MOSFET, is
tied to the VBUS pin in the Type-C receptacle. IN2 has a current-limiting switch and is multiplexed either to the
CC1 or CC2 pin in the Type-C receptacle, depending on cable plug polarity. AUX is the device supply. In most
applications, all three supplies are tied together. In a special implementation like power wake, IN1 and IN2 are
tied to a single supply, whereas AUX is powered by a supply that is always ON and can be as low as 2.9 V.
USB Specification Revisions 2.0 and 3.1 require VBUS voltage at the connector to be between 4.75 V and 5.5 V.
Depending on layout and routing from the supply to the connector, the voltage drop on VBUS must be tightly
controlled. Locate the input supply close to the device. For all applications, a 10-μF or greater ceramic bypass
capacitor between OUT and GND is recommended, located as close to the Type-C connector of the device as
possible for local noise decoupling. The power supply should be rated higher than the current limit setting to
avoid voltage droops during overcurrent and short-circuit conditions.
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11 Layout
11.1 Layout Guidelines
Layout best practices as they apply to the TPS25810A-Q1 device are listed as follows.
• For all applications, a 10-µF ceramic capacitor is recommended near the Type-C receptacle and another
120‑µF ceramic capacitor close to the IN1 pin.
– The optimum placement of the 120-µF capacitor is closest to the IN1 and GND pins of the device.
– Care must be taken to minimize the loop area formed by the bypass capacitor connection, the IN1 pin,
and the GND pin of the device. See Figure 28 for a PCB layout example.
• High-current-carrying power-path connections to the device should be as short as possible and should be
sized to carry at least twice the full-load current.
– Have the input and output traces as short as possible. The most common cause of voltage loss failure in
USB power delivery is the resistance associated with the VBUS trace. Trace length, maximum current being
supplied for normal operation, and total resistance associated with the VBUS trace must be taken into
account while budgeting for voltage loss.
– For example, a power-carrying trace that supplies 3 A, at a distance of 20 inches, 0.1-in. wide, with 2‑oz.
copper on the outer layer has a total resistance of approximately 0.046 Ω and voltage loss of 0.14 V. The
same trace at 0.05 in. wide has a total resistance of approximately 0.09 Ω and voltage loss of 0.28 V.
– Make power traces as wide as possible.
• The resistor attached to the REF pin of the device has several requirements:
– It is recommended to use a 1% 100-kΩ low-temperature-coefficient resistor.
– It should be connected to the REF and REF_RTN pins (pins 9 and pin 10, respectively).
– The REF_RTN pin should be isolated from the GND plane. See Figure 28.
– The trace routing between the REF and REF_RTN pins of the device should be as short as possible to
reduce parasitic effects on current-limit and current-advertisement accuracy. These traces should not have
any coupling to switching signals on the board.
• Locate all TPS25810A-Q1 pullup resistors for open-drain outputs close to their connection pin. Pullup
resistors should be 100 kΩ.
– When a particular open-drain output is not used or needed in the system, leave the associated pin open or
tied to GND.
• Keep the CC lines close to the same length.
• Thermal considerations:
– When properly mounted, the thermal-pad package provides significantly greater cooling ability than an
ordinary package. To operate at rated power, the thermal pad must be soldered to the board GND plane
directly under the device. The thermal pad is at GND potential and can be connected using multiple vias
to inner-layer GND. Other planes, such as the bottom side of the circuit board, can be used to increase
heat sinking in higher-current applications. See PowerPad™ Thermally Enhanced Package and
PowerPAD™ Made Easy for more information on using this thermal pad package.
– Obtaining acceptable performance with alternate layout schemes is possible; however, the layout example
in the following section has been shown to produce good results and is intended as a guideline.
• ESD considerations:
– The TPS25810A-Q1 device has built-in ESD protection for CC1 and CC2. Keep trace length to a minimum
from the Type-C receptacle to the TPS25810A-Q1 device on CC1 and CC2.
– A 10-µF output capacitor should be placed near the Type-C receptacle.
– See the TPS25810EVM-745 evaluation module for an example of a double-layer board that passes
IEC61000-4-2 testing.
– Do not create stubs or test points on the CC lines. Keep the traces short if possible, and use minimal vias
along the traces [1–2 inches (2.54 cm–5.08 cm) or less].
– See ESD Protection Layout Guide for additional information.
– Have a dedicated ground plane layer, if possible, to avoid differential voltage buildup.
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11.2 Layout Example
Top Layer Signal Trace
Top Layer Signal Ground Plane
Bottom Layer Signal Trace
Bottom Layer Signal Ground Plane
AUDIO
17
DEBUG
POL
18
UFP
CS
FAULT
Via to Bottom Layer Signal Ground Plane
Via to Bottom Layer Signal
19
20
AUX
1
16
2
15
Thermal
Pad
IN1
3
OUT
14
12
GND
EN
6
11
CC1
7
CHG
Signal Ground
Top Layer
REF 10
5
9
AUX
REF_RTN
CC2
8
13
CHG_HI
4
IN2
Signal Ground
Bottom Layer
Figure 28. Layout Example
30
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12 Device and Documentation Support
12.1 Device Support
12.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
12.2 Documentation Support
12.2.1 Related Documentation
PowerPad™ Thermally Enhanced Package
PowerPAD™ Made Easy
TPS25810EVM-745 User's Guide
Protecting the TPS25810 from High Voltage DFPs
12.2.2 Related Links
The following table lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to order now.
12.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.5 Trademarks
E2E is a trademark of Texas Instruments.
USB Type-C is a trademark of USB Implementers Forum, Inc..
All other trademarks are the property of their respective owners.
12.6 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
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13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the mostcurrent data available for the designated devices. This data is subject to change without notice and without
revision of this document. For browser-based versions of this data sheet, see the left-hand navigation pane.
32
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS25810ATWRVCRQ1
ACTIVE
WQFN
RVC
20
3000
RoHS & Green
SN
Level-2-260C-1 YEAR
-40 to 125
25810AQ
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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