TPS25910
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SLUSAR6D – SEPTEMBER 2012 – REVISED JANUARY 2014
6.5-A, 20-V Integrated Hotswap with Programmable Inrush Slew Rate
Check for Samples: TPS25910
FEATURES
DESCRIPTION
•
•
•
The TPS25910 device provides highly integrated hotswap power management and superior protection in
applications up to 20 V. The maximum UV turn-on
threshold of 2.9 V makes the TPS25910 device well
suited to standard bus voltages as low as 3.3 V. This
device is intended for systems where a voltage bus
must be protected from undesired permanent and
transient overload.
1
•
•
•
•
•
•
Up to 20-V Bus Operation
Integrated 30-mΩ Pass MOSFET
Programmable Current Limit from:
0.83 A to 6.5 A
Programmable Inrush Current Slew Rate
Thermal Shutdown and fault alert
4-mm x 4-mm QFN16
–40°C to 125°C Junction Temperature Range
UL2367 Recognized - File Number E169910
CB Certified
At start-up or when hot plugging into the system bus,
the TPS25910 device limits the inrush current by
controlling the ramp rate of the output voltage, VOUT.
The slew rate of VOUT can be adjusted with a
capacitor between the GATE pin and the GND pin.
APPLICATIONS
•
•
•
•
•
•
•
•
Built in SOA protection ensures that the internal
MOSFET operates inside a safe operating area
(SOA) under the harshest operating conditions. In
addition, the current-limit threshold, which is
independent of the power limit, can be adjusted with
a resistor between the ILIM pin and the GND pin.
Solid State Drive (SSD)
Hard Disk Drive (HDD)
RAID Arrays
Telecommunications
Plug-In Circuit Boards
Notebooks and Netbooks
PCIE
Fan Control
The TPS25910 device provides a fault indicator
output when in thermal fault.
The TPS25910 device is available in a 16-pin QFN
package.
12-V, 4.75-A APPLICATION
1/2/3 IN
OUT 10/11 /12
TPS25910
16 EN
FLT 15
CLOAD
4
Input
Voltage
Bus
GATE
GND
GND
ILIM
GND
GND
5/6
8/9
7
13
14
C EXT
40.2 k?
Optional: To
System
Monitor
Output To Voltage
Bus or DC -to-DC
Converter
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2012–2014, Texas Instruments Incorporated
TPS25910
SLUSAR6D – SEPTEMBER 2012 – REVISED JANUARY 2014
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ABSOLUTE MAXIMUM RATINGS
over device junction temperature range (unless otherwise noted) (1) (2)
MIN
MAX
Input voltage range IN, OUT
–0.3
22
Voltage range, GATE
–0.3
30
Voltage range FLT
–0.3
20
Voltage ILIM
1.75
Output sink current FLT
10
Input voltage range, EN
–0.3
Voltage range ILIM (3)
ESD rating
–0.3
Human body model (HBM)
Charged device model (CDM)
Operating junction temperature range, TJ
(2)
(3)
2
–65
V
V
mA
3
V
2 .5
kV
500
V
Internally Limited
Storage temperature range, Tstg
(1)
6
UNIT
150
°C
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.
All voltage values are with respect to GND.
Do not apply voltage to pin.
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RECOMMENDED OPERATING CONDITIONS
over device junction temperature range (unless otherwise noted)
PARAMETER
MIN
NOM
MAX
UNIT
Input voltage range IN, OUT
3
20
Voltage range EN
0
5
Voltage range FLT
0
20
Continuous output current IOUT
0
5
A
Output sink current FLT
0
1
mA
External Capacitor, GATE
1
47
nF
12
V/μS
dv/dt, VIN (1)
RLIM (2)
Junction temperature
(1)
(2)
V
0
237k
Ω
–40
125
°C
dV/dt, VIN should be limited to 12 V/μS to confine the shoot-through current to the load.
When RLIM value is beyond this range, ILIM will not be as accurate as within this range.
THERMAL INFORMATION
TPS25910
THERMAL METRIC (1)
RSA (QFN)
UNITS
16 PINS
θJA
Junction-to-ambient thermal resistance (2)
34.8
θJCtop
Junction-to-case (top) thermal resistance (3)
35.3
θJB
Junction-to-board thermal resistance (4)
11.9
(5)
ψJT
Junction-to-top characterization parameter
ψJB
Junction-to-board characterization parameter (6)
12.0
θJCbot
Junction-to-case (bottom) thermal resistance (7)
3.3
(1)
(2)
(3)
(4)
(5)
(6)
(7)
0.4
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDECstandard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
Spacer
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ELECTRICAL CHARACTERISTICS
Over operating free-air temperature range, VIN = 3 V – 20 V, EN = 0 V, FLT = open, R(RLIM) = 40.2 kΩ, No external capacitors
are connected to either GATE or OUT, (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
2.60
2.75
2.9
UNIT
IN
UVLO
Bias current
VIN ↑
Hysteresis
100
EN = 2.4 V
2.5
4
EN = 0 V
3.3
5
V
mV
mA
OUT
RON
R(VIN-VOUT), I(VOUT) < I(RLIM), 1 A ≤ I(VOUT) ≤ 4.5 A
Power limit
VIN: 12 V, COUT = 1000 μF, EN: 3 V → 0 V
Reverse diode voltage
VOUT > VIN , EN = 5 V, IIN = –1 A
3
29.5
42
mΩ
5
7.5
W
0.77
1
V
ILIM
current-limit program IVOUT,
V(VIN -– OUT) = 0.3 V, pulsed
test
R(RLIM) = 237 kΩ
0.5
0.82
1.1
R(RLIM) = 200 kΩ
0.75
1
1.25
R(RLIM) = 100 kΩ
1.75
2
2.25
R(RLIM) = 66.5 kΩ
2.65
3
3.3
R(RLIM) = 40.2 kΩ
4.5
5
5.5
R(RLIM) = 29.4 kΩ
5.7
6.5
7.3
V(EN) falling
1.1
1.35
A
EN
Threshold voltage
Input bias current
V(EN)rising
1.5
Hysteresis
150
V(EN) = 2.4 V (sinking)
V(EN) = 0.2 V (sourcing)
V
1.75
mV
–1.5
–1
0.5
–2
–1
0.5
Turn on propagation delay
VIN = 3.3 V, ILOAD = 1 A,
V(EN) : 2.4 V → 0.2 V, till IGATE changes direction.
10
Turn off propagation delay
VIN = 3.3 V, ILOAD = 1 A,
V(EN) : 0.2 V → 2.4 V, till IGATE changes direction.
2.5
VOL
I(FLT) = 1 mA, Fault active (Over Temperature)
0.2
Leakage current
V(FLT) = 18 V
μA
μs
FLT
0.4
V
1
μA
THERMAL SHUTDOWN
Thermal shutdown
TJ
160
Hysteresis
°C
20
GATE
Sourcing current
V(GATE-OUT) = 3.5 V, V(EN) = Low
8
11
15
Strong pull down resistor
V(EN) = Low
10
40
80
Ω
Weak pull down current
V(EN) = Low
250
500
750
µA
5.5
6.6
7.5
V
Output Voltage, V(GATE-OUT)
4
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DEVICE INFORMATION
TPS25910 FUNCTIONAL BLOCK DIAGRAM
I(D)
Detector
1
IN
IOUT
12
11 OUT
2
V(DS) Detector
3
+
S
10
11 uA
Q
Pump
14
4
GATE
15
FLT
1kΩ
13
GND
40 Ω
5
6
8
9
Constant
Power
Engine
1.0V
LCA
+
+
ILIM 7
Fast Trip
Comparator
One-Shot
6.5 kΩ
+
1.6 x ILIM
EN 16
Control
+
1.5 V / 1.35 V
UVLO
+
2.7 V / 2.6 V
THERMAL
SHUTDOWN
VIN
Figure 1. Functional Block Diagram
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TPS25910 PIN ASSIGNMENT
IN
1
IN
2
EN
FLT
GND
GND
RSA-16 Package
(Top View)
16
15
14
13
12
OUT
11
OUT
Thermal Pad
GATE
4
9
GND
5
6
7
8
GND
OUT
ILIM
10
GND
3
GND
IN
PIN FUNCTIONS
6
PIN NAME
PIN NUMBER
EN
16
DESCRIPTION
IN
1, 2, 3
GATE
4
If the chip die temperature exceeds the OTSD rising threshold, GATE is pulled down to GND by a
7.5KOhm resistor.
ILIM
7
A resistor to ground sets the current-limit level.
GND
5, 6, 8, 9, 13, 14
OUT
10, 11, 12
FLT
15
Device is enabled when this pin is pulled low.
Power In and control supply voltage.
GND
Output to the load.
Fault low indicates that the internal pass FET junction temperature exceeds the thermal shutdown
threshold
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PIN DESCRIPTION
FLT: Open-drain output that pulls low during thermal shutdown. FLT activates when device thermally shuts down
and deactivates when die temperature cools down below the device thermal protection threshold and the device
ends thermal shutdown cycle. FLT becomes operational before UV, when VIN is greater than 1 V.
GND: This is the most negative voltage in the circuit and is used as reference for all voltage measurements
unless otherwise specified. All the GND pins must be connected to system power supply negative return point
GATE: Output that provides gate drive for the internal pass FET. Its sourcing current is about 11 µA. An internal
clamp prevents GATE from rising 6.6 V above OUT. CINT is 200 pF.
The GATE pin is disabled by the following mechanisms:
1. When EN is above its rising threshold, GATE is pulled down by a 40-Ω resistor connecting to GND for
approximately 50 µs. Then, a 7.5-kΩ resistor ties GATE to GND to ensure the GATE is off.
2. When VIN drops below the UVLO threshold, GATE is pulled down by a 40-Ω resistor connecting to GND for
approximately 50 µs. Then, a 7.5-kΩ resistor ties GATE to GND to ensure the GATE is off.
3. When short circuit fault occurs, GATE is pulled down by a 40-Ω resistor connecting to GND for approximately
50 µs. Then, a 500-µA current source continues to pull down on the GATE.
4. If the chip die temperature exceeds the OTSD rising threshold, GATE is pulled down to GND by a 7.5-kΩ
resistor.
An external capacitor can be connected from GATE pin to GND pin to create linear inrush profile. The slew rate
of the inrush can be controlled by a different capacitor value.
dV
ICHARGE = (CEXT + CINT ) OUT
dt
where
•
•
ICHARGE is 11 µA (typical)
CINT, the equivalent gate input capacitance of the internal FET (200 pF typical)
ILIM: A resistor connected from this pin to ground sets I(LIM). RLIM is set by the formula:
197.388
RLIM =
ILIM0.976944 for currents below 2 A where R is in kΩ.
LIM
RLIM =
(1)
(2)
205.62
ILIM1.02912 for currents above 2 A where R is in kΩ.
LIM
(3)
EN: When this pin is pulled low, the device is enabled. The input threshold is hysteretic, allowing the user to
program a startup delay with an external RC circuit. EN is pulled to VIN by a 10-MΩ resistor, pulled to GND by
16.8 MΩ and is clamped to ground by a 7-V Zener diode. Because high impedance pullup and or down resistors
are used to reduce current draw, any external FET controlling this pin must be low leakage.
IN: Input voltage to the TPS25910 device. The recommended operating voltage range is 3 V to 20 V. All VIN
pins must be connected together and to the power source.
OUT: Output connection for the TPS25910 device. When switched on, the output voltage is approximately:
VOUT = VIN - 0.04 ´ IOUT
(4)
All OUT pins must be connected together and to the load.
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TYPICAL CHARACTERISTICS
current-limit
vs
JUNCTION TEMPERATURE
POWER LIMIT
vs
JUNCTION TEMPERATURE
2.05
5.5
R(RLIM) = 100 kΩ
ILOAD = 1.2 A
5.3
Power Limit (W)
Current Limit (A)
2.02
1.99
1.96
1.93
1.90
−50
5.1
4.9
4.7
−25
0
25
50
75
100
Junction Temperature (°C)
125
4.5
−50
150
−25
0
25
50
75
100
Junction Temperature (°C)
125
G001
G002
Figure 2.
Figure 3.
ON-STATE SUPPLY CURRENT
vs
JUNCTION TEMPERATURE
OFF-STATE SUPPLY CURRENT
vs
JUNCTION TEMPERATURE
3.37
2.51
VIN = 12 V
VIN = 12 V
2.50
Supply Current (OFF) (mA)
Supply Current (ON) (mA)
3.36
3.35
3.34
3.33
3.32
−50
2.49
2.48
2.47
−25
0
25
50
75
100
Junction Temperature (°C)
125
150
2.46
−50
−25
0
25
50
75
100
Junction Temperature (°C)
G003
Figure 4.
8
150
125
150
G004
Figure 5.
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APPLICATION INFORMATION
Programming the Current-Limit Threshold
The over-current threshold is user programmable via an external resistor. The TPS25910 device uses an internal
regulation loop to provide a regulated voltage on the ILIM pin. The current-limit threshold is proportional to the
current sourced out of ILIM. The recommended 1% resistor range for RILIM is 0 kΩ ≤ RILIM ≤ 237 kΩ to ensure
stability of the internal regulation loop. Many applications require that the minimum current-limit is above a certain
current level or that the maximum current-limit is below a certain current level, so it is important to consider the
tolerance of the over-current threshold when selecting a value for RILIM. Consult the ELECTRICAL
CHARACTERISTICS table for specific current-limit settings. The traces routing the RILIM resistor to the
TPS25910 device must be as short as possible to reduce parasitic effects on the current-limit accuracy.
Equation 5 through Equation 7 can be used to estimate current-limit below 2 A:
1051.9
ILIM(min) =
RLIM(max)1.3854
ILIM(typ) =
(5)
223.61
RLIM(typ)1.0236
ILIM(max) =
(6)
104.95
RLIM(min)0.8347
(7)
Equation 8 through Equation 10 can be used to estimate current-limit above 2 A:
161.24
ILIM(min) =
RLIM(max)0.9796
ILIM(typ) =
(8)
176.85
RLIM(typ)0.9717
ILIM(max) =
(9)
194.81
RLIM(min)0.9694
(10)
where
• RLIM(max) is the maximum resistor value in factoring in error
• RLIM(typ) is the typical resistor value
• RLIM(min) is the minimum resistor value factoring in error
All
•
•
•
resistor values are represented in kΩ. For example, a 100-kΩ, 1% resistor would have the following values:
RLIM(min) = 99 kΩ
RLIM(typ) = 100 kΩ
RLIM(max) = 101 kΩ
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A plot of the current-limit threshold versus RLIM using equations Equation 5 through Equation 10 above is shown
in Figure 6.
8
ILIM(min)
ILIM(typ)
ILIM(max)
Current Limit Threshold (A)
7
6
5
4
3
2
1
0
20
30
40
50
60
70
80
90 100 110 120 130 140 150 160 170 180 190 200 210 220 230 240
RILIM − Resistance (kΩ)
G001
Figure 6. Current-Limit Threshold Versus RILIM
10
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Slew Rate Control Using CGATE
The TPS25910 device can be used with applications that require constant turn-on currents. The current is
controlled by a single capacitor from the GATE terminal to ground. The TPS25910 internal MOSFET appears to
operate as a source follower (following the gate voltage) in this implementation. Choose a time to charge, Δt,
based on the output capacitor, input voltage VI, and desired charge current, ICHARGE. Select the device load to be
less than 5 W / VIN.
C
´ VIN
Δt = LOAD
IC-LOAD
(11)
To select the gate capacitance:
Δt
CEXT = ICHARGE ´
- CINT
VIN
•
•
ICHARGE = 11 µA
CINT = 200 pF (typical)
(12)
Figure 7 and Figure 8 illustrate the effects of CEXT = 0.1 µF on inrush current using TPS25910EVM-088.
Figure 7. Typical Power Limited Inrush Start Up (No CEXT)
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Figure 8. Start-Up With Slew Rate Control (CEXT = 0.1 µF)
12
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Thermal Sense
The TPS25910 self protects by using a thermal sensing circuit that monitors the operating temperature of the
power switch and disables operation if the temperature exceeds the thermal shutdown condition (160°C typical).
The TPS25910 device operates in power-limit mode during an overload condition and increases the voltage drop
across power switch. The thermal sensor turns off the power switch when the die temperature exceeds 160°C.
Hysteresis is built into the thermal sensor, and the switch turns on after the device has cooled approximately
20°C. Figure 9 below illustrates the thermal behavior during output overload.
Figure 9. Thermal Sense Behavior
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Back-to-Back (B2B) FET Operation
Many applications require reverse current blocking (from load to input source) so that pending system activities
can be completed (such as writing important data to non-volatile memory) prior to power down or during brown
out. The TPS25910 device provides the GATE pin externally for slew rate control, but this external connection
can also be used to control an external blocking MOSFET, Q1 as shown in Figure 10.
As VIN drops during input power removal, the comparator circuit de-asserts ENb, GATE falls, and both the
TPS25910 internal MOSFET and Q1 is turned off and block any current flow from VLOAD to VIN. CLOAD can then
be chosen to furnish the required load current for long enough to complete the required power down system
activities.
CSD17313Q2
TPS25910
1/2/3 IN
OUT 10/11/12
Q1
REN1
VIN
VREF
+
–
16 EN
+
Comparator
REN2
7
GATE
4
ILIM
FLT 15
5/6 GND
GND 13/14
RLOAD
CLOAD
+
VLOAD
-
RLIM
Figure 10. B2B Implementation
NOTE
Connecting the load voltage to the non-inverting input of the external comparator can
provide a simple ORing function that prevents holdup energy in CLOAD from discharging
through the TPS25910 device to VIN(source) when VIN(source) droops or collapses.
14
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Circuit operation is illustrated in Figure 11 and Figure 12. Figure 11 shows the power down event with no load at
the output. When VIN drops to approximately 10 V (threshold of comparator circuit), ENb is de-asserted and
GATE falls and enables reverse current blocking. The voltage on CLOAD then stops following VIN and remains flat
for a long duration.
Figure 11. B2B Performance with No-Load
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Figure 12 illustrates the power down event with a 200-mA load. As VIN starts to fall, the output load is supplied by
CLOAD. CLOAD must be large enough to support VLOAD for long enough for the power down activities to complete.
For the case shown in Figure 12, CLOAD is a 3900-µF capacitor and can support a droop from approximately 10 V
to approximately 5 V for approximately 170 ms.
The TPS3700DDC (dual comparator with wide input voltage range) can be used for the B2B comparator circuit
shown in Figure 10. Only one comparator is needed, but the second comparator can be utilized as either a
power good flag or as a notification to the system load that a brownout or power down event is about to occur.
Figure 12. B2B Performance with 200-mA Load
16
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Maximum Load at Startup
The power limiting function of the TPS25910 device provides effective protection for the internal FET.
Expectedly, there is a supply voltage dependent maximum load which the device is able to power up. Loads
above this level can cause the device to shut off current before startup is complete. Neglecting any load
capacitance, the maximum load (minimum load resistance) is calculated using Equation 13;
V 2
RMIN = IN
12
(13)
Adding load capacitance may reduce the maximum load which can be present at start up.
If EN is tied to GND at startup and IN does not ramp quickly, the TPS25910 device can momentarily turn off then
on during startup. This can happen if a capacitive load pulls down the input voltage below the UV threshold. If
necessary, this can be avoided by delaying the EN assertion until VIN is fully up.
Transient Protection
The need for transient protection in conjunction with hot-swap controllers should always be considered. When
the TPS25910 device interrupts current flow, input inductance generates a positive voltage spike on the input
and output inductance generates a negative voltage spike on the output. Such transients can easily exceed twice
the supply voltage if steps are not taken to address the issue. Typical methods for addressing transients include;
• Minimizing lead length/inductance into and out of the device.
• Transient Voltage Suppressors (TVS) on the input to absorb inductive spikes.
• Schottky diode across the output to absorb negative spikes.
• A combination of ceramic and electrolytic capacitors on the input and output to absorb energy.
The following equation estimates the magnitude of these voltage spikes:
Where;
VSPIKE(absolute ) = VNOM + ILOAD ´ L
•
•
•
•
C
VNOM equals the nominal supply voltage
ILOAD equals the load current
C equals the capacitance present at the input or output of the TPS25910 device
L equals the effective inductance seen looking into the source or the load
(14)
The inductance because of a straight length of wire equals approximately.
Where;
æ 4´L
ö
- 0.75 ÷ (nH)
Lstraightwire » 0.2 ´ L ´ ln ç
D
è
ø
•
•
L equals the length of the wire
D equals wire diameter
(15)
Some applications may require the addition of a TVS to prevent transients from exceeding the absolute ratings if
sufficient capacitance cannot be included.
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Copyright © 2012–2014, Texas Instruments Incorporated
Product Folder Links: TPS25910
17
TPS25910
SLUSAR6D – SEPTEMBER 2012 – REVISED JANUARY 2014
www.ti.com
REVISION HISTORY
Changes from Original (September 2012) to Revision A
Page
•
Changed the 12-V, 4.75-A APPLICATION image ................................................................................................................ 1
•
Changed Equation 3 text From: below 2 A where RLIM is in kΩ. To: above 2 A where RLIM is in kΩ. .................................. 7
•
Changed Equation 12 ......................................................................................................................................................... 11
•
Changed Figure 10 ............................................................................................................................................................. 14
Changes from Revision A (September 2012) to Revision B
Page
•
Changed Figure 1 LCA polarity symbols .............................................................................................................................. 5
•
Changed Figure 10 Q1 connection ..................................................................................................................................... 14
Changes from Revision B (March, 2013) to Revision C
Page
•
Added Bullet: UL Listed - File Number E169910 to the Features section. ........................................................................ 1
•
Added Bullet: CB Certified to the Features section. ............................................................................................................ 1
Changes from Revision C (May 2013) to Revision D
Page
•
Deleted the minimum voltage from the voltage range listed in the document title, features list and description ................. 1
•
Added 6.5-A to document title .............................................................................................................................................. 1
•
Changed listed to recognized in last FEATURES bullet ....................................................................................................... 1
•
Added 2367 to UL number in the FEATURES list. Moved File Number to same list item as UL Recognized .................... 1
•
Added PCIE and Fan Control to the APPLICATIONS list .................................................................................................... 1
•
Deleted where the load is powered by busses up to 20 V from the first paragraph of the DESCRIPTION and
replaced it with UV turn-on threshold and bus voltage text .................................................................................................. 1
•
Deleted ORDERING INFORMATION table .......................................................................................................................... 2
18
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Copyright © 2012–2014, Texas Instruments Incorporated
Product Folder Links: TPS25910
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS25910RSAR
ACTIVE
QFN
RSA
16
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
TPS
25910
TPS25910RSAT
ACTIVE
QFN
RSA
16
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
TPS
25910
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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