TPS2833DG4


  
   
 
 
 
 SLVS195C − FEBRUARY 1999 − REVISED JANUARY 2001 D Floating Bootstrap or Ground-Reference D D D D D D D D D D PACKAGE (TOP VIEW) High-Side Driver Adaptive Dead-Time Control 50-ns Max Rise/Fall Times and 100-ns Max Propagation Delay − 3.3-nF Load Ideal for High-Current Single or Multiphase Power Supplies 2.4-A Typical Peak Output Current 4.5-V to 15-V Supply Voltage Range Internal Schottky Bootstrap Diode Low Supply Current....3-mA Typical −40°C to 125°C Operating Virtual Junction Temperature Available in SOIC Package IN PGND DT VCC 1 8 2 7 3 6 4 5 BOOT HIGHDR BOOTLO LOWDR description The TPS2832 and TPS2833 are MOSFET drivers for synchronous-buck power stages. These devices are ideal for designing a high-performance power supply using switching controllers that do not have MOSFET drivers. The drivers are designed to deliver 2.4-A peak currents into large capacitive loads. The high-side driver can be configured as a ground-reference driver or as a floating bootstrap driver. An adaptive dead-time control circuit eliminates shoot-through currents through the main power FETs during switching transitions and provides high efficiency for the buck regulator. The TPS2832 has a noninverting input. The TPS2833 has an inverting input. The TPS2832/33 drivers, available in 8-terminal SOIC packages, operate over a junction temperature range of − 40°C to 125°C. AVAILABLE OPTIONS PACKAGED DEVICES TJ SOIC (D) TPS2832D TPS2833D −40°C to 125°C The D package is available taped and reeled. Add R suffix to device type (e.g., TPS2832DR) Related Synchronous MOSFET Drivers DEVICE NAME ADDITIONAL FEATURES INPUTS TPS2830 TPS2831 Noninverted ENABLE, SYNC and CROWBAR CMOS ENABLE, SYNC and CROWBAR TTL W/O ENABLE, SYNC and CROWBAR TTL TPS2834 TPS2835 Noninverted TPS2836 TPS2837 Inverted Inverted Noninverted Inverted Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright  2001, Texas Instruments Incorporated 
 
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 SLVS195C − FEBRUARY 1999 − REVISED JANUARY 2001 functional block diagram 4 8 7 (TPS2832 Only) 6 VCC BOOT HIGHDR BOOTLO 1 IN VCC (TPS2833 Only) 5 2 LOWDR PGND 3 DT Terminal Functions TERMINAL NAME NO. I/O DESCRIPTION BOOT 8 I Bootstrap terminal. A ceramic capacitor is connected between BOOT and BOOTLO terminals to develop the floating bootstrap voltage for the high-side MOSFET. The capacitor value is typically between 0.1 µF and 1 µF. A 1-MΩ resistor should be connected across the bootstrap capacitor to provide a discharge path when the driver has been powered down. BOOTLO 6 O This terminal connects to the junction of the high-side and low-side MOSFETs. DT 3 I Dead-time control terminal. Connect DT to the junction of the high-side and low-side MOSFETs HIGHDR 7 O Output drive for the high-side power MOSFET IN 1 I Input signal to the MOSFET drivers (noninverting input for the TPS2832; inverting input for the TPS2833). LOWDR 5 O Output drive for the low-side power MOSFET PGND 2 VCC 4 2 Power ground. Connect to the FET power ground. I Input supply. Recommended that a 1 µF capacitor be connected from VCC to PGND. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 

  
   
 
 
 
 SLVS195C − FEBRUARY 1999 − REVISED JANUARY 2001 detailed description low-side driver The low-side driver is designed to drive low Rds(on) N-channel MOSFETs. The current rating of the driver is 2 A, source and sink. high-side driver The high-side driver is designed to drive low Rds(on) N-channel MOSFETs. The current rating of the driver is 2 A, source and sink. The high-side driver can be configured as a ground-reference driver or a floating bootstrap driver. The internal bootstrap diode, is a Schottky for improved drive efficiency. The maximum voltage that can be applied between the BOOT terminal and ground is 30 V. dead-time (DT) control† Dead-time control prevents shoot through current from flowing through the main power FETs during switching transitions by controlling the turn-on times of the MOSFET drivers. The high-side driver is not allowed to turn on until the gate drive voltage to the low-side FET is low, and the low-side driver is not allowed to turn on until the voltage at the junction of the power FETs (Vdrain) is low; the DT terminal connects to the junction of the power FETs. IN† The IN terminal is a digital terminal that is the input control signal for the drivers. The TPS2832 has a noninverting input; the TPS2833 has an inverting input. †High-level input voltages on IN and DT must be greater than or equal to 0.7VCC. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 

  
   
 
 
 
 SLVS195C − FEBRUARY 1999 − REVISED JANUARY 2001 absolute maximum ratings over operating free-air temperature (unless otherwise noted)† Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 16 V Input voltage range: BOOT to PGND (high-side driver ON) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 30 V BOOTLO to PGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 16 V BOOT to BOOTLO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 16 V IN (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 16 V DT (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 30 V Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table Operating virtual junction temperature range, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 125°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C Lead temperature soldering 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . 260°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. Unless otherwise specified, all voltages are with respect to PGND. 2. High-level input voltages on the IN and DT terminals must be less than or equal to VCC. DISSIPATION RATING TABLE PACKAGE TA ≤ 25°C POWER RATING DERATING FACTOR ABOVE TA = 25°C TA = 70°C POWER RATING TA = 85°C POWER RATING D 600 mW 6.0 mW/°C 330 mW 240 mW recommended operating conditions MIN NOM MAX UNIT Supply voltage, VCC 4.5 15 V Input voltage 4.5 28 V BOOT to PGND electrical characteristics over recommended operating virtual junction temperature range, VCC = 6.5 V, CL = 3.3 nF (unless otherwise noted) supply current PARAMETER TEST CONDITIONS Supply voltage range VCC TYP 4.5 VCC =15 V VCC =12 V, fSWX = 200 kHz, CHIGHDR = 50 pF, Quiescent current BOOTLO grounded, CLOWDR = 50 pF, See Note 3 NOTE 3: Ensured by design, not production tested. 4 MIN POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 MAX UNIT 15 V 100 µA mA 

  
   
 
 
 
 SLVS195C − FEBRUARY 1999 − REVISED JANUARY 2001 electrical characteristics over recommended operating virtual junction temperature range, VCC = 6.5 V, CL = 3.3 nF (unless otherwise noted) (continued) output drivers PARAMETER High-side sink (see Note 4) Peak outputcurrent High-side source (see Note 4) Low-side sink (see Note 4) Low-side source (see Note 4) TEST CONDITIONS MIN TYP Duty cycle < 2%, tpw < 100 µs (see Note 3) VBOOT – VBOOTLO = 4.5 V, VHIGHDR = 4 V VBOOT – VBOOTLO = 6.5 V, VHIGHDR = 5 V VBOOT – VBOOTLO = 12 V, VHIGHDR = 10.5 V 0.7 1.1 1.1 1.5 2 2.4 Duty cycle < 2%, tpw < 100 µs (see Note 3) VBOOT – VBOOTLO = 4.5 V, VHIGHDR = 0.5V VBOOT – VBOOTLO = 6.5 V, VHIGHDR = 1.5 V VBOOT – VBOOTLO = 12 V, VHIGHDR = 1.5 V 1.2 1.4 1.3 1.6 2.3 2.7 Duty cycle < 2%, tpw < 100 µs (see Note 3) VCC = 4.5 V, VCC = 6.5 V, VLOWDR = 4 V VLOWDR = 5 V 1.3 1.8 2 2.5 VCC = 12 V, VCC = 4.5 V, VLOWDR = 10.5 V VLOWDR = 0.5V 3 3.5 1.4 1.7 VCC = 6.5 V, VCC = 12 V, VLOWDR = 1.5 V VLOWDR = 1.5 V 2 2.4 2.5 3 Duty cycle < 2%, tpw < 100 µs (see Note 3) High-side sink (see Note 4) High-side source (see Note 4) Output resistance Low-side sink (see Note 4) Low-side source (see Note 4) MAX A A A A VBOOT – VBOOTLO = 4.5 V, VHIGHDR = 0.5 V VBOOT – VBOOTLO = 6.5 V, VHIGHDR = 0.5 V VBOOT – VBOOTLO = 12 V, VHIGHDR = 0.5 V 5 VBOOT – VBOOTLO = 4.5 V, VHIGHDR = 4 V VBOOT – VBOOTLO = 6.5 V, VHIGHDR = 6 V VBOOT – VBOOTLO = 12 V, VHIGHDR =11.5 V 75 VDRV = 4.5 V, VDRV = 6.5 V VLOWDR = 0.5 V VLOWDR = 0.5 V VDRV = 12 V, VDRV = 4.5 V, VLOWDR = 0.5 V VLOWDR = 4 V VDRV = 6.5 V, VDRV = 12 V, VLOWDR = 6 V VLOWDR = 11.5 V UNIT 5 Ω 5 75 Ω 75 9 7.5 Ω 6 75 75 Ω 75 NOTES: 3. Ensured by design, not production tested. 4. The pull-up/pull-down circuits of the drivers are bipolar and MOSFET transistors in parallel. The peak output current rating is the combined current from the bipolar and MOSFET transistors. The output resistance is the Rds(on) of the MOSFET transistor when the voltage on the driver output is less than the saturation voltage of the bipolar transistor. dead time PARAMETER VIH VIL High-level input voltage VIH VIL High-level input voltage TEST CONDITIONS Low-level input voltage Low-level input voltage LOWDR Over the VCC range (see Note 3) DT Over the VCC range MIN TYP MAX 0.7VCC 1 0.7VCC 1 UNIT V V NOTE 3: Ensured by design, not production tested. digital control terminals PARAMETER VIH VIL High-level input voltage Low-level input voltage TEST CONDITIONS Over the VCC range POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MIN TYP MAX 0.7VCC UNIT V 1 V 5 

  
   
 
 
 
 SLVS195C − FEBRUARY 1999 − REVISED JANUARY 2001 switching characteristics over recommended operating virtual junction temperature range, CL = 3.3 nF (unless otherwise noted) PARAMETER TEST CONDITIONS HIGHDR output (see Note 3) Rise time LOWDR output (see Note 3) HIGHDR output (see Note 3) Fall time LOWDR output (see Note 3) HIGHDR going low (excluding dead time) (see Note 3) Propagation delay time LOWDR going high (excluding dead time) (see Note 3) Propagation delay time Driver nonoverlap time NOTE 3: 6 LOWDR going low (excluding dead time) (see Note 3) DT to LOWDR and LOWDR to HIGHDR (see Note 3) MIN TYP MAX VBOOT = 4.5 V, VBOOT = 6.5 V, VBOOTLO = 0 V VBOOTLO = 0 V 60 VBOOT = 12 V, VCC = 4.5 V VBOOTLO = 0 V 50 50 ns 40 VCC = 6.5 V VCC = 12 V 30 ns 30 VBOOT = 4.5 V, VBOOT = 6.5 V, VBOOTLO = 0 V VBOOTLO = 0 V 60 VBOOT = 12 V, VCC = 4.5 V VBOOTLO = 0 V 50 50 ns 40 VCC = 6.5 V VCC = 12 V 30 ns 30 VBOOT = 4.5 V, VBOOT = 6.5 V, VBOOTLO = 0 V VBOOTLO = 0 V 130 VBOOT = 12 V, VBOOT = 4.5 V, VBOOTLO = 0 V VBOOTLO = 0 V 75 VBOOT = 6.5 V, VBOOT = 12 V, VBOOTLO = 0 V VBOOTLO = 0 V 70 100 VCC = 12 V VCC = 4.5 V VCC = 6.5 V VCC = 12 V Ensured by design, not production tested. • DALLAS, TEXAS 75265 ns 80 ns 60 VCC = 4.5 V VCC = 6.5 V POST OFFICE BOX 655303 UNIT 80 70 ns 60 40 170 25 135 15 85 ns 

  
   
 
 
 
 SLVS195C − FEBRUARY 1999 − REVISED JANUARY 2001 TYPICAL CHARACTERISTICS FALL TIME vs SUPPLY VOLTAGE RISE TIME vs SUPPLY VOLTAGE 50 50 CL = 3.3 nF TJ = 25°C 45 40 40 t f − Fall Time − ns t r − Rise Time − ns CL = 3.3 nF TJ = 25°C 45 High Side 35 30 Low Side 25 35 High Side 30 25 20 20 15 15 10 Low Side 10 4 5 6 7 9 10 11 12 13 8 VCC − Supply Voltage − V 14 15 4 5 6 Figure 1 10 11 12 13 14 15 50 VCC = 6.5 V CL = 3.3 nF 45 VCC = 6.5 V CL = 3.3 nF 40 40 t f − Fall Time − ns High Side t r − Rise Time − ns 9 FALL TIME vs JUNCTION TEMPERATURE 50 35 30 Low Side 25 High Side 35 30 25 Low Side 20 20 15 15 10 −50 8 Figure 2 RISE TIME vs JUNCTION TEMPERATURE 45 7 VCC − Supply Voltage − V −25 0 25 50 75 100 125 10 −50 −25 0 25 50 75 100 125 TJ − Junction Temperature − °C TJ − Junction Temperature − °C Figure 3 Figure 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 

  
   
 
 
 
 SLVS195C − FEBRUARY 1999 − REVISED JANUARY 2001 TYPICAL CHARACTERISTICS HIGH-TO-LOW PROPAGATION DELAY TIME vs SUPPLY VOLTAGE, HIGH TO LOW LEVEL 150 t PHL − High-to-Low Propagation Delay Time − ns t PLH − Low-to-High Propagation Delay Time − ns LOW-TO-HIGH PROPAGATION DELAY TIME vs SUPPLY VOLTAGE, LOW TO HIGH LEVEL CL = 3.3 nF TJ = 25°C 140 130 120 110 100 90 High Side 80 70 60 Low Side 50 40 30 20 4 5 6 7 8 9 10 11 12 13 14 15 150 CL = 3.3 nF TJ = 25°C 140 130 120 110 100 90 80 High Side 70 60 50 40 Low Side 30 20 4 5 6 VCC − Supply Voltage − V 7 Figure 5 VCC = 6.5 V CL = 3.3 nF 120 110 100 High Side 90 80 70 60 Low Side 50 40 30 20 −50 12 13 14 15 −25 25 75 0 50 100 TJ − Junction Temperature − °C 125 150 140 130 VCC = 6.5 V CL = 3.3 nF 120 110 100 90 High Side 80 70 60 50 Low Side 40 30 20 −50 −25 0 25 Figure 8 POST OFFICE BOX 655303 50 75 TJ − Junction Temperature − °C Figure 7 8 11 HIGH-TO-LOW PROPAGATION DELAY TIME vs JUNCTION TEMPERATURE t PHL − High-to-Low Propagation Delay Time − ns t PLH − Low-to-High Propagation Delay Time − ns 150 130 10 Figure 6 LOW-TO-HIGH PROPAGATION DELAY TIME vs JUNCTION TEMPERATURE 140 9 8 VCC − Supply Voltage − V • DALLAS, TEXAS 75265 100 125 

  
   
 
 
 
 SLVS195C − FEBRUARY 1999 − REVISED JANUARY 2001 TYPICAL CHARACTERISTICS FALL TIME vs LOAD CAPACITANCE RISE TIME vs LOAD CAPACITANCE 1000 1000 VCC = 6.5 V TJ = 25°C t f − Fall Time − ns t r − Rise Time − ns VCC = 6.5 V TJ = 25°C 100 High Side Low Side 10 1 0.1 1 10 100 High Side Low Side 10 1 0.1 100 1 100 CL − Load Capacitance − nF CL − Load Capacitance − nF Figure 9 Figure 10 SUPPLY CURRENT vs SUPPLY VOLTAGE SUPPLY CURRENT vs SUPPLY VOLTAGE 25 6000 TJ = 25°C CL = 50 pF 5500 TJ = 25°C CL = 50 pF 5000 20 4500 ICC − Supply Current − mA ICC − Supply Current − µ A 10 500 kHz 4000 300 kHz 3500 200 kHz 3000 100 kHz 50 kHz 25 kHz 2500 2000 1500 1000 2 MHz 15 10 1 MHz 5 500 0 0 4 6 8 10 12 14 16 4 VCC − Supply Voltage − V 6 8 10 12 14 16 VCC − Supply Voltage − V Figure 11 Figure 12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 

  
   
 
 
 
 SLVS195C − FEBRUARY 1999 − REVISED JANUARY 2001 TYPICAL CHARACTERISTICS PEAK SOURCE CURRENT vs SUPPLY VOLTAGE PEAK SINK CURRENT vs SUPPLY VOLTAGE 4 4 TJ = 25°C TJ = 25°C 3.5 3 3 Low Side Peak Sink Current − A Peak Source Current − A 3.5 2.5 2 High Side 1.5 Low Side 2.5 2 High Side 1.5 1 1 0.5 0.5 0 0 4 6 8 12 10 16 14 4 6 VCC − Supply Voltage − V 8 Figure 13 Figure 14 INPUT THRESHOLD VOLTAGE vs SUPPLY VOLTAGE 9 TJ = 25°C V IT − Input Threshold Voltage − V 8 7 6 5 4 3 2 1 0 4 6 8 10 12 14 VCC − Supply Voltage − V Figure 15 10 10 12 VCC − Supply Voltage − V POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 16 14 16 

  
   
 
 
 
 SLVS195C − FEBRUARY 1999 − REVISED JANUARY 2001 APPLICATION INFORMATION Figure 16 shows the circuit schematic of a 100-kHz synchronous-buck converter implemented with a TL5001A pulse-width-modulation (PWM) controller and a TPS2833 driver. The converter operates over an input range from 4.5 V to 12 V and has a 3.3 V output. The circuit can supply 3 A continuous load and the transient load is 5 A. The converter achieves an efficiency of 94% for VIN = 5 V, Iload=1 A, and 93% for Vin = 5 V, Iload = 3 A. VIN + C10 100 µF C5 100 µF + R1 1 kΩ U1 TPS2833 1 IN C11 0.47 µF R5 0Ω BOOT 2 PGND HIGHDR 3 BOOTLO DT 4 LOWDR VCC 8 C15 1.0 µF 7 R6 1 MΩ Q1 Si4410 6 L1 27 µH 5 R7 3.3 Ω R11 4.7 Ω Q2 Si4410 C14 1 µF GND C9 0.22 µF OUT C7 100 µF + C12 100 µF + C6 1000 pF C3 0.0022 µF U2 TL5001A 2 C2 VCC 0.033 µF R2 1.6 kΩ 3 COMP 6 DTC FB 4 5 SCP RT 7 R8 121 kΩ 3.3 V RTN C8 0.1 µF 1 C13 10 µF C4 0.022 µF R3 180 Ω R4 2.32 kΩ GND C1 1 µF 8 R9 90.9 kΩ R10 1.0 kΩ Figure 16. 3.3 V 3 A Synchronous-Buck Converter Circuit POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 

  
   
 
 
 
 SLVS195C − FEBRUARY 1999 − REVISED JANUARY 2001 APPLICATION INFORMATION Great care should be taken when laying out the pc board. The power-processing section is the most critical and will generate large amounts of EMI if not properly configured. The junction of Q1, Q2, and L1 should be very tight. The connection from Q1 drain to the positive sides of C5, C10, and C11 and the connection from Q2 source to the negative sides of C5, C10, and C11 should be as short as possible. The negative terminals of C7 and C12 should also be connected to Q2 source. Next, the traces from the MOSFET driver to the power switches should be considered. The BOOTLO signal from the junction of Q1 and Q2 carries the large gate drive current pulses and should be as heavy as the gate drive traces. The bypass capacitor (C14) should be tied directly across VCC and PGND. The next most sensitive node is the FB node on the controller (terminal 4 on the TL5001A) This node is very sensitive to noise pickup and should be isolated from the high-current power stage and be as short as possible. The ground around the controller and low-level circuitry should be tied to the power ground as the output. If these three areas are properly laid out, the rest of the circuit should not have any other EMI problems and the power supply will be relatively free of noise. 12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) TPS2832D ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 2832 TPS2832DR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 2832 TPS2833D ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 2833 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of