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TPS3808-EP
SBVS103D – APRIL 2008 – REVISED DECEMBER 2014
TPS3808-EP Low Quiescent Current, Programmable Delay Supervisory Circuit
1 Features
2 Applications
•
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1
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(1)
Controlled Baseline
– One Assembly Site
– One Test Site
– One Fabrication Site
Extended Temperature Performance of
–55°C to 125°C
Enhanced Diminishing Manufacturing Sources
(DMS) Support
Enhanced Product-Change Notification
Qualification Pedigree (1)
Power-On Reset Generator With Adjustable Delay
Time: 1.25 ms to 10 s
Very Low Quiescent Current: 2.4 μA Typical
High Threshold Accuracy: 0.5% Typical
Fixed Threshold Voltages for Standard Voltage
Rails From 0.9 V to 5 V and Adjustable Voltage
Down to 0.4 V Are Available
Manual Reset (MR) Input
Open-Drain RESET Output
Temperature Range: –55°C to 125°C
Small SOT-23 Package
DSP or Microcontroller Applications
Notebook/Desktop Computers
PDAs and Hand-Held Products
Portable and Battery Powered Products
FPGA and ASIC Applications
3 Description
The
TPS3808xxx
family
of
microprocessor
supervisory circuits monitors system voltages from
0.4 V to 5.0 V, asserting an open-drain RESET signal
when the SENSE voltage drops below a preset
threshold or when the manual reset (MR) pin drops to
a logic low. The RESET output remains low for the
user-adjustable delay time after the SENSE voltage
and manual reset (MR) return above the respective
thresholds.
The TPS3808 uses a precision reference to achieve
0.5% threshold accuracy for VIT ≤ 3.3 V. The reset
delay time can be set to 20 ms by disconnecting the
CT pin, 300 ms by connecting the CT pin to VDD using
a resistor, or can be user-adjusted between 1.25 ms
and 10 s by connecting the CT pin to an external
capacitor. The TPS3808 has a very low typical
quiescent current of 2.4 μA, so it is well-suited to
battery-powered applications. It is available in a small
SOT-23 package, and is fully specified over a
temperature range of –55°C to +125°C (TJ).
Component qualification in accordance with JEDEC and
industry standards to ensure reliable operation over an
extended temperature range. This includes, but is not limited
to, Highly Accelerated Stress Test (HAST) or biased 85/85,
temperature cycle, autoclave or unbiased HAST,
electromigration, bond intermetallic life, and mold compound
life. Such qualification testing should not be viewed as
justifying use of this component beyond specified
performance and environmental limits.
Device Information(1)
PART NUMBER
TPS3808-EP
PACKAGE
BODY SIZE (NOM)
SOT (6)
2.90 mm x 1.60 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Typical Application Circuit
3.3V
3.3V
50kΩ
3.3V
SENSE VDD
SENSE VDD
SENSE VDD
TPS3808G33
TPS3808G33
TPS3808G33
CT
CT
RESET
RESET
CT
RESET
CT
300ms Delay
(a)
20ms Delay
(b)
Delay (s) = CT (nF) + 0.5 x 10−3 (s)
175
(c)
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS3808-EP
SBVS103D – APRIL 2008 – REVISED DECEMBER 2014
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
4
4
4
4
5
5
7
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Switching Characteristics ..........................................
Typical Characteristics ..............................................
Detailed Description .............................................. 9
7.1 Overview ................................................................... 9
7.2 Functional Block Diagrams ....................................... 9
7.3 Feature Description................................................... 9
7.4 Device Functional Modes.......................................... 9
8
Application and Implementation ........................ 10
8.1 Application Information............................................ 10
8.2 Typical Application .................................................. 13
9 Power Supply Recommendations...................... 15
10 Layout................................................................... 15
10.1 Layout Guidelines ................................................. 15
10.2 Layout Example .................................................... 15
11 Device and Documentation Support ................. 16
11.1 Trademarks ........................................................... 16
11.2 Electrostatic Discharge Caution ............................ 16
11.3 Glossary ................................................................ 16
12 Mechanical, Packaging, and Orderable
Information ........................................................... 16
4 Revision History
Changes from Revision C (September 2008) to Revision D
•
2
Page
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section ................................................................................................. 4
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SBVS103D – APRIL 2008 – REVISED DECEMBER 2014
5 Pin Configuration and Functions
DBV PACKAGE
SOT-23
(TOP VIEW)
RESET
1
6
VDD
GND
2
5
SENSE
MR
3
4
CT
Pin Functions
PIN
I/O
DESCRIPTION
1
O
RESET is an open-drain output that is driven to a low impedance state when RESET is asserted
(either the SENSE input is lower than the threshold voltage (VIT) or the MR pin is set to a logic low).
RESET remains low (asserted) for the reset period after both SENSE is above VIT and MR is set to a
logic high. A pullup resistor from 10 kΩ to 1 MΩ should be used on this pin, and allows the reset pin to
attain voltages higher than VDD.
GND
2
—
Ground
MR
3
I
Driving the manual reset pin (MR) low asserts RESET. MR is internally tied to VDD by a 90kΩ pullup
resistor.
CT
4
I
Reset period programming pin. Connecting this pin to VDD through a 40-kΩ to 200-kΩ resistor or
leaving it open results in fixed delay times (see Switching Characteristics). Connecting this pin to a
ground referenced capacitor ≥ 100 pF gives a user-programmable delay time. See the Selecting the
Reset Delay Time section for more information.
SENSE
5
I
This pin is connected to the voltage to be monitored. If the voltage at this terminal drops below the
threshold voltage VIT, then RESET is asserted.
VDD
6
I
Supply voltage. It is good analog design practice to place a 0.1-μF ceramic capacitor close to this pin.
NAME
NO.
RESET
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6 Specifications
6.1 Absolute Maximum Ratings
Over operating junction temperature range, unless otherwise noted. (1)
MIN
MAX
Input voltage, VDD
–0.3
7.0
CT voltage, VCT
–0.3
VDD + 0.3
Other voltage: VRESET, VMR, VSENSE
–0.3
7
RESET pin current
5
Operating junction temperature, TJ
(2)
Storage temperature, Tstg
(1)
(2)
–55
150
–65
150
UNIT
V
mA
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
As a result of the low dissipated power in this device, it is assumed that TJ = TA.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1)
±3000
Charged device model (CDM), per JEDEC specification JESD22-C101, all
pins (2)
±1000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
VDD
Input supply range
Power-up reset voltage
VOL (max) = 0.2 V, I
NOM
1.7
RESET
= 15 μA
MAX
UNIT
6.5
V
0.8
V
6.4 Thermal Information
TPS3808-EP
THERMAL METRIC
(1)
DBV
UNIT
6 PINS
RθJA
Junction-to-ambient thermal resistance
180.9
RθJC(top)
Junction-to-case (top) thermal resistance
117.8
RθJB
Junction-to-board thermal resistance
27.8
ψJT
Junction-to-top characterization parameter
1.12
ψJB
Junction-to-board characterization parameter
27.3
(1)
4
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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6.5 Electrical Characteristics
1.7 V ≤ VDD ≤ 6.5 V, RLRESET = 100 kΩ, CLRESET = 50 pF, over operating temperature range (TJ = –55°C to +125°C), unless
otherwise noted. Typical values are at TJ = +25°C.
PARAMETER
VDD
Input supply range
IDD
Supply current (current into VDD pin)
VOL
TEST CONDITIONS
Power-up reset voltage (1)
Negative-going input
threshold accuracy
VDD = 6.5 V, RESET not asserted
MR, RESET, CT open
2.7
6.0
1.3 V ≤ VDD < 1.8 V, IOL = 0.4 mA
0.3
1.8 V ≤ VDD ≤ 6.5 V, IOL = 1.0 mA
0.4
RESET
= 15 μA
+2.0%
+1.7%
3.3 V < VIT ≤ 5.0 V
–2.0%
±1.0%
+2.0%
TPS3808G01
1.5%
3.0%
Fixed versions
1.0%
2.5%
70
VSENSE = VIT
Fixed versions
VSENSE = 6.5 V
kΩ
25
μA
300
VIN = 0 V to VDD
5
Other pins
VIN = 0 V to 6.5 V
5
MR logic low input
VIH
MR logic high input
θJA
Thermal resistance, junction-to-ambient
nA
1.7
CT pin
VIL
VIT
90
–25
V RESET = 6.5 V, RESET not asserted
Input capacitance,
any pin
V
0.8
±0.5%
TPS3808G01
V
μA
±1.0%
CIN
(1)
5.0
–1.7%
MR Internal pullup resistance
RESET leakage current
2.4
–2.0%
R MR
IOH
VDD = 3.3 V, RESET not asserted
MR, RESET, CT open
VOL (max) = 0.2 V, I
UNIT
6.5
VIT ≤ 3.3 V
Hysteresis on VIT pin
Input current at
SENSE pin
MAX
TPS3808G01
VHYS
ISENSE
TYP
1.7
Low-level output voltage
VIT
MIN
nA
pF
0
0.3 VDD
0.7 VDD
VDD
V
290
°C/W
The lowest supply voltage (VDD) at which RESET becomes active. Trise(VDD) ≥ 15 μs/V.
6.6 Switching Characteristics
1.7 V ≤ VDD ≤ 6.5 V, RLRESET = 100 kΩ, CLRESET = 50 pF, over operating temperature range (TJ = –55°C to +125°C), unless
otherwise noted. Typical values are at TJ = +25°C.
PARAMETER
tw
Input pulse width to
RESET
TEST CONDITIONS
RESET delay time
20
MR
VIH = 0.7 VDD, VIL = 0.3 VDD
0.00
1
CT = VDD
See Timing Diagram
CT = 100 pF
CT = 180 nF
tpHL
TYP MAX UNIT
VIH = 1.05 VIT, VIL = 0.95 VIT
CT = Open
td
MIN
SENSE
μs
12
20
29
180
300
440
0.75
1.25
1.8
0.7
1.2
1.8
ms
s
Propagation delay
MR to RESET
VIH = 0.7 VDD, VIL = 0.3 VDD
150
ns
High-to-low level RESET
delay
SENSE to RESET
VIH = 1.05 VIT, VIL = 0.95 VIT
20
μs
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VDD
0.8V
0.0V
RESET
tD = Reset Delay
tD
tD
tD
= Undefined State
SENSE
VIT + VHYS
VIT
MR
0.7VDD
0.3VDD
Time
Figure 1. TPS3808 Timing Diagram Showing MR and SENSE Reset Timing
Table 1. Truth Table
6
MR
SENSE > VIT
RESET
L
0
L
L
L
1
H
0
L
H
1
H
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6.7 Typical Characteristics
At TJ = +25°C, VDD = 3.3 V, RLRESET = 100kΩ, and CLRESET = 50pF, unless otherwise noted.
4.0
100
3.5
+125_ C
+85_ C
2.5
2.0
+25_C
1.5
10
RESET Timeout (sec)
IDD (µA)
3.0
1.0
−40°C, +25°C, +125°C
1
0.1
0.01
− 40_ C
0.5
0
0
1
2
3
4
5
6
0.001
0.0001
7
0.001
0.01
VDD (V)
Figure 2. Supply Current vs Supply Voltage
1
10
Figure 3. RESET Timeout Period vs CT
100
Transient Duration below VIT (µs)
10
Normalized RESET Timeout Period (%)
0.1
CT (µF)
8
6
4
2
0
−2
−4
−6
−8
RESET OCCURS
ABOVE THE CURVE
10
1
−10
−50
−30
−10
10
30
50
70
90
110
0
130
5
10
15
20
25
30
35
40
45
50
Overdrive (%VIT)
Temperature (°C)
CT = Open, CT = VDD, CT = Any
Figure 4. Normalized RESET Timeout Period vs
Temperature
Figure 5. Maximum Transient Duration at Sense vs Sense
Threshold Overdrive Voltage
4.5
VOL Low−Level RESET Voltage (V)
1.0
0.8
Normalized VIT (%)
0.6
0.4
0.2
0
−0.2
−0.4
−0.6
−0.8
−1.0
−50
4.0
3.5
3.0
2.5
2.0
VDD = 1.8V
1.5
1.0
0.5
0
−30
−10
10
30
50
70
90
110
130
0
Temperature (°C)
Figure 6. Normalized Sense Threshold Voltage (VIT) vs
Temperature
0.5
1.0
1.5
2.0
2.5
RESET Current (mA)
3.0
3.5
4.0
Figure 7. Low-Level RESET Voltage vs RESET Current
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Typical Characteristics (continued)
At TJ = +25°C, VDD = 3.3 V, RLRESET = 100kΩ, and CLRESET = 50pF, unless otherwise noted.
VOL Low−Level RESET Voltage (V)
0.8
0.7
0.6
0.5
0.4
VDD = 3.3V
0.3
0.2
0.1
VDD = 6.5V
0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
RESET Current (mA)
Figure 8. Low-Level RESET Voltage vs RESET Current
8
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7 Detailed Description
7.1 Overview
The TPS3808 microprocessor supervisory product family is designed to assert a RESET signal when either the
SENSE pin voltage drops below VIT or the manual reset (MR) is driven low. The RESET output remains asserted
for a user-adjustable time after both the manual reset (MR) and SENSE voltages return above the respective
thresholds.
7.2 Functional Block Diagrams
VDD
VDD
VDD
TPS3808G01
Adjustable Voltage
VDD
90k
90k
RESET
MR
SENSE
Reset
Logic
Timer
SENSE
Reset
Logic
Timer
RESET
MR
R1
-
-
CT
+
CT
+
R2
0.4V
VREF
0.4V
VREF
R1 + R2 = 4MW
GND
GND
Adjustable Voltage Version
Fixed Voltage Version
7.3 Feature Description
A broad range of voltage threshold and reset delay time adjustments are available for the TPS3808 device,
allowing these devices to be used in a wide array of applications. Reset threshold voltages can be factory-set
from 0.82 V to 3.3 V or from 4.4 V to 5.0 V, while the TPS3808G01 can be set to any voltage above 0.405 V
using an external resistor divider. Two preset delay times are also user-selectable: connecting the CT pin to VDD
results in a 300 ms reset delay, while leaving the CT pin open yields a 20-ms reset delay. In addition, connecting
a capacitor between CT and GND allows the designer to select any reset delay period from 1.25 ms to 10 s.
7.4 Device Functional Modes
The TPS3808 has two functional modes:
• MR high: in this mode, RESET is high or low depending on the value of the SENSE pin relative to VIT.
• MR low: in this mode, RESET is held low regarldess of the value of the SENSE pin.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The following sections describe in detail how to properly use this device depending on the requirements of the
final application.
8.1.1 SENSE Input
The SENSE input provides a terminal at which any system voltage can be monitored. If the voltage on this pin
drops below VIT, then RESET is asserted. The comparator has a built-in hysteresis to ensure smooth RESET
assertions and de-assertions. It is good analog design practice to put a 1-nF to 10-nF bypass capacitor on the
SENSE input to reduce sensitivity to transients and layout parasitics.
The TPS3808 device is relatively immune to short negative transients on the SENSE pin. Sensitivity to transients
is dependent on threshold overdrive, as shown in the Maximum Transient Duration at Sense vs Sense Threshold
Overdrive Voltage graph (Figure 5) in Typical Characteristics.
The TPS3808G01 can be used to monitor any voltage rail down to 0.405 V using the circuit shown in Figure 9.
VIN
VOUT
VDD
VIT¢ = (1 +
R1
R1
) 0.405
R2
TPS3808G01
SENSE
RESET
1nF
R2
GND
Figure 9. Using the TPS3808G01 to Monitor a User-Defined Threshold Voltage
8.1.2 Selecting the RESET Delay Time
The TPS3808 has three options for setting the RESET delay time as shown in Figure 10. Figure 10a shows the
configuration for a fixed 300-ms typical delay time by tying CT to VDD; a resistor from 40 kΩ to 200 kΩ must be
used. Supply current is not affected by the choice of resistor. Figure 10b shows a fixed 20-ms delay time by
leaving the CT pin open. Figure 10c shows a ground referenced capacitor connected to CT for a user-defined
program time between 1.25 ms and 10 s.
10
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Application Information (continued)
3.3V
3.3V
50kΩ
3.3V
SENSE VDD
SENSE VDD
SENSE VDD
TPS3808G33
TPS3808G33
TPS3808G33
CT
CT
RESET
RESET
CT
RESET
CT
300ms Delay
Delay (s) = CT (nF) + 0.5 x 10−3 (s)
20ms Delay
175
(c)
(b)
(a)
Figure 10. Configuration Used to Set the RESET Delay Time
The capacitor CT should be ≥ 100 pF nominal value in order for the TPS3808xxx to recognize that the capacitor
is present. The capacitor value for a given delay time can be calculated using Equation 1.
C T (nF) = t D (s) – 0.5 × 10 - 3 (s) × 175
(1)
[
]
The reset delay time is determined by the time it takes an on-chip precision 220-nA current source to charge the
external capacitor to 1.23 V. When a RESET is asserted the capacitor is discharged. When the RESET
conditions are cleared, the internal current source is enabled and begins to charge the external capacitor. When
the voltage on this capacitor reaches 1.23 V, RESET is deasserted. Note that a low-leakage type capacitor such
as a ceramic should be used, and that stray capacitance around this pin may cause errors in the reset delay
time.
8.1.3 Manual RESET(MR) Input
The manual reset (MR) input allows a processor or other logic circuits to initiate a reset. A logic low (0.3 VDD) on
MR causes RESET to assert. After MR returns to a logic high and SENSE is above its reset threshold, RESET is
de-asserted after the user defined reset delay expires. Note that MR is internally tied to VDD using a 90-kΩ
resistor so this pin can be left unconnected if MR will not be used.
See Figure 11 for how MR can be used to monitor multiple system voltages. Note that if the logic signal driving
MR does not go fully to VDD, there will be some additional current draw into VDD as a result of the internal pullup
resistor on MR. To minimize current draw, a logic-level FET can be used as illustrated in Figure 12.
1.2V
3.3V
SENSE
V DD
SENSE V DD
TPS3808G12
RESET
CT
GND
TPS3808G33
MR
CT
RESET
GND
V I/O
V CORE
DSP
GPIO
GND
Figure 11. Using MR to Monitor Multiple System Voltages
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Application Information (continued)
3.3V
V DD SENSE
90kW
MR
TPS3808xxx
GND
Figure 12. Using an External MOSFET to Minimize IDD When MR Signal Does Not Go to VDD
8.1.4 RESET Output
RESET remains high (unasserted) as long as SENSE is above its threshold (VIT) and the manual reset (MR) is
logic high. If either SENSE falls below VIT or MR is driven low, RESET is asserted, driving the RESET pin to a
low impedance.
Once MR is again logic high and SENSE is above VIT + VHYS (the threshold hysteresis), a delay circuit is enabled
which holds RESET low for a specified reset delay period. Once the reset delay has expired, the RESET pin
goes to a high impedance state. The pullup resistor from the open-drain RESET to the supply line can be used to
allow the reset signal for the microprocessor to have a voltage higher than VDD (up to 6.5 V). The pullup resistor
should be no smaller than 10 kΩ as a result of the finite impedance of the RESET line.
12
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8.2 Typical Application
A typical application of the TPS3808G33 used with a 3.3 V processor is shown in Figure 13. The open-drain
RESET output is typically connected to the RESET input of a microprocessor. A pullup resistor must be used to
hold this line high when RESET is not asserted. The RESET output is undefined for voltage below 0.8 V, but this
is normally not a problem since most microprocessors do not function below this voltage.
+3.3 V
0.1 µF
1 MŸ
SENSE
VDD
3.3 V PROCESSOR
TPS3808G33
CT
VDD
RESET
RESET
MR
GND
GND
Figure 13. Typical Application of the TPS3808 with a 3.3 V Processor
8.2.1 Design Requirements
The TPS3808 is intended to drive the RESET input of a microprocessor. The RESET pin is pulled high with a 1
MΩ resistor and the reset delay time is controlled by CT depending on the reset requirement times of the
microprocessor. In this case, CT is left open for a typical reset delay time of 20 ms.
8.2.2 Detailed Design Procedure
The main constraint for this application is the reset delay time. In this case, since CT is open, it is set to 20 ms. A
0.1 µF decoupling capacitor is connected to the VDDpin and a 1 MΩ resistor is used to pull-up the RESET pin
high. The MR pin can be connected to an external signal if desired.
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13
TPS3808-EP
SBVS103D – APRIL 2008 – REVISED DECEMBER 2014
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Typical Application (continued)
8.2.3 Application Curve
Transient Duration below VIT (µs)
100
RESET OCCURS
ABOVE THE CURVE
10
1
0
5
10
15
20
25
30
35
40
45
50
Overdrive (%VIT)
Figure 14. Maximum Transient Duration at Sense vs Sense Threshold Overdrive Voltage
14
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TPS3808-EP
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SBVS103D – APRIL 2008 – REVISED DECEMBER 2014
9 Power Supply Recommendations
These devices are designed to operate from an input supply with a voltage range between 1.7 and 6.5 V. Use a
low-impedance power supply to eliminate inaccuracies caused by the current during the voltage reference
refresh.
10 Layout
10.1 Layout Guidelines
Make sure the connection to the VDD pin is low impedance. Place a 0.1-µF ceramic capacitor near the VDD pin.
10.2 Layout Example
The layout example in Figure 15 shows how the TPS3808 is laid out on a PCB for a 20 ms delay.
VDD
VDD
RESET
CIN
GND
SENSE
MR
CT
GND
VIAS USED TO CONNECT PINS FOR APPLICATION SPECIFIC CONNECTIONS
Figure 15. Layout Example for a 20 ms Delay
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11 Device and Documentation Support
11.1 Trademarks
All trademarks are the property of their respective owners.
11.2 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.3 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
16
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS3808G01MDBVTEP
ACTIVE
SOT-23
DBV
6
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
NXS
TPS3808G33MDBVREP
ACTIVE
SOT-23
DBV
6
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
CHK
V62/08607-01XE
ACTIVE
SOT-23
DBV
6
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
NXS
V62/08607-09XE
ACTIVE
SOT-23
DBV
6
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
CHK
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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