TPS3813J25-EP,, TPS3813L30-EP
TPS3813K33-EP, TPS3813I50-EP
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SGLS343A – MAY 2006 – REVISED MAY 2006
PROCESSOR SUPERVISORY CIRCUITS WITH WINDOW-WATCHDOG
FEATURES
APPLICATIONS
•
•
•
•
•
•
•
•
•
•
•
•
(1)
Controlled Baseline
– One Assembly/Test Site, One Fabrication
Site
Extended Temperature Performance of -55°C
to 125°C
Enhanced Diminishing Manufacturing
Sources (DMS) Support
Enhanced Product-Change Notification
Qualification Pedigree (1)
Window-Watchdog With Programmable Delay
and Window Ratio
6-Pin SOT-23 Package
Supply Current of 9 µA (Typ)
Power On Reset Generator With a Fixed
Delay Time of 25 ms
Precision Supply Voltage Monitor 2.5 V, 3 V,
3.3 V, 5 V
Open-Drain Reset Output
•
•
•
Applications Using DSPs, Microcontrollers,
or Microprocessors
Safety Critical Systems
Automotive Systems
Healing Systems
TPS3813
DBV PACKAGE
(TOP VIEW)
WDI
1
6
RESET
GND
2
5
WDR
WDT
3
4
VDD
ACTUAL SIZE
3,00 mm x 3,00 mm
Component qualification in accordance with JEDEC and
industry standards to ensure reliable operation over an
extended temperature range. This includes, but is not limited
to, Highly Accelerated Stress Test (HAST) or biased 85/85,
temperature cycle, autoclave or unbiased HAST,
electromigration, bond intermetallic life, and mold compound
life. Such qualification testing should not be viewed as
justifying use of this component beyond specified
performance and environmental limits.
DESCRIPTION
The TPS3813 family of supervisory circuits provides circuit initialization and timing supervision, primarily for
DSPs and processor-based systems.
During power on, RESET is asserted when supply voltage (VDD) becomes higher than 1.1 V. Thereafter, the
supervisory circuit monitors VDD and keeps RESET active as long as VDD remains below the threshold voltage
(VIT). An internal timer delays the return of the output to the inactive state (high) to ensure proper system reset.
The delay time, td = 25 ms typical, starts after VDD has risen above the threshold voltage (VIT). When the supply
voltage drops below the threshold voltage (VIT), the output becomes active (low) again. No external components
are required. All the devices of this family have a fixed-sense threshold voltage (VIT) set by an internal voltage
divider.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006, Texas Instruments Incorporated
TPS3813J25-EP,, TPS3813L30-EP
TPS3813K33-EP, TPS3813I50-EP
www.ti.com
SGLS343A – MAY 2006 – REVISED MAY 2006
TYPICAL OPERATING CIRCUIT
VDD
0.1 µF
0.1 µF
R
VDD
WDR
VDD
RESET
RESET
TPS3813
WDT
uC
WDI
I/O
GND
CWP
GND
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
DESCRIPTION (CONTINUED)
For safety critical applications the TPS3813 family incorporates a so-called window-watchdog with
programmable delay and window ratio. The upper limit of the watchdog time-out can be set by either connecting
WDT to GND, VDD, or using an external capacitor. The lower limit and thus the window ratio is set by connecting
WDR to GND or VDD. The supervised processor now needs to trigger the TPS3813 within this window not to
assert a RESET.
The product spectrum is designed for supply voltages of 2.5 V, 3 V, 3.3 V, and 5 V. The circuits are available in
a 6-pin SOT-23 package.
The TPS3813 devices are characterized for operation over a temperature range of –55°C to 125°C.
PACKAGE INFORMATION
TA
–55°C to 125°C
DEVICE NAME
THRESHOLD VOLTAGE
MARKING
TPS3813J25MDBVREP
2.25 V
PLEM
TPS3813L30MDBVREP
2.64 V
PLFM
TPS3813K33MDBVREP
2.93 V
PLGM
TPS3813I50MDBVREP
4.55 V
PLHM
ORDERING INFORMATION
TPS381
3
J
25
DBV
R
Reel
Package
Nominal Supply Voltage
Nominal Threshold Voltage
Functionality
Family
TPS3813 FUNCTION/TRUTH
TABLE
VDD > VIT
2
RESET
0
L
1
H
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SGLS343A – MAY 2006 – REVISED MAY 2006
RESET
Oscillator
WDT
Reset Logic
and Timer
Detection
Circuit
VDD
GND
Power to circuitry
Watchdog
Ratio
Detection
R1
+
_
WDR
R2
Bandgap
Voltage
Reference
GND
GND
Rising Edge
Detection
WDI
GND
VDD
VIT
0.6 V
t
td
td
td
RESET
Output Condition
Undefined
Output Condition
Undefined
t
WDI
1st Window
Without Lower
Boundary
t
2nd Window
With Lower
Boundary
3rd Window
With Lower
Boundary
Trigger Pulse
1st Window
Lower Window
Without Lower 2nd Window
1st Window
Boundary
Boundary
With Lower
Without Lower
Boundary
Boundary
3rd Window
With Lower
Boundary
Figure 1. Timing Diagram
The lower boundary of the watchdog window starts with the rising edge of the WDI trigger pulse. At the same
time, all internal timers will be reset. If an external capacitor is used, the lower boundary is impacted due to the
different oscillator frequency. This is described in more detail in the following section. The timing diagram and
especially the shaded boundary is prepared in a nonreal ratio scale to better visualize the description.
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SGLS343A – MAY 2006 – REVISED MAY 2006
Terminal Functions
TERMINAL
NAME
NO.
I/O
DESCRIPTION
GND
2
I
Ground
RESET
6
O
Open-drain reset output
VDD
4
I
Supply voltage and supervising input
WDI
1
I
Watchdog timer input
WDR
5
I
Selectable watchdog window ratio input
WDT
3
I
Programmable watchdog delay input
DETAILED DESCRIPTION
IMPLEMENTED WINDOW-WATCHDOG SETTINGS
There are two different ways to set up the watchdog window. The first way is to use the implemented timing
which is a default setting. Or, the default settings can be activated by wiring the WDT and WDR pin to VDD or
GND. There are a total of four different timings available with these settings which are listed in the table below.
SELECTED OPERATION MODE
WDR = 0 V
WDT = 0 V
WDR = VDD
WDR = 0 V
WDT = VDD
WDR = VDD
WINDOW FRAME
LOWER WINDOW FRAME
Max = 0.3 s
Max = 9.46 ms
Typ = 0.25 s
Typ = 7.86 ms
Min = 0.2 s
Min = 6.27 ms
Max = 0.3 s
Max = 2.43 ms
Typ = 0.25 s
Typ = 2 ms
Min = 0.2 s
Min = 1.58 ms
Max = 3 s
Max = 93.8 ms
Typ = 2.5 s
Typ = 78.2 ms
Min = 2 s
Min = 62.5 ms
Max = 3 s
Max = 23.5 ms
Typ = 2.5 s
Typ = 19.6 ms
Min = 2 s
Min = 15.6 ms
To visualize the values named in the table, a timing diagram (see Figure 2) was prepared. The timing diagram is
used to describe the upper and lower boundary settings. For an application, the important boundaries are the
tboundary,max and twindow,min. Within these values, the watchdog timer should be retriggered to avoid a timeout
condition or a boundary violation in the event of a trigger pulse in the lower boundary. The values in the table
above are typical and worst case conditions. They are valid over the whole temperature range of –55°C to
125°C.
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
In the shaded area of Figure 2, it cannot be predicted if the device will detect a violation or not and release a
reset. This is also the case between the boundary tolerance of tboundary,min and tboundary,max as well as between
twindow,min and twindow,max. It is important to set up the trigger pulses accordingly to avoid violations in these areas.
WDI
Detection of
Rising Edge
tboundary, min
tboundary, max
Window Frame to Reset the WDI
tboundary, typ
twindow, typ
twindow, min
twindow, max
Figure 2. Upper and Lower Boundary Visualization
4
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TIMING RULES OF WINDOW-WATCHDOG
After the reset of the supervisor is released, the lower boundary of the first WDI window is disabled. However,
after the first WDI pulse low-to-high transition is detected, the lower boundary function of the window is enabled.
All further WDI pulses will need to fit into the configured window frame.
PROGRAMMABLE WINDOW-WATCHDOG BY USING AN EXTERNAL CAPACITOR
The upper boundary of the watchdog timer can be set by an external capacitor connected between the WDT pin
and GND. Common consumer electronic capacitors can be used to implement this feature. They should have
low ESR and low tolerances since the tolerances have to be considered if the calculations are performed. The
first formula is used to calculate the upper window frame. After calculating the upper window frame, the lower
boundary can be calculated. As in the last example, the most important values are the tboundary,max and twindow,min.
The trigger pulse has to fit into this window frame.
The external capacitor should have a value between a minimum of 47 pF and a maximum of 63 nF.
SELECTED OPERATION MODE
WDT = external capacitor C(ext)
t
window,typ
+
ǒ
WDR = 0 V and WDR = VDD
Ǔ
C
WINDOW FRAME
(ext)
)1
15.55 pF
twindow,max = 1.25 x twindow,typ
twindow,min = 0.75 x twindow,typ
6.25 ms
(1)
LOWER BOUNDARY CALCULATION
The lower boundary can be calculated based on the values given in the switching characteristics. Additionally,
facts have to be taken into account to verify that the lower boundary is where it is expected. Since the internal
oscillator of the window watchdog is running free, any rising edge at the WDI pin will be taken into account at
the next internal clock cycle. This happens regardless of the external source. Since the shift between internal
and external clock is not known, it is best to consider the worst case condition for calculating this value.
SELECTED OPERATION MODE
LOWER BOUNDARY OF FRAME
tboundary,max = twindow,max / 23.5
WDR = 0 V
tboundary,typ = twindow,typ / 25.8
tboundary,min = twindow,min / 28.7
WDT = external capacitor C(ext)
tboundary,max = twindow,max / 51.6
WDR = VDD
tboundary,typ = twindow,typ / 64.5
tboundary,min = twindow,min / 92.7
WATCHDOG SOFTWARE CONSIDERATIONS
To benefit from the window watchdog feature and help the watchdog timer monitor the software execution more
closely, it is recommended that the watchdog be set and reset at different points in the program rather than
pulsing the watchdog input periodically by using the prescaler of a microcontroller or DSP. Furthermore, the
watchdog trigger pulses should be set to different timings inside the window frame to release a defined reset, if
the program should hang in any subroutine. This allows the window watchdog to detect timeouts of the trigger
pulse as well as pulses that distort the lower boundary.
APPLICATION EXAMPLE
A typical application example (see Figure 3) is used to describe the function of the watchdog in more detail.
To configure the window watchdog function, two pins are provided by the TPS3813. These pins set the window
timeout and ratio.
The window watchdog ratio is a fixed ratio, which determines the lower boundary of the window frame. It can be
configured in two different frame sizes.
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SGLS343A – MAY 2006 – REVISED MAY 2006
If the window watchdog ratio pin (WDR) is set to VDD, Position 1 in Figure 3, then the lower window frame is a
value based on a ratio calculation of the overall window timeout size: For the watchdog timeout pin (WDT)
connected to GND, it is a ratio of 1:124.9, for WDT connected to VDD, it is a ratio of 1:127.7, and for an external
capacitor connected to WDT, it is a ratio of 1:64.5.
If the window watchdog ratio pin (WDR) is set to GND, Position 2, the lower window frame will be a value based
on a ratio calculation of the overall window timeout size: For the watchdog timeout pin (WDT) connected to
GND, it will be a ratio of 1:31.8, for WDT connected to VDD it will be 1:32, and for an external capacitor
connected to WDT it will be 1:25.8.
The watchdog timeout can be set in two fixed timings of 0.25 seconds and 2.5 seconds for the window or can by
programmed by connecting a external capacitor with a low leakage current at WDT.
Example: If the watchdog timeout pin (WDT) is connected to VDD, the timeout will be 2.5 seconds. If the window
watchdog ratio pin (WDR) is set in this configuration to a ratio of 1:127.7 by connecting the pin to VDD, the lower
boundary is 19.6 ms.
VDD
0.1 µF
0.1 µF
VDD
R
Position 1
See Note A
VDD
Position 2
See Note B
WDR
RESET
WDT
Position 5
See Note E
Position 3
See Note C
uC
WDI
GND
VDD
A.
Watchdog window ratio
B.
Watchdog timeout set to typical 2.5 sec
C.
Watchdog timeout programmed by external capacitor
D.
Watchdog timeout set to typical 0.25 sec
Figure 3. Application Example
6
RESET
TPS3813
Position 4
See Note D
C(ext)
VDD
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GND
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SGLS343A – MAY 2006 – REVISED MAY 2006
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
(1)
UNIT
Supply voltage (2)
VDD
7V
RESET
–0.3 V to VDD + 0.3 V
All other pins
(2)
–0.3 V to 7 V
IOL
Maximum low output current
5 mA
IOH
Maximum high output current
–5 mA
IIK
Input clamp current (VI < 0 or VI > VDD)
±20 mA
IOK
Output clamp current (VO < 0 or VO > VDD)
±20 mA
Continuous total power dissipation
See Dissipation Rating Table
TA
Operating free-air temperature range
–55°C to 125°C
Tstg
Storage temperature range
–65°C to 150°C
Soldering temperature
(2)
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to GND. For reliable operation, the device should not be operated at 7 V for more than t = 1000h
continuously.
DISSIPATION RATING TABLE
PACKAGE
TA < 25°C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
DBV
437 mW
3.5 mW/°C
280 mW
227 mW
100
Estimated Years of Life
(1)
260°C
10
1
120
125
130
135
140
145
150
155
160
Continuous TJ − 5C
Figure 4. TPS3813K33DBV Wirebond Life
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SGLS343A – MAY 2006 – REVISED MAY 2006
RECOMMENDED OPERATING CONDITIONS
at specified temperature range
MIN
MAX
VDD
Supply voltage
2
6
UNIT
V
VI
Input voltage
0
VDD + 0.3
V
VIH
High-level input voltage
VIL
Low-level input voltage
∆t/∆V
Input transition rise and fall rate
tw
Pulse width of WDI trigger pulse
TA
Operating free-air temperature range
0.7 x VDD
V
0.3 x VDD
V
100
ns/V
125
°C
50
ns
–55
ELECTRICAL CHARACTERISTICS
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
VOL
TEST CONDITIONS
Low-level output voltage
Power up reset voltage
MIN
0.2
VDD = 3.3 V IOL = 2 mA
0.4
VDD = 6 V, IOL = 4 mA
0.4
VDD ≥ 1.1 V, IOL= 50 µA
(1)
0.2
TPS3813J25
VIT
Negative-going input
threshold
voltage (2)
TPS3813L30
TPS3813K33
TA = 25°C
TA = Full Range
Hysteresis
2.2
2.25
2.3
2.58
2.64
2.7
2.87
2.93
2.8
TPS3813I50
Vhys
4.45
IIL
TPS3813L30
35
TPS3813K33
40
WDI, WDR
WDI = VDD = 6 V, WDR = VDD = 6 V
WDT
WDT = VDD = 6 V, VDD > VIT,
RESET = High
WDI, WDR
WDI = 0 V, WDR = 0 V, VDD = 6 V
Low-level input current
High-level output current
IDD
Supply current
CI
Input capacitance
(1)
(2)
V
V
V
4.65
mV
60
High-level input current
IOH
4.55
30
WDT
3
UNIT
3.1
TPS3813J25
TPS3813I50
IIH
TYP MAX
VDD = 2 V to 6 V, IOL = 500 µA
WDT = 0 V, VDD > VIT, RESET = High
TA = 25°C
TA = Full Range
TA = 25°C
TA = Full Range
TA = 25°C
TA = Full Range
TA = 25°C
TA = Full Range
–100
100
–1000
1000
–100
100
–1000
1000
–100
100
–1000
1000
–100
100
–1000
1000
TA = 25°C
VDD = VOH = 6 V
100
TA = Full Range
1000
VDD = 2 V output unconnected
9
13
VDD = 5 V output unconnected
20
25
VI = 0 V to VDD
5
nA
nA
µA
pF
The lowest supply voltage at which RESET becomes active. tr, VDD ≥ 15 µs/V.
To ensure the best stability of the threshold voltage, a bypass capacitor (ceramic, 0.1 µF) should be placed near the supply terminals.
TIMING REQUIREMENTS
at RL = 1 MΩ, CL = 50 pF, TA = –40°C to 85°C
PARAMETER
tw
8
Pulse width at VDD
TEST CONDITIONS
VDD = VIT– + 0.2 V, VDD = VIT–– 0.2 V
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MIN
3
TYP MAX
UNIT
µs
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TPS3813K33-EP, TPS3813I50-EP
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SGLS343A – MAY 2006 – REVISED MAY 2006
SWITCHING CHARACTERISTICS
at RL = 1 MΩ, CL = 50 pF, TA = -55°C to 125°C
PARAMETER
TEST CONDITIONS
VDD ≥ VIT + 0.2 V, See Figure 1
td
Delay time
tt(out
Watchdog time-out
Upper limit
)
MIN
TA = 25°C
20
TA = Full Range
15
0.25
2.5
(1)
See
s
(2)
ms
1:25.8
WDR = VDD, WDT = 0 V
1:124.9
WDR = VDD, WDT = VDD
1:127.7
WDR = VDD, WDT = programmable
(1)
(2)
ms
1:32
WDR = 0 V, WDT = programmable
VDD to RESET
delay
UNIT
1:31.8
WDR = 0 V, WDT = VDD
tPHL
30
40
WDT = VDD
WDR = 0 V, WDT = 0 V
Propagation (delay)
time, high-to-low-level
output
25
WDT = 0 V
WDT = programmable
Watchdog window ratio
TYP MAX
1:64.5
VIL = VIT - 0.2 V, VIH = VIT + 0.2 V
µs
30
155 pF < C(ext) < 63 nF
(C(ext) ÷ 15.55 pF + 1) x 6.25 ms
TYPICAL CHARACTERISTICS
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
2
20
WDI = GND,
WDT = GND,
WDR = GND
16
85°C
14
12
25°C
10
8
−40°C
6
0°C
4
1.50
25°C
1.25
1
0.75
85°C
0°C
0.50
−40°C
0.25
2
0
VDD = 2 V,
WDI = GND,
WDT = GND,
WDR = GND
1.75
VOL − Low-Level Output Voltage − V
I DD − Supply Current − µ A
18
0
1
2
3
4
5
6
0
0
VDD − Supply Voltage − V
1
2
3
4
5
6
7
IOL − Low-Level Output Current − mA
Figure 5.
Figure 6.
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TYPICAL CHARACTERISTICS (continued)
NORMALIZED INPUT THRESHOLD VOLTAGE
vs
FREE-AIR TEMPERATURE AT VDD
VIT − Normalized Input Threshold Voltage − V (25 ° C)
INPUT CURRENT
vs
INPUT VOLTAGE AT WDT
1000
800
I − Input Current − nA
600
25°C
400
85°C
200
0°C
0
−200
−40°C
−400
I
VDD = 6 V,
WDI = GND,
WDR = GND
−600
−800
−1000
0
1
2
3
4
5
6
1.001
1.000
0.999
0.998
0.997
WDI = Triggered,
WDR = GND,
WDT = GND
0.996
0.995
−40
−20
0
Figure 7.
Figure 8.
t W − Minimum Pulse Duration at V DD − µ s
20
MINIMUM PULSE DURATION AT VDD
vs
VDD THRESHOLD OVERDRIVE VOLTAGE
18
16
14
12
10
8
6
4
2
0
0
40
60
TA − Free-Air Temperature At VDD − °C
VI − Input Voltage at WDT − V
0.2
0.4
0.6
0.8
1
1.2
VDD − Threshold Overdrive Voltage − V
Figure 9.
10
20
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80
PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
2T13K33MDBVREPG4
ACTIVE
SOT-23
DBV
6
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
PLGM
TPS3813K33MDBVREP
ACTIVE
SOT-23
DBV
6
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
PLGM
V62/06627-01XE
ACTIVE
SOT-23
DBV
6
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
PLGM
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of