TPS3836E18-EP / J25-EP / H30-EP / L30-EP / K33-EP
TPS3837E18-EP / J25-EP / L30-EP / K33-EP
TPS3838E18-EP / J25-EP / L30-EP / K33-EP
www.ti.com.................................................................................................................................................... SGLS322D – MAY 2006 – REVISED NOVEMBER 2008
NANOPOWER SUPERVISORY CIRCUITS
FEATURES
1
•
•
•
•
•
•
•
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
Supply Current of 220 nA (Typ)
Precision Supply Voltage Supervision Range:
1.8 V, 2.5 V, 3 V, 3.3 V
Power-On Reset Generator With Selectable
Delay Time of 10 ms or 200 ms
Push/Pull RESET Output (TPS3836), RESET
Output (TPS3837), or
Open-Drain RESET Output (TPS3838)
Manual Reset
5-Pin SOT-23 Package
SUPPORTS DEFENSE, AEROSPACE,
AND MEDICAL APPLICATIONS
•
•
•
•
•
•
•
TPS3836, TPS3838
DBV PACKAGE
(TOP VIEW)
CT
1
GND
2
MR
3
5
VDD
4
RESET
TPS3837
DBV PACKAGE
(TOP VIEW)
CT
1
GND
2
MR
3
5
VDD
4
RESET
Controlled Baseline
One Assembly/Test Site
One Fabrication Site
Available in Military (–55°C/125°C)
Temperature Range (1)
Extended Product Life Cycle
Extended Product-Change Notification
Product Traceability
APPLICATIONS
•
•
•
•
•
(1)
Applications Using Automotive Low-Power
DSPs, Microcontrollers, or Microprocessors
Battery-Powered Equipment
Intelligent Instruments
Wireless Communication Systems
Automotive Systems
Custom temperature ranges available
DESCRIPTION
The TPS3836, TPS3837, TPS3838 families of supervisory circuits provide circuit initialization and timing
supervision, primarily for digital signal processing (DSP) and processor-based systems.
During power on, RESET is asserted when the supply voltage VDD becomes higher than 1.1 V. Thereafter, the
supervisory circuit monitors VDD and keeps RESET output active as long as VDD remains below the threshold
voltage (VIT). An internal timer delays the return of the output to the inactive state (high) to ensure proper system
reset. The delay time starts after VDD has risen above VIT.
When CT is connected to GND, a fixed delay time of typical 10 ms is asserted. When connected to VDD, the
delay time is typically 200 ms.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006–2008, Texas Instruments Incorporated
TPS3836E18-EP / J25-EP / H30-EP / L30-EP / K33-EP
TPS3837E18-EP / J25-EP / L30-EP / K33-EP
TPS3838E18-EP / J25-EP / L30-EP / K33-EP
SGLS322D – MAY 2006 – REVISED NOVEMBER 2008.................................................................................................................................................... www.ti.com
When the supply voltage drops below VIT, the output becomes active (low) again.
All the devices of this family have a fixed-sense VIT set by an internal voltage divider.
The TPS3836 has an active-low push-pull RESET output. The TPS3837 has active-high push-pull RESET, and
the TPS3838 integrates an active-low open-drain RESET output.
TPS3836K33
VDD
MSP430
VCC
CT
Xin
RESET
MR
T
RST
Xout
GND
VSS
Quartz
32 kHz
Lithium
Battery
3.6 V
Figure 1. Typical Operating Circuit
The product spectrum is designed for supply voltages of 1.8 V, 2.5 V, 3 V, and 3.3 V. The circuits are available in
a 5-pin SOT-23 package. The TPS3836, TPS3837, and TPS3838 families are characterized for operation over a
temperature range of –55°C to 125°C.
2
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Copyright © 2006–2008, Texas Instruments Incorporated
Product Folder Link(s): TPS3836E18-EP / J25-EP / H30-EP / L30-EP / K33-EP TPS3837E18-EP / J25-EP / L30-EP /
K33-EP TPS3838E18-EP / J25-EP / L30-EP / K33-EP
TPS3836E18-EP / J25-EP / H30-EP / L30-EP / K33-EP
TPS3837E18-EP / J25-EP / L30-EP / K33-EP
TPS3838E18-EP / J25-EP / L30-EP / K33-EP
www.ti.com.................................................................................................................................................... SGLS322D – MAY 2006 – REVISED NOVEMBER 2008
ORDERING INFORMATION
TA
–55°C to 125°C
(1)
ORDERABLE PART
NUMBER (1)
THRESHOLD VOLTAGE
SYMBOL
TPS3836J25MDBVTEP
2.25 V
PKRM
TPS3836L30MDBVREP
2.64 V
BTX
TPS3837K33MDBVREP
2.93 V
PKZM
DBVR indicates reel of 3000 parts, DBVT indicates tape of 250 parts.
ORDERING INFORMATION
TPS383 6 E 18 M DBV R/T EP
EP Designator
Reel/Tape
Package
M-Temperature Designator
Nominal Supply Voltage
Typical Reset Threshold Voltage
Functionality
Family
FUNCTION TABLE
(1)
(2)
RESET
(1)
RESET (2)
MR
VDD > VIT
L
0
L
H
L
1
L
H
H
0
L
H
H
1
H
L
TPS3836 and TPS3838
TPS3837
Copyright © 2006–2008, Texas Instruments Incorporated
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K33-EP TPS3838E18-EP / J25-EP / L30-EP / K33-EP
3
TPS3836E18-EP / J25-EP / H30-EP / L30-EP / K33-EP
TPS3837E18-EP / J25-EP / L30-EP / K33-EP
TPS3838E18-EP / J25-EP / L30-EP / K33-EP
SGLS322D – MAY 2006 – REVISED NOVEMBER 2008.................................................................................................................................................... www.ti.com
FUNCTIONAL BLOCK DIAGRAM
VDD
R3
CT
MR
C1
R1
+
S1
Reset Logic
and Timer
−
RESET (TPS3837-Push-Pull)
RESET (TPS3836-Push-Pull
TPS3838-Open-Drain)
R2
C2
S2
Band-Gap
Reference
S3
C3
Refresh
Timer
GND
4
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Copyright © 2006–2008, Texas Instruments Incorporated
Product Folder Link(s): TPS3836E18-EP / J25-EP / H30-EP / L30-EP / K33-EP TPS3837E18-EP / J25-EP / L30-EP /
K33-EP TPS3838E18-EP / J25-EP / L30-EP / K33-EP
TPS3836E18-EP / J25-EP / H30-EP / L30-EP / K33-EP
TPS3837E18-EP / J25-EP / L30-EP / K33-EP
TPS3838E18-EP / J25-EP / L30-EP / K33-EP
www.ti.com.................................................................................................................................................... SGLS322D – MAY 2006 – REVISED NOVEMBER 2008
TIMING DIAGRAM
A
B
C
D
E
F
G
VDD
VIT
< 1.1 V
t
MR
t
RESET
t
Undefined
Output
td
td
td
Undefined
Output
Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
VDD
Supply voltage (2)
All other pins (2)
(1)
7V
–0.3 V to 7 V
IOL
Maximum low output current
5 mA
IOH
Maximum high output current
–5 mA
IIK
Input clamp current (VI < 0 or VI > VDD)
±10 mA
IOK
Output clamp current (VO < 0 or VO > VDD)
TA
Operating free-air temperature range
–55°C to 125°C
Tstg
Storage temperature range
–65°C to 150°C
TJ
Maximum junction temperature
150°C
Soldering temperature
260°C
(1)
(2)
±10 mA
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to GND. For reliable operation, the device must not be continuously operated at 7 V for more than
t = 1000 h.
Copyright © 2006–2008, Texas Instruments Incorporated
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K33-EP TPS3838E18-EP / J25-EP / L30-EP / K33-EP
5
TPS3836E18-EP / J25-EP / H30-EP / L30-EP / K33-EP
TPS3837E18-EP / J25-EP / L30-EP / K33-EP
TPS3838E18-EP / J25-EP / L30-EP / K33-EP
SGLS322D – MAY 2006 – REVISED NOVEMBER 2008.................................................................................................................................................... www.ti.com
Thermal Resistance Table
RESISTANCE
HIGH
LOW
θJC (°C/W)
130.9
148.1
θJA (°C/W)
205.6
347
Recommended Operating Conditions
VDD
Supply voltage
VI
Input voltage
VIH
High-level input voltage
VIL
Low-level input voltage
Δt/Δv
Input transition rise and fall rate at MR
TA
Operating free-air temperature
MIN
MAX
1.6
6
UNIT
V
0
VDD + 0.3
V
0.7 × VDD
V
0.3 × VDD
–55
V
100
ns/V
125
°C
MAX
UNIT
Electrical Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
VOH
VOL
High-level output
voltage
Low-level output
voltage
Power-up reset
voltage (1)
VIT
Negative-going
input threshold
voltage (2)
TEST CONDITIONS
RESET
(TPS3836)
VDD = 3.3 V, IOH = –2 mA
RESET
(TPS3837)
VDD = 2 V, IOH = –1 mA
RESET
(TPS3836/8)
VDD = 2 V, IOL = 1 mA
RESET
(TPS3837)
VDD = 3.3 V, IOL = 2 mA
TPS3836/8
VDD ≥ 1.1 V, IOL = 50 µA
TPS3837
IIH
Low-level input
current
IOH
High-level output
current
(1)
(2)
(3)
6
V
VDD = 3.3 V, IOH = –2 mA
VDD = 3.3 V, IOL = 2 mA
0.4
VDD ≥ 1.1 V, IOH = –50 µA
0.2
TA = 25°C
0.8 × VDD
TA = Full range
0.6 × VDD
V
1.71
1.73
2.16
2.25
2.31
TPS383xH30
2.7
2.79
2.85
TPS383xL30
2.54
2.64
2.71
TA = 25°C
2.82
2.93
3.1
TA = Full range
2.72
2.93
3.2
MR
(3)
MR
1.7 V < VIT < 2.5 V
30
2.5 V < VIT < 3.5 V
40
3.5 V < VIT < 5 V
50
MR = 0.7 × VDD, VDD = 6 V
–30
–60
–90
TA = Full range
–20
–60
–120
MR = 0 V, VDD = 6 V
CT
CT = 0 V, VDD = 6 V
TPS3838
VDD = VIT + 0.2 V, VOH = VDD
–25
TA = 25°C
TA = Full range
25
–130
–200
–340
–90
–200
–350
–25
V
mV
TA = 25°C
CT = VDD = 6 V
(3)
V
VDD = 6 V, IOL = 3 mA
1.64
CT
IIL
0.8 × VDD
TPS383xJ25
Hysteresis at VDD input
High-level input
current
VDD = 6 V, IOH = –3 mA
TYP
TPS383xE18
TPS383xK33
Vhys
MIN
µA
nA
µA
25
nA
25
nA
The lowest voltage at which RESET output becomes active, tr, VDD ≥ 15 µs/V
To ensure best stability of the threshold voltage, a bypass capacitor (ceramic, 0.1 µF) should be placed near the supply terminal.
If manual reset is unused, MR should be connected to VDD to minimize current consumption.
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Product Folder Link(s): TPS3836E18-EP / J25-EP / H30-EP / L30-EP / K33-EP TPS3837E18-EP / J25-EP / L30-EP /
K33-EP TPS3838E18-EP / J25-EP / L30-EP / K33-EP
TPS3836E18-EP / J25-EP / H30-EP / L30-EP / K33-EP
TPS3837E18-EP / J25-EP / L30-EP / K33-EP
TPS3838E18-EP / J25-EP / L30-EP / K33-EP
www.ti.com.................................................................................................................................................... SGLS322D – MAY 2006 – REVISED NOVEMBER 2008
Electrical Characteristics (continued)
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VDD > VIT, VDD < 3 V
IDD
Supply current
VDD > VIT, VDD > 3 V
VDD < VIT
MIN
TA = 25°C
Input capacitance at MR, CT
MAX
220
500
TA = Full range
600
TA = 25°C
250
550
TA = Full range
UNIT
nA
650
TA = 25°C
10
25
TA = Full range
30
Internal pullup resistor at MR
CI
TYP
VI = 0 V to VDD
µA
33
kΩ
5
pF
Timing Requirements
RL = 1 MΩ, CL = 50 pF, TA = 25°C
PARAMETER
tw
Pulse width
TEST CONDITIONS
TYP
UNIT
At VDD
VIH = VIT + 0.2 V, VIL = VIT – 0.2 V
6
µs
At MR
VDD ≥ VIT + 0.2 V, VIL = 0.3 × VDD, VIH = 0.7 × VDD
1
µs
Switching Characteristics
RL = 1 MΩ, CL = 50 pF, TA = 25°C
PARAMETER
TEST CONDITIONS
VDD ≥ VIT + 0.2 V, MR = 0.7 × VDD,
See timing diagram
td
Delay time
tPHL
Propagation (delay)
time, high- to low-level
output
VDD to RESET delay
(TPS3836,
TPS3838)
tPLH
MIN
CT = GND
CT = VDD
5
TYP MAX
10
15
200
UNIT
ms
VIL = VIT – 0.2 V, VIH = VIT + 0.2 V
10
VIL = 1.6 V
50
Propagation (delay)
time, low- to high-level
output
VIL = VIT – 0.2 V, VIH = VIT + 0.2 V
VDD to RESET delay
(TPS3837)
VIL = 1.6 V
10
tPHL
Propagation (delay)
time, high- to low-level
output
MR to RESET delay
(TPS3836,
TPS3838)
VDD ≥ VIT + 0.2 V, VIL = 0.3 × VDD, VIH = 0.7 × VDD
0.3
µs
tPLH
Propagation (delay)
time, low- to high-level
output
MR to RESET delay
(TPS3837)
VDD ≥ VIT + 0.2 V, VIL = 0.3 × VDD, VIH = 0.7 × VDD
0.3
µs
Copyright © 2006–2008, Texas Instruments Incorporated
50
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K33-EP TPS3838E18-EP / J25-EP / L30-EP / K33-EP
µs
µs
7
TPS3836E18-EP / J25-EP / H30-EP / L30-EP / K33-EP
TPS3837E18-EP / J25-EP / L30-EP / K33-EP
TPS3838E18-EP / J25-EP / L30-EP / K33-EP
SGLS322D – MAY 2006 – REVISED NOVEMBER 2008.................................................................................................................................................... www.ti.com
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
IDD
Supply current
vs Supply voltage
2
IMR
Manual reset current
vs Manual reset voltage
3
VOL
Low-level output voltage
vs Low-level output current
4
VOH
High-level output voltage
vs High-level output current
5
Normalized reset threshold voltage
vs Free-air temperature
6
Minimum pulse duration at VDD
vs VDD threshold overdrive
7
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
MANUAL RESET CURRENT
vs
MANUAL RESET VOLTAGE
100
10
MR = Open
CT = GND
IMR − Manual Reset Current − µA
TA = 85°C
IDD − Supply Current − µA
8
TA = 25°C
6
TA = 0°C
4
TA = −40°C
2
0
0
2
4
VDD − Supply Voltage − V
Figure 2.
8
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6
VDD = 6 V
CT = GND
0
TA = −40°C
−100
TA = 0°C
−200
TA = 25°C
−300
TA = 85°C
−400
−500
−2
0
2
4
6
VMR − Manual Reset Voltage − V
Figure 3.
Copyright © 2006–2008, Texas Instruments Incorporated
Product Folder Link(s): TPS3836E18-EP / J25-EP / H30-EP / L30-EP / K33-EP TPS3837E18-EP / J25-EP / L30-EP /
K33-EP TPS3838E18-EP / J25-EP / L30-EP / K33-EP
TPS3836E18-EP / J25-EP / H30-EP / L30-EP / K33-EP
TPS3837E18-EP / J25-EP / L30-EP / K33-EP
TPS3838E18-EP / J25-EP / L30-EP / K33-EP
www.ti.com.................................................................................................................................................... SGLS322D – MAY 2006 – REVISED NOVEMBER 2008
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
2.0
VDD = 2 V
MR = Open
CT = GND
VOH − High-Level Output Voltage − V
VOL − Low-Level Output Voltage − V
2.0
1.5
TA = 25°C
1.0
TA = 85°C
TA = 0°C
0.5
TA = −40°C
0.0
VDD = 2 V
MR = Open
CT = GND
1.5
TA = 85°C
TA = 25°C
1.0
TA = 0°C
0.5
TA = −40°C
0.0
0
1
2
3
4
5
6
7
0
1
IOL − Low-Level Output Current − mA
3
4
Figure 4.
Figure 5.
NORMALIZED RESET THRESHOLD VOLTAGE
vs
FREE-AIR TEMPERATURE
MINIMUM PULSE DURATION AT VDD
vs
VDD THRESHOLD OVERDRIVE
1.001
MR = Open
CT = GND
TA = 25°C
20
1
0.999
0.998
0.997
5
22
Minimum Pulse Duration at VDD − µs
Normalized Reset Threshold Voltage − V
2
IOH − High-Level Output Current − mA
CT = GND
MR = Open
0.996
18
16
14
12
10
8
6
4
2
0.995
−40
−15
10
35
60
TA − Free-Air Temperature − °C
Figure 6.
Copyright © 2006–2008, Texas Instruments Incorporated
85
0
0
0.2
0.4 0.6
0.8
1
1.2 1.4
1.6 1.8
2
VDD − Threshold Overdrive − V
Figure 7.
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K33-EP TPS3838E18-EP / J25-EP / L30-EP / K33-EP
9
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS3836J25MDBVTEP
ACTIVE
SOT-23
DBV
5
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
PKRM
TPS3836L30MDBVREP
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
BTX
TPS3837K33MDBVREP
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
PKZM
TPS3837K33QDBVREP
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
PLSQ
V62/06637-09XE
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
PLSQ
V62/06637-15XE
ACTIVE
SOT-23
DBV
5
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
PKRM
V62/06637-17XE
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
BTX
V62/06637-22XE
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
PKZM
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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