TPS40131
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SLVS635 – FEBRUARY 2007
TWO-PHASE, SYNCHRONOUS BUCK CONTROLLER
WITH INTEGRATED MOSFET DRIVERS
FEATURES
APPLICATIONS
•
•
•
•
•
•
Point-of-Load Converter
Graphic Cards
Internet Servers
Networking Equipment
Telecommunications Equipment
DC Power Distributed Systems
SW2
PGND
LDRV2
VIN5
LDRV1
HDRV1
SW1
HDRV2
BOOT2
3
UVLO
4
21
BP5
5
20
AGND
6
19
CS2
CSRT1
7
18
CSRT2
COMP
8
17
9 10 11 12 13 14 15 16
DIFFO
CS1
RT
PGOOD
VOUT
GSNS
ILIM
SS
22
EN/SYNC
2
23
BP8
•
•
•
•
•
OVSET
32 31 30 29 28 27 26 25
24
1
VDD
•
•
BOOT1
FB
•
RHB PACKAGE
(TOP VIEW)
+EA
•
•
Supports 5-V Output
Two-Phase Interleaved Operation
Operates With Pre-Biased Outputs
1-V to 40-V Power Stage Operation Range
Requires VIN5 @ 50 mA (typ) Depending on
External MOSFETs and Switching
Frequency
10-μA Shutdown Current
Programmable Switching Frequency up to 1
MHz/Phase
Current Mode Control with Forced Current
Sharing
Better than 1% Internal 0.7-V Reference
Resistive Divider Sets Direct Output Over
Voltage Threshold.
Programmable Input Undervoltage Lockout
True Remote Sensing Differential Amplifier
Resistive or Inductor’s DCR Current Sensing
32-Pin QFN Package
Can Be Used with TPS40120 to Provide a 6-Bit
Digitally Controlled Output
VREF
•
•
•
•
•
DESCRIPTION
The TPS40131 is a two-phase synchronous buck
controller that is optimized for low-output voltage,
high-output current applications powered from a
supply between 1 V and 40 V. A multi-phase
converter offers several advantages over a single
power stage including lower current ripple on the
input and output capacitors, faster transient response
to load steps, improved power handling capabilities,
and higher system efficiency.
Each phase can be operated at a switching
frequency up to 1 MHz, resulting in an effective
ripple frequency of up to 2 MHz at the input and the
output. The two phases operates 180 degrees
out-of-phase.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2007, Texas Instruments Incorporated
TPS40131
www.ti.com
SLVS635 – FEBRUARY 2007
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
SIMPLIFIED APPLICATION DIAGRAM
CS1
CSRT1
CSRT2
CS2
VOUT
VIN1
VIN1
5V
5V
32
31
30
29
28
27
26
25
HDRV1
SW1
VIN5
LDRV1
PGND
LDRV2
SW2
HDRV2
5V
VOUT
1
BOOT`
BOOT2 24
2
OVSET
SS 23
3
VOUT
4
GSNS
5
DIFFO
CS1
6
CS1
CSRT1
7
CSRT1
CSRT2 18
8
COMP
RT 17
VOUT
5 V VIN1
UVLO 22
LOAD
BP5 21
TPS40131
AGND 20
VREF
+EA
FB
VDD
BP8
EN/SYNC
ILIM
PGOOD
CS2 19
9
10
11
12
13
14
15
16
CS2
CSRT2
VREF
UDG-07030
2
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TPS40131
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SLVS635 – FEBRUARY 2007
ORDERING INFORMATION
TA
PACKAGE
-40°C to 85°C
Plastic QFN(RHB)
PART NUMBER
TAPE AND REEL
QUANTITY
TPS40131RHBT
250
TPS40131RHBR
3000
ABSOLUTE MAXIMUM RATING
over operating free-air temperature range unless otherwise noted
TPS40131
VDD
-1 to 30
DIFFO, VOUT
Input voltage range
VBP8
SW1, SW2
-1 to 44
BP8
-1 to 10
BOOT1, BOOT2, HDRV1, HDRV2
All other pins
Sourcing current
UNITS
V
-0.3 to VSW + 6.0
-0.3 to 6.0
RT
200
TJ
Operating junction temperature range
-40 to 125
Tstg
Storage temperature
-55 to 150
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
μA
°C
260
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range unless otherwise noted (1)
TPS40131
Input voltage range
VDD
4.5 to 28
DIFFO, VOUT
(VBP8-1)
SW1, SW2
-1 to 44
BP8
-1 to 8
BOOT1, BOOT2, HDRV1, HDRV2
All other pins
Sourcing current
V
-0.3 to VSW + 5.5
-0.3 to 5.5
RT
200
TJ
Operating junction temperature range
-40 to 85
Tstg
Storage temperature
-55 to 150
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
(1)
UNITS
μA
°C
260
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
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TPS40131
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SLVS635 – FEBRUARY 2007
ELECTRICAL CHARACTERISTICS
TA = -40°C to 85°C, VIN = 5.0 V, VDD = 12.0 V, RRT = 64.9 kΩ, TJ = TA (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
4.5
5.0
5.8
5
μA
1.0
2.0
mA
5.0
5.5
3
5
4.25
4.45
VIN5 INPUT SUPPLY
VIN
Operating voltage range, VIN5
IIN
Shutdown current, VIN5
EN/SYNC = GND
Operating current
Outputs switching, No load
V
BP5 INPUT SUPPLY
Operating voltage range
IBP5
Operating current
4.3
Outputs switching, no external FETs
Turn-on BP5 rising
Turn-off hysteresis
VDD
INPUT SUPPLY
BP8VBP8
Output Voltage
3.90
(1)
150
4.5
Internal load < 1 mA, No external load
V
mA
V
mV
28
7.5
V
V
OSCILLATOR/SYNCHRONIZATION
Phase frequency accuracy
RT = 64.9 kΩ
355
400
RT = 64.9 kΩ, 0°C ≤ TJ ≤ 85°C
360
400
455
440
Phase frequency set range (1)
100
1200
Synchronization frequency
range (1)
800
9600
Synchronization input
threshold (1)
VBP5/2
kHz
V
EN/SYNC
Enable threshold
Pulse width > 50 ns
0.8
Voltage capability (1)
1.0
1.5
VBP5
V
PWM
Maximum duty cycle per
channel (1)
87.5%
Minimum duty cycle per
channel (1)
0
VREF
Voltage reference
ILOAD = 100 uA
0.687
0.700
0.709
V
ERROR AMPLIFIER
VFB
Voltage feedback, trimmed
(including differential amplifier)
0.691
0.700
0.705
VFB
Voltage feedback, without
differential amplifier
0.687
0.700
0.710
CMRR
Input common mode range (1)
0.0
0.7
2.0
55
200
Input bias current
VFB = 0.7 V
Input offset voltage
nA
V
ISRC
Output source current
VCOMP = 1.1 V, VFB = 0.6 V
1
2
ISINK
Output sink current
VCOMP = 1.1 V, VFB =VBP5
1
2
VOH
High-level output voltage
ICOMP = -1 mA
2.5
2.9
VOL
low-level output voltage
ICOMP = 1 mA
GBW
Gain bandwidth (1)
3
5
MHz
AVOL
Open loop gain (1)
60
90
dB
(1)
4
0
V
Ensured by design. Not production tested.
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0.5
mA
0.8
V
TPS40131
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SLVS635 – FEBRUARY 2007
ELECTRICAL CHARACTERISTICS (continued)
TA = -40°C to 85°C, VIN = 5.0 V, VDD = 12.0 V, RRT = 64.9 kΩ, TJ = TA (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
3.0
5.0
7.0
μA
500
Ω
0.95
1.00
1.05
V
-15
-3
10
SOFT START
ISS
Soft-start source current
RSS
Soft-start pull down resistance
VSS
Fault enable threshold voltage
32 clocks after EN/SYNC before SS current
begins
CURRENT SENSE AMPLIFIER
Input offset voltage
CS1, CS2
Gain transfer to PWM
comparator
-100 mV ≤ VCS≤ 100 mV, VCSRT = 1.5 V
Gain variance between phases
VCS - VCSRTn = 100 mV
Input offset variance between
phases
VCS = 0 V
Input common mode
Bandwidth
(1)
(1)
5
mV
V/V
-6%
0
6%
-6
0
6
0
1
VBP8-0.7
18
mV
V
MHz
DIFFERENTIAL AMPLIFIER
Gain
CMRR
1
Gain tolerance
VOUT = 5.5 V vs VOUT = 0.7 V, VGSNS = 0 V
Common mode rejection ratio
0.7 V≤ VOUT ≤ 5.5 V
Output source current
VOUT - VGSNS = 2.0 V, VDIFFO ≥ 1.95 V
2
4
Output sink current
VOUT - VGSNS = 2.0 V, VDIFFO ≥ 2.05 V
2
4
Bandwidth (1)
-0.5%
V/V
0.5%
50
dB
mA
5
MHz
Input impedance, non-inverting (1) VOUT to GND
40
Input impedance, inverting (1)
40
VGSNS to VDIFFO
kΩ
GATE DRIVERS
Source on-resistance, HDRV1,
HDRV2
VBOOT1 = 5 V, VBOOT2 = 5 V, VSW1 = 0 V,
VSW2 = 0 V, Sourcing 100 mA
1.0
2.0
3.5
Sink on-resistance, HDRV1,
HDRV2
VBOOT1 = 5 V, VBOOT2 = 5 V, VVIN5 = 5 V,
VSW1 = 0 V, VSW2 = 0 V, Sinking 100 mA
0.5
1.0
2.0
Source on-resistance, LDRV1,
LDRV2
VVIN5 = 5 V, VSW1 = 0 V, VSW2 = 0 V,
Sourcing 100 mA
1
2
3.5
Sink on-resistance, LDRV1,
LDRV2
VVIN5 = 5 V, VSW1 = 0 V, VSW2 = 0 V,
Sinking 100 mA
0.30
0.75
1.50
tRISE
Rise time, HDRV (1)
CLOAD = 3.3 nF
25
75
tFALL
Fall time, HDRV (1)
CLOAD = 3.3 nF
25
75
CLOAD = 3.3 nF
25
75
CLOAD = 3.3 nF
25
60
ns
SW falling to LDRV rising
50
mV
(1)
tRISE
Rise time, LDRV
tFALL
Fall time, LDRV (1)
tDEAD
Dead time (1)
tON
Minimum controllable on-time (1)
Ω
Ω
LDRV falling to SW rising
30
CLOAD = 3.3 nF
150
OUTPUT UNDERVOLTAGE FAULT
Undervoltage fault threshold
VFB relative to GND
560
588
610
-20%
-16%
-13%
VOVSET relative to GND
800
820
840
VOVSET relative to VVREF
15%
16%
20%
VFB relative to VVREF
OUTPUT OVERVOLTAGE SET
Overvoltage threshold
(1)
mV
Ensured by design. Not production tested.
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TPS40131
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SLVS635 – FEBRUARY 2007
ELECTRICAL CHARACTERISTICS (continued)
TA = -40°C to 85°C, VIN = 5.0 V, VDD = 12.0 V, RRT = 64.9 kΩ, TJ = TA (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
0.4
0.5
0.6
UNIT
RAMP
Ramp amplitude
(1)
Ramp valley (1)
1.4
V
POWER GOOD
PGOOD high threshold
VFB relative to VREF
10%
14%
PGOOD low threshold
VFB relative to VREF
-14%
-10%
VOL
Low-level output voltage
IPGOOD = 4 mA
ILEAK
PGOOD bias current
VPGOOD = 5.0 V
0.35
0.60
V
50
80
μA
1.0
1.1
INPUT UVLO PROGRAMMABLE
Input threshold voltage, turn-on
0.9
Input threshold voltage, turn-off
(1)
6
0.810
Ensured by design. Not production tested.
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TPS40131
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SLVS635 – FEBRUARY 2007
SW2
HDRV2
PGND
LDRV2
32 31 30 29 28 27 26 25
24
1
BOOT2
BP5
5
20
AGND
6
19
CS2
CSRT1
7
18
CSRT2
COMP
8
17
9 10 11 12 13 14 15 16
VREF
CS1
RT
PGOOD
DIFFO
ILIM
4
EN/SYNC
UVLO
21
BP8
3
VOUT
GSNS
VDD
SS
22
FB
2
23
+EA
OVSET
VIN5
LDRV1
HDRV1
BOOT1
SW1
RHB PACKAGE
(TOP VIEW)
Terminal Functions
TERMINAL
NAME
NO.
I/O
DESCRIPTION
AGND
20
-
Low noise ground connection to the device.
BOOT1
1
I
Provides a bootstrapped supply for the high-side FET driver for PWM1, enabling the gate of the high-side
FET to be driven above the input supply rail. Connect a capacitor from this pin to SW1 pin and a Schottky
diode from this pin to VIN5.
BOOT2
24
I
Provides a bootstrapped supply for the high-side FET driver for PWM2, enabling the gate of the high-side
FET to be driven above the input supply rail. Connect a capacitor from this pin to SW2 pin and a Schottky
diode from this pin to VIN5.
BP5
21
O
Filtered input from the VIN5 pin. A 10-Ω resistor should be connected between VIN5 and BP5 and a
1.0-μF ceramic capacitor should be connected from this pin to ground.
BP8
13
O
Output of the LDO that powers the differential amplifer and the current sense amplifiers. The voltage is
approximately (VVDD -0.2 V) until the output regulates at approximately 7.5 V. Decouple this pin with a
minimum capacitance of 1.0-μF to GND.
COMP
8
O
Output of the error amplifier. The voltage at this pin determines the duty cycle for the PWM.
CS1
6
I
CS2
19
I
These pins are used to sense the inductor phase current. Inductor current can be sensed with an external
current sense resistor or by using an external R-C circuit and the inductor's DC resistance. The traces for
these signals must be connected directly at the current sense element. See Layout Guidelines for more
information.
CSRT1
7
O
CSRT2
18
O
DIFFO
5
O
Output of the differential amplifier. The voltage at this pin represents the true output voltage without IR
drops that result from high-current in the PCB traces. The VOUT and GSNS pins must be connected
directly at the point of load where regulation is required. See Layout Guidelines for more information.
+EA
10
I
This is the input to the non-inverting input of the Error Amplifier. This pin is normally connected to the
VREF pin and is the voltage that the feedback loop regulates to.
EN/SYNC
14
I
A logic high signal on this input enables the controller operation. A pulsing signal to this pin synchronizes
the rising edge of SW to the falling edge of an external clock source.
FB
11
I
Inverting input of the error amplifier. In closed loop operation, the voltage at this pin is the internal
reference level of 700 mV. This pin is also used for the PGOOD and undervoltage comparators.
GSNS
4
I
Inverting input of the differential amplifier. This pin should be connected to ground at the point of load.
HDRV1
32
O
Gate drive output for the high-side N-channel MOSFET switch for PWM1. Output is referenced to SW1
and is bootstrapped for enhancement of the high-side switch.
Return point of current sense voltage. The traces for these signals must be connected directly at the
current sense element. See Layout Guidelines for more information.
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Terminal Functions (continued)
TERMINAL
NAME
8
NO.
I/O
DESCRIPTION
HDRV2
25
O
Gate drive output for the high-side N-channel MOSFET switch for PWM2. Output is referenced to SW2
and is bootstrapped for enhancement of the high-side switch
ILIM
15
I
Used to set the cycle-by-cycle current limit threshold. If ILIM threshold is reached, the PWM cycle is
terminated and the converter delivers limited current to the output. The relationship between ILIM and the
maximum phase current is described in Equation 2 and Equation 3. See the Overcurrent Protection
section for more details.
LDRV1
29
O
Gate drive output for the low-side synchronous rectifier (SR) N-channel MOSFET for PWM1. See Layout
Considerations section.
LDRV2
27
O
Gate drive output for the low-side synchronous rectifier (SR) N-channel MOSFET for PWM2. See Layout
Considerations section.
OVSET
2
I
A resistor divider, on this pin connected to the output voltage sets the overvoltage sense point.
PGOOD
16
O
Power good indicator of the output voltage. This open-drain output connects to a voltage via an external
resistor. When the FB pin voltage is between 0.616 V to 0.784 V (88% to 112% of VREF), the PGOOD
output is in a high impedance state.
PGND
28
-
Power ground reference for the controller lower gate drivers. There should be a high-current return path
from the sources of the lower MOSFETs to this pin.
RT
17
I
Connecting a resistor from this pin to ground sets the oscillator frequency.
SS
23
I
Provides user programmable soft-start by means of a capacitor connected to the pin. If an undervoltage or
over current fault is detected the soft-start capacitor cycles 7 times with no switching before a normal
soft-start sequence allowed.
SW1
31
I
Connect to the switched node on converter 1. Power return for the channel 1 upper gate driver. There
should be a high-current return path from the source of the upper MOSFET to this pin. It is also used by
the adaptive gate drive circuits to minimize the dead time between upper and lower MOSFET conduction.
SW2
26
I
Connect to the switched node on converter 2. Power return for the channel 2 upper gate driver. There
should be a high-current return path from the source of the upper MOSFET to this pin. It is also used by
the adaptive gate drive circuits to minimize the dead time between upper and lower MOSFET conduction.
UVLO
22
O
A voltage divider from VIN to this pin, set to 1V, determines the input voltage that starts the controller.
VDD
12
I
Power input for the LDO linear regulator that powers the differential amplifer and the current sense
amplifiers.
VOUT
3
I
Non-inverting input of the differential amplifier. This pin should be connected to VOUT at the point of load.
VREF
9
O
Output of an internal reference voltage. The load may be up to 100-μA DC.
VIN5
30
I
Power input for the device. A 1.0-μF ceramic capacitor should be connected from this pin to ground.
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SLVS635 – FEBRUARY 2007
FUNCTIONAL BLOCK DIAGRAM
VDD
12
BP5
21
AGND
20
CS1
6
CSRT1
7
VOUT
3
LDO
13
BP8
1
BOOT1
32
HDRV1
31
SW1
30
VIN5
29
LDRV1
28
PGND
24
BOOT2
25
HDRV2
26
SW2
27
LDRV2
16
PGOOD
TPS40131RHB
U1
+
20 kW
U7
+
20 kW
20 kW
GSNS
4
U6
20 kW
DIFFO
9
+
VREF
5
Ramp1
U2
0.7 V
U3
PWM1
+EA
+
U9
ICTLR
10
U12
U5
Anti
Cross
Conduction
U10
+
FB
11
SS
23
U4
PWM
LOGIC
5 mA
COMP
8
BP8
U15
+
U18
CS2
19
CSRT2
18
ILIM
15
UVLO
22
EN/SYNC
14
U17
+
Ramp2
U14
UV
FB
VIN5
BP5
RT
OVSET
17
2
SS
PWM2
U20
U19
OC/UV
Detect
U22
Power-On Reset
U23
Clock
U24
Ramp Gen
U16
Anti
Cross
Conduction
VIN5
U21
OC
Ramp1
OV
100 ns
Delay
Ramp2
U25
OV Detect
UDG-07021
FUNCTIONAL DESCRIPTION
The TPS40131 uses programmable fixed-frequency, peak current mode control with forced phase current
balancing. Phase current is sensed by using either the DCR (direct current resistance) of the filter inductors or
current sense resistors installed in series with output. The first method involves generation of a current signal
with an R-C circuit (shown in the applications diagram). The R-C values are selected by matching time constants
of the RC circuit and the inductor time constant, R×C = L/DCR. With either current sense method, the current
signal is amplified and superimposed on the amplified voltage error signal to provide current mode PWM control.
Other features include: a true differential output sense amplifier, programmable current limit, programmable
output over-voltage set-point, capacitor set soft-start, power good indicator, programmable input undervoltage
lockout (UVLO), user programmable operation frequency for design flexibility, external synchronization
capability, programmable pulse-by-pulse overcurrent protection, output undervoltage shutdown and restart.
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FUNCTIONAL DESCRIPTION (continued)
Startup Sequence
Figure 1 shows a typical start up with the VIN5 and BP5 applied to the controller and then the EN/SYNC being
enabled. Shut down occurs when the VIN5 is removed
VIN5
BP5
EN/SYNC
1.0V
0.7V
SS
SSWAIT
VOUT
PGOOD
EN_SSWAIT
UDG−04031
Figure 1. Startup and Shutdown Sequence
Differential Amplifier (U7)
The unity gain differential amplifier with high bandwidth allows improved regulation at a user-defined point and
eases layout constraints. The output voltage is sensed between the VOUT and GSNS pins. The output voltage
programming divider is connected to the output of the amplifier (DIFFO).
If there is no need for a differential amplifer, the differential amplifier can be disabled by connecting the GSNS
pin to the BP5 pin and leaving VOUT and DIFFO open. The voltage programming divider in this case should be
connected directly to the output of the converter.
TPS40131
VOUT
20 kΩ
3
20 kΩ
GSNS
20 kΩ
Differential
Amplifier
+
DIFFO
5
20 kΩ
4
UDG−04081
Figure 2. Differential Amplifier Configuration
Because of the resistor configuration of the differential amplifier, the input impedance must be kept very low or
there will be error in setting the output voltage.
10
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SLVS635 – FEBRUARY 2007
FUNCTIONAL DESCRIPTION (continued)
Current Sensing and Balancing (U1, U9 and U18)
The controller employs peak current mode control scheme, thus naturally provides certain degree of current
balancing. With current mode, the level of current feedback should comply with certain guidelines depending on
duty factor known as “slope compensation” to avoid the sub-harmonic instability. This requirement can prohibit
achieving a higher degree of phase current balance. To avoid the controversy, a separate current loop that
forces phase currents to match is added to the proprietary control scheme. This effectively provides high degree
of current sharing independent of the controller’s small signal response and is implemented in U9, ICTLR. The
useable range of the controller bandwidth is also extended.
High bandwidth current amplifiers, U1 and U18 can accept as an input voltage either the voltage drop across
dedicated precise current sense resistors, or inductor’s DCR voltage derived by an RC network. The wide range
of current sense arrangements ease the cost/complexity constraints and provides superior performance
compared to controllers utilizing the low-side MOSFET current sensing. See the Inductor DCR Current Sense
section for more information on selecting component values for the R-C network.
Hiccup Mode
Hiccup mode is a feature that is invoked when certain faults are detected. Hiccup mode allows a time for a fault
to clear itself,for instance, a momentary short circuit on the output. The hiccup mode consists of 7 cycles of
charging and discharging the soft-start capacitor and then attempting a re-start. If the fault has been cleared, the
re-start will cause the output to come up in regulation. If the fault has not been cleared, Hiccup mode is initiated
again and another restart will occure after another 7 soft-start cycles.
PowerGood
The PGOOD pin indicates when the inputs and output are within their specified ranges of operation. Also
monitored are the EN/SYNC and SS pins. PGOOD has high impedance when indicating inputs and outputs are
within specified limits and is pulled low to indicate an out-of-limits condition. .
Soft-Start
A capacitor connected to the soft start pin (SS) sets the power-up time. When EN is high and POR is cleared,
the calibrated current source starts charging the external soft start capacitor. The PGOOD pin is held low during
the start up. The rising voltage across the capacitor serves as a reference for the error amplifier, U12. When the
soft-start voltage reaches the level of the reference voltage, the converter’s output reaches the regulation point
and further voltage rise of the soft start voltage has no effect on the output. When the soft start voltage reaches
1.0 V, the power good (PGOOD) function is cleared to be reported on the PGOOD pin. Normally the PGOOD
pin goes high at this time. Equation 1 is used to calculate the value of the soft-start capacitor.
0.7 C SS
t SS +
5 10 *6
(1)
Overcurrent Protection
The overcurrent function, U19, monitors the output of current sense amplifiers U1 and U18. These currents are
converted to voltages and compared to the voltage on the ILIM pin. The relationship between the maximum
phase current and the current sense resistance is given in the following equation. In case a threshold of
VILIM/3.75 is exceeded the PWM cycle on the associated phase is terminated. The overcurrent threshold,
IPH(max), and the voltage to set on the ILIM pin is determined by Equation 2 and Equation 3.
VILIM = 3.75 ´ IPH(max ) ´ R CS
I PH(max) +
(2)
ǒV IN * VOUTǓ
I OUT
)
2
2
L OUT
f SW
VOUT
V IN
(3)
where
•
•
•
IPH(max) is a maximum value of the phase current allowed
IOUT is the total maximum DC output current
RCS is a value of the current sense resistor used or the DCR value of the output inductor, LOUT
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FUNCTIONAL DESCRIPTION (continued)
If the overcurrent condition persists, both phases have PWM cycles terminated by the overcurrent signals. This
puts a converter in a constant current mode with the output current programmed by the ILIM voltage. A counter
is incremented for each PWM cycle in which an overcurrent event is detected. The counter is reset every 32
PWM cycles. If the counter accumulates a count of 7 before being reset, the converter enters a hiccup mode.
The HDRV and LDRV signals are set low during the hiccup mode.
The SS capacitor serves as a hiccup timing capacitor controlled by U20, the fault control circuit. The soft-start
pin is periodically charged and discharged by U20. After seven hiccup cycles, the controller attempts another
soft-start cycle to restore normal operation. If the overload condition persists, the controller returns to the hiccup
mode. This condition may continue indefinitely. In such conditions the average current delivered to the load is
approximately 1/8 of the set overcurrent value.
Overvoltage Protection, Non-Latching
The voltage on OVSET is compared with 0.817 V, 16% higher than VREF, in U25 to determine the output
overvoltage point. When an overvoltage is detected, the output drivers command the upper MOSFETs off and
the lower MOSFETs on. If the overvoltage condition has been cleared, the output comes up and normal
operation continues. Turning the lower MOSFET on may cause the output to reach an undervoltage condition
and enter the hiccup mode. Using a voltage divider with the same ratio, that sets the output voltage, an output
overvoltage is declared when the output rises 16% above nominal.
Output Undervoltage Protection
If the output voltage, as sensed by U19 on the FB pin becomes less than 0.588 V, the undervoltage protection
threshold (84% of VREF), the controller enters the hiccup mode.
Programmable Input Undervoltage Lockout Protection
A voltage divider that sets 1V on the UVLO pin determines when the controller starts operating. Operation
commences when the voltage on the UVLO pin exceeds 1.0 V. If the voltage on the UVLO pin falls to 0.81 V,
the controller is turned off and the HDRV and LDRV signals are set low.
Power-On Reset (POR)
The power-on reset (POR) function, U22, insures the VIN5 and BP5 voltages are within their regulation windows
before the controller is allowed to start.
Fault Masking Operation
If the SS pin voltage is externally limited below the 1-V threshold, the controller does not respond to most faults
and the PGOOD output is always low. Only the overcurrent function remains active. The overcurrent protection
still continues to terminate PWM cycle every time when the threshold is exceeded but the hiccup mode is not
entered.
Fault Conditions and MOSFET Control
Table 1 shows a summary of the fault conditions and the state of the MOSFETs.
Table 1. Fault Condifions
12
FAULT MODE
UPPER MOSFET
LOWER MOSFET
EN/SYNC = LOW
OFF
OFF
FIXED UVLO, VBP5 < 4.25 V
OFF
OFF
Programmable UVLO, < 1.0 V
OFF
OFF
Output undervoltage
OFF, Hiccup mode
OFF, Hiccup mode
Output overvoltage
OFF
ON
Output overcurrent
OFF, Hiccup mode
OFF, Hiccup mode
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Setting the Switching Frequency
The clock frequency is programmed by the value of the timing resistor connected from the RT pin to ground.
See Equation 4.
R T + 0.8
ƪǒ
Ǔ ƫ
103 * 9
36
f PH
(4)
fPH is a single phase frequency, kHz. The RT resistor value is expressed in kΩ. See Figure 3.
500
RT − Timing Resistance − kΩ
450
400
350
300
250
200
150
100
50
0
0
200
400
600
800
1000
fSW − Phase Switching Frequency − kHz
Figure 3. Phase Switching Frequency vs. Timing Resistance
EN/SYNC Function
The output ripple frequency is twice that of the single-phase frequency. The switching frequency of the controller
can be synchronized to an external clock applied to the EN/SYNC pin. The external clock synchronizes the
rising edge of HDRV and the falling edge of an external clock source. The switching frequency is one-eighth of
the external clock frequency.
Setting Overcurrent Protection
Setting the overcurrent protection is given in the following equations. Care must be taken when calculating VILIM
to include the increase in RCS caused by the output current as it approaches the overcurrent trip point. The DCR
(RCS in the equation) of the inductor increases approximately 0.39% per degree Centigrade.
VILIM = 3.75 ´ IPH(max) ´ RCS
I PH(max) +
(5)
ǒV IN * VOUTǓ
I OUT
)
2
2
L OUT
f SW
VOUT
V IN
(6)
where
•
•
•
•
•
•
•
IPH(max) is a maximum value of the phase current allowed
IOUT is the total maximum DC output current
LOUT is the output inductor value
fSW is the switching frequency
VOUT is the output voltage
VIN is the input voltage
RCS is a value of the current sense resistor used or the DCR value of the output inductor, LOUT
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Resistor Divider Calculation for VOUT, ILIM, OVSET and UVLO
Use Figure 4 for setting the output voltage, current limit voltage and overvoltage setting voltage. Select RBIAS
using Equation 7. With a voltage divider from VREF, select R6 using Equation 8. WIth a voltage from DIFFO
select R4 using Equation 9. With a voltage divider from VIN, select R8 using Equation 10.
R1
R BIAS + 0.7
ǒV OUT * 0.7Ǔ
(7)
R6 + R5
R4 + 0.812
R8 + 1.0
VILIM
ǒ0.7 * V ILIMǓ
(8)
R3
ǒVOUT(ov) * 0.812Ǔ
(9)
R7
ǒVIN * 1.0Ǔ
(10)
TPS40131RHB
OVSET
2
GSNS
Differential
Amplifier
4
VOUT
3
+
DIFFO
5
R2
R3
C1
COMP
8
R1
Error
Amplifier
FB
11
R4
+
+EA
RBIAS
VIN
10
VREF
9
R5
ILIM
15
R6
UVLO
R7
22
+
700 mV
R8
UDG−04032
Figure 4. Use for Resistor Divider Calculations
INDUCTOR DCR CURRENT SENSE
The preferred method for sampling the output current for the TPS40131 is known as the inductor DCR method.
This is a lossless approach, as opposed to using a discrete current sense resistor which occupies board area
and impacts efficiency as well. The inductor DCR implementation is shown in Figure 5.
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VIN
L1
DCR
VOUT
C1
R1
+
VC
−
To CSRTx
To CSx
Figure 5. Inductor DCR Current Sense Approach
The inductor L1 consists of inductance, L, and resistance, DCR. The time constant of the inductor: L / DCR
should equal the R1×C1 time constant. Then choosing a value for C1 (0.1 μF is a good choice) solving for R1 is
shown in Equation 11.
L1
R1 +
DCR C1
(11)
The voltage into the current sense amplifier of the controller , VC, is calculated in Equation 12.
V OUT
V C + ǒVIN * VOUTǓ
) I OC DCR
R1 C1 f SW V IN
(12)
As the DC load increases the majority of the voltage, VC, is determined by (IOC ×DCR), where IOC is the per
phase DC output current. It is important that at the overcurrent set point that the peak voltage of VC does not
exceed 60 mV, the maximum differential input voltage. If the voltage VC exceeds 60 mV, a resistor, R2,can be
added in parallel with C1 as shown in Figure 6. Adding R2 reduces the equivalent inductor DCR by the ratio
shown in Equation 14
VIN
L1
DCR
VOUT
C1
R1
R2
+
VC
−
To CSRTx
To CSx
Figure 6. Using Resistor R2 to Reduce the Current Sense Amplifier Voltage
The parallel combination of R1 and R2 is shown in Equation 13.
L1
R1 ø R2 +
DCR C1
(13)
The ratio shown in Equation 14 provides the required voltage attenuation.
R2
R1 ) R2
(14)
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APPLICATION INFORMATION
LAYOUT CONSIDERATIONS
Power Stage
A synchronous BUCK power stage has two primary current loops. One is the input current loop that carries high
AC discontinuous current . The other is the output current loop that carries high DC continuous current.
The input current loop includes
capacitors and the ground path
generally good practice to place
MOSFET and the source of the
MOSFETs.
the input capacitors, the main switching MOSFET, the inductor, the output
back to the input capacitors. To keep this loop as small as possible, it is
some ceramic capacitance directly between the drain of the main switching
synchronous rectifier (SR) through a power ground plane directly under the
The output current loop includes the SR MOSFET, the inductor, the output capacitors, and the ground return
between the output capacitors and the source of the SR MOSFET. As with the input current loop, the ground
return between the output capacitor ground and the source of the SR MOSFET should be routed under the
inductor and SR MOSFET to minimize the power loop area.
The SW node area should be as small as possible to reduce the parasitic capacitance and minimize the radiated
emissions. The gate drive loop impedance (HDRV-gate-source-SW and LDRV-gate-source- GND) should be
kept to as low as possible. The HDRV and LDRV connections should widen to 20 mils as soon as possible out
from the device's pin.
Device Peripheral
The TPS40131 provides separate signal ground (GND) and power ground (PGND) pins. It is required to
separate properly the circuit grounds. The return path for the pins associated with the power stage should be
through PGND. The other pins especially for those sensitive pins such as FB, RT and ILIM should be through
the low noise GND. The GND and PGND plane are suggested to be connected at the output capacitor with
single 20 mil trace.
A minimum 0.1-μF ceramic capacitor must be placed as close to the VDD pin and GND as possible with at least
15-mil wide trace from the bypass capacitor to the GND. A 1-μF ceramic capacitor should be placed as close to
VIN5 pin and GND as possible.
BP5 is the filtered input from the VIN5 pin. A 10 Ω resistor should be connected between VIN5 and BP5 and a
1-μF ceramic capacitor should be connected from BP5 to GND. Both components should be as close to BP5 pin
as possible.
When DCR sensing method is applied, the sensing resistor is placed close to the SW node. It is connected to
the inductor with Kelvin connection. The sensing traces from the power stage to the device should be away from
the switching components. The sensing capacitor should be placed very close to the CS and CSRT pins. The
frequency setting resistor should be placed as close to RT pin and GND as possible.
The VOUT and GSNS pins should be directly connected to the point of load where the voltage regulation is
required. A parallel pair of 10-mil traces connects the regulated voltage back to the chip. They should be away
from the switching components. The PowerPAD should be electrically connected to GND. Figure 7 shows the
device peripheral schematic and Figure 8 shows the suggested layout.
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APPLICATION INFORMATION (continued)
R2
C4
R3
C6
C7
R5
C5
R10
R7
R8
D1
R9
C11
R14
R15
C20
C22
C25
9
10
11
12
13
14
R16 15
16
COMP
CSRT1
CS1
DIFFO
GSNS
VOUT
OVSET
BOOT1
R6
VREF
+EA
FB
VDD
BP8
EN/SYNC
ILIM
PGOOD
U1
RT
CSRT2
CS2
AGND
BP5
UVLO
SS
BOOT2
C9
8
7
6
5
4
3
2
1
R11
17
18
19
20
21
22
23
24
R17
C10
PwPd
HDRV1
SW1
VIN5
LDRV1
PGND
LDRV2
SW2
HDRV2
33
32
31
30
29
28
27
26
25
C21
R18
C26
R20
R19
C31
C27
D2
R22
C30
C32
R25
C33
Figure 7. TPS40131 Peripheral Schematic
AGND
AGND
CSRT1
FB
AGND
VOUT
GSNS
CS1
BOOT1
HDRV1
FB
VIN5
AGND
LDRV1
12VIN
PGND
ILIM
LDRV2
HDRV2
AGND
BOOT2
AGND
AGND
CSRT1
CS2
BP5
12VIN
AGND
Figure 8. TPS40131 Recommended Layout for Peripheral Components
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APPLICATION INFORMATION (continued)
PowerPAD™ Layout
The PowerPAD™ package provides low thermal impedance for heat removal from the device. The PowerPAD™
derives its name and low thermal impedance from the large bonding pad on the bottom of the device. The circuit
board must have an area of solder-tinned-copper underneath the package. The dimensions of this area depend
on the size of the PowerPAD™ package.
Thermal vias connect this area to internal or external copper planes and should have a drill diameter sufficiently
small so that the via hole is effectively plugged when the barrel of the via is plated with copper. This plug is
needed to prevent wicking the solder away from the interface between the package body and the solder-tinned
area under the device during solder reflow. Drill diameters of 0.33 mm (13 mils) works well when 1-oz. copper is
plated at the surface of the board while simultaneously plating the barrel of the via. If the thermal vias are not
plugged when the copper plating is performed, then a solder mask material should be used to cap the vias with
a diameter equal to the via diameter plus 0.1 mm minimum. This capping prevents the solder from being wicked
through the thermal vias and potentially creating a solder void under the package. Refer to PowerPAD™
Thermally Enhanced Package (SLMA002) for more information on the PowerPAD™ package.
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DESIGN EXAMPLE
Two Phase Single Output Configuration from 12 V to 1.5 V DC/DC Converter Using a TPS40131
The following example illustrates the design process and component selection for a two phase single output
synchronous buck converter using TPS40131. The design goal parameters are given in the table below.
Design Goal Parameters
PARAMETER
TEST CONDITIONS
VIN
Input voltage
VOUT
Output voltage
VRIPPLE
Output ripple
IOUT
Output current
fSW
Switching frequency
MIN
TYP
MAX
10.8
12.0
13.2
1.5
IOUT = 40 A
30
UNIT
V
mV
40
A
350
kHz
Setp 1: Inductor Selection
The inductor is determined by the desired ripple current. The required inductor is calculated using Equation 15.
L=
VIN(max) - VOUT
IRIPPLE
´
VOUT
1
´
VIN(max) fSW
(15)
Typically the peak-to-peak inductor current IRIPPLE is selected to be around 20% of the rated output current. In
this design, IRIPPLE is targeted at 23% of IPHASE. The calculated inductor is 0.815 μH and in practical a 0.82-μH,
30-A inductor with 2-mΩ DCR from Vishay is selected. The real inductor ripple current is 4.63 A.
Step 2: Output Capacitor Slection
The output capacitor is typically selected by the output load transient response requirement. Equation 16
estimates the minimum capacitor to reach the undervoltage requirement with load step up. Equation 17
estimates the minimum capacitor for overvoltage requirement with load step down. When VIN(min) < 2×VOUT, the
minimum output capacitance can be calculated using Equation 16. Otherwise, Equation 17 is used.
COUT(min)
2
1
´ ITRAN(max) ´ L
2
=
VIN(min) - VOUT ´ VUNDER
(
)
(
)
2
1
´ ITRAN(max) ´ L
COUT(min) = 2
(VOUT ´ VOVER )
(
(16)
)
(17)
In this design, VIN(min) is much larger than 2 × VOUT, so Equation 17 is used to determine the minimum
capacitance. Based on a 15-A load transient with a maximum of 80-mV deviation, a minimum 1-mF output
capacitor is required. In the design, six 180-μF, 6.3-V SP capacitors are selected to meet this requirement. Each
capacitor has an ESR of 5 mΩ.
Due to the interleaving of channels, the total output ripple current is smaller than the ripple current from a single
phase. The ripple cancellation factor is expressed in Equation 18.
DIOUT (D) =
1- 2 ´ D ´ 2 - 2 ´ D
1- 2 ´ D + 1
(18)
where
•
D is the duty cycle for a single phase
The maximum output ripple current is calculated in Equation 19.
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IRIPPLE =
VOUT
´ DIOUT (D) = 4.04 A
L ´ fsw
(19)
With 1.08-mF output capacitance, the ripple voltage at the capacitor is calculated to be 1.34 mV. In the
specification, the output ripple voltage should be less than 30 mV, so based on the following equation, the
required maximum ESR is 7.1 mΩ. The selected capacitors can meet this requirement.
æ
ö
IRIPPLE
VRIPPLE(TotOUT) - ç
÷
VRIPPLE(TotOUT) - VRIPPLE(COUT)
è 8 ´ COUT ´ fSW ø
=
ESRCo =
IRIPPLE
IRIPPLE
(20)
Step 3: Input Capacitor Selection
The input voltage ripple depends on input capacitance and ESR. The minimum capacitor and the maximum ESR
can be estimated using Equation 21.
CIN(min) =
ESR Cin =
IOUT ´ VOUT
VRIPPLE(CIN) ´ VIN ´ fSW
(21)
VRIPPLE(CinESR)
IOUT +
((12 )´ IRIPPLE )
(22)
For this design, assume VRIPPLE(Cin) is 60 mV and VRIPPLE(CinESR) is 30 mV, so the calculated minimum
capacitance is 120-μF and the maximum ESR is 1.35 mΩ. Choosing six 22-μF, 16V, 2-mΩ ESR ceramic
capacitors meets this requirement.
Another important thing for the input capacitor is the RMS ripple current rating. Due to the interleaving of
multi-phase, the input RMS current is reduced. The input ripple current RMS value over load current is
calculated using Equation 23.
DIIN (D) = D ´ (0.5 - D) ´ IOUT
(23)
So in this design, the maximum input ripple RMS current is calculated to be 8.96 A with the minimum input
voltage. It is about 35% reduction compared with a 40-A single-phase converter design. Each selected ceramic
capacitor has a RMS current rating of 4.3 A, so it is sufficient to meet this requirement.
Step 4: MOSFET Selection
The MOSFET selection determines the converter efficiency. In this design, the duty cycle is very small so that
the high-side MOSFET is dominated with switching losses and the low-side MOSFET is dominated with
conduction loss. To optimize the efficiency, choose smaller gate charge for the high-side MOSFET and smaller
RDS(on) for the low-side MOSFET. Renesas HAT2167H and HAT2164H are selected as the high-side and
low-side MOSFET respectively.
In the following calculations, only the losses for one phase are shown. The power losses in the high-side
MOSFET is calculated with the following equations.
The RMS current in the high-side MOSFET is shown in Equation 24.
2
æ
2 (IRIPPLE )
ISWrms = D ´ ç (IOUT ) +
ç
12
è
ö
÷ = 7.08
÷
ø
(24)
The RDS(on)(sw) is 9.3 mΩ when the MOSFET gate voltage is 4.5 V. The conduction loss is shown in Equation 25.
2
PSWcond = (ISWrms ) ´ RDS(on)(sw) = 0.467 W
The switching loss is shown in Equation 26.
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I ´ VIN ´ fSW ´ RDRV ´ (Qgdsw + Qgssw )
PSW(sw) = PK
= 0.438 W
Vgtdrv
(26)
The calculated total loss is the high-side MOSFET is shown in Equation 27.
PSW(tot) = Psw (cond) + PSW(SW ) = 0.935 W
(27)
The power losses in the low-side SR MOSFET is calculated using .
The RMS current in the low-side MOSFET is calculated using Equation 28.
2
æ
2 (IRIPPLE )
ISRrms = (1 - D) ´ ç (IOUT ) +
ç
12
è
ö
÷ = 18.7A
÷
ø
(28)
The RDS(on)(sr) of each HAT2164H is 4.4mΩ when the gate voltage is 4.5 V. Two HAT2164H are used in parallel
to reduce the conduction loss. The conduction loss in the low-side MOSFETs is shown in Equation 29.
2 æ RDS(on)(sr)
PSR(cond) = (ISRrms ) ´ ç
ç
2
è
ö
÷÷ = 0.77 W
ø
(29)
The total power loss in the body diode is shown in Equation 30.
PDIODE = 2 ´ IOUT ´ tD ´ Vf ´ fSW = 0.49 W
(30)
Therefore, the calculated total loss in the SR MOSFETs is as described in Equation 31.
PSR(tot) = PSR(cond) + PDIODE = 1.26 W
(31)
Step 5: Peripheral Component Design
RT (Pin 17) Switching Frequency Setting
æ 36 ´ (10 )3
ö
- 9 ÷ = 75kW
RT = 0.8 ´ ç
ç
÷
fSW
è
ø
(32)
In Equation 32, the phase switching frequency and it is 350 kHz here.
SS (Pin 23) Soft-Start
To obtain a 3-ms soft-start time, calculate CSS which is connected between SS and GND.
CSS =
-3
tSS
3
140 ´ (10 )
=
3 ´ (10 )
3
= 21nF
140 ´ (10 )
(33)
FB (Pin 11) Output Voltage Setting
Select the top resistor to be 10 kΩ, calculate the bottom resistor RBAIS using Equation 34.
æ 10 ´ (10 )3 ö
÷ = 8.75kW
RBIAS = 0.7 ´ ç
ç (VOUT - 0.7 ) ÷
è
ø
(34)
(Pin 6, Pin 7, Pin 18 and Pin 19) Current Sensing Network Design
In this design, the lossless inductor DCR sensing is applied. Choose the sense capacitor a value for 0.1 μF, and
calculate the sense resistor R with Equation 35 and Equation 36.
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R=
L
= 6kW
DCR ´ C
(35)
The simplified equation to determine if the design produces sub-harmonics is shown in Equation 35.
VIN ´ 6
L
>
DCR 2 ´ VRAMP ´ fSW
(36)
This condition is satisfied in this design. Both CSRT1 and CSRT2 are recommended to connect to GND with a
1-μF capacitor for the purpose of eliminating noise.
ILIM (Pin 15) Current Limit
The overcurrent protection level is calculated with equations below.
IPK = IOC(dc ) +
(VIN - VOUT )´ VOUT
2 ´ L ´ fSW ´ VIN
= 27.32 A
(37)
VILIM = 3.75 ´ IPK ´ DCR = 205mV
(38)
IOC(dc) is the DC overcurrent protection level for each phase. In this design, it is 25 A per phase. DCR is 2 mΩ. A
resistor divider is connected from VREF (pin 9) to GND to provide an accurate VILIM voltage. Choose a value of
10 kΩ for the top resistor, and then the bottom resistor is calculated using Equation 39.
æ 10 ´ (10 )3 ö
÷ = 4.02kW
RB = VLIM ´ ç
ç VREF - VLIM ÷
è
ø
(39)
OVSET (Pin 2) Output Voltage Setting
A resistor divider is connected from VOUT to GND to set the overvoltage protection threshold. In this design, the
resistor divider is the same as the output voltage setting resistor divider, so the OVSET level is 16% of the set
output voltage.
UVLO (Pin 22) Undervoltage Lockout
UVLO is connected to the input voltage and GND with a resistor divider. The resistor connected to VIN is chosen
to be 10 kΩ and the resistor connected to GND is selected to be a value of 2.49 kΩ. When the input voltage is
higher than 5 V, the chip is enabled.
PGOOD (Pin 16) Powergood
PGOOD is connected to BP5 with a 10-kΩ resistor.
VOUT, GSNS and DIFFO (Pin 3) (Pin 4) (Pin 5)
VOUT and GSNS are connected to the remote sensing output connector. DIFFO is connected to the feedback
resistor divider. If the differential amplifier is not used, VOUT and GSNS should be grounded, and DIFFO is left
open.
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BOOT1, BOOT2, SW1, SW2 (Pin 1) (Pin 24) (Pin 31) (Pin 26)
A bootstrap capacitor is connected between the BOOT1 and SW1 pin or between BOOT2 and SW2 pin. The
bootstrap capacitor depends on the total gate charge of the high-side MOSFET and the amount of droop
allowed on the bootstrap capacitor.
CBOOT =
Qg
= 85nF
DV
(40)
where
•
•
Qg is 17nC
ΔV is 0.2 V
For this application, a 0.1-μF capacitor is selected. To reduce the turn on speed of the high-side MOSFET and
control the ringing, a 2-Ω resistor is placed in series with the BOOT pin.
EN/SYNC (Pin 14) Enable and Synchronization
This pin is either tied to BP5 to enable the chip or connected to an external clock.
VREF EA+ (Pin 9) (Pin 10) Voltage Reference and Error Amplifier
VREF and EA+ are directly connected together. A 0.1-μF decoupling capacitor is recommended.
VDD, VIN5, BP5, BP8, AGND, PGND, PwPd (Pin 12) (Pin 30) (Pin 21) (Pin 13) (Pin 20) (Pin 28) (Pin 33)
VDD is directly connected to VIN and a 0.1-μF decoupling capacitor is recommended.
VIN5 is connected to external +5 V and a 100-μF bulk capacitor and a 1-μF decoupling capacitor are
recommended.
BP5 is filtered from VIN5. A 10-Ω resistor and a 0.1-μF capacitor are recommended for the low pass filter.
BP8 is decoupled with a 0.1-μF capacitor to GND. A
GND and PwPd are tied to analog GND and PGND is tied to power GND.
Feedback Compensator Design
Peak current mode control method is employed in the controller. A small signal model is developed from the
COMP signal to the output.
GVC(s) =
(s ´ COUT ´ ESR + 1) ´ ROUT
1
1
´
´
DCR ´ Ac s ´ ts + 1
s ´ COUT ´ ROUT + 1
(41)
The time constant, τS, is defined by Equation 42.
ts =
T
æ æ æ VRAMP ö æ VIN - VOUT ö
öö
+ç
´ DCR ´ Ac ÷ ÷
ç çç
÷
÷
L
ø
ç è T ø è
ø÷
lnç è
÷
æ VRAMP ö æ VOUT ö
ç
÷
-ç
´ DCR ´ Ac
÷
ç
÷
ç
÷
è T ø è L ø
è
ø
(42)
The low frequency pole is calculated in Equation 43.
fVCP1 =
1
= 3.84kHz
2 ´ p ´ COUT ´ ROUT
(43)
Another pole from control to output is calculated in Equation 44.
fVCP2 =
1
= 46.3kHz
2 ´ p ´ tS
(44)
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TPS40131
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The ESR zero is calculated in Equation 45.
fESR =
1
= 176.8kHz
2 ´ p ´ COUT ´ ESR
(45)
In this design, a Type III compensator is employed to compensate the loop.
R1
R3
VREF
C1
+
C3
R2
C2
Figure 9. Type III Compensator
The compensator transfer function is shown in Equation 46.
æ
1
GC(s) = ç
ç R1´ (C2 + C3 )
è
(
(
)
ö
s ´ (R1 + R3 )´ C1 + 1 ´ (s ´ R2 ´ C2 + 1)
÷´
÷
æ
C2 ´ C3 ö ö
ø s ´ (s ´ R3 ´ C1 + 1)´ ç s ´ R2 ´ çæ
+ 1÷
C2
+ C3 ÷ø ø
è
è
)
(46)
The loop gain transfer function is shown in Equation 47.
TV(s) = GC(s) ´ GVC(s)
(47)
Assume the desired crossover frequency is 20 kHz. Place one zero at fVCP1 and another zero at fVCP2, then
place one pole at fESRand another pole at fSW. The compensator gain is then calculated to achieve the desired
bandwidth. In this design, the compensator gain, pole and zero are selected using the following equations:
fP1 =
fP2 =
fZ1 =
fZ2 =
1
= fESR
2 ´ p ´ R3 ´ C1
(48)
1
= fSW
æ C2 ´ C3 ö
2 ´ p ´ R2 ´ ç
÷
è C2 + C3 ø
(49)
1
= fVCP1
2 ´ p ´ R2 ´ C2
(50)
1
= fVCP2
2 ´ p ´ (R1 + R3 ) ´ C1
(51)
TV ( j ´ 2 ´ p ´ fC ) = 1
(52)
4
From Equation 52 the compensator gain is solved as 2.09×10 .
æ
ö
1
4
A CM = ç
÷ = 2.09 ´ (10 )
ç R1´ (C2 + C3 ) ÷
è
ø
Set R1 equal to 10 kΩ, and then calculate all the other components.
24
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TPS40131
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SLVS635 – FEBRUARY 2007
•
•
•
•
•
R2
R3
C1
C2
C3
=
=
=
=
=
8.4 kΩ
3.5 kΩ
260 pF
4.7 nF
50 pF
In the real lab practice, the final components are selected as following to increase the phase margin and reduce
PWM jitter.
• R1 = 10 kΩ
• R2 = 5 kΩ
• R3 = 3 kΩ
• C1 = 470 pF
• C2 = 4.7 nF
• C3 = 47 pF
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TPS40131
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SLVS635 – FEBRUARY 2007
Design Example Summary
Figure 10 shows the schematic summarizes the above design.
26
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3K
0.1uF
0.1uF
4. 02K
0.1uF
470pF
10K
0.1uF
10K
8.75K
0.1uF
open
0.1uF 0.1uF
22nF
2.49K
10K
2
0.1uF
10
33
32
31
30 1uF
29
28
27
26
25
100uF
+
22uF
BAT54HT1
0.1uF
0.1uF
BAT54HT1
1uF
PwPd
HDRV1
SW1
VIN5
LDRV1
PGND
LDRV2
SW2
HDRV2
2
20 8.75K
10K
VREF
+EA
FB
VDD
TPS40131RHB
BP8
EN/SYNC
ILIM
PGOOD
1uF
75k
10K
5.1
9
10
11
12
13
14
15
16
47pF
4.7nF
8
7
6
5
4
3
2
1
COMP
CSRT1
CS1
DIFFO
GSNS
VOUT
OVSET
BOOT1
RT
CSRT2
CS2
AGND
BP5
UVLO
SS
BOOT2
17
18
19
20
21
22
23
24
5K
open
0.1uF
6K
6K
1
0.82uH
3.3n
3.3n
1
0.82uH
+
180u
10
10
47u
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SLVS635 – FEBRUARY 2007
TPS40131
Figure 10. Converting from 12 V to 1.5 V Output for IOUT = 40 A
27
TPS40131
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SLVS635 – FEBRUARY 2007
EFFICIENCY
vs
LOAD CURRENT
OUTPUT VOLTAGE
vs
LOAD CURRENT
1.510
100
90
VOUT - Output Voltage - V
80
h - Efficiency - %
70
60
50
40
30
VIN
20
1.505
VIN = 10.8 V
1.500
VIN = 13.2 V
1.495
VIN
10.8 V
12.0 V
13.2 V
10.8 V
12.0 V
13.2 V
10
1.490
0
0
5
10
15
20
25
30
35
40
0
5
15
20
25
30
IOUT - Load Current - A
IOUT - Load Current - A
Figure 11. Efficiency vs. Load
Figure 12. Load Regulation
VOUT
(50 mV / div)
IOUT
(10 A / div)
T - Time - 200 ms/div
Figure 13. 0 A to 15 A Load Step
28
10
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35
40
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TL431
1K
3K
100K
9
10
11
12
13
14
15
16
0.1uF
20
open
0.1uF 0.1uF
22nF
2.49K
10K
2
0.1uF
10
33
32
31
30 1uF
29
28
27
26
25
100uF
+
22uF
BAT54HT1
0.1uF
0.1uF
BAT54HT1
1uF
PwPd
HDRV1
SW1
VIN5
LDRV 1
PGND
LDRV 2
SW2
HDRV2
2
1.5K
10K
VREF
+EA
FB
VDD
TPS40131RHB
BP8
EN/SYNC
ILIM
PGOOD
1uF
75k
10K
5.1
1N5819
0.1uF
10K
1.5K
2N7002
0.1uF
0.1uF
90K
2.7K
0.1uF
470pF
10K
47pF
4.7nF
8
7
6
5
4
3
2
1
COMP
CSRT1
CS1
DIFFO
GSNS
VOUT
OVSET
BOOT1
RT
CSRT2
CS2
AGND
BP5
UVLO
SS
BOOT2
17
18
19
20
21
22
23
24
5K
open
0.1uF
6K
6K
1
2.65uH
3.3n
3.3n
1
2.65uH
+
180u
10
10
47u
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SLVS635 – FEBRUARY 2007
TPS40131
12 V to 5 V Converter Application
The following schematic shows an application that converts 12 V to 5 V. The 5-V output is used to power up the
device after start up.
Figure 14. Converting from 12 V to 5 V Output for IOUT = 20 A
29
TPS40131
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SLVS635 – FEBRUARY 2007
EFFICIENCY
vs
LOAD CURRENT
OUTPUT VOLTAGE
vs
LOAD CURRENT
5.400
100
VIN = 12 V
90
5.395
VOUT - Output Voltage - V
80
h - Efficiency - %
70
60
50
40
30
20
5.390
5.385
5.380
5.375
10
VIN = 12 V
5.370
0
0
0
4
8
12
16
8
12
IOUT - Load Current - A
IOUT - Load Current - A
Figure 15. Efficiency vs. Load Current
30
4
20
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Figure 16. Load Regulation
16
20
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2.7K
0.1uF
0.1uF
0.1uF
470pF
10K
3K
0.1uF
10K
8.75K
open
0.1uF 0.1uF
22nF
3K
10K
2
0.1uF
10
33
32
31
30 1uF
29
28
27
26
25
100uF
+
22uF
BAT54HT1
0.1uF
0.1uF
BAT54HT1
1uF
PwPd
HDRV1
SW1
VIN5
LDRV1
PGND
LDRV2
SW2
HDRV2
2
20 8.75K
10K
VREF
+EA
FB
VDD
TPS40131RHB
BP8
EN/SYNC
ILIM
PGOOD
1uF
75k
10K
5.1
9
10
11
12
13
14
15
16
47pF
4.7nF
COMP
CSRT1
CS1
DIFFO
GSNS
VOUT
OVSET
BOOT1
RT
CSRT2
CS2
AGND
BP5
UVLO
SS
BOOT2
17
18
19
20
21
22
23
24
5K
8
7
6
5
4
3
2
1
0.1uF
open
0.1uF
6K
6K
1
0.82uH
3.3n
3.3n
1
0.82uH
+
180u
10
10
47u
www.ti.com
SLVS635 – FEBRUARY 2007
TPS40131
5 V to 1.5 V Converter Application
The following schematic shows an application that converts 5 V to 1.5 V.
Figure 17. Converting from 5 V to 1.5 V Output for IOUT = 30 A
31
TPS40131
www.ti.com
SLVS635 – FEBRUARY 2007
EFFICIENCY
vs
LOAD CURRENT
OUTPUT VOLTAGE
vs
LOAD CURRENT
1.520
100
VIN = 5 V
90
1.518
VOUT - Output Voltage - V
80
h - Efficiency - %
70
60
50
40
30
1.516
1.514
1.512
20
10
VIN = 5 V
1.510
0
0
5
10
15
20
25
30
0
10
15
20
IOUT - Load Current - A
IOUT - Load Current - A
Figure 18. Efficiency vs. Load Current
32
5
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Figure 19. Load Regulation
25
30
TPS40131
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SLVS635 – FEBRUARY 2007
Table 2. Definitions
SYMBOL
DESCRIPTION
VIN(min)
Minimum Operating Input Voltage
VIN(max)
Maximum Operating Input Voltage
VOUT
Output Voltage
IRIPPLE
Inductor Peak-Peak Ripple Current
ITRAN(max)
Maximum Load Transient
VUNDER
Output Voltage Undershot
VOVER
Output Voltage Overshot
VRIPPLE(totOUT)
Total Output Ripple
VRIPPLE(Cout)
Output Voltage Ripple Due to Output Capacitance
VRIPPLE(Cin)
Input Voltage Ripple Due to Input Capacitance
VRIPPLE(CinESR)
Input Voltage Ripple Due to the ESR of Input Capacitance
PSW(cond)
High-Side MOSFET Conduction Loss
ISW(rms)
RMS Current in the High-Side MOSFET
RDS(on)(sw)
"ON" Drain-Source Resistance of the High-Side MOSFET
PSW(sw)
High-Side MOSFET Switching Loss
IPK
Peak Current Through the High-Side MOSFET
RDRV
Driver Resistance of the High-Side MOSFET
Qgd(SW)
Gate to Drain Charge of the High-Side MOSFET
Qgs(SW)
Gate to Source Charge of the High-Side MOSFET
VqSW
Gate Drive Voltage of the High-Side MOSFET
PSW(gate)
Gate Drive Loss of the High-Side MOSFET
Qg(SW)
Gate Charge of the High-Side MOSFET
PSW(tot)
Total Losses of the High-Side MOSFET
PSR(cond)
Low-Side MOSFET Conduction Loss
ISRrms
RMS Current in the Low-Side MOSFET
RDS(on)(sr)
"ON" Drain-Source Resistance of the Low-Side MOSFET
PSR(gate)
Gate Drive Loss of the Low-Side MOSFET
QgSR
Gate Charge of the Low-Side MOSFET
VqSW
Gate Drive Voltage of the Low-Side MOSFET
PDIODE
Power Loss in the Diode
tD
Dead Time Between the Conduction of High and Low-Side MOSFET
VF
Forward Voltage Drop of the Body Diode of the Low-Side MOSFET
PSR(tot)
Total Losses of the Low-Side MOSFET
DCR
Inductor DC Resistance
AC
The Gain of the Current Sensing Amplifier, typically it is 13
ROUT
Output Load Resistance
VRAMP
Ramp Amplitude, typically it is 0.5V
T
Switching Period
GVC(s)
Control to Output Transfer Function
GC(s)
Compensator Transfer Function
TV(s)
Loop Gain Transfer Function
ACM
Gain of the Compensator
fP1, fP2
Pole Frequency of the Compensator
fZ1, fZ2
Zero Frequency of the Compensator
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33
PACKAGE OPTION ADDENDUM
www.ti.com
13-Aug-2021
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS40131RHBR
ACTIVE
VQFN
RHB
32
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TPS
40131
TPS40131RHBRG4
ACTIVE
VQFN
RHB
32
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TPS
40131
TPS40131RHBT
ACTIVE
VQFN
RHB
32
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TPS
40131
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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