TPS40425EVM-594

User's Guide SLVUA86 – July 2014 Using the PWR594 EVM Dual Output DC/DC Analog with PMBus Interface The PWR594EVM evaluation module (EVM) uses the TPS40425 or TPS40428 controller. Both TPS40425 and TPS40428 are dual output, 2-phase, stackable PMBus synchronous buck, driverless controllers that operate from a nominal 4.5-V to 20-V supply. The controllers allow programming and monitoring via the PMBus interface. TPS40425 is in non smart-power mode (DCR mode) in factory default, it uses inductor DCR for current sense and external thermal transistor for temperature sense. TPS40428 is in smart-power mode in factory default, it obtains current and temperature signals from TI smart power stage. 1 2 3 4 5 6 7 8 9 10 11 Contents Description .................................................................................................................... 3 1.1 Typical Applications ................................................................................................ 3 1.2 Features .............................................................................................................. 3 Electrical Performance Specifications ..................................................................................... 4 Schematic ..................................................................................................................... 5 Test Setup .................................................................................................................... 7 4.1 Test and Configuration Software ................................................................................. 7 4.2 Test Equipment ..................................................................................................... 7 4.3 Power Sequence Between Soft-Start and +5 V for Power Stage ............................................ 8 4.4 Recommended Test Setup ........................................................................................ 8 4.5 USB Interface Adapter and Cable ................................................................................ 9 4.6 List of Test Points and Connectors ............................................................................... 9 EVM Configuration Using the Fusion GUI .............................................................................. 11 5.1 Configuration Procedure ......................................................................................... 11 Test Procedure ............................................................................................................. 12 6.1 Line/Load Regulation and Efficiency Measurement Procedure ............................................. 12 6.2 Control Loop Gain and Phase Measurement Procedure .................................................... 12 6.3 Efficiency ........................................................................................................... 13 6.4 Equipment Turn On and Shutdown ............................................................................. 13 Performance Data and Typical Characteristic Curves................................................................. 14 7.1 Efficiency ........................................................................................................... 14 7.2 Load Regulation ................................................................................................... 15 7.3 Bode Plot ........................................................................................................... 16 7.4 Transient Response............................................................................................... 17 7.5 Output Ripple ...................................................................................................... 19 7.6 Enable Turn On and Turn Off Waveforms ..................................................................... 20 EVM Assembly Drawing and PCB Layout .............................................................................. 22 Bill of Materials ............................................................................................................. 26 Screenshots ................................................................................................................. 28 10.1 Fusion GUI Screenshots ......................................................................................... 28 Two-Phase Configuration ................................................................................................. 38 List of Figures 1 TPS40425EVM-PWR594 Schematic...................................................................................... 5 2 TPS40428EVM-PWR594 Schematic...................................................................................... 6 SLVUA86 – July 2014 Submit Documentation Feedback Using the PWR594 EVM Dual Output DC/DC Analog with PMBus Interface Copyright © 2014, Texas Instruments Incorporated 1 www.ti.com 3 PWR594 EVM Recommended Test Set Up.............................................................................. 8 4 Texas Instruments USB-to-GPIO Adapter and Connections 5 Tip and Barrel Measurement ............................................................................................... 9 6 Test Setup for Efficiency Measurement ................................................................................. 13 7 Efficiency of 1.2-V Output Versus Line and Load ...................................................................... 14 8 Efficiency of 1.8-V Output Versus Line and Load ...................................................................... 14 9 Load Regulation of 1.2-V Output ......................................................................................... 15 10 Load Regulation of 1.8-V Output ......................................................................................... 15 11 Bode Plot (12 VIN, 1.2 VOUT, 20 A) ........................................................................................ 16 12 Bode Plot (12 VIN, 1.8 VOUT, 20 A) ........................................................................................ 16 13 Transient Response (12 VIN, 1.2 VOUT, Load Step 10 A to 20 A, 5 A/µs) ............................................ 17 14 Transient Response (12 VIN, 1.2 VOUT, Load Step 20 A to 10 A, 5 A/µs) ............................................ 17 15 Transient Response (12 VIN, 1.8 VOUT, Load Step 10 A to 20 A, 5 A/µs) ............................................ 18 16 Transient Response (12 VIN, 1.8 VOUT, Load Step 20 A to 10 A, 5 A/µs) ............................................ 18 17 Output Ripple (12 VIN, 1.2 VOUT, 20 A) ................................................................................... 19 18 Output Ripple (12 VIN, 1.8 VOUT, 20 A) ................................................................................... 19 19 Enable Startup (12 VIN, 1.2 VOUT, 0 A) 20 20 Enable Startup (12 VIN, 1.8 VOUT, 0 A) 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 .......................................................... ................................................................................... ................................................................................... Enable Startup (12 VIN, 1.2 VOUT, 0.1 A) ................................................................................. Enable Startup (12 VIN, 1.8 VOUT, 0.1 A) ................................................................................. PWR594 EVM Top Layer Assembly Drawing (Top View) ............................................................ PWR594 EVM Bottom Assembly Drawing (Bottom View) ............................................................ PWR594 EVM Top Copper (Top View) ................................................................................. PWR594 EVM Internal Layer 1 (Top View) ............................................................................. PWR594 EVM Internal Layer 2 (Top View) ............................................................................. PWR594 EVM Internal Layer 3 (Top View) ............................................................................. PWR594 EVM Internal Layer 4 (Top View) ............................................................................. PWR594 EVM Bottom Copper (Top View) ............................................................................. Select Device Scanning Mode ............................................................................................ Configure- Limits and On/Off ............................................................................................. Configure - Device Information ........................................................................................... Configure - All Config ...................................................................................................... Configure - Limits and On/Off- On/Off Config Pop-up ................................................................. Change Screens to Other VOUT Rail ...................................................................................... Monitor Screen ............................................................................................................. System Dashboard ......................................................................................................... Status Screen ............................................................................................................... Import Configuration File .................................................................................................. TPS40425EVM 2-Phase Schematic ..................................................................................... TPS40428EVM 2-Phase Schematic ..................................................................................... 9 21 21 22 22 23 23 24 24 25 25 28 29 30 31 32 33 34 35 36 37 38 39 List of Tables 1 PWR594 EVM-001 Electrical Performance Specifications ............................................................. 4 2 Test Point Functions......................................................................................................... 9 3 Connector Functions ....................................................................................................... 10 4 Key Factory Configuration Parameters .................................................................................. 11 5 List of Test Points for Loop Response Measurements ................................................................ 12 6 TPS40425EVM-PWR594 Components List 7 2 ............................................................................ TPS40428EVM-PWR594 Components List ............................................................................ Using the PWR594 EVM Dual Output DC/DC Analog with PMBus Interface Copyright © 2014, Texas Instruments Incorporated 26 27 SLVUA86 – July 2014 Submit Documentation Feedback Description www.ti.com 1 8 TPS40425EVM 2-Phase Components List ............................................................................. 40 9 TPS40428EVM 2-Phase Components List ............................................................................. 41 Description The PWR594EVM is designed as a dual-output converter in default. It uses a nominal 12-V bus to produce a regulated 1.2-V output at up to 20 A of load current, and a regulated 1.8-V output at up to 20 A of load current. The PWR594EVM is designed to demonstrate the controllers in a typical low-voltage application while providing a number of test points to evaluate the performance of the controllers. The PWR594EVM can be configured as 2-phase by changing the bill of materials (BOM). Refer to the TPS40425 (SLUSBO6) and TPS40428 (SLUSBV0) datasheets for more information on multi-phase configuration. To simplify the BOM, power stage CSD95378B is used for both TPS40425 EVM and TPS40428 EVM. In user's application, power stage CSD95372A can be considered for a TPS40425 design at non smartpower mode. 1.1 Typical Applications • • 1.2 Wireless infrastructure Switcher/Router Network/Server/Storage Features • • • • Regulated 1.2-V output up to 20-A DC steady-state output current Regulated 1.8-V output up to 20-A DC steady-state output current Both outputs are marginable and trimmable via the PMBus interface – Programmable UVLO, soft start, and enable via the PMBus interface – Programmable overcurrent warning and fault limits and programmable response to faults via the PMBus interface – Programmable overvoltage and undervoltage fault limit via the PMBus interface – Programmable high- and low-output margin voltages with a maximum range of +10%, –20% of nominal output voltage Convenient test points for probing critical waveforms All trademarks are the property of their respective owners. SLVUA86 – July 2014 Submit Documentation Feedback Using the PWR594 EVM Dual Output DC/DC Analog with PMBus Interface Copyright © 2014, Texas Instruments Incorporated 3 Electrical Performance Specifications 2 www.ti.com Electrical Performance Specifications Table 1 lists the electrical performance specifications. Table 1. PWR594 EVM-001 Electrical Performance Specifications Parameter Test Conditions MIN TYP MAX Unit 7 12 14 V Input Characteristics Voltage range VIN Maximum input current VIN = 7 V, IO1 = 20 A, IO2 = 20 A 10 A No load input current VIN = 12 V, IO1 = 0 A, IO2 = 0 A 80 mA Output voltage, VOUT1 1.2 V Output voltage, VOUT2 1.8 Output Characteristics Output load current, IOUT1 (1) Output load current, IOUT2 0 (1) 0 V 20 A 20 A Line Regulation: Input voltage = 7 V to 14 V 0.5% Output voltage regulation Load Regulation: Output current = 0 A to 20 A, both outputs 0.5% Output voltage ripple, VOUT1 VIN = 12 V, IOUT = 20 A 10 mVpp Output voltage ripple, VOUT2 VIN = 12 V, IOUT = 20 A 10 mVpp Inductor peak current, TPS40425EVM 30 A Inductor peak current, TPS40428EVM 40 A Switching frequency VIN = 12 V 500 kHz Full load efficiency, VOUT1 VIN = 12 V, IO1 = 20 A, VOUT2 disabled 90% Full load efficiency, VOUT2 VIN = 12 V, IO2 = 20 A, VOUT1 disabled 92% Operating temperature Toper Output overcurrent Systems Characteristics (1) 4 25 °C The output current IOUT1 and IOUT2 can be up to 25 A, if the output overcurrent limit (IOUT_OC_FAULT_LIMIT) is set to 40 A. Using the PWR594 EVM Dual Output DC/DC Analog with PMBus Interface Copyright © 2014, Texas Instruments Incorporated SLVUA86 – July 2014 Submit Documentation Feedback Schematic www.ti.com 3 Schematic Figure 1 and Figure 2 illustrate the TPS40425 EVM and TPS40428 EVM schematics. J1 PEC02SAAN PEC02SAAN 3 R3 0 4 SW EN VOS EN_HYS R4 DNP 0 C10 22uF VIN 7 TP1 VIN 2 1 J5 FLT1 C1 100uF D1 BAT54HT1G C2 100uF C3 22uF C4 22uF C6 22uF 4 3 2 1 C7 22uF C8 10uF C9 10uF GND +5V_PG GND R6 210k GND VIN C11 22uF C12 22uF C13 22uF C14 22uF C15 22uF GND VSNS2 GND GSNS2 R1 10.0k R7 0 DNP R9 10.0k R12 280 R13 10.0k FLT TP10 C17 100pF R14 DNP 0 DNP 3300pF C19 TSNS1 COMP DNP R21 0 10 AGND VSNS1 8 VIN C30 0.1uF AGND DIFFO1 R24 40.2k Fsw: 500k Hz 9 R19 DNP C31 0.1uF GSNS1 TP15 R17 1.00 C27 470pF R18 121k C29 470pF 12 11 DNP R15 0 FLT1 R16 4.99k AGND TP14 CS1P 7 PWM ENABLE BOOT PGND VIN C32 3300pF GND REFIN FCCM BOOT_R GSNS1 DNP IOUT TAO/FAULT CS1N DNP R10 0 Q1 CSD95378BQ5M PWM1 C26 VOUT1 VDD VSW TP11 1 C18 0.1uF 2 C20 100uF 3 GND J6 C39 1000pF R23 4.22k GND 11 24 R49 16.2k TP22 22 C42 1uF AGND VOUT1 AGND COMP BP5 R36 0 R38 DNP DNP 0 ISH TSNS2 C54 470pF 11 DNP R43 0 R47 121k 10 R46 DNP R44 1.00 9 C55 470pF 8 C57 0.1uF 7 VIN PWM TAO/FAULT REFIN FCCM ENABLE BOOT BOOT_R VIN DNP IOUT PGND VDD VSW C45 0.1uF 1 C46 100uF 2 AGND R54 4.99k TP25 5 GND VOUT2 C58 1000pF GND R55 1.00 0 TP30 R63 10.0k BP5 CNTL2 4 TP32 3.3V 5 R66 4.99k AGND 6 SMBA LERT 8 R67 280 DNP PMBCLK 9 AGND C63 DNPC64 100uF 100uF 1 2 3 4 Vout2 1.8V, 20A R56 1.00 R53 GND GSNS2 10.0 Q4 GND 1000pF R58 12.4k CS2N GND NT1 C71 CNTL1 7 PEC05DAAN C62 100uF VSNS2 C70 1500pF PMBUS P rogram I nt erf ace SMBALERT PMBDATA C61 100uF AGND TP29 R64 49.9 DNP R65 0 CNTL2 C66 0.22uF CS2P TP28 2 4 6 8 10 C68 R59 R62 DNP J12 C60 100uF TP27 TSNS2 1 3 5 7 9 C59 100uF J11 ED120/4DS R52 4.22k FLT TP31 VSNS2 10.0 GND GND C69 3300pF 3.3V CNTL1 PMBCLK C50 DNPC51 100uF 100uF R45 L3 470nH 6 R57 DNP 0 3.3V SMBALERT PMBCLK PMBDATA C49 100uF TP24 +5V C53 1uF R51 0 C67 100pF R61 DNP C48 100uF GND 4 GND C65 3300pF C47 100uF 3 FLT2 TP26 R60 DNP R39 8.06k Q3 CSD95378BQ5M PWM2 12 AGND R50 0 DNP R34 DNP 0.001 CS2N R35 1.00 13 Address : 9 dec R32 R33 DNP 0.001 DNP 0.001 VOUT2 CS2P R40 10.0k C56 0.1uF VIO=1.8 or 2.5V CS1P AGND TP23 VSNS2 VIO GSNS1 10.0 CS1N C44 1uF PG2 DNP R41 0 AGND J10 PEC02SAAN GND VIN 21 CS2N GSNS2 R27 GND CS2P R48 16.2k GND C41 1000pF Q2 MMBT3904T-7-F 23 PWM2 TSNS2 CS2P CS2N C43 1uF C52 0.1uF AGND 1 2 R26 1.00 TP17 BP5 Vout1 1.2V, 20A ED120/4DS R28 12.4k PGND CS1P CS1N TSNS1 FB1 FLT1 VSNS1 COMP1 GSNS1 ISH2 R42 100 1 2 DIFFO1 PG2 AVSCLK1 ADDR1 J9 PEC02SAAN AVSDATA1 19 9 10 VIO 4 3 2 1 C37 DNPC38 100uF 100uF BP3 BP5 PWM2 18 AGND AGND 27 VDD AGND PWM1 25 BP5 PMBCLK 28 26 BP3 PMBDATA 8 C36 100uF GND PG1 20 7 C35 100uF C34 100uF C40 0.22uF R29 0 DNP 29 TP21 PGND U2 TPS40425RHA SMBALERT FLT2 PMBCLK CNTL2 17 6 FB2 5 PMBDATA COMP2 4 SMBALERT VSNS2 1 2 CNTL2 30 PWM1 16 AGND J8 PEC02SAAN CNTL1 15 3 PG1 GSNS2 CNTL1 ISH1 PHSET 12 1 2 R30 10.0k R31 0 SYNC ADDR0 2 14 1 13 SYNC PHSET C33 100uF R22 0 TSNS1 TP18 VSNS1 10.0 VOUT1 31 32 33 36 34 35 39 37 38 41 40 RT PAD GND TP19 R20 GND R25 1.00 ISH TP20 C24 DNPC25 100uF 100uF TP12 TP13 5 6 AGND J7 PEC02SAAN C23 100uF L2 470nH GND AGND C22 100uF C21 100uF GND C28 1uF +5V 4 GND CS1P TP9 R11 8.06k CS1N TP16 R37 100 TP5 TP6 VSNS1 C16 1500pF PGND R8 49.9 DIFFO1 TP8 GND 13 TP7 Vin 7V - 14V TP4 1 9 GND PAD C5 22uF D2 BAT54HT1G ED120/4DS 8 +5V_PG PG FLT2 +5V_EXT R2 1.10Meg 5 TP3 J4 ED120/2DS 6 FB R5 DNP +5V 2 1 1 2 2 J2 PEC02SAAN TP2 L1 10uH U1 TPS62125DSG 2 1 J3 VIN VOUT2 AGND GND AGND to PGND Strap at ONLY 1 point PMBDATA 10 AGND Near Power Pad of Controller IC Figure 1. TPS40425EVM-PWR594 Schematic SLVUA86 – July 2014 Submit Documentation Feedback Using the PWR594 EVM Dual Output DC/DC Analog with PMBus Interface Copyright © 2014, Texas Instruments Incorporated 5 Schematic www.ti.com J1 PEC02SAAN PEC02SAAN VIN 3 R3 0 EN 4 C10 22uF 2 1 J5 FLT1 C1 100uF D1 BAT54HT1G C2 100uF C3 22uF C4 22uF C9 10uF C6 22uF 4 3 2 1 C7 22uF +5V_PG GND R6 210k GND VIN C11 22uF C12 22uF C13 22uF C14 22uF C15 22uF GND VSNS2 GND GSNS2 R1 10.0k TP7 R8 49.9 DIFFO1 TP8 GND R7 0 R9 10.0k CS1P VSNS1 Q1 CSD95378BQ5M PWM1 R14 DNP 0 C26 DNP 3300pF 11 R15 0 10 AGND COMP DNP R21 0 8 VIN C30 0.1uF AGND DIFFO1 9 R19 DNP C31 0.1uF GSNS1 R24 40.2k Fsw: 500k Hz TP15 R17 1.00 C27 470pF R18 121k C29 470pF AGND VSNS1 12 TSNS1 FLT1 R16 4.99k 7 PWM ENABLE BOOT BOOT_R VIN C32 3300pF GND REFIN FCCM GSNS1 DNP IOUT TAO/FAULT PGND VDD PGND R13 10.0k FLT TP10 C17 100pF R10 0 VSW TP11 1 C18 0.1uF 2 C20 100uF GND J6 C39 1000pF DNP DNP 32 GND 24 R49 16.2k TP22 TSNS2 CS2P AGND VOUT1 TP23 AGND COMP BP5 DNP R41 0 R36 0 ISH TSNS2 11 R43 0 R47 121k 10 R46 DNP R44 1.00 9 C55 470pF 8 C57 0.1uF 7 VIN PWM DNP IOUT TAO/FAULT REFIN FCCM ENABLE BOOT PGND BOOT_R VIN VDD VSW C45 0.1uF 1 C46 100uF 2 R54 4.99k GND C58 1000pF GND TSNS2 TP28 R63 10.0k CNTL2 4 TP32 CNTL2 R66 4.99k C63 DNPC64 100uF 100uF 1 2 3 4 DNP C66 0.22uF R53 Vout2 1.8V, 20A GND GSNS2 10.0 TP27 DNP Q4 C68 DNP 1000pF GND R58 12.4k CS2N R67 280 GND NT1 C71 SMBA LERT 8 DNP PMBCLK 9 AGND PEC05DAAN 3.3V 5 AGND 6 CNTL1 7 SMBALERT PMBDATA C62 100uF VSNS2 C70 1500pF PMBUS P rogram I nt erf ace 2 4 6 8 10 C61 100uF AGND TP29 R64 49.9 DNP R65 0 J12 R56 1.00 DNP CS2P BP5 1 3 5 7 9 R59 DNP 0 R62 DNP TP30 TP31 C60 100uF DNP FLT 3.3V CNTL1 PMBCLK C59 100uF R51 0 J11 ED120/4DS R52 4.22k R55 1.00 C69 3300pF SMBALERT PMBCLK PMBDATA VOUT2 GND 3.3V R61 DNP VSNS2 10.0 GND 6 R57 DNP 0 C67 100pF R60 DNP C50 DNPC51 100uF 100uF R45 L3 470nH TP25 5 DNP TP26 C49 100uF TP24 +5V C53 1uF GND C65 3300pF C48 100uF GND 4 FLT2 AGND C47 100uF 3 AGND R50 0 DNP R39 8.06k Q3 CSD95378BQ5M PWM2 12 C54 470pF R38 0 13 Address : 9 dec R34 DNP 0.001 CS2N R35 1.00 R40 10.0k C56 0.1uF VIO=1.8 or 2.5V R32 R33 DNP 0.001 DNP 0.001 VOUT2 CS2P AGND VSNS2 VIO CS1P C44 1uF PG2 21 AGND J10 PEC02SAAN GSNS1 10.0 CS1N DNPC41 1000pF VIN 22 CS2N GSNS2 R27 TP17 GND CS2P AGND R48 16.2k GND GND DNP Q2 MMBT3904T-7-F C42 1uF 23 PWM2 20 11 C43 1uF C52 0.1uF 1 2 Vout1 1.2V, 20A ED120/4DS DNP BP5 4 3 2 1 C37 DNPC38 100uF 100uF R28 12.4k PGND CS1P TSNS1 FB1 FLT1 CS1N VSNS1 ISH2 R42 100 1 2 COMP1 PG2 AVSCLK1 ADDR1 J9 PEC02SAAN AVSDATA1 19 9 10 C36 100uF BP3 BP5 PWM2 CS2N AGND VIO PWM1 25 VDD AGND AGND R37 100 GSNS1 PMBCLK 8 FLT2 7 28 26 BP5 C35 100uF GND PG1 27 BP3 PMBDATA C34 100uF C40 0.22uF R26 1.00 DNP R29 0 DNP 29 TP21 PGND U2 TPS40428RHA SMBALERT FB2 PMBCLK CNTL2 18 6 17 5 PMBDATA 16 4 SMBALERT COMP2 CNTL2 30 PWM1 VSNS2 1 2 CNTL1 15 AGND J8 PEC02SAAN PG1 14 3 ISH1 PHSET GSNS2 CNTL1 R31 0 SYNC 13 2 C33 100uF R22 DNP 0 R23 4.22k 31 35 34 33 38 37 36 40 41 39 RT PAD 1 ADDR0 SYNC PHSET 12 1 2 DIFFO1 GND TP19 TP20 J7 PEC02SAAN R30 10.0k VSNS1 10.0 VOUT1 R25 1.00 TSNS1 TP18 R20 GND AGND AGND C24 DNPC25 100uF 100uF TP12 TP13 5 GND ISH C23 100uF L2 470nH 6 GND CS1P C22 100uF C21 100uF GND C28 1uF +5V 4 CS1N TP16 TP9 R11 8.06k 3 13 R12 280 C19 TP14 TP5 TP6 CS1N C16 1500pF VOUT1 Vin 7V - 14V TP4 GND 1 9 GND PAD C5 22uF D2 BAT54HT1G ED120/4DS C8 10uF 8 +5V_PG PG FLT2 +5V_EXT R2 1.10Meg 5 FB R5 DNP TP1 VIN TP3 J4 ED120/2DS 6 VOS EN_HYS R4 DNP 0 7 SW +5V 2 1 1 2 2 J2 PEC02SAAN TP2 L1 10uH U1 TPS62125DSG 2 1 J3 VIN VOUT2 AGND GND AGND to PGND Strap at ONLY 1 point PMBDA TA 10 AGND Near Power Pad of Controller IC Figure 2. TPS40428EVM-PWR594 Schematic 6 Using the PWR594 EVM Dual Output DC/DC Analog with PMBus Interface Copyright © 2014, Texas Instruments Incorporated SLVUA86 – July 2014 Submit Documentation Feedback Test Setup www.ti.com 4 Test Setup 4.1 Test and Configuration Software In order to change any of the default configuration parameters on the EVM, it is necessary to obtain the TI Fusion Digital Power Designer software. 4.1.1 Description Fusion Digital Power Designer is the Graphical User Interface (GUI) used to configure and monitor the controller on this EVM. The application uses the PMBus protocol to communicate with the controller over serial bus via TI USB adapter (see Figure 4). 4.1.2 Features Some of the tasks you can perform with the GUI include: • Turn on or off the power supply output, either through the hardware control line or the PMBus operation command. • Monitor real-time data. Items such as output voltage, output current, temperature, warnings and faults which are continuously monitored and displayed by the GUI. • Configure common operating characteristics such as VOUT trim and margin, UVLO, soft-start time, warning and fault thresholds, fault response, and ON/OFF modes. This software is available for download at this location: http://www.ti.com/tool/fusion_digital_power_designer 4.2 Test Equipment Voltage Source: The input voltage source VIN should be a 0-V to 14-V variable DC source capable of supplying 15 ADC. Connect VIN to J5 as shown in Figure 3. Multimeters: It is recommended to use three separate multimeters as shown in Figure 3. One meter to measure VIN, the other two to measure VOUT1 and VOUT2. Output Load: Two variable electronic loads are recommended for the test setup as shown in Figure 3. Both Load 1 and Load 2 should be capable of 20 A. Oscilloscope: An oscilloscope is recommended for measuring output noise and ripple. Output ripple should be measured using a Tip-and-Barrel method or better as shown in Figure 5. Fan: During prolonged operation at high loads, it may be necessary to provide forced air cooling with a small fan aimed at the EVM. The temperature of the devices on the EVM should be maintained at less than 105°C. USB-to-GPIO Interface Adapter: A communications adapter is required between the EVM and the host computer. This EVM was designed to use the Texas Instruments USB-to-GPIO Adapter, see Figure 4. This adapter can be purchased here: http://www.ti.com/tool/usb-to-gpio. 4.2.1 Recommended Wire Gauge • VIN to J5 (12-V input) – The recommended wire size is 2xAWG #10, with the total length of wire less than 4 feet (2 feet input, 2 feet return). • Load1 to J6 (1.2-V output) – The minimum recommended wire size is 2xAWG #10, with the total length of wire less than 4 feet (2 feet OUTPUT, 2 feet return). • Load2 to J11 (1.8-V output) – The minimum recommended wire size is 2xAWG #10, with the total length of wire less than 4 feet (2 feet OUTPUT, 2 feet return). SLVUA86 – July 2014 Submit Documentation Feedback Using the PWR594 EVM Dual Output DC/DC Analog with PMBus Interface Copyright © 2014, Texas Instruments Incorporated 7 Test Setup 4.3 www.ti.com Power Sequence Between Soft-Start and +5 V for Power Stage A +5-V power supply is required by power stage CSD95378B and must be prepared before soft-start. Without preparation, the controller outputs the PWM signal at maximum duty cycle because the power stage is not working and output voltage is not regulated. The +5 V for power stage needs to be provided until the controller is turned off. There is an onboard +5 V generated by the TPS62125 circuit. In default, a jumper is placed on J1 and the onboard +5 V is used for power stage. The FLT1 and FLT2 pins of the controller are connected to the PG pin of TPS62125 via diodes for power sequence between soft-start and onboard +5 V. Only when onboard +5 V is regulated, the FLT pins will be released to allow soft-start. Therefore, if onboard +5 V is selected, the power sequence is provided by the EVM design and no other procedure need to be conducted by user. If an external +5 V is used for power stage, the external +5 V must be prepared before soft-start, and +5 V need to be provided until the controller is turned off. The following list shows the jumper configurations for onboard and external +5 V: • Onboard +5 V (In default): place jumpers on J1 and J3, remove jumper on J2 • External +5 V: place jumpers on J2 and J3, remove jumper on J1 4.4 Recommended Test Setup Figure 3 shows the recommended test setup. Figure 3. PWR594 EVM Recommended Test Set Up 8 Using the PWR594 EVM Dual Output DC/DC Analog with PMBus Interface Copyright © 2014, Texas Instruments Incorporated SLVUA86 – July 2014 Submit Documentation Feedback Test Setup www.ti.com 4.5 USB Interface Adapter and Cable Figure 4 illustrates the USB interface adapter and cable. Figure 4. Texas Instruments USB-to-GPIO Adapter and Connections Figure 5 illustrates the tip and barrel measurement. Figure 5. Tip and Barrel Measurement 4.6 List of Test Points and Connectors Table 2 lists the test point functions. Table 2. Test Point Functions Test Point Type Name TP1 T-H Loop VIN VIN+ measurement point TP4 T-H Loop GND VIN– measurement point TP12 T-H Loop VOUT1 SLVUA86 – July 2014 Submit Documentation Feedback Description VOUT1+ measurement point Using the PWR594 EVM Dual Output DC/DC Analog with PMBus Interface Copyright © 2014, Texas Instruments Incorporated 9 Test Setup www.ti.com Table 2. Test Point Functions (continued) Test Point Type TP17 TP9 Name Description T-H Loop GND VOUT1– measurement point T-H Loop VSNS1 VSNS1 measurement point TP11 T-H Loop GSNS1 GSNS1 measurement point TP13 T-H Loop SW1 Switching point of Channel 1 TP21 T-H Loop PWM1 TP18 T-H Loop PG1 TP10 T-H Loop COMP1 TP2 T-H Loop FLT1 FLT signal of Channel 1 TP8 T-H Loop CH1A Input for control loop measurements for Channel 1 TP7 T-H Loop CH1B OUTPUT for control loop measurements for Channel 1 TP24 T-H Loop VOUT2 VOUT2+ measurement point TP27 T-H Loop GND VOUT2– measurement point TP5 T-H Loop VSNS2 VSNS2 measurement point TP6 T-H Loop GSNS2 GSNS2 measurement point TP25 T-H Loop SW2 Switching point of Channel 2 TP22 T-H Loop PWM2 TP23 T-H Loop PG2 TP26 T-H Loop COMP2 TP3 T-H Loop FLT2 FLT signal of Channel 2 TP28 T-H Loop CH2A Input for control loop measurements for Channel 2 TP29 T-H Loop CH2B OUTPUT for control loop measurements for Channel 2 TP19 T-H Loop SYNC SYNC signal TP20 T-H Loop PHSET PHSET signal TP30 T-H Loop SMB SMBALERT signal TP31 T-H Loop 3.3V 3.3V pull-up voltage of PMBus PWM signal of Channel1 PGOOD signal of Channel 1 COMP signal of Channel 1 PWM signal of Channel2 PGOOD signal of Channel 2 COMP signal of Channel 2 Table 3 lists the EVM connector functions. Table 3. Connector Functions 10 Connector Type Description J1 PEC02SAAN Use onboard +5 V for power stage J2 PEC02SAAN Use external +5 V for power stage J3 PEC02SAAN Connect the input of onboard +5-V converter to VIN J4 ED120/2DS External +5-V connector J5 ED120/2DS VIN connector J6 ED120/2DS VOUT1 connector J7 PEC02SAAN CNTL1 connector J8 PEC02SAAN CNTL2 connector J9 PEC02SAAN AVSDATA connector J10 PEC02SAAN AVSCLK connector J11 ED120/2DS VOUT2 connector J12 PEC05DAAN PMBus connector Using the PWR594 EVM Dual Output DC/DC Analog with PMBus Interface Copyright © 2014, Texas Instruments Incorporated SLVUA86 – July 2014 Submit Documentation Feedback EVM Configuration Using the Fusion GUI www.ti.com 5 EVM Configuration Using the Fusion GUI The controller on this EVM leaves the factory pre-configured. See Table 4 for a short list of key factory configuration parameters as obtained from the configuration file. Table 4. Key Factory Configuration Parameters Cmd NAME CmdCodeHex EncodedHex Decoded Comments VIN_OFF 0x36 0xF014 4.0 V Turn OFF voltage VIN_ON 0x35 0xF01C 4.25 V Turn ON voltage IOUT_CAL_GAIN 0x38 0x8021 0.5 mΩ Equivalent DCR value IOUT_CAL_OFFSET 0x39 0xE000 0.0000 A Current offset for GUI readout IOUT_OC_FAULT_LIMIT 0x46 0xF83C 30.0 A TPS40425EVM, OC fault level 0xF850 40.0 A TPS40428EVM, OC fault level IOUT_OC_FAULT_RESPONSE 0x47 0x3C Restart continuously Response to OC fault IOUT_OC_WARN_LIMIT 0x4A 0xF836 27.0 A TPS40425EVM, OC warning level 0xF84A 37.0 A TPS40428EVM, OC warning level MFR_04 (VREF_TRIM) 0xD4 0x0000 0.000 V Trim voltage ON_OFF_CONFIG 0x02 0x16 Control only, logic high Control signal and OPERATION command not required OT_FAULT_LIMIT 0x4F 0x007D 125 C TPS40425 EVM, OT fault level 0x0091 145 C TPS40428 EVM, OT fault level 0x0064 100 C TPS40425 EVM, OT warn level 0x007D 125 C TPS40428 EVM, OT warn level 0xE02B 2.7 ms Soft-start time OT_WARN_LIMIT 0x51 TON_RISE 0x61 If it is desired to configure the EVM to settings other than the factory settings shown above, the TI Fusion Digital Power Designer software can be used for reconfiguration. It is necessary to have input voltage applied to the EVM prior to launching the software so that the controller may respond to the GUI and the GUI can recognize the controller. In order to avoid any converter activity during configuration, an input voltage less than VIN_ON voltage should be applied. An input voltage of 4 V is recommended. 5.1 Configuration Procedure 1. 2. 3. 4. Adjust the input supply to provide 4 VDC, current limited to 1 A. Apply the input voltage to the EVM. Refer to Figure 3 and Figure 4 for connections and test setup. Launch the Fusion GUI software. Refer to the screenshots in Section 10 for more information. Configure the EVM operating parameters as desired. NOTE: The IOUT_CAL_GAIN parameter is used by the controller in the calculation of output current level. In the TPS40425 EVM, the controller is at non smart-power mode in default, the IOUT_CAL_GAIN needs to be equal to the equivalent inductor DCR value for accurate current readout. In the TPS40428 EVM, the controller is at smart-power mode in default, IOUT_CAL_GAIN must be set to 0.5 mΩ for accurate current readout. The incorrect IOUT_CAL_GAIN value also affects OC Fault and OC Warn performance. The TON_RISE parameter may affect proper startup if the rise time and output capacitance bank result in a current that exceeds the OC Fault level. The startup surge current in the output capacitance bank is added to the load current, so the sum of these two currents must be less than the OC Fault level for proper startup. SLVUA86 – July 2014 Submit Documentation Feedback Using the PWR594 EVM Dual Output DC/DC Analog with PMBus Interface Copyright © 2014, Texas Instruments Incorporated 11 Test Procedure www.ti.com 6 Test Procedure 6.1 Line/Load Regulation and Efficiency Measurement Procedure 1. Set up the EVM as described in Figure 3. 2. Ensure both electronic loads are set to draw 0 Adc. 3. Increase VIN from 0 V to 12 V using voltage meter #3 to measure input voltage. 4. Use voltage meter #1 to measure output voltage VOUT1. 5. Vary the load from 0 to 20 Adc. VOUT1 should remain in regulation as defined in Table 1. 6. Vary VIN from 7 V to 14 V. VOUT1 should remain in regulation as defined in Table 1. 7. Decrease the load to 0 A. 8. Use voltage meter #2 to measure output voltage VOUT2. 9. Vary the load from 0 to 20 Adc. VOUT2 should remain in regulation as defined in Table 1. 10. Vary VIN from 7 V to 14 V. VOUT2 should remain in regulation as defined in Table 1. 11. Decrease the load to 0 A. 12. Decrease VIN to 0 V. 6.2 Control Loop Gain and Phase Measurement Procedure The PWR594 EVM includes a 49.9-Ω series resistor in the feedback loop for both VOUT1 and VOUT2. These resistors are used for loop response analysis, and are accessible at the test points TP7 and TP8 for VOUT1, and TP28 and TP29 for VOUT2. Those test points should be used during loop response measurements as the injection points for the loop perturbation. See the description in Table 5. Table 5. List of Test Points for Loop Response Measurements Test Point Node Name Description Comment TP8 INPUT1 Input to feedback divider of VOUT1 The amplitude of the perturbation at this node should be limited to less than 100 mV TP7 OUTPUT1 Resulting output of VOUT1 Bode can be measured by a network analyzer as TP7/TP8 TP28 INPUT2 Input to feedback divider of VOUT2 The amplitude of the perturbation at this node should be limited to less than 100 mV TP29 VOUT2 Resulting output of VOUT2 Bode can be measured by a network analyzer as TP29/TP28 Measure only one output at a time, with the following procedure: 1. Set up the EVM as described in Figure 3. 2. For VOUT1, connect the network analyzer’s isolation transformer from TP7 to TP8, 3. Connect the input signal measurement probe to TP8. Connect the output signal measurement probe to TP7. 4. Connect the ground leads of both probe channels to TP16. 5. On the network analyzer, measure the Bode as TP7/TP8 (Out/In). 6. For VOUT2, connect the network analyzer’s isolation transformer from TP29 to TP28. 7. Connect the input signal measurement probe to TP28. Connect output signal measurement probe to TP29. 8. Connect the ground leads of both probe channels to TP15. 9. On the network analyzer, measure the Bode as TP29/TP28 (Out/In). 10. Disconnect the isolation transformer from the bode plot test points before making other measurements, because the signal injection into the feedback loop may interfere with the accuracy of other measurements. 12 Using the PWR594 EVM Dual Output DC/DC Analog with PMBus Interface Copyright © 2014, Texas Instruments Incorporated SLVUA86 – July 2014 Submit Documentation Feedback Test Procedure www.ti.com 6.3 Efficiency In order to measure the efficiency of the power train on the EVM, it is important to measure the voltages at the correct location. This is necessary because otherwise the measurements will include losses that are not related to the power train itself. Losses incurred by the voltage drop in the copper traces and in the input and output connectors are not related to the efficiency of the power train, and they should not be included in efficiency measurements. When measuring the efficiency of VOUT1, disable VOUT2 via the Fusion GUI. Likewise, when measuring the efficiency of VOUT2, disable VOUT1. Input current can be measured at any point in the input wires, and output current can be measured anywhere in the output wires of the output being measured. Figure 6 shows the measurement points for input voltage and output voltage. VIN1 and VOUT1 are measured to calculate the efficiency of channel 1, and VIN2 and VOUT2 are measured to calculate the efficiency of channel 2. Using these measurement points will result in efficiency measurements that do not include losses due to the connectors and PWB traces. Figure 6. Test Setup for Efficiency Measurement 6.4 Equipment Turn On and Shutdown • • Turn on sequence: – Turn on external +5 V if in use. Skip this step if onboard +5 V is in use. – Turn on input power supply and increase VIN above 7 V. – Turn on PWM. – Adjust load current on both outputs, as desired. Shutdown sequence: – Reduce the load current on both outputs to zero amperes. – Turn off PWM. – Reduce input voltage to zero volts. – Shut down external +5 V, if in use. Skip this step if onboard +5 V is in use. – Shut down the external FAN if in use. SLVUA86 – July 2014 Submit Documentation Feedback Using the PWR594 EVM Dual Output DC/DC Analog with PMBus Interface Copyright © 2014, Texas Instruments Incorporated 13 Performance Data and Typical Characteristic Curves 7 www.ti.com Performance Data and Typical Characteristic Curves Figure 7 to Figure 22 present typical performance curves and waveforms for the TPS40425EVM (TPS40425 EVM). Collect curves and waveforms on the TPS40428EVM with the test procedures in the previous section. 7.1 Efficiency Figure 7. Efficiency of 1.2-V Output Versus Line and Load Figure 8. Efficiency of 1.8-V Output Versus Line and Load 14 Using the PWR594 EVM Dual Output DC/DC Analog with PMBus Interface Copyright © 2014, Texas Instruments Incorporated SLVUA86 – July 2014 Submit Documentation Feedback www.ti.com 7.2 Performance Data and Typical Characteristic Curves Load Regulation Figure 9. Load Regulation of 1.2-V Output Figure 10. Load Regulation of 1.8-V Output SLVUA86 – July 2014 Submit Documentation Feedback Using the PWR594 EVM Dual Output DC/DC Analog with PMBus Interface Copyright © 2014, Texas Instruments Incorporated 15 Performance Data and Typical Characteristic Curves 7.3 www.ti.com Bode Plot Figure 11. Bode Plot (12 VIN, 1.2 VOUT, 20 A) Figure 12. Bode Plot (12 VIN, 1.8 VOUT, 20 A) 16 Using the PWR594 EVM Dual Output DC/DC Analog with PMBus Interface Copyright © 2014, Texas Instruments Incorporated SLVUA86 – July 2014 Submit Documentation Feedback Performance Data and Typical Characteristic Curves www.ti.com 7.4 Transient Response spacerof16characCh1 = VOUT1 at 20 mV/division, Ch2 = Iout1 at 10 A/division Figure 13. Transient Response (12 VIN, 1.2 VOUT, Load Step 10 A to 20 A, 5 A/µs) spacerof16characCh1 = VOUT1 at 20 mV/division, Ch2 = Iout1 at 10 A/division Figure 14. Transient Response (12 VIN, 1.2 VOUT, Load Step 20 A to 10 A, 5 A/µs) SLVUA86 – July 2014 Submit Documentation Feedback Using the PWR594 EVM Dual Output DC/DC Analog with PMBus Interface Copyright © 2014, Texas Instruments Incorporated 17 Performance Data and Typical Characteristic Curves www.ti.com spacerof16characCh1 = VOUT2 at 20 mV/division, Ch2 = Iout2 at 10 A/division Figure 15. Transient Response (12 VIN, 1.8 VOUT, Load Step 10 A to 20 A, 5 A/µs) spacerof16characCh1 = VOUT2 at 20 mV/division, Ch2 = Iout2 at 10 A/division Figure 16. Transient Response (12 VIN, 1.8 VOUT, Load Step 20 A to 10 A, 5 A/µs) 18 Using the PWR594 EVM Dual Output DC/DC Analog with PMBus Interface Copyright © 2014, Texas Instruments Incorporated SLVUA86 – July 2014 Submit Documentation Feedback www.ti.com 7.5 Performance Data and Typical Characteristic Curves Output Ripple spacerof16characCh1 = VOUT1 at 10 mV/division, Ch2 = SW node at 5 V/division Figure 17. Output Ripple (12 VIN, 1.2 VOUT, 20 A) spacerof16characCh1 = VOUT2 at 10 mV/division, Ch2 = SW node at 10 V/division Figure 18. Output Ripple (12 VIN, 1.8 VOUT, 20 A) SLVUA86 – July 2014 Submit Documentation Feedback Using the PWR594 EVM Dual Output DC/DC Analog with PMBus Interface Copyright © 2014, Texas Instruments Incorporated 19 Performance Data and Typical Characteristic Curves 7.6 www.ti.com Enable Turn On and Turn Off Waveforms spacerof16characCh1 = VOUT1 at 500 mV/division, Ch2 = SW node at 10 V/division, Ch3 = CNTL1 at 2 V/division Figure 19. Enable Startup (12 VIN, 1.2 VOUT, 0 A) spacerof16characCh1 = VOUT2 at 1 V/division, Ch2 = SW node at 10 V/division, Ch3 = CNTL2 at 2 V/division Figure 20. Enable Startup (12 VIN, 1.8 VOUT, 0 A) 20 Using the PWR594 EVM Dual Output DC/DC Analog with PMBus Interface Copyright © 2014, Texas Instruments Incorporated SLVUA86 – July 2014 Submit Documentation Feedback www.ti.com Performance Data and Typical Characteristic Curves spacerof16characCh1 = VOUT1 at 500 mV/division, Ch2 = SW node at 10 V/division, Ch3 = CNTL1 at 2 V/division Figure 21. Enable Startup (12 VIN, 1.2 VOUT, 0.1 A) spacerof16characCh1 = VOUT2 at 1 V/division, Ch2 = SW node at 10 V/division, Ch3 = CNTL2 at 2 V/division Figure 22. Enable Startup (12 VIN, 1.8 VOUT, 0.1 A) SLVUA86 – July 2014 Submit Documentation Feedback Using the PWR594 EVM Dual Output DC/DC Analog with PMBus Interface Copyright © 2014, Texas Instruments Incorporated 21 EVM Assembly Drawing and PCB Layout 8 www.ti.com EVM Assembly Drawing and PCB Layout Figure 23 through Figure 30 show the design of the PWR594 EVM printed circuit board. Figure 23. PWR594 EVM Top Layer Assembly Drawing (Top View) Figure 24. PWR594 EVM Bottom Assembly Drawing (Bottom View) 22 Using the PWR594 EVM Dual Output DC/DC Analog with PMBus Interface Copyright © 2014, Texas Instruments Incorporated SLVUA86 – July 2014 Submit Documentation Feedback EVM Assembly Drawing and PCB Layout www.ti.com Figure 25. PWR594 EVM Top Copper (Top View) Figure 26. PWR594 EVM Internal Layer 1 (Top View) SLVUA86 – July 2014 Submit Documentation Feedback Using the PWR594 EVM Dual Output DC/DC Analog with PMBus Interface Copyright © 2014, Texas Instruments Incorporated 23 EVM Assembly Drawing and PCB Layout www.ti.com Figure 27. PWR594 EVM Internal Layer 2 (Top View) Figure 28. PWR594 EVM Internal Layer 3 (Top View) 24 Using the PWR594 EVM Dual Output DC/DC Analog with PMBus Interface Copyright © 2014, Texas Instruments Incorporated SLVUA86 – July 2014 Submit Documentation Feedback EVM Assembly Drawing and PCB Layout www.ti.com Figure 29. PWR594 EVM Internal Layer 4 (Top View) Figure 30. PWR594 EVM Bottom Copper (Top View) SLVUA86 – July 2014 Submit Documentation Feedback Using the PWR594 EVM Dual Output DC/DC Analog with PMBus Interface Copyright © 2014, Texas Instruments Incorporated 25 Bill of Materials 9 www.ti.com Bill of Materials Table 6 lists the BOM for the PWR594-001 (TPS40425 EVM). Table 7 lists the BOM for the PWR594-002 (TPS40428 EVM). Table 6. TPS40425EVM-PWR594 Components List Qty Designator Description Part Number Manufacturer 2 C1, C2 CAP, AL, 100 µF, 25 V, ±20%, 0.3 Ω, SMD EEE-FC1E101P Panasonic 11 C3–C7, C10– C15 CAP, CERM, 22 µF, 25 V, ±10%, X5R, 1210 STD STD 2 C8, C9 CAP, CERM, 10 µF, 10 V, ±10%, X5R, 0805 STD STD 2 C16, C70 CAP, CERM, 1500 pF, 25 V, ±10%, X7R, 0603 STD STD 2 C17, C67 CAP, CERM, 100 pF, 50 V, ±5%, C0G/NP0, 0603 STD STD 7 C18, C30, C31, C45, C52, C56, C57 CAP, CERM, 0.1 µF, 25 V, ±10%, X7R, 0603 STD STD 20 C20–C24, C33–C37, C46–C50, C59–C63 CAP, CERM, 100 µF, 6.3 V, ±20%, X5R, 1210 STD STD 2 C26, C69 CAP, CERM, 3300 pF, 25 V, ±10%, X7R, 0603 STD STD 4 C27, C29, C54, C55 CAP, CERM, 470 pF, 50 V, ±10%, X7R, 0603 STD STD 5 C28, C42–C44, C53 CAP, CERM, 1 µF, 25 V, ±10%, X5R, 0603 STD STD 2 C32, C65 CAP, CERM, 3300 pF, 50 V, ±10%, X7R, 0603 STD STD 4 C39, C41, C58, C68 CAP, CERM, 1000 pF, 50 V, ±10%, X7R, 0603 STD STD 2 C40, C66 CAP, CERM, 0.22 µF, 25 V, ±10%, X7R, 0603 STD STD 2 D1, D2 Diode, Schottky, 30 V, 0.2 A, SOD-323 BAT54HT1G ON Semiconductor 7 J1–J3, J7–J10 Header, 100 mil, 2x1, Tin plated, TH PEC02SAAN Sullins Connector Solutions 1 J4 TERMINAL BLOCK 5.08 mm VERT 2POS, TH ED120/2DS On-Shore Technology 3 J5, J6, J11 TERMINAL BLOCK 5.08 mm VERT 4POS, TH ED120/4DS On-Shore Technology 1 J12 Header, 100 mil, 5x2, Tin plated, TH PEC05DAAN Sullins Connector Solutions 1 L1 Inductor, Shielded Drum Core, Ferrite, 10 µH, 0.7 A, 0.33 Ω, SMD LPS3314-103MLB Coilcraft 2 L2, L3 Inductor, Shielded Drum Core, WE-Perm, 470 nH, 30 A, 0.00067 Ω, SMD 744355147 Wurth Elektronik eiSos 2 Q1, Q3 Synchronous Buck NexFET Power Stage, DQP0012A CSD95378BQ5M Texas Instruments 2 Q2, Q4 Transistor, NPN, 20 V, 0.2 A, SOT-523 MMBT3904T-7-F Diodes Inc. 1 R2 RES, 1.10 MΩ, 1%, 0.1 W, 0603 STD STD 5 R3, R22, R29, R51, R59 RES, 0 Ω, 5%, 0.1 W, 0603 STD STD 1 R6 RES, 210 kΩ, 1%, 0.1 W, 0603 STD STD 2 R8, R64 RES, 49.9 Ω, 1%, 0.1 W, 0603 STD STD 6 R1, R9, R13, R30, R40, R63 RES, 10.0 kΩ, 1%, 0.1 W, 0603 STD STD 2 R12, R67 RES, 280 Ω, 1%, 0.1 W, 0603 STD STD 3 R16, R54, R66 RES, 4.99 kΩ, 1%, 0.1 W, 0603 STD STD 7 R17, R25, R26, R35, R44, R55, R56 RES, 1.00 Ω, 1%, 0.1 W, 0603 STD STD 2 R18, R47 RES, 121 kΩ, 1%, 0.1 W, 0603 STD STD 4 R20, R27, R45, R53 RES, 10.0 Ω, 1%, 0.1 W, 0603 STD STD 2 R23, R52 RES, 4.22 kΩ, 1%, 0.1 W, 0603 STD STD 1 R24 RES, 40.2 kΩ, 1%, 0.1 W, 0603 STD STD 2 R28, R58 RES, 12.4 kΩ, 1%, 0.1 W, 0603 STD STD 2 R37, R42 RES, 100 Ω, 1%, 0.1 W, 0603 STD STD 2 R48, R49 RES, 16.2 kΩ, 1%, 0.1 W, 0603 STD STD 2 SH-J1, SH-J3 Shunt, 100 mil, Gold plated, Black 969102-0000-DA 3M 6 TP1, TP5, TP9, TP12, TP24, TP31 Test Point, Miniature, Red, TH 5000 Keystone 17 TP2, TP3, TP7, TP8, TP10, TP13, TP18–TP23, TP25, TP26, TP28–TP30 Test Point, Miniature, White, TH 5002 Keystone 26 Using the PWR594 EVM Dual Output DC/DC Analog with PMBus Interface Copyright © 2014, Texas Instruments Incorporated SLVUA86 – July 2014 Submit Documentation Feedback Bill of Materials www.ti.com Table 6. TPS40425EVM-PWR594 Components List (continued) Qty Designator Description Part Number Manufacturer 9 TP4, TP6, TP11, TP14–TP17, TP27, TP32 Test Point, Miniature, Black, TH 5001 Keystone 1 U1 IC, 3 V–17 V, 200 mA High Efficient Buck Converter TPS62125DSG TI U2 IC, Dual output, 2-Phase, Stackable PMBUS Synchronous Buck Driverless Controller with AVS Bus TPS40425RHA TI 1 Table 7. TPS40428EVM-PWR594 Components List Qty Designator Description Part Number Manufacturer 2 C1, C2 CAP, AL, 100 µF, 25 V, ±20%, 0.3 Ω, SMD EEE-FC1E101P Panasonic 11 C3–C7, C10–C15 CAP, CERM, 22 µF, 25 V, ±10%, X5R, 1210 STD STD 2 C8, C9 CAP, CERM, 10 µF, 10 V, ±10%, X5R, 0805 STD STD 2 C16, C70 CAP, CERM, 1500 pF, 25 V, ±10%, X7R, 0603 STD STD 2 C17, C67 CAP, CERM, 100 pF, 50 V, ±5%, C0G/NP0, 0603 STD STD 7 C18, C30, C31, C45, C52, C56, C57 CAP, CERM, 0.1 µF, 25 V, ±10%, X7R, 0603 STD STD 20 C20–C24, C33–C37, C46–C50, C59–C63 CAP, CERM, 100 µF, 6.3 V, ±20%, X5R, 1210 STD STD 2 C26, C69 CAP, CERM, 3300 pF, 25 V, ±10%, X7R, 0603 STD STD 4 C27, C29, C54, C55 CAP, CERM, 470 pF, 50 V, ±10%, X7R, 0603 STD STD 5 C28, C42–C44, C53 CAP, CERM, 1 µF, 25 V, ±10%, X5R, 0603 STD STD 2 C32, C65 CAP, CERM, 3300 pF, 50 V, ±10%, X7R, 0603 STD STD 2 C39, C58 CAP, CERM, 1000 pF, 50 V, ±10%, X7R, 0603 STD STD 2 D1, D2 Diode, Schottky, 30 V, 0.2 A, SOD-323 BAT54HT1G ON Semiconductor 7 J1–J3, J7–J10 Header, 100 mil, 2x1, Tin plated, TH PEC02SAAN Sullins Connector Solutions 1 J4 TERMINAL BLOCK 5.08 mm VERT 2POS, TH ED120/2DS On-Shore Technology 3 J5, J6, J11 TERMINAL BLOCK 5.08 mm VERT 4POS, TH ED120/4DS On-Shore Technology 1 J12 Header, 100 mil, 5x2, Tin plated, TH PEC05DAAN Sullins Connector Solutions 1 L1 Inductor, Shielded Drum Core, Ferrite, 10 µH, 0.7 A, 0.33 Ω, SMD LPS3314-103MLB Coilcraft 2 L2, L3 Inductor, Shielded Drum Core, WE-Perm, 470 nH, 30 A, 0.00067 Ω, SMD 744355147 Wurth Elektronik eiSos 1 LBL1 Thermal Transfer Printable Labels, 1.250" W x 0.250" H - 10,000 per roll THT-13-457-10 Brady 2 Q1, Q3 Synchronous Buck NexFET Power Stage, DQP0012A CSD95378BQ5M Texas Instruments 1 R2 RES, 1.10 MΩ, 1%, 0.1 W, 0603 STD STD 7 R3, R7, R10, R15, R36, R38, R43 RES, 0 Ω, 5%, 0.1 W, 0603 STD STD 1 R6 RES, 210 kΩ, 1%, 0.1 W, 0603 STD STD 2 R8, R64 RES, 49.9 Ω, 1%, 0.1 W, 0603 STD STD 6 R1, R9, R13, R30, R40, R63 RES, 10.0 kΩ, 1%, 0.1 W, 0603 STD STD 2 R12, R67 RES, 280 Ω, 1%, 0.1 W, 0603 STD STD 3 R16, R54, R66 RES, 4.99 kΩ, 1%, 0.1 W, 0603 STD STD 7 R17, R25, R26, R35, R44, R55, R56 RES, 1.00 Ω, 1%, 0.1 W, 0603 STD STD 2 R18, R47 RES, 121 kΩ, 1%, 0.1 W, 0603 STD STD 4 R20, R27, R45, R53 RES, 10.0 Ω, 1%, 0.1 W, 0603 STD STD 1 R24 RES, 40.2 kΩ, 1%, 0.1 W, 0603 STD STD 2 R37, R42 RES, 100 Ω, 1%, 0.1 W, 0603 STD STD 2 R48, R49 RES, 16.2 kΩ, 1%, 0.1 W, 0603 STD STD 2 SH-J1, SH-J3 Shunt, 100 mil, Gold plated, Black 969102-0000-DA 3M 6 TP1, TP5, TP9, TP12, TP24, TP31 Test Point, Miniature, Red, TH 5000 Keystone SLVUA86 – July 2014 Submit Documentation Feedback Using the PWR594 EVM Dual Output DC/DC Analog with PMBus Interface Copyright © 2014, Texas Instruments Incorporated 27 Screenshots www.ti.com Table 7. TPS40428EVM-PWR594 Components List (continued) Qty Designator Description Part Number Manufacturer 17 TP2, TP3, TP7, TP8, TP10, TP13, TP18–TP23, TP25, TP26, TP28–TP30 Test Point, Miniature, White, TH 5002 Keystone 9 TP4, TP6, TP11, TP14–TP17, TP27, TP32 Test Point, Miniature, Black, TH 5001 Keystone 1 U1 IC, 3 V-17 V, 200-mA High Efficient Buck Converter TPS62125DSG TI U2 IC, Dual output, 2-Phase, Stackable PMBUS Synchronous Buck Driverless Controller with AVS Bus TPS40428RHA TI 1 10 Screenshots 10.1 Fusion GUI Screenshots When launching the Fusion GUI, select DEVICE_CODE as scanning mode to find TPS40425 or TPS40428. Figure 31. Select Device Scanning Mode 28 Using the PWR594 EVM Dual Output DC/DC Analog with PMBus Interface Copyright © 2014, Texas Instruments Incorporated SLVUA86 – July 2014 Submit Documentation Feedback Screenshots www.ti.com • Use the screen displayed in Figure 32 to configure the following: – OC Fault and OC Warn – OT Fault and OT Warn – Power Good Limits – Fault response – UVLO – On/Off Config – Soft Start time – Margin voltage Figure 32. Configure- Limits and On/Off SLVUA86 – July 2014 Submit Documentation Feedback Using the PWR594 EVM Dual Output DC/DC Analog with PMBus Interface Copyright © 2014, Texas Instruments Incorporated 29 Screenshots • www.ti.com Use the screen in Figure 33 to configure: – Vref Trim – IOUT_CAL_GAIN – Write Protect – MFR_SPECIFIC_21 register Figure 33. Configure - Device Information 30 Using the PWR594 EVM Dual Output DC/DC Analog with PMBus Interface Copyright © 2014, Texas Instruments Incorporated SLVUA86 – July 2014 Submit Documentation Feedback Screenshots www.ti.com Use this screen (Figure 34) to configure all of the configurable parameters, also shows other details like Hex encoding. Figure 34. Configure - All Config SLVUA86 – July 2014 Submit Documentation Feedback Using the PWR594 EVM Dual Output DC/DC Analog with PMBus Interface Copyright © 2014, Texas Instruments Incorporated 31 Screenshots www.ti.com After a change is selected, an orange “U” icon is displayed, offering an Undo Change option. Change is not retained until either Write to Hardware or Store User Defaults is selected. When Write to Hardware is selected, the change is committed to volatile memory and defaults back to previous setting upon input power cycle. When Store User Defaults is selected, the change is committed to non-volatile memory and becomes the new default (Figure 35) Figure 35. Configure - Limits and On/Off- On/Off Config Pop-up 32 Using the PWR594 EVM Dual Output DC/DC Analog with PMBus Interface Copyright © 2014, Texas Instruments Incorporated SLVUA86 – July 2014 Submit Documentation Feedback Screenshots www.ti.com A scroll-down menu in the upper right corner can be selected to change the view screens to one output rail or the other (Figure 36). Figure 36. Change Screens to Other VOUT Rail SLVUA86 – July 2014 Submit Documentation Feedback Using the PWR594 EVM Dual Output DC/DC Analog with PMBus Interface Copyright © 2014, Texas Instruments Incorporated 33 Screenshots www.ti.com When the Monitor screen is selected (Figure 37), the screen changes to display real-time data of the parameters that are measured by the controller. This screen provides access to: • Graphs of VOUT, Iout, Temperature, and Pout. As shown, the Pout display is turned OFF. • Start/Stop Polling which turns ON or OFF the real-time display of data. • Quick access to On/Off config • Control pin activation, and OPERATION command. • Margin control. • Clear Fault. Selecting Clear Faults clears any prior fault flags. Figure 37. Monitor Screen 34 Using the PWR594 EVM Dual Output DC/DC Analog with PMBus Interface Copyright © 2014, Texas Instruments Incorporated SLVUA86 – July 2014 Submit Documentation Feedback Screenshots www.ti.com Selecting System Dashboard from mid-left screen adds a new window which displays system level information (Figure 38). Figure 38. System Dashboard SLVUA86 – July 2014 Submit Documentation Feedback Using the PWR594 EVM Dual Output DC/DC Analog with PMBus Interface Copyright © 2014, Texas Instruments Incorporated 35 Screenshots www.ti.com Selecting Status from lower left corner shows the status of the controller (Figure 39). Figure 39. Status Screen 36 Using the PWR594 EVM Dual Output DC/DC Analog with PMBus Interface Copyright © 2014, Texas Instruments Incorporated SLVUA86 – July 2014 Submit Documentation Feedback Screenshots www.ti.com Selecting the pull down menu File- Import Project from the upper left menu bar can be used to configure all parameters in the device at once with a desired configuration, or even revert back to a known-good configuration (Figure 40). This action results in a browse-type sequence where the desired configure file can be located and loaded. Figure 40. Import Configuration File SLVUA86 – July 2014 Submit Documentation Feedback Using the PWR594 EVM Dual Output DC/DC Analog with PMBus Interface Copyright © 2014, Texas Instruments Incorporated 37 Two-Phase Configuration 11 www.ti.com Two-Phase Configuration The PWR594 EVM can be configured as 2-phase by changing the BOM. Figure 41 and Figure 42 show the schematics of 2-phase configuration. Table 8 and Table 9 are the components lists of 2-phase configuration. J1 PEC02SAAN PEC02SAAN 3 R3 0 4 SW EN VOS EN_HYS R4 DNP 0 C10 22uF VIN 7 TP1 VIN 2 1 J5 FLT1 C1 100uF D1 BAT54HT1G C2 100uF C3 22uF C4 22uF C6 22uF 4 3 2 1 C7 22uF C8 10uF C9 10uF GND +5V_PG GND R6 210k GND VIN C11 22uF C12 22uF C13 22uF C14 22uF C15 22uF GND VSNS2 GND GSNS2 R1 10.0k TP8 R9 10.0k R12 280 C17 47pF R13 10.0k FLT TP10 R14 0 DNP 3300pF C19 TSNS1 COMP R21 0 10 VSNS1 8 VIN C30 0.1uF AGND DIFFO1 9 R19 DNP C31 0.1uF GSNS1 R24 40.2k Fsw: 500k Hz TP15 R17 1.00 C27 470pF R18 121k C29 470pF AGND 12 11 DNP R15 0 FLT1 R16 4.99k AGND TP14 CS1P 7 PWM ENABLE BOOT PGND VIN C32 3300pF GND REFIN FCCM BOOT_R GSNS1 DNP IOUT TAO/FAULT CS1N DNP R10 0 Q1 CSD95378BQ5M PWM1 C26 VOUT1 VDD VSW TP11 1 C18 0.1uF 2 C20 100uF 3 J6 C39 1000pF TSNS1 CS1P FB1 FLT1 CS1N VSNS1 GSNS1 COMP1 ISH2 GND 11 C43 1uF 24 R49 16.2k C42 1uF AGND COMP R32 0.001 CS2P CS2N R35 1.00 BP5 R36 R38 0 DNP DNP 0 R40 10.0k ISH TSNS2 C54 470pF 11 DNP R43 0 R47 121k 10 R46 DNP R44 1.00 9 C55 470pF 8 C57 0.1uF 7 VIN PWM DNP IOUT TAO/FAULT REFIN FCCM ENABLE BOOT PGND BOOT_R VIN VDD VSW C45 0.1uF 1 C46 100uF 2 5 VSNS2 10.0 GND GND VOUT2 13 C58 1000pF C59 100uF C60 100uF C61 100uF J11 ED120/4DS C62 100uF C63 DNPC64 100uF 100uF 1 2 3 4 1.2V, 20A R52 4.22k GND C66 0.22uF R56 1.00 R53 GND GSNS2 10.0 GND TP27 TSNS2 C68 R59 0 DNPC69 3300pF Q4 GND 1000pF R58 12.4k CS2N CS2P R62 DNP TP28 TP30 R63 10.0k DNP BP5 TP29 R64 49.9 DNP GND AGND VSNS2 R65 0 PMBUS P rogram I nt erf ace J12 1 3 5 7 9 C50 DNPC51 100uF 100uF R45 L3 470nH 6 R57 0 3.3V TP31 C53 1uF TP25 FLT 3.3V CNTL1 PMBCLK C49 100uF TP24 +5V R55 1.00 C67 DNP 100pF SMBALERT PMBCLK PMBDATA C48 100uF GND 4 R51 0 C65 3300pF C47 100uF 3 GND TP26 R61 DNP R39 8.06k Q3 CSD95378BQ5M PWM2 12 AGND R60 DNP R34 0.001 AGND TP23 FLT2 R54 DNP 4.99k R33 0.001 VOUT2 AGND R50 0 CS1P VOUT1 C56 0.1uF Address : 9 dec GSNS1 10.0 CS1N C44 1uF PG2 VSNS2 VIO VIO=1.8 or 2.5V R27 AGND R41 0 AGND J10 PEC02SAAN GND C41 1000pF Q2 MMBT3904T-7-F VIN TP22 22 CS2N GSNS2 GND TP17 BP5 23 PWM2 21 CS2P AGND R48 16.2k R26 1.00 GND C52 0.1uF 1 2 R30 10.0k Vout1 1.2V, 20A ED120/4DS BP3 BP5 25 20 VIO PWM1 TSNS2 PG2 AVSCLK1 28 26 PWM2 AVSDATA1 CS2P 10 R42 100 1 2 DIFFO1 VDD ADDR1 J9 PEC02SAAN PMBCLK AGND 9 AGND C37 DNPC38 100uF 100uF C36 100uF R28 12.4k PGND 8 AGND BP5 PG1 TP21 BP3 PMBDATA 19 7 C35 100uF GND 29 27 PGND U2 TPS40425R HA SMBALERT CS2N PMBCLK CNTL2 FLT2 6 FB2 5 PMBDATA 16 SMBALERT 18 1 2 17 AGND J8 PEC02SAAN PWM1 COMP2 4 PG1 CNTL1 15 CNTL2 TP18 PHSET VSNS2 3 GSNS2 CNTL1 C34 100uF 4 3 2 1 C40 0.22uF R29 0 30 ISH1 ADDR0 1 2 C33 100uF R22 0 R23 4.22k TSNS1 R31 0 SYNC 14 2 13 1 12 SYNC PHSET VSNS1 10.0 VOUT1 31 34 33 32 35 38 36 37 41 39 40 RT PAD GND TP19 R20 GND R25 1.00 ISH TP20 C24 DNPC25 100uF 100uF TP12 GND AGND J7 PEC02SAAN C23 100uF L2 470nH TP13 5 6 GND AGND C22 100uF C21 100uF GND C28 1uF +5V 4 GND CS1P TP9 R11 8.06k CS1N TP16 R37 100 TP5 TP6 VSNS1 C16 1800pF PGND R8 49.9 GND R7 0 DNP 13 TP7 DIFFO1 Vin 7V - 14V TP4 1 9 GND PAD C5 22uF D2 BAT54HT1G ED120/4DS 8 +5V_PG PG FLT2 +5V_EXT R2 1.10Meg 5 TP3 J4 ED120/2DS 6 FB R5 DNP +5V 2 1 1 2 2 J2 PEC02SAAN TP2 L1 10uH U1 TPS62125DSG 2 1 J3 VIN CNTL2 4 2 4 6 8 10 TP32 CNTL2 R66 DNP 4.99k SMBALERT PMBDATA DNP C70 1500pF NT1 C71 CNTL1 7 SMBA LERT 8 DNP PMBCLK 9 AGND PEC05DAAN 3.3V 5 AGND 6 DNP R67 280 VOUT2 AGND GND AGND to PGND Strap at ONLY 1 point PMBDA TA 10 AGND Near Powe r Pad of Controller IC Figure 41. TPS40425EVM 2-Phase Schematic 38 Using the PWR594 EVM Dual Output DC/DC Analog with PMBus Interface Copyright © 2014, Texas Instruments Incorporated SLVUA86 – July 2014 Submit Documentation Feedback Two-Phase Configuration www.ti.com J1 PEC02SAAN PEC02SAAN VIN 3 R3 0 EN 4 2 1 J5 FLT1 C1 100uF D1 BAT54HT1G C2 100uF C3 22uF C4 22uF C9 10uF C6 22uF 4 3 2 1 C7 22uF +5V_PG GND R6 210k GND VIN C11 22uF C12 22uF C13 22uF C14 22uF C15 22uF GND VSNS2 GND GSNS2 R1 10.0k TP7 R8 49.9 DIFFO1 TP8 GND R7 0 R9 10.0k CS1P VSNS1 R13 10.0k FLT TP10 Q1 CSD95378BQ5M PWM1 R14 0 C26 DNP 3300pF 11 R15 0 10 AGND COMP R21 0 8 VIN C30 0.1uF AGND DIFFO1 9 R19 DNP C31 0.1uF GSNS1 R24 40.2k Fsw: 500k Hz TP15 R17 1.00 C27 470pF R18 121k C29 470pF AGND VSNS1 12 TSNS1 FLT1 R16 4.99k 7 PWM ENABLE BOOT PGND BOOT_R VIN C32 3300pF GND REFIN FCCM GSNS1 DNP IOUT TAO/FAULT VDD PGND C17 47pF R10 0 VSW TP11 C18 0.1uF 2 C20 100uF 3 GND J6 C39 1000pF DNP DNP TSNS1 GND R48 16.2k R49 16.2k TP22 22 C42 1uF AGND VOUT1 AGND COMP CS2N BP5 R36 0 R41 0 PWM2 12 TSNS2 11 R43 0 C54 470pF R47 121k R38 0 10 R46 DNP R44 1.00 9 C55 470pF 8 C57 0.1uF 7 VIN PWM TAO/FAULT REFIN FCCM ENABLE BOOT BOOT_R VIN DNP IOUT PGND VDD VSW C45 0.1uF 1 C46 100uF 2 R54 DNP 4.99k GND C60 100uF C61 100uF C62 100uF C63 DNPC64 100uF 100uF 1 2 3 4 1.2V, 20A R52 4.22k GND R56 1.00 DNP DNP C66 0.22uF R53 GND GSNS2 10.0 TP27 DNP DNPC69 3300pF R59 DNP 0 DNP Q4 C68 DNP 1000pF GND R58 12.4k CS2N CS2P R62 DNP TP28 TP30 R63 10.0k DNP BP5 R64 49.9 DNP GND AGND TP29 VSNS2 R65 0 PMBUS P rogram I nt erf ace J12 1 3 5 7 9 C59 100uF R51 0 J11 ED120/4DS GND TSNS2 TP31 VOUT2 C58 1000pF R57 0 3.3V 3.3V CNTL1 PMBCLK VSNS2 10.0 GND 6 FLT SMBALERT PMBCLK PMBDATA C50 DNPC51 100uF 100uF R45 L3 470nH TP25 5 R55 1.00 C67 DNP 100pF R61 DNP C49 100uF TP24 +5V C53 1uF DNP TP26 C48 100uF GND 4 GND C65 3300pF C47 100uF 3 FLT2 AGND R60 DNP R39 8.06k Q3 CSD95378BQ5M AGND R50 0 R34 0.001 CS2P 13 Address : 9 dec R33 0.001 VOUT2 R35 1.00 C56 0.1uF VIO=1.8 or 2.5V R32 0.001 C44 1uF R40 10.0k VSNS2 VIO CS1P AGND TP23 ISH AGND J10 PEC02SAAN GSNS1 10.0 CS1N DNPC41 1000pF PG2 21 CS2N GSNS2 GND DNP VIN CS2P AGND R27 TP17 GND C52 0.1uF 1 2 Q2 MMBT3904T-7-F 23 PWM2 TSNS2 CS2P C43 1uF 24 20 11 CS2N VIO GND DNP BP5 Vout1 1.2V, 20A ED120/4DS R28 12.4k PGND 33 FLT1 CS1P CS1N FB1 COMP1 ISH2 R42 100 1 2 VSNS1 PG2 AVSCLK1 ADDR1 J9 PEC02SAAN AVSDATA1 FLT2 9 10 C37 DNPC38 100uF 100uF BP3 BP5 PWM2 19 AGND PWM1 25 VDD AGND AGND R37 100 GSNS1 PMBCLK 8 28 26 BP5 18 7 PG1 27 BP3 PMBDATA C36 100uF GND 29 TP21 PGND U2 TPS40428RHA SMBALERT FB2 PMBCLK CNTL2 COMP2 6 16 5 PMBDATA 15 4 SMBALERT 17 1 2 CNTL2 C35 100uF C34 100uF 4 3 2 1 C40 0.22uF R26 1.00 DNP R29 0 30 PWM1 VSNS2 AGND J8 PEC02SAAN CNTL1 GSNS2 3 PG1 14 CNTL1 ISH1 PHSET 13 1 2 R31 0 SYNC C33 100uF R22 DNP 0 R23 4.22k 31 32 36 35 34 39 37 38 41 40 RT PAD 2 ADDR0 1 12 SYNC PHSET DIFFO1 GND TP19 TP20 J7 PEC02SAAN R30 10.0k VSNS1 10.0 VOUT1 R25 1.00 TSNS1 TP18 R20 GND AGND AGND C24 DNPC25 100uF 100uF TP12 TP13 5 GND ISH C23 100uF L2 470nH 6 GND CS1P C22 100uF C21 100uF GND C28 1uF +5V 4 CS1N TP16 TP9 R11 8.06k 1 13 R12 280 C19 TP14 TP5 TP6 CS1N C16 1800pF VOUT1 Vin 7V - 14V TP4 GND 1 9 GND PAD C5 22uF D2 BAT54HT1G ED120/4DS C8 10uF 8 +5V_PG PG FLT2 +5V_EXT R2 1.10Meg 5 FB R5 DNP TP1 VIN TP3 J4 ED120/2DS 6 VOS EN_HYS R4 DNP 0 C10 22uF 7 SW +5V 2 1 1 2 2 J2 PEC02SAAN TP2 L1 10uH U1 TPS62125DSG 2 1 J3 VIN CNTL2 4 2 4 6 8 10 TP32 CNTL2 R66 DNP 4.99k DNP R67 280 DNP CNTL1 7 C71 SMBA LERT 8 DNP PMBCLK 9 AGND PEC05DAAN 3.3V 5 AGND 6 SMBALERT PMBDATA C70 1500pF VOUT2 NT1 AGND GND AGND to PGND Strap at ONLY 1 point PMBDA TA 10 AGND Near Power Pad of Controller IC Figure 42. TPS40428EVM 2-Phase Schematic SLVUA86 – July 2014 Submit Documentation Feedback Using the PWR594 EVM Dual Output DC/DC Analog with PMBus Interface Copyright © 2014, Texas Instruments Incorporated 39 Two-Phase Configuration www.ti.com Table 8. TPS40425EVM 2-Phase Components List Qty Designator Description Part Number Manufacturer 2 C1, C2 CAP, AL, 100 µF, 25 V, ±20%, 0.3 Ω, SMD EEE-FC1E101P Panasonic 11 C3–C7, C10–C15 CAP, CERM, 22 µF, 25 V, ±10%, X5R, 1210 STD STD 2 C8, C9 CAP, CERM, 10 µF, 10 V, ±10%, X5R, 0805 STD STD 1 C16 CAP, CERM, 1500 pF, 25 V, ±10%, X7R, 0603 STD STD 1 C17 CAP, CERM, 100 pF, 50 V, ±5%, C0G/NP0, 0603 STD STD 7 C18, C30, C31, C45, C52, C56, C57 CAP, CERM, 0.1 µF, 25 V, ±10%, X7R, 0603 STD STD 20 C20–C24, C33–C37, C46–C50, C59–C63 CAP, CERM, 100 µF, 6.3 V, ±20%, X5R, 1210 STD STD 1 C26 CAP, CERM, 3300 pF, 25 V, ±10%, X7R, 0603 STD STD 4 C27, C29, C54, C55 CAP, CERM, 470 pF, 50 V, ±10%, X7R, 0603 STD STD 5 C28, C42–C44, C53 CAP, CERM, 1 µF, 25 V, ±10%, X5R, 0603 STD STD 2 C32, C65 CAP, CERM, 3300 pF, 50 V, ±10%, X7R, 0603 STD STD 4 C39, C41, C58, C68 CAP, CERM, 1000 pF, 50 V, ±10%, X7R, 0603 STD STD 2 C40, C66 CAP, CERM, 0.22µFF, 25 V, ±10%, X7R, 0603 STD STD 2 D1, D2 Diode, Schottky, 30 V, 0.2 A, SOD-323 BAT54HT1G ON Semiconductor 7 J1– J3, J7–J10 Header, 100 mil, 2x1, Tin plated, TH PEC02SAAN Sullins Connector Solutions 1 J4 TERMINAL BLOCK 5.08 mm VERT 2POS, TH ED120/2DS On-Shore Technology 3 J5, J6, J11 TERMINAL BLOCK 5.08 mm VERT 4POS, TH ED120/4DS On-Shore Technology 1 J12 Header, 100 mil, 5x2, Tin plated, TH PEC05DAAN Sullins Connector Solutions 1 L1 Inductor, Shielded Drum Core, Ferrite, 10 µH, 0.7 A, 0.33 Ω, SMD LPS3314103MLB Coilcraft 2 L2, L3 Inductor, Shielded Drum Core, WE-Perm, 470 nH, 30 A, 0.00067 Ω, SMD 744355147 Wurth Elektronik eiSos 1 LBL1 Thermal Transfer Printable Labels, 1.250" W x 0.250" H - 10,000 per roll THT-13-457-10 Brady 2 Q1, Q3 Synchronous Buck NexFET Power Stage, DQP0012A CSD95378BQ5M Texas Instruments 2 Q2, Q4 Transistor, NPN, 20 V, 0.2 A, SOT-523 MMBT3904T-7-F Diodes Inc. 1 R2 RES, 1.10 MΩ, 1%, 0.1 W, 0603 STD STD 12 R3, R14, R21, R22, R29, R31, R41, R50, R51, R57, R59, R65 RES, 0 Ω, 5%, 0.1 W, 0603 STD STD 1 R6 RES, 210 kΩ, 1%, 0.1 W, 0603 STD STD 1 R8 RES, 49.9 Ω, 1%, 0.1 W, 0603 STD STD 5 R1, R9, R13, R30, R40 RES, 10.0 kΩ, 1%, 0.1 W, 0603 STD STD 1 R12 RES, 280 Ω, 1%, 0.1 W, 0603 STD STD 1 R16 RES, 4.99 kΩ, 1%, 0.1 W, 0603 STD STD 7 R17, R25, R26, R35, R44, R55, R56 RES, 1.00 Ω, 1%, 0.1 W, 0603 STD STD 2 R18, R47 RES, 121 kΩ, 1%, 0.1 W, 0603 STD STD 4 R20, R27, R45, R53 RES, 10.0 Ω, 1%, 0.1 W, 0603 STD STD 2 R23, R52 RES, 4.22 kΩ, 1%, 0.1 W, 0603 STD STD 1 R24 RES, 40.2 kΩ, 1%, 0.1 W, 0603 STD STD 2 R28, R58 RES, 12.4 kΩ, 1%, 0.1 W, 0603 STD STD 3 R32, R33, R34 RES, 0.001 Ω, 1%, 1W, 2512 STD STD 2 R37, R42 RES, 100 Ω, 1%, 0.1 W, 0603 STD STD 2 R48, R49 RES, 16.2 kΩ, 1%, 0.1 W, 0603 STD STD 2 SH-J1, SH-J3 Shunt, 100 mil, Gold plated, Black 969102-0000-DA 3M 6 TP1, TP5, TP9, TP12, TP24, TP31 Test Point, Miniature, Red, TH 5000 Keystone 17 TP2, TP3, TP7, TP8, TP10, TP13, TP18–TP23, TP25, TP26, TP28–TP30 Test Point, Miniature, White, TH 5002 Keystone 9 TP4, TP6, TP11, TP14–TP17, TP27, TP32 Test Point, Miniature, Black, TH 5001 Keystone 40 Using the PWR594 EVM Dual Output DC/DC Analog with PMBus Interface Copyright © 2014, Texas Instruments Incorporated SLVUA86 – July 2014 Submit Documentation Feedback Two-Phase Configuration www.ti.com Table 8. TPS40425EVM 2-Phase Components List (continued) Qty 1 1 Designator Description Part Number Manufacturer U1 IC, 3 V-17 V, 200-mA High Efficient Buck Converter TPS62125DSG TI U2 IC, Dual output, 2-Phase, Stackable PMBUS Synchronous Buck Driverless Controller with AVS Bus TPS40425RHA TI Table 9. TPS40428EVM 2-Phase Components List Qty Designator Description Part Number Manufacturer 2 C1, C2 CAP, AL, 100 µF, 25 V, ±20%, 0.3 Ω, SMD EEE-FC1E101P Panasonic 11 C–C7, C10–C15 CAP, CERM, 22 µF, 25 V, ±10%, X5R, 1210 STD STD 2 C8, C9 CAP, CERM, 10 µF, 10 V, ±10%, X5R, 0805 STD STD 2 C16, C70 CAP, CERM, 1500 pF, 25 V, ±10%, X7R, 0603 STD STD 2 C17, C67 CAP, CERM, 100 pF, 50 V, ±5%, C0G/NP0, 0603 STD STD 7 C18, C30, C31, C45, C52, C56, C57 CAP, CERM, 0.1 µF, 25 V, ±10%, X7R, 0603 STD STD 20 C20–C24, C33–C37, C46–C50, C59–C63 CAP, CERM, 100 µF, 6.3 V, ±20%, X5R, 1210 STD STD 2 C26, C69 CAP, CERM, 3300 pF, 25 V, ±10%, X7R, 0603 STD STD 4 C27, C29, C54, C55 CAP, CERM, 470 pF, 50 V, ±10%, X7R, 0603 STD STD 5 C28, C42–C44, C53 CAP, CERM, 1 µF, 25 V, ±10%, X5R, 0603 STD STD 2 C32, C65 CAP, CERM, 3300 pF, 50 V, ±10%, X7R, 0603 STD STD 2 C39, C58 CAP, CERM, 1000 pF, 50 V, ±10%, X7R, 0603 STD STD 2 D1, D2 Diode, Schottky, 30 V, 0.2 A, SOD-323 BAT54HT1G ON Semiconductor 7 J1–J3, J7–J10 Header, 100 mil, 2x1, Tin plated, TH PEC02SAAN Sullins Connector Solutions 1 J4 TERMINAL BLOCK 5.08 mm VERT 2POS, TH ED120/2DS On-Shore Technology 3 J5, J6, J11 TERMINAL BLOCK 5.08 mm VERT 4POS, TH ED120/4DS On-Shore Technology 1 J12 Header, 100 mil, 5x2, Tin plated, TH PEC05DAAN Sullins Connector Solutions 1 L1 Inductor, Shielded Drum Core, Ferrite, 10 µH, 0.7 A, 0.33 Ω, SMD LPS3314103MLB Coilcraft 2 L2, L3 Inductor, Shielded Drum Core, WE-Perm, 470 nH, 30 A, 0.00067 Ω, SMD 744355147 Wurth Elektronik eiSos 1 LBL1 Thermal Transfer Printable Labels, 1.250" W x 0.250" H - 10,000 per roll THT-13-457-10 Brady 2 Q1, Q3 Synchronous Buck NexFET Power Stage, DQP0012A CSD95378BQ5M Texas Instruments 1 R2 RES, 1.10 MΩ, 1%, 0.1 W, 0603 STD STD 14 R3, R7, R10, R14, R15, R21, R31, R36, R38, R41, R43, R50, R57, R65 RES, 0 Ω, 5%, 0.1 W, 0603 STD STD 1 R6 RES, 210 kΩ, 1%, 0.1 W, 0603 STD STD 2 R8, R64 RES, 49.9 Ω, 1%, 0.1 W, 0603 STD STD 5 R1, R9, R13, R30, R40 RES, 10.0 kΩ, 1%, 0.1 W, 0603 STD STD 2 R12, R67 RES, 280 Ω, 1%, 0.1 W, 0603 STD STD 3 R16, R54, R66 RES, 4.99 kΩ, 1%, 0.1 W, 0603 STD STD 7 R17, R25, R26, R35, R44, R55, R56 RES, 1.00 Ω, 1%, 0.1 W, 0603 STD STD 2 R18, R47 RES, 121 kΩ, 1%, 0.1 W, 0603 STD STD 4 R20, R27, R45, R53 RES, 10.0 Ω, 1%, 0.1 W, 0603 STD STD 1 R24 RES, 40.2 kΩ, 1%, 0.1 W, 0603 STD STD 3 R32, R33, R34 RES, 0.001 Ω, 1%, 1W, 2512 STD STD 2 R37, R42 RES, 100 Ω, 1%, 0.1 W, 0603 STD STD 2 R48, R49 RES, 16.2 kΩ, 1%, 0.1 W, 0603 STD STD 2 SH-J1, SH-J3 Shunt, 100 mil, Gold plated, Black 969102-0000-DA 3M 6 TP1, TP5, TP9, TP12, TP24, TP31 Test Point, Miniature, Red, TH 5000 Keystone SLVUA86 – July 2014 Submit Documentation Feedback Using the PWR594 EVM Dual Output DC/DC Analog with PMBus Interface Copyright © 2014, Texas Instruments Incorporated 41 Two-Phase Configuration www.ti.com Table 9. TPS40428EVM 2-Phase Components List (continued) Qty Designator Description Part Number Manufacturer 17 TP2, TP3, TP7, TP8, TP10, TP13, TP18–TP23, TP25, TP26, TP28–TP30 Test Point, Miniature, White, TH 5002 Keystone 9 TP4, TP6, TP11, TP14–TP17, TP27, TP32 Test Point, Miniature, Black, TH 5001 Keystone 1 U1 IC, 3 V-17 V, 200-mA High Efficient Buck Converter TPS62125DSG TI U2 IC, Dual output, 2-Phase, Stackable PMBUS Synchronous Buck Driverless Controller with AVS Bus TPS40428RHA TI 1 42 Using the PWR594 EVM Dual Output DC/DC Analog with PMBus Interface Copyright © 2014, Texas Instruments Incorporated SLVUA86 – July 2014 Submit Documentation Feedback ADDITIONAL TERMS AND CONDITIONS, WARNINGS, RESTRICTIONS, AND DISCLAIMERS FOR EVALUATION MODULES Texas Instruments Incorporated (TI) markets, sells, and loans all evaluation boards, kits, and/or modules (EVMs) pursuant to, and user expressly acknowledges, represents, and agrees, and takes sole responsibility and risk with respect to, the following: 1. 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Should any EVM not meet the specifications indicated in the user’s guide or other documentation accompanying such EVM, the EVM may be returned to TI within 30 days from the date of delivery for a full refund. THE FOREGOING LIMITED WARRANTY IS THE EXCLUSIVE WARRANTY MADE BY TI TO USER AND IS IN LIEU OF ALL OTHER WARRANTIES, EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING ANY WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. TI SHALL NOT BE LIABLE TO USER FOR ANY INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES RELATED TO THE HANDLING OR USE OF ANY EVM. 8. No license is granted under any patent right or other intellectual property right of TI covering or relating to any machine, process, or combination in which EVMs might be or are used. TI currently deals with a variety of customers, and therefore TI’s arrangement with the user is not exclusive. TI assumes no liability for applications assistance, customer product design, software performance, or infringement of patents or services with respect to the handling or use of EVMs. 9. User assumes sole responsibility to determine whether EVMs may be subject to any applicable federal, state, or local laws and regulatory requirements (including but not limited to U.S. Food and Drug Administration regulations, if applicable) related to its handling and use of EVMs and, if applicable, compliance in all respects with such laws and regulations. 10. User has sole responsibility to ensure the safety of any activities to be conducted by it and its employees, affiliates, contractors or designees, with respect to handling and using EVMs. Further, user is responsible to ensure that any interfaces (electronic and/or mechanical) between EVMs and any human body are designed with suitable isolation and means to safely limit accessible leakage currents to minimize the risk of electrical shock hazard. 11. User shall employ reasonable safeguards to ensure that user’s use of EVMs will not result in any property damage, injury or death, even if EVMs should fail to perform as described or expected. 12. User shall be solely responsible for proper disposal and recycling of EVMs consistent with all applicable federal, state, and local requirements. Certain Instructions. User shall operate EVMs within TI’s recommended specifications and environmental considerations per the user’s guide, accompanying documentation, and any other applicable requirements. Exceeding the specified ratings (including but not limited to input and output voltage, current, power, and environmental ranges) for EVMs may cause property damage, personal injury or death. If there are questions concerning these ratings, user should contact a TI field representative prior to connecting interface electronics including input power and intended loads. Any loads applied outside of the specified output range may result in unintended and/or inaccurate operation and/or possible permanent damage to the EVM and/or interface electronics. Please consult the applicable EVM user's guide prior to connecting any load to the EVM output. If there is uncertainty as to the load specification, please contact a TI field representative. During normal operation, some circuit components may have case temperatures greater than 60°C as long as the input and output are maintained at a normal ambient operating temperature. These components include but are not limited to linear regulators, switching transistors, pass transistors, and current sense resistors which can be identified using EVMs’ schematics located in the applicable EVM user's guide. When placing measurement probes near EVMs during normal operation, please be aware that EVMs may become very warm. As with all electronic evaluation tools, only qualified personnel knowledgeable in electronic measurement and diagnostics normally found in development environments should use EVMs. Agreement to Defend, Indemnify and Hold Harmless. User agrees to defend, indemnify, and hold TI, its directors, officers, employees, agents, representatives, affiliates, licensors and their representatives harmless from and against any and all claims, damages, losses, expenses, costs and liabilities (collectively, "Claims") arising out of, or in connection with, any handling and/or use of EVMs. User’s indemnity shall apply whether Claims arise under law of tort or contract or any other legal theory, and even if EVMs fail to perform as described or expected. Safety-Critical or Life-Critical Applications. If user intends to use EVMs in evaluations of safety critical applications (such as life support), and a failure of a TI product considered for purchase by user for use in user’s product would reasonably be expected to cause severe personal injury or death such as devices which are classified as FDA Class III or similar classification, then user must specifically notify TI of such intent and enter into a separate Assurance and Indemnity Agreement. RADIO FREQUENCY REGULATORY COMPLIANCE INFORMATION FOR EVALUATION MODULES Texas Instruments Incorporated (TI) evaluation boards, kits, and/or modules (EVMs) and/or accompanying hardware that is marketed, sold, or loaned to users may or may not be subject to radio frequency regulations in specific countries. General Statement for EVMs Not Including a Radio For EVMs not including a radio and not subject to the U.S. Federal Communications Commission (FCC) or Industry Canada (IC) regulations, TI intends EVMs to be used only for engineering development, demonstration, or evaluation purposes. EVMs are not finished products typically fit for general consumer use. EVMs may nonetheless generate, use, or radiate radio frequency energy, but have not been tested for compliance with the limits of computing devices pursuant to part 15 of FCC or the ICES-003 rules. Operation of such EVMs may cause interference with radio communications, in which case the user at his own expense will be required to take whatever measures may be required to correct this interference. General Statement for EVMs including a radio User Power/Frequency Use Obligations: For EVMs including a radio, the radio included in such EVMs is intended for development and/or professional use only in legally allocated frequency and power limits. Any use of radio frequencies and/or power availability in such EVMs and their development application(s) must comply with local laws governing radio spectrum allocation and power limits for such EVMs. It is the user’s sole responsibility to only operate this radio in legally acceptable frequency space and within legally mandated power limitations. Any exceptions to this are strictly prohibited and unauthorized by TI unless user has obtained appropriate experimental and/or development licenses from local regulatory authorities, which is the sole responsibility of the user, including its acceptable authorization. U.S. Federal Communications Commission Compliance For EVMs Annotated as FCC – FEDERAL COMMUNICATIONS COMMISSION Part 15 Compliant Caution This device complies with part 15 of the FCC Rules. Operation is subject to the following two conditions: (1) This device may not cause harmful interference, and (2) this device must accept any interference received, including interference that may cause undesired operation. Changes or modifications could void the user's authority to operate the equipment. FCC Interference Statement for Class A EVM devices This equipment has been tested and found to comply with the limits for a Class A digital device, pursuant to part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference when the equipment is operated in a commercial environment. This equipment generates, uses, and can radiate radio frequency energy and, if not installed and used in accordance with the instruction manual, may cause harmful interference to radio communications. Operation of this equipment in a residential area is likely to cause harmful interference in which case the user will be required to correct the interference at its own expense. FCC Interference Statement for Class B EVM devices This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipment generates, uses and can radiate radio frequency energy and, if not installed and used in accordance with the instructions, may cause harmful interference to radio communications. However, there is no guarantee that interference will not occur in a particular installation. If this equipment does cause harmful interference to radio or television reception, which can be determined by turning the equipment off and on, the user is encouraged to try to correct the interference by one or more of the following measures: • Reorient or relocate the receiving antenna. • Increase the separation between the equipment and receiver. • Connect the equipment into an outlet on a circuit different from that to which the receiver is connected. • Consult the dealer or an experienced radio/TV technician for help. Industry Canada Compliance (English) For EVMs Annotated as IC – INDUSTRY CANADA Compliant: This Class A or B digital apparatus complies with Canadian ICES-003. Changes or modifications not expressly approved by the party responsible for compliance could void the user’s authority to operate the equipment. Concerning EVMs Including Radio Transmitters This device complies with Industry Canada licence-exempt RSS standard(s). Operation is subject to the following two conditions: (1) this device may not cause interference, and (2) this device must accept any interference, including interference that may cause undesired operation of the device. Concerning EVMs Including Detachable Antennas Under Industry Canada regulations, this radio transmitter may only operate using an antenna of a type and maximum (or lesser) gain approved for the transmitter by Industry Canada. To reduce potential radio interference to other users, the antenna type and its gain should be so chosen that the equivalent isotropically radiated power (e.i.r.p.) is not more than that necessary for successful communication. This radio transmitter has been approved by Industry Canada to operate with the antenna types listed in the user guide with the maximum permissible gain and required antenna impedance for each antenna type indicated. Antenna types not included in this list, having a gain greater than the maximum gain indicated for that type, are strictly prohibited for use with this device. Canada Industry Canada Compliance (French) Cet appareil numérique de la classe A ou B est conforme à la norme NMB-003 du Canada Les changements ou les modifications pas expressément approuvés par la partie responsable de la conformité ont pu vider l’autorité de l'utilisateur pour actionner l'équipement. Concernant les EVMs avec appareils radio Le présent appareil est conforme aux CNR d'Industrie Canada applicables aux appareils radio exempts de licence. L'exploitation est autorisée aux deux conditions suivantes : (1) l'appareil ne doit pas produire de brouillage, et (2) l'utilisateur de l'appareil doit accepter tout brouillage radioélectrique subi, même si le brouillage est susceptible d'en compromettre le fonctionnement. Concernant les EVMs avec antennes détachables Conformément à la réglementation d'Industrie Canada, le présent émetteur radio peut fonctionner avec une antenne d'un type et d'un gain maximal (ou inférieur) approuvé pour l'émetteur par Industrie Canada. Dans le but de réduire les risques de brouillage radioélectrique à l'intention des autres utilisateurs, il faut choisir le type d'antenne et son gain de sorte que la puissance isotrope rayonnée équivalente (p.i.r.e.) ne dépasse pas l'intensité nécessaire à l'établissement d'une communication satisfaisante. Le présent émetteur radio a été approuvé par Industrie Canada pour fonctionner avec les types d'antenne énumérés dans le manuel d’usage et ayant un gain admissible maximal et l'impédance requise pour chaque type d'antenne. Les types d'antenne non inclus dans cette liste, ou dont le gain est supérieur au gain maximal indiqué, sont strictement interdits pour l'exploitation de l'émetteur. Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2014, Texas Instruments Incorporated spacer Important Notice for Users of EVMs Considered “Radio Frequency Products” in Japan EVMs entering Japan are NOT certified by TI as conforming to Technical Regulations of Radio Law of Japan. If user uses EVMs in Japan, user is required by Radio Law of Japan to follow the instructions below with respect to EVMs: 1. 2. 3. Use EVMs in a shielded room or any other test facility as defined in the notification #173 issued by Ministry of Internal Affairs and Communications on March 28, 2006, based on Sub-section 1.1 of Article 6 of the Ministry’s Rule for Enforcement of Radio Law of Japan, Use EVMs only after user obtains the license of Test Radio Station as provided in Radio Law of Japan with respect to EVMs, or Use of EVMs only after user obtains the Technical Regulations Conformity Certification as provided in Radio Law of Japan with respect to EVMs. Also, do not transfer EVMs, unless user gives the same notice above to the transferee. Please note that if user does not follow the instructions above, user will be subject to penalties of Radio Law of Japan. http://www.tij.co.jp 【無線電波を送信する製品の開発キットをお使いになる際の注意事項】 本開発キットは技術基準適合証明を受けておりません。 本製品の ご使用に際しては、電波法遵守のため、以下のいずれかの措置を取っていただく必要がありますのでご注意ください。 1. 2. 3. 電波法施行規則第6条第1項第1号に基づく平成18年3月28日総務省告示第173号で定められた電波暗室等の試験設備でご使用いただく。 実験局の免許を取得後ご使用いただく。 技術基準適合証明を取得後ご使用いただく。。 なお、本製品は、上記の「ご使用にあたっての注意」を譲渡先、移転先に通知しない限り、譲渡、移転できないものとします 上記を遵守頂けない場合は、電波法の罰則が適用される可能性があることをご留意ください。 日本テキサス・インスツルメンツ株式会社 東京都新宿区西新宿６丁目２４番１号 西新宿三井ビル http://www.tij.co.jp Texas Instruments Japan Limited (address) 24-1, Nishi-Shinjuku 6 chome, Shinjuku-ku, Tokyo, Japan IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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