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TPS51124
SLVS616C – NOVEMBER 2005 – REVISED DECEMBER 2014
TPS51124 Dual Synchronous Step-Down Controller for Low-Voltage Power Rails
1 Features
3 Description
•
The TPS51124 is a dual, adaptive on-time D-CAP™
mode synchronous buck controller. The part enables
system designers to cost effectively complete the
suite of notebook power bus regulators with the
absolute lowest external component count and lowest
standby consumption. The fixed frequency emulated
adaptive on-time control supports seamless operation
between PWM mode at heavy load condition and
reduced frequency operation at light load for high
efficiency down to milliampere range. The main
control loop for the TPS51124 uses the D-CAP mode
that optimized for low ESR output capacitors such as
POSCAP or SP-CAP promises fast transient
response with no external compensation. Simple and
separate power good signals for each channel allow
flexibility of power sequencing. The part provides a
convenient and efficient operation with supply input
voltages (V5IN, V5FILT) ranging from 4.5 V to 5.5 V,
conversion voltages (drain voltage for the
synchronous high-side MOSFET) from 3 V to 28 V
and output voltages from 0.76 V to 5.5 V.
1
•
•
•
•
•
•
•
•
•
•
•
•
High Efficiency, Low-Power Consumption,
Shutdowns to 3 V to VFBx regulation value =
735 mV
Internal SS time
435
ns
0.85
1.2
1.40
Wake up
3.7
4.0
4.3
Hysteresis
0.2
0.3
0.4
Wake up
1.0
1.3
1.5
ms
UVLO/LOGIC THRESHOLD
VUV5VFILT V5FILT UVLO threshold
VEN
ENx threshold
IEN
ENx input current
(1)
(2)
Hysteresis
0.2
Absolute value (2)
0.02
0.1
V
V
μA
Specified by design. Not production tested.
Ensured by design. Not production tested.
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SLVS616C – NOVEMBER 2005 – REVISED DECEMBER 2014
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Electrical Characteristics (continued)
over operating free-air temperature range, V5IN = V5FILT = 5 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
Fast
VTONSEL
TONSEL threshold
(2)
MIN
TYP
TONSEL input current
UNIT
V5FIL
T –0.3
Medium (2)
V5FILT
–1.0
2
Slow (2)
ITONSEL
MAX
V
0.5
TONSEL=0V, current out of the pin (2)
1
TONSEL=5V, current in to the pin (2)
1
μA
CURRENT SENSE
ITRIP
TRIP source current
VTRIPx < 0.3 V, TA = 25°C
TCITRIP
ITRIP temperature
coeffficent
On the basis of 25°C (2)
VOCLoff
OCP compensation offset
VZC
Zero cross detection
comparator offset
VPGNDx-LLx voltage, PGOODx = Hi (2)
VRtrip
Current limit threshold
setting range
VTRIPx-GND voltage, all temperatures (2)
(VTRIPx-GND – VPGNDx-LLx) voltage,
VTRIPx-GND = 60 mV
9
10
11
4200
–10
0
10
0.5
30
μA
ppm/°
C
mV
mV
200
mV
POWERGOOD COMPARATOR
PG in from lower (PGOODx goes hi)
92.5%
PG low hysteresis (PGOODx goes low)
95%
97.5%
–5%
VTHPG
PG threshold
IPGMAX
PG sink current
PGOODx = 0.5 V
2.5
5.0
TPGDEL
PG delay
Delay for PG in
400
510
620
110%
115%
120%
PG in from higher (PGOODx goes hi)
102.5
%
PG high hysteresis (PGOODx goes low)
105% 107.5%
5%
mA
μs
OUTPUT UNDERVOLTAGE AND OVERVOLTAGE PROTECTION
VOVP
Output OVP trip threshold OVP detect
tOVPDEL
Output OVP prop delay
VUVP
Output UVP trip threshold Hysteresis (recovery < 20 μs)
tUVPDEL
Output UVP delay
tUVPEN
Output UVP enable delay
μs
1.5
After 1.7 × Tss, UVP protection engaged
10%
20
32
40
μs
1.4
2
2.4
ms
THERMAL SHUTDOWN
TSDN
6
Thermal shutdown
threshold
Shutdown temperature (2)
Hysteresis (2)
160
10
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°C
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SLVS616C – NOVEMBER 2005 – REVISED DECEMBER 2014
6.5 Typical Characteristics
1
I V5FLTSDN − Shutdown Current − µ A
I V5FILT − Supply Current − µ A
500
400
300
200
100
0
−50
0
50
100
TJ − Junction Temperature − 5C
0.6
0.4
0.2
0
−50
150
Figure 1. V5FILT Supply Current vs Junction Temperature
0.8
0
50
100
TJ − Junction Temperature − 5C
150
Figure 2. V5FILT Shutdown Current vs Junction
Temperature
16
1
ITRIP − Trip Source Current − µ A
I V5INSDN − Shutdown Current − µ A
14
0.8
0.6
0.4
0.2
12
10
8
6
4
2
0
−50
0
50
100
TJ − Junction Temperature − 5C
0
−50
150
Figure 3. V5IN Shutdown Current vs Junction Temperature
0
50
100
TJ − Junction Temperature − 5C
150
Figure 4. Trip Source Current vs Junction Temperature
500
140
fSW − Switching Frequency − kHz
VOVP VUVP − OVP/UVP Threshold − %
TONSEL = GND
120
OVP
100
80
UVP
60
40
−50
150
CH2
300
CH1
200
100
0
0
50
100
TJ − Junction Temperature − 5C
0
5
10
15
20
25
VI − Input Voltage − V
Figure 5. OVP/UVP Threshold vs Junction Temperature
(1)
400
Figure 6. Switching Frequency (Slow) vs Input Voltage
(1)
The data of Figure 6–Figure 8 are measured from the Typical Application Circuit of Figure 18 and Table 2.
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Typical Characteristics (continued)
500
500
TONSEL = V5FILT
CH2
fSW − Switching Frequency − kHz
fSW − Switching Frequency − kHz
TONSEL = FLOAT
400
CH2
300
CH1
200
100
400
CH1
300
200
100
0
0
0
5
10
15
20
0
25
5
20
25
Figure 7. Switching Frequency (MED) vs Input Voltage
Figure 8. Switching Frequency (Fast) vs Input Voltage
500
TONSEL = FLOAT
fSW − Switching Frequency − kHz
fSW − Switching Frequency − kHz
TONSEL = GND
400
CH2
300
200
CH1
100
0
0.001
0.01
0.1
1
400
CH2
300
CH1
200
100
0
0.001
10
0.01
0.1
1
IO − Output Current − A
IO − Output Current − A
Figure 9. Switching Frequency (Slow) vs Output Voltage
(1)
1.1
TONSEL = V5FILT
400
CH2
1.05 V
TONSEL = FLOAT
CH1
VOUT1 − Output Voltage − V
fSW − Switching Frequency − kHz
10
Figure 10. Switching Frequency (MED) vs Output Voltage
500
300
200
1.075
VI = 21 V
1.050
VI = 7 V
VI = 12 V
1.025
100
0
0.001
0.01
0.1
1
IO − Output Current − A
1
0.001
10
Figure 11. Switching Frequency (Fast) vs Output Voltage
8
15
VI − Input Voltage − V
500
(1)
10
VI − Input Voltage − V
0.01
0.1
1
IOUT1 − Output Current − A
10
Figure 12. 1.05-V Output Voltage vs Output Current
The data of Figure 9–Figure 12 are measured from the Typical Application Circuit of Figure 18 and Table 2.
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Typical Characteristics (continued)
1.1
1.575
1.05 V
TONSEL = FLOAT
1.5 V
TONSEL = FLOAT
VOUT1 − Output Voltage − V
VOUT2 − Output Voltage − V
1.550
VI = 21 V
1.525
1.500
VI = 7 V
VI = 12 V
1.475
1.075
IO = 0 A
1.050
IO = 5 A
1.025
1.450
1.425
0.001
1
0.01
0.1
1
IOUT2 − Output Current − A
0
10
Figure 13. 1.5-V Output Voltage vs Output Current
(1)
10
15
VI − Input Voltage − V
20
25
Figure 14. 1.05-V Output Voltage vs Input Voltage
100
1.575
1.5 V
TONSEL = FLOAT
1.550
VI = 7 V
1.05 V
TONSEL = FLOAT
80
VI = 21 V
− Efficiency − %
VOUT2 − Output Voltage − V
5
1.525
IO = 0 A
1.500
IO = 5 A
VI = 12 V
60
40
1.475
20
1.450
0
0.001
1.425
0
5
10
15
VI − Input Voltage − V
20
25
Figure 15. 1.5-V Output Voltage vs Input Voltage
100
10
Figure 16. 1.05-V Efficiency vs Output Current
VI = 7 V
1.5 V
TONSEL = FLOAT
80
VI = 21 V
− Efficiency − %
0.01
0.1
1
IOUT1 − Output Current − A
VI = 12 V
60
40
20
0
0.001
0.01
0.1
1
IOUT2 − Output Current − A
10
Figure 17. 1.5-V Efficiency vs Output Current
(1)
(1)
(1)
The data of Figure 13–Figure 16 are measured from the Typical Application Circuit of Figure 18 and Table 2
The data of Figure 17–Figure 22 are measured from the Typical Application Circuit of Figure 18 and Table 2
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7 Detailed Description
7.1 Overview
The TPS51124 is a cost-effective, dual-synchronous buck controller targeted for notebook I/O and low voltage
system bus supply solutions. With D-CAP™ control mode implemented, compensation network can be removed.
Besides, the fast transient response also reduced the output capacitance.
7.2 Functional Block Diagram
V5IN
Frequency Control
160 °C/
150 °C
4V
FAST
MID
4 V/3.7 V
T ONSEL
V5OK
SLOW
THOK
1V
V5FIL T
VO2
VO1
VBST1
V5DRV
V5DRV
VBST2
Switcher Controller
LL1
Fault
Fault
LL2
DRVL1
Sdn
Sdn
DRVL2
ANALOG/SUB GND
DRVH2
ON2
Ref
BGR
SS2
PGND1
SS1
Switcher Controller Ref
ON1
DRVH1
PGND2
Ref −30/10%
UV
TRIP2
VFB2
PGOOD2
GND
EN2
EN1
PGOOD1
TRIP1
VFB1
EN/SS
Control
Ref +5/10%
PGOODx
Delay
PGNDx
OV
Ref +15%
Ref −5/10%
758 mV
Ref
SSx
PWM
V5OK
VFBx
THOK
10 µA
GND
TRIPx
V5IN
Control Logic
OCP
LLx
VBSTx
DRVHx
LLx
1
Shot
XCON
PGNDx
LLx
V5IN
DRVLx
PGNDx
ZC
LLx
VOx
PGNDx
10
ONx
On/Off T ime
Minimum On/Of
f
Light Load,
OVP/UVP,
Discharge
Control
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Fault
Sdn
T ONSEL
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7.3 Feature Description
7.3.1 PWM Operation
The main control loop of the switching mode power supply (SMPS) is designed as an adaptive on-time pulse
width modulation (PWM) controller. It supports a proprietary D-CAP Mode. D-CAP Mode uses an internal
compensation circuit and is suitable for low external component-count configuration, with appropriate amount of
ESR at the output capacitor(s). The output voltage is monitored at a feedback point voltage. The reference
voltage at the feedback point is a combination of a fixed 0.750-V precision reference and a synchronized,
precision 15-mV ramp signal. Lower output voltages in notebook systems (e.g., 1.05 V, 1.5 V) require extremely
low output ripple. By providing a ramp signal, the TPS51124 is easier to use in low-output ripple systems. The
combination of the precision ramp and reference yield an effective target reference of 0.758 V. The accuracy of
this effective reference remains 1.3% over line and temperature.
At the beginning of each cycle, the synchronous high-side MOSFET is turned on, or becomes ON state. This
MOSFET is turned off, or becomes OFF state, after the internal one-shot timer expires. This one shot is
determined by the converter’s input voltage, VIN, and the output voltage, VOUT, to keep the frequency fairly
constant over the input voltage range; hence, it is called adaptive on-time control (see PWM Frequency and
Adaptive On-time Control). The high-side MOSFET is turned on again when feedback information indicates
insufficient output voltage, and inductor current information indicates a below-the-over-current limit condition.
Repeating operation in this manner, the controller regulates the output voltage. The synchronous low-side
MOSFET is turned on each OFF state to keep the conduction loss at a minimum. The low-side MOSFET is
turned off when the inductor current information detects zero level. This enables seamless transition to the
reduced frequency operation at light-load conditions so that high efficiency is kept over a broad range of load
current.
7.3.2 Light-Load Condition
TPS51124 automatically reduces switching frequency at light-load conditions to maintain high efficiency. This
reduction of frequency is achieved smoothly and without increase of Vout ripple or load regulation. Detail
operation is described as follows. As the output current decreases from heavy-load condition, the inductor
current is also reduced, and eventually comes to the point that its valley touches zero current, which is the
boundary between continuous conduction and discontinuous conduction modes. The low-side MOSFET is turned
off when this zero inductor current is detected. As the load current is further decreased, the converter runs in
discontinuous conduction mode and it takes longer and longer to discharge the output capacitor to the level that
requires the next ON cycle. The ON time is kept the same as that in the heavy-load condition. In reverse, when
the output current increases from light load to heavy load, the switching frequency increases to the preset value
as the inductor current reaches the continuous conduction. The transition load point to the light-load operation,
IOUT(LL) (i.e., the threshold between continuous and discontinuous conduction mode) can be calculated as follows;
I
OUT(LL)
+
2
1
L
ǒVIn * VOUTǓ
ƒ
V
V
OUT
IN
(1)
where f is the PWM switching frequency.
Switching frequency versus output current in the light-load condition is a function of L, f, Vin, and Vout, but it
decreases almost proportional to the output current from the IOUT(LL) given in Equation 1.
It should be noted that in the PWM control path, there is a small ramp. This ramp is transparent in normal,
continuous conduction mode and does not measurably affect the regulation voltage. However, in discontinuous,
light-load mode, an upward shift in regulation voltage of about 0.75% will be observed. The variation of this shift
minimally affects the reference tolerance. Therefore, the reference value in skip mode is 0.764 V ±1.3% over line
and temperature.
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Feature Description (continued)
7.3.3 Low-Side Driver
The low-side driver is designed to drive high current low RDS(on) N-channel MOSFET(s). The drive capability is
represented by its internal resistances, which are 4 Ω for V5IN to DRVLx, and 1 Ω for DRVLx to PGNDx. A dead
time to prevent shoot through is internally generated between high-side MOSFET off to low-side MOSFET on,
and low-side MOSFET off to high-side MOSFET on. A 5-V bias voltage is delivered from V5IN supply. The
instantaneous drive current is supplied by an input capacitor connected between V5IN and GND. The average
drive current is equal to the gate charge at Vgs = 5 V times switching frequency. This gate drive current, as well
as the high-side gate drive current times 5 V, makes the driving power that needs to be dissipated from
TPS51124 package.
7.3.4 High-Side Driver
The high-side driver is designed to drive high-current, low RDS(on) N-channel MOSFET(s). When configured as a
floating driver, 5-V bias voltage is delivered from V5IN supply. The average drive current is also calculated by the
gate charge at Vgs = 5 V times switching frequency. The instantaneous drive current is supplied by the flying
capacitor between VBSTx and LLx pins. The drive capability is represented by its internal resistances, which are
5 Ω for VBSTx to DRVHx and 1.5 Ω for DRVHx to LLx.
7.3.5 PWM Frequency and Adaptive On-Time Control
TPS51124 employs adaptive on-time control scheme and does not have a dedicated oscillator on board.
However, the part runs with pseudo-constant frequency by feed-forwarding the input and output voltage into the
on-time one-shot timer. The frequencies are set by TONSEL terminal connection as Table 1. The on-time is
controlled inverse proportional to the input voltage and proportional to the output voltage so that the duty ratio is
kept as VOUT/VIN technically with the same cycle time. Although the TPS51124 does not have a pin connected
to VIN, the input voltage is monitored at LLx pin during the ON state. This helps pin count reduction to make the
part compact without sacrificing its performance.
Table 1. TONSEL Connection and Switching Frequency Table
(Frequencies Are Approximate)
TONSEL CONNECTION
SWITCHING FREQUENCY
CH1
CH2
GND
240 kHz
300 kHz
FLOAT (Open)
300 kHz
360 kHz
V5FILT
360 kHz
420 kHz
7.3.6 Powergood
The TPS51124 has the powergood output for both switcher channels. The powergood function is activated after
soft start has finished. If the output voltage becomes within ±5% of the target value, internal comparators detect
power good state and the power good signal becomes high after a 510-μs internal delay. During start-up, this
internal delay starts after 1.7 times internal soft-start time to avoid a glitch of powergood signal. If the feedback
voltage goes outside of ±10% of the target value, the powergood signal becomes low after 10-μs internal delay.
Also note that if the feedback voltage goes +10% above target value and the powergood signal flags low, then
the loop attempts to correct the output by turning on the low-side driver (forced PWM mode). After the feedback
voltage returns to be within +5% of the target value and the powergood signal goes high, the controller returns
back to auto-skip mode.
7.3.7 Output Discharge Control
TPS51124 discharges the output when ENx is low, or the controller is turned off by the protection functions
(OVP, UVP, UVLO, and thermal shutdown). TPS51124 discharges outputs using an internal, 10-Ω MOSFET
which is connected to VOx and PGNDx. The external low-side MOSFET is not turned on for the output discharge
operation to avoid the possibility of causing negative voltage at the output. Output discharge time constant is a
function of the output capacitance and the resistance of the internal discharge MOSFET. This discharge ensures
that, on restart, the regulated voltage always starts from zero volts. In case a SMPS is restarted before discharge
completion, discharge is terminated and the switching resumes after the reference level, ramped up by an
internal DAC, comes back to the remaining output voltage.
12
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7.3.8 Current Protection
TPS51124 has cycle-by-cycle over-current limiting control. The inductor current is monitored during the OFF
state and the controller keeps the OFF state during the inductor current is larger than the over-current trip level.
In order to provide both good accuracy and cost effective solution, TPS51124 supports temperature
compensated MOSFET RDS(on) sensing. TRIPx pin should be connected to GND through the trip voltage setting
resistor, Rtrip. TRIPx terminal sources 10-μA Itrip current and the trip level is set to the OCL trip voltage Vtrip as
below.
V (mV) + R (kW) 10 (mA)
trip
trip
(2)
The trip level should be in the range of 30 mV to 200 mV over all operational temperatures. The inductor current
is monitored by the voltage between PGNDx pin and LLx pin so that LLx pin should be connected to the drain
terminal of the low-side MOSFET. Itrip has 4200 ppm/°C temperature slope to compensate the temperature
dependency of the RDS(on). PGNDx is used as the positive current sensing node so that PGNDx should be
connected to the source terminal of the low-side MOSFET. As the comparison is done during the OFF state, Vtrip
sets the valley level of the inductor current. Thus, the load current at over-current threshold, Iocl, can be
calculated as follows;
V
I
ocl
+V
trip
ńR
DS(on)
)I
ripple
ń2 +
R
trip
DS(on)
)
2
1
L
ƒ
ǒVIN * VOUTǓ
V
V
OUT
IN
(3)
In an over-current condition, the current to the load exceeds the current to the output capacitor; thus, the output
voltage tends to fall off (droop). Eventually, it ends up crossing the under-voltage protection threshold and shuts
down.
7.3.9 Over and Undervoltage Protection
TPS51124 monitors a resistor divided feedback voltage to detect over and under voltage. When the feedback
voltage becomes higher than 115% of the target voltage, the OVP comparator output goes high and the circuit
latches as the high-side MOSFET driver OFF and the low-side MOSFET driver ON.
Also, the TPS51124 monitors VOx voltage directly and if it becomes greater than 5.75 V, the TPS51124 turns off
the top MOSFET driver, and shuts off both drivers of the other channel.
When the feedback voltage becomes lower than 70% of the target voltage, the UVP comparator output goes
high and an internal UVP delay counter begins counting. After 32 μs, TPS51124 latches OFF both top and
bottom MOSFET drivers, and shuts off both drivers of the other channel. This function is enabled after 1.7 times
soft-start delay time, approximately 2 ms, to ensure start-up properly.
7.3.10 UVLO Protection
TPS51124 has V5FILT under-voltage lock-out protection (UVLO). When the V5FILT voltage is lower than UVLO
threshold voltage, the TPS51124 is shut off. This is non-latch protection.
7.3.11 Thermal Shutdown
TPS51124 monitors its own temperature. If the temperature exceeds the threshold value (typically 160°C), the
switchers are shut off as both DRVH and DRVL at low; the output discharge function is enabled. TPS51124 is
shut off. This is non-latch protection.
7.4 Device Functional Modes
7.4.1 Enable and Soft-Start
The TPS51124 has dedicated ENx pin to enable/disable each channel. When the ENx pin is low, the
corresponding channel is disabled; When the ENx pin becomes high, an internal 1.2-ms, voltage servo begins
ramping up the reference voltage to the PWM comparator, the output voltage of corresponding channel will ramp
up accordingly. By this mean, smooth control of the output voltage is maintained during start-up.
As TPS51124 shares one voltage servo with both channels, if ENx pin is set to high while another channel is
starting up, soft start is postponed until another channel soft start has completed. If both of EN1 and EN2 are set
high at a same time, both channels start up at same time.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TPS51124 is typically used as a dual-synchronous buck controller, which convert an input voltage ranging
from 3V to 28 V, to output voltage ranging 0.76 V to 5.5 V, targeted for notebook I/O and low voltage system bus
supply solutions.
8.2 Typical Application
Input Voltage
3 V to 28 V
EN2
C5
0.1 µF
GND
VFB1
TONSEL
2
1
EN1 23
9 VBST2
EN1
TPS51124RGE
(QFN24)
13
C2
0.1 µF
DRVH1 21
15
16 17
R7 R3
3.3Ω 6.8
kΩ
R6
6.8 kΩ
C7
4.7μF
PGND
PGND1
14
V5IN
V5FILT
C4
2 x 330 µF
Q1
IRF7821
VBST1 22
LL1 20
12 DRVL2
PGND
Power
Good1
PGOOD1 24
11 LL2
Q4
IRF8113
4.5 V to 5.5 V
3
8 EN2
10 DRVH2
V5IN
R1
28.7 kΩ
TRIP1
L2
1 µH
7 PGOOD2
TRIP2
VO2
1.5 V/10 A
10 µF
Q3
IRF7821
4
PGND2
C6
5
VO2
Power
Good2
6
VFB2
SGND PGND
R2
75
kΩ
SGND
VO1
R5
R4 75 kΩ
73.2 kΩ
C9
22 µF
C3
L1
1 µH
Q2
IRF8113
DRVL1 19
10 µF
VO1
1.05 V/10 A
C1
2 x 330 µF
18
PGND
C8
1μF
SGND
Figure 18. Typical Application Circuit
Table 2. Typical Application Circuit Components
14
SYMBOL
SPECIFICATION
MANUFACTURER
PART NUMBER
C1
330 μF, 2.5 V, 15 mΩ
SANYO
2R5TPE330MF
C4
330 μF, 2.5 V, 18 mΩ
SANYO
2R5TPE330MI
L1, L2
1 μH, 2 mΩ
TOKO
FDA1254-1R0M
C3, C6
10 μF, 25 V
TDK
C3225X5R1E106
Q1, Q3
30 V, 13 mΩ
International Rectifier
IRF7821
Q2, Q4
30 V, 7 mΩ
International Rectifier
IRF8113
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8.2.1 Design Requirements
Table 3. Design Parameters
PARAMETER
VALUE
Input voltage range
3 V to 28 V
Channel 1 output voltage
1.05 V
Channel 1 output current
10 A
Channel 2 output voltage
1.5 V
Channel 2 output current
10 A
8.2.2 Detailed Design Procedure
Figure 19 shows a simplified buck converter system using D-CAP Mode.
VIN
R1
DRVH
VFB
PWM
−
+
R2
+
Control
Logic
And
Driver
Lx
IL
0.758V
Voltage Divider
IC
DRVL
IO
ESR
Vc
Switching Modulator
RL
Co
Output Capacitor
Figure 19. Simplifying the Modulator
The output voltage is compared with an internal reference voltage after divider resistors, R1 and R2. The PWM
comparator determines the timing to turn on the high-side MOSFET. The gain and speed of the comparator is
high enough to keep the voltage at the beginning of each on cycle (or the end of off cycle) substantially constant.
The DC output voltage may have line regulation due to ripple amplitude that slightly increases as the input
voltage increase.
For the loop stability, the 0-dB frequency, f 0, defined in Equation 4 needs to be lower than 1/4 of the switching
frequency.
ƒ
1
ƒo +
v sw
4
2p ESR Co
(4)
As f 0 is determined solely by the output capacitor’s characteristics, loop stability of D-CAP Mode is determined
by the capacitor’s chemistry. For example, specialty polymer capacitors (SP-CAP) have Co in the order of
several 100 μF and ESR in range of 10 mΩ. These make f 0 in the order of 100 kHz or less and the loop is
stable. However, ceramic capacitors have f 0 at more than 700 kHz, which is not suitable for this operational
mode.
Although D-CAP Mode provides many advantages such as ease-of-use, minimum external components
configuration, and extremely short response time, a sufficient amount of feedback signal needs to be provided by
an external circuit to reduce jitter level. This is due to not employing an error amplifier in the loop. The required
signal level is approximately 10 mV at the comparing point (VFB terminal). This gives Vripple at the output node
as shown in the following equation.
Vripple + Vout
10 [mV]
0.758
(5)
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The output capacitor's ESR should meet this requirement.
The external components selection is much simpler in D-CAP Mode.
1. Determine the value of R1 and R2.
Recommended R2 value is from 10 kΩ to 100 kΩ. Determine R1 using the following equation.
R1 +
ǒV out * 0.758Ǔ
0.758
2. Choose inductor.
R2
(6)
The inductance value should be determined to give the ripple current of approximately 1/4 to 1/2 of maximum
output current. Larger ripple current increases the output ripple voltage, improves S/N ratio, and contributes
to a stable operation.
L+
ǒVIN(max) * VOUTǓ
1
I
IND(ripple)
ƒ
V
V
OUT
IN(max)
+
ǒVIN(max) * VOUTǓ
3
I
ƒ
OUT(max)
V
V
OUT
IN(max)
(7)
The inductor also needs to have low DCR to achieve good efficiency, as well as enough room above peak
inductor current before saturation. The peak inductor current can be estimated as follows.
V
I
IND(peak)
+
R
trip
DS(on)
)
1
L
ǒVIN(max) * VOUTǓ
ƒ
V
V
OUT
IN(max)
(8)
3. Choose output capacitor(s).
Organic semiconductor capacitor(s) or specialty polymer capacitor(s) are recommended. Determine ESR to
meet the required ripple voltage indicated previously. A quick approximation is shown here:
VOUT
VOUT x 0.0132
ESR =
=
= 30 [mW]
Iripple
IOUT(max)
(9)
8.2.3 Application Curves
TONSEL = FLOAT
TONSEL = FLOAT
VOUT1 (50 mV/div)
IIND1 (5 A/div)
IIND2 (5 A/div)
IOUT1 (5 A/div)
IOUT2 (5 A/div)
t − Time − 20 ms/div
t − Time − 20 ms/div
Figure 20. 1.05-V Load Transient Response
16
VOUT2 (50 mV/div)
Figure 21. 1.5-V Load Transient Response
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EN2 (5 V/div)
EN1 (5 V/div)
VO2 (0.5 V/div)
VO1 (0.5 V/div)
PGOOD1 (5 V/div)
PGOOD2 (5 V/div)
t − Time − 500 ms/div
t − Time − 500 ms/div
Figure 22. 1.05-V Start-Up Waveforms
EN1 (5 V/div)
EN2 (5 V/div)
VO1 (1 V/div)
VO2 (1 V/div)
PGOOD1 (5 V/div)
PGOOD2 (5 V/div)
DRVL1 (5 V/div)
DRVL2 (5 V/div)
(1)
t − Time − 1 ms/div
t − Time −1 ms/div
Figure 24. 1.05-V Discharge Waveforms
(1)
Figure 23. 1.5-V Start-Up Waveforms
Figure 25. 1.5-V Discharge Waveforms
The data of Figure 23–Figure 25 are measured from the Typical Application Circuit of Figure 18 and Table 2
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9 Power Supply Recommendations
The TPS51124 is designed to operate from input supply voltage in the range of 3V to 28 V, make sure power
supply voltage in this range.
10 Layout
10.1 Layout Guidelines
Certain points must be considered before starting a layout using the TPS51124.
• Connect RC low-pass filter from V5IN to V5FILT, 1-μF and 3.3-Ω are recommended. Place the filter capacitor
close to the IC, within 12 mm (0.5 inch) if possible.
• Connect the over-current setting resistors from TRIPx to GND, and as close as possible to the IC. The trace
from TRIPx to resistor, and resistor to GND, should avoid coupling to high-voltage switching node.
• The discharge path (VOx) should have a dedicated trace to the output capacitor(s), separate from the output
voltage sensing trace. Use 1,5-mm (60 mils) or wider trace, with no loops. Tie the feedback-current-setting
resistor (the resistor between VFBx to GND) close to the IC’s GND. The trace from this resistor to VFBx pin
should be short and thin. Place on the component side and avoid vias between this resistor and the IC.
• Connections from the drivers to the respective gate of the high-side or the low-side MOSFET should be as
short as possible to reduce stray inductance. Use 0,65-mm (25 mils) or wider trace.
• All sensitive analog traces and components such as VOx, VFBx, GND, ENx, PGOODx, TRIPx, V5FILT, and
TONSEL should be placed away from high-voltage switching nodes such as LLx, DRVLx, DRVHx, or VBSTx
nodes to avoid coupling. Use internal layer(s) as ground plane(s) and shield the feedback trace from power
traces and components.
• Gather ground terminal of VIN capacitor(s), Vout capacitor(s), and source of low-side MOSFETs as close as
possible. GND (signal ground) and PGNDx (power ground) should be connected strongly together near the
IC. PCB trace defined as LLx node, which connects to source of high-side MOSFET, drain of low-side
MOSFET and high-voltage side of the inductor, should be as short and wide as possible.
• In order to effectively remove heat from the package, prepare thermal land and solder to the package’s
thermal pad. Two by two or more vias with a 0,33-mm (13 mils) diameter connected from the thermal land to
the internal ground plane should be used to help dissipation. Do NOT connect PGNDx to this thermal land
underneath the package.
18
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10.2 Layout Example
Figure 26. Layout Example
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11 Device and Documentation Support
11.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
11.2 Trademarks
D-CAP is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
20
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PACKAGE OPTION ADDENDUM
www.ti.com
9-Oct-2021
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS51124RGER
ACTIVE
VQFN
RGE
24
3000
RoHS & Green
Call TI | NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TPS
51124
TPS51124RGERG4
ACTIVE
VQFN
RGE
24
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TPS
51124
TPS51124RGET
ACTIVE
VQFN
RGE
24
250
RoHS & Green
Call TI | NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TPS
51124
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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