TPS51222
www.ti.com............................................................................................................................................................................................... SLUS908 – JANUARY 2009
Fixed Frequency, 99% Duty Cycle Peak Current Mode Notebook System Power Controller
FEATURES
1
• Input Voltage Range: 4.5 V to 32 V
• Output Voltage Range: 1 V to 12 V
• Selectable Light Load Operation
(Continuous / Auto Skip / Out-Of-Audio™ Skip)
• Programmable Droop Compensation
• Voltage Servo Adjustable Soft Start
• 200-kHz to 1-MHz Fixed-Frequency PWM
• Current Mode Architecture
• 180° Phase Shift Between Channels
• Resistor or Inductor DCR Current Sensing
• Current Monitor Output for Each Channel
• Adaptive Zero Crossing Circuit
• Powergood Output for Each Channel
• OCL/OVP/UVP/UVLO Protections
• Thermal Shutdown (Non-Latch)
• Output Discharge Function
• Integrated Boot Strap MOSFET Switch
• QFN-32 (RTV) Package
APPLICATIONS
2
•
•
Notebook Computer System and I/O Bus
Point of Load in LCD TV, MFP
DESCRIPTION
The TPS51222 is a dual synchronous buck regulator
controller with two LDOs. It is optimized for 5-V/3.3-V
system controller, enabling designers to cost
effectively complete 2-cell to 4-cell notebook system
power supply. The TPS51222 supports high
efficiency, fast transient response, and 99% duty
cycle operation. It supports supply input voltage
ranging from 4.5 V to 32 V, and output voltages from
1 V to 12 V. Peak current mode supports stability
operation with lower ESR capacitor and output
accuracy. The high duty cycle (99%) operation and
the wide input/output voltage range supports flexible
design for small mobile PCs and a wide variety of
other applications. The fixed frequency can be
adjusted from 200 kHz to 1 MHz by a resistor, and
each channel runs 180° out-of-phase. The TPS51222
can also synchronize to the external clock, and the
interleaving ratio can be adjusted by its duty. The
TPS51222 is available in the 32-pin 5 × 5 QFN
package and is specified from –40°C to 85°C.
VBAT
26
25
SW2
RF
27
VBST
3
28
DRVL2
V5SW
29
GND
DRVH1
2
30
DRVL1
1
31
VREG5
VO1
32
SW1
VO1
5V
VBST1
VBAT
VREG5
5 V/
100 mA
VO2
3.3 V
DRVH2 24
VIN 23
VBAT
VREG3
3.3 V/
10 mA
VREG3 22
EN1
4
EN1
PGOOD1
5
PGOOD1
PGOOD2 20
EN2 21
EN2
PGOOD2
SKIPSEL1
6
SKIPSEL1
SKIPSEL2 19
SKIPSEL2
7
CSP1
8
CSN1
TPS51222RTV
EN
IMON1
VO1
VFB1
COMP1
IMON1
EN
VREF2
IMON2
COMP2
VFB2
CSP2 18
9
10
11
12
13
14
15
16
CSN2 17
IMON2
VO2
UDG-09009
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Out-Of-Audio, PowerPAD are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2009, Texas Instruments Incorporated
TPS51222
SLUS908 – JANUARY 2009............................................................................................................................................................................................... www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
FUNCTIONAL BLOCK DIAGRAM
VIN
EN
V5SW
4.7V/ 4.5V
+
+
EN1 OK
1.25V
+
+
4.7V/ 4.5V
V5SW OK
VREG5
VREG3
GND
+
V5OK
4.2V/ 3.8V
GND
Ready
+
THOK
150/ 140
Deg-C
VREF2
1.25V
GND
GND
CLK2
OSC
RF
CLK1
GND
1V +5%/ 10%
+
PGOOD1
Delay
+
1V - 5%/ 10%
+
1V -30%
GND
CLK1
UVP
+
Ready
OVP
Fault2
SDN2
1V +15%
Fault1
Clamp (+)
COMP1
Ramp
Comp
Clamp (-)
SDN1
+
+ PWM
VFB1
EN1
IMON1
VREG5
1V
+
Enable/
Soft-start
+
Filter
VREF2
VBST1
Amp.
Ramp
Comp
+
Skip
Control
Logic
DRVH1
CS-AMP
CSN1
CSP1
VFB-AMP
SW1
+
OCP
+
XCON
VREG5
100mV
DRVL1
AZC
Discharge
Control
GND
GND
100mV
VREF2
N-OCP
+
GND
OOA
Ctrl
GND
SKIPSEL1
Channel-1 Switcher shown
2
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TPS51222
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ABSOLUTE MAXIMUM RATINGS (1)
over operating free-air temperature range (unless otherwise noted)
TPS51222
VIN
VBST1, VBST2
VBST1, VBST2
Input voltage range
–0.3 to 39
(3)
–0.3 to 7
SW1, SW2
(2)
Output voltage range (2)
UNIT
–0.3 to 34
–5 to 34
CSN1, CSN2, CSP1, CSP2
–1 to 13.5
EN, EN1, EN2, SKIPSEL1, SKIPSEL2, VFB1, VFB2
–0.3 to 7
V5SW
–1 to 7
V5SW (to VREG5) (4)
–7 to 7
V
DRVH1, DRVH2
–5 to 39
V
DRVH1, DRVH2 (3)
–0.3 to 7
V
COMP1, COMP2, DRVL1, DRVL2, IMON1, IMON2, PGOOD1,
PGOOD2, RF, VREF2, VREG5
–0.3 to 7
V
–0.3 to 3.6
V
TJ
Junction temperature
VREG3
150
°C
Tstg
Storage temperature
–55 to 150
°C
(1)
(2)
(3)
(4)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to the network ground terminal unless otherwise noted.
Voltage values are with respect to the corresponding SW terminal.
When EN is high and V5SW is grounded, or voltage is applied to V5SW when EN is low.
DISSIPATION RATINGS (2 oz. Trace and Copper Pad with Solder)
PACKAGE
TA < 25°C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C
TA = 85°C
POWER RATING
32-pin RTV
1.7 W
17 mW/°C
0.7 W
RECOMMENDED OPERATING CONDITIONS
MIN
Supply voltage
I/O voltage
TA
VIN
TYP
MAX
4.5
32
V5SW
–0.8
6
VBST1, VBST2
–0.1
37
DRVH1, DRVH2
–4.0
37
DRVH1, DRVH2 (wrt SW1, 2)
–0.1
6
SW1, SW2
–4.0
32
CSP1, CSP2, CSN1, CSN2
–0.8
13
COMP1, COMP2, DRVL1, DRVL2, EN, EN1, EN2, IMON1, IMON2,
PGOOD1, PGOOD2, RF, SKIPSEL1, SKIPSEL2, VFB1, VFB2,
VREF2, VREG5
–0.1
6
VREG3
–0.1
3.5
–40
85
Operating free-air temperature
UNIT
V
V
°C
ORDERING INFORMATION
TA
PACKAGE (1)
ORDERABLE PART
NUMBER
TRANSPORT MEDIA
QUANTITY
ECO PLAN
-40°C to 85°C
Plastic Quad Flat Pack
(32-Pin QFN)
TPS51222RTVT
Tape and Reel
250
TPS51222RTVR
Tape and Reel
3000
Green (RoHS
and no Sb/Br)
(1)
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
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TPS51222
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ELECTRICAL CHARACTERISTICS
over operating free-air temperature range, EN = 3.3V, VIN = 12V, V5SW = 5V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
7
15
µA
80
120
µA
SUPPLY CURRENT
I(VINSDN)
VIN shutdown current
VIN shutdown current, TA = 25°C,
No Load, EN = 0V, V5SW = 0 V
I(VINSTBY)
VIN Standby Current
VIN standby current, TA = 25°C, No Load,
EN1 = EN2 = V5SW = 0 V
I(VBATSTBY)
Vbat Standby Current
Vbat standby current, TA = 25°C, No Load
SKIPSEL2 = 2V, EN2 = open, EN1 = V5SW = 0V (1)
500
µA
I(V5SW)
V5SW Supply Current
V5SW current, TA = 25°C, No Load,
ENx = 5V, VFBx = 1.05 V
0.8
mA
VREF2 OUTPUT
V(VREF2)
VREF2 Output Voltage
I(VREF2) < ±10 µA, TA = 25°C
1.98
2.00
2.02
I(VREF2) < ±100 µA, 4.5V < VIN < 32 V
1.97
2.00
2.03
V
VREG3 OUTPUT
V5SW = 0 V, I(VREG3) = 0 mA, TA = 25°C
3.279
3.313
3.347
V(VREG3)
VREG3 Output Voltage
V5SW = 0 V, 0 mA < I(VREG3) < 10 mA,
5.5 V < VIN < 32 V
3.135
3.300
3.400
I(VREG3)
VREG3 Output Current
VREG3 = 3 V
10
15
20
V5SW = 0 V, I(VREG5) = 0 mA, TA = 25°C
4.99
5.04
5.09
V5SW = 0 V, 0 mA < I(VREG5) < 100 mA,
6 V < VIN < 32 V
4.90
5.03
5.15
V5SW = 0 V, 0 mA < I(VREG5) < 100 mA,
5.5 V < VIN < 32 V
4.50
5.03
5.15
V5SW = 0 V, VREG5 = 4.5 V
100
150
200
V5SW = 5 V, VREG5 = 4.5 V
200
300
400
Turning on
4.55
4.7
4.8
Hysteresis
0.15
0.20
0.25
V
mA
VREG5 OUTPUT
V(VREG5)
VREG5 Output Voltage
V
V
I(VREG5)
VREG5 Output Current
mA
V(THV5SW)
Switchover Threshold
td(V5SW)
Switchover Delay
Turning on
7.7
ms
R(V5SW)
5V SW Ron
I(VREG5) = 100 mA
0.5
Ω
V(VFB)
VFB Regulation Voltage
Tolerance
TA = 25°C, No Load
I(VFB)
VFB Input Current
VFBx = 1.05 V, COMPx = 1.8 V, TA = 25°C
R(Dischg)
CSNx Discharge Resistance
ENx = 0 V, CSNx = 0.5 V, TA = 25°C
V
OUTPUT
TA = –40°C to 85°C , No Load
0.9925
1.000
1.0075
0.990
1.000
1.010
–50
20
V
50
nA
40
Ω
VOLTAGE TRANSCONDUCTANCE AMPLIFIER
Gmv
Gain
VID
Differential Input Voltage
Range
I(COMPSINK)
COMP Maximum Sink
Current
COMPx = 1.8 V
I(COMPSRC)
COMP Maximum Source
Current
COMPx = 1.8 V
VCOMP
COMP Clamp Voltage
VCOMPN
COMP Negative Clamp
Voltage
(1)
4
TA = 25°C
µS
500
–30
30
mV
TA = 0 to 85°C
27
33
µA
TA = –40 to 85°C
22
33
µA
–33
–43
µA
2.18
2.22
2.26
V
1.73
1.77
1.81
V
Specified by design. Detail external condition follows application circuit of Figure 52.
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www.ti.com............................................................................................................................................................................................... SLUS908 – JANUARY 2009
ELECTRICAL CHARACTERISTICS (continued)
over operating free-air temperature range, EN = 3.3V, VIN = 12V, V5SW = 5V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
CURRENT AMPLIFIER
GC
Gain
VIC
Common mode Input
Voltage Range
VID
Differential Input Voltage
Range
CSNx = 5V, TA = 25°C (2)
1.667
TA = 25°C
0
13
V
–75
75
mV
POWERGOOD
PG in from lower
92.5%
95%
97.5%
PG in from higher
102.5%
105%
107.5%
V(THPG)
PG threshold
I(PG)
PG sink Current
PGOOD = 0.5 V
t(PGDLY)
PGOOD Delay
Delay for PG in
t(SSDYL)
Soft Start Delay
Delay for Soft Start, ENx = Hi to SS-ramp starts
200
µs
t(SS)
Soft Start Time
Internal Soft Start
960
µs
PG hysteresis
5%
5
0.8
1
mA
1.2
ms
SOFTSTART
FREQUENCY AND DUTY CONTROL
f(SW)
Switching Frequency
V(THRF)
RF Threshold
f(SYNC)
Sync Input Frequency
Range (2)
tONmin
Minimum On Time
tOFFmin
Minimum Off Time
Rf = 330 kΩ
273
303
333
Lo to Hi
0.7
1.3
2
Hysteresis
0.2
200
kHz
V
V
1000
kHz
V(DRVH) = 90% to 10%, No Load, CCM/ OOA (2)
120
V(DRVH) = 90% to 10%, No Load, Auto-skip
160
250
ns
V(DRVH) = 10% to 90%, No Load
290
400
ns
ns
DRVH-off to DRVL-on
10
30
50
ns
DRVL-off to DRVH-on
30
40
70
ns
tD
Dead time
V(DTH)
DRVH-off threshold
DRVH to GND
V(DTL)
DRVL-off threshold
DRVL to GND (2)
(2)
1
V
1
V
CURRENT SENSE
2 V< VCSNx < 12.6 V
V(OCL)
Current limit threshold
0.95 V < VCSNx < 12.6 V
VZCAJ
Auto-Zero cross adjustable
offset range
0.95 V < VCSNx < 12.6 V, Auto-skip
V(ZC)
Zero cross detection
comparator Offset
0.95 V < VCSNx < 12.6 V, OOA
V(OCLN-LV)
Negative current limit
threshold
0.95 V < VCSNx < 12.6 V
(2)
TA = 0 to 85°C
56
60
65
TA = –40 to 85°C
55
60
68
TA = 0 to 85°C
55
60
67
TA = –40 to 85°C
54
60
72
Positive
5
Negative
–5
mV
mV
–4
0
4
TA = 0 to 85°C
–50
–60
–73
TA = –40 to 85°C
–49
–60
–77
mV
Specified by design.
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TPS51222
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ELECTRICAL CHARACTERISTICS (continued)
over operating free-air temperature range, EN = 3.3V, VIN = 12V, V5SW = 5V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
1.7
5
1
3
Source, V(VREG5-DRVL) = 0.1 V
1.3
4
Sink, V(DRVL-GND) = 0.1 V
0.7
2
UNIT
OUTPUT DRIVERS
R(DRVH)
DRVH resistance
R(DRVL)
DRVL resistance
Source, V(VBST-DRVH) = 0.1 V
Sink, V(DRVH-SW) = 0.1 V
Ω
Ω
CURRENT MONITOR
GIMON
Current monitor gain
50
VIMON
Current monitor output
VCSPx–VCSNx = 60 mV, 0.95 V < VCSNx < 12.6 V,
TA = 25°C
VIMON-OFF
Current monitor output offset
VCSPx–VCSNx = 0 mV, 0.95 V < VCSNx < 12.6 V,
TA = 25°C
2.75
–200
3.00
3.25
V
200
mV
UVP, OVP AND UVLO
V(OVP)
OVP Trip Threshold
t(OVPDLY)
OVP Prop Delay
V(UVP)
UVP Trip Threshold
t(UVPDLY)
UVP Delay
V(UVREF2)
VREF2 UVLO Threshold
V(UVREG3)
VREG3 UVLO Threshold
V(UVREG5)
VREG5 UVLO Threshold
OVP detect
110%
115%
120%
µs
1.5
UVP detect
65%
70%
73%
0.8
1
1.2
Wake up
1.7
1.8
1.9
V
Hysteresis
75
100
125
mV
Wake up
Hysteresis
Wake up
Hysteresis
3
3.1
3.2
0.10
0.15
0.20
ms
V
4.1
4.2
4.3
V
0.35
0.40
0.44
V
INTERFACE AND LOGIC THRESHOLD
V(EN)
EN Threshold
V(EN12)
EN1/EN2 Threshold
V(EN12SS)
EN1/EN2 SS Start
Threshold
Wake up
0.8
1
1.2
Hysteresis
0.1
0.2
0.3
0.45
0.50
0.55
0.1
0.2
0.3
Wake up
Hysteresis
SS-ramp start threshold at external soft start
V(EN12SSEND)
EN1/EN2 SS End Threshold
SS-End threshold at external soft start
I(EN12)
EN1/EN2 Source Current
VEN1/EN2 = 0V
1
(3)
2
Continuous
V(SKIPSEL)
SKIPSEL1/SKIPSEL2
Setting Voltage
SKIPSEL Input Current
V
2.4
µA
1.5
Auto Skip
1.9
2.1
OOA Skip (min 1/8 Fsw)
3.2
3.4
OOA Skip (min 1/16 Fsw)
I(SKIPSEL)
V
V
2
1.6
V
V
3.8
SKIPSELx = 0 V
–0.5
0.5
SKIPSELx = 5 V
–0.5
0.5
µA
BOOT STRAP SW
V(FBST)
Forward Voltage
VVREG5-VBST, IF = 10 mA, TA = 25°C
0.10
0.20
V
I(BSTLK)
VBST Leakage Current
VVBST = 37 V, VSW = 32 V
0.01
1.5
µA
Shutdown temperature (3)
150
THERMAL SHUTDOWN
T(SDN)
(3)
6
Thermal SDN Threshold
Hysteresis (3)
10
°C
Specified by design.
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TPS51222
www.ti.com............................................................................................................................................................................................... SLUS908 – JANUARY 2009
DEVICE INFORMATION
PINOUT
VBST2
SW2
25
GND
DRVL2
27
26
30
DRVH2
VIN
5
6
20
19
7
8
18
17
PGOOD2
SKIPSEL2
CSP2
CSN2
3
4
VFB1
COMP1
IMON1
VREG3
EN2
15
16
TPS51122
9
10
CSN1
24
23
22
21
VREF2
IMON2
COMP2
VFB2
SKIPSEL1
CSP1
1
2
11
12
13
14
V5SW
RF
EN1
PGOOD1
EN
DRVH1
29
28
32
31
SW1
VBST1
DRVL1
VREG5
RTV PACKAGE
(TOP VIEW)
PIN FUNCTIONS
PIN
NAME
NO.
COMP1
10
COMP2
15
CSN1
8
CSN2
17
CSP1
7
CSP2
18
DRVH1
1
DRVH2
24
DRVL1
30
DRVL2
27
EN
12
EN1
4
EN2
21
GND
28
IMON1
11
IMON2
14
PGOOD1
5
PGOOD2
20
RF
3
I/O
DESCRIPTION
I
Loop compensation pin for current mode (error amplifier output). Connect R (and C if required) from this pin
to VREF2 for proper loop compensation with current mode operation.
I
Current sense comparator inputs (–). See the current sensing scheme section. Used as power supply for the
current sense circuit for 5 V or higher output voltage setting. Also, used for output discharge terminal.
I/O
Current sense comparator inputs (+). An RC network with high quality X5R or X7R ceramic capacitor should
be used to extract voltage drop across DCR. 0.1-µF is a good value to start the design. See the current
sensing scheme section for more details.
O
High-side MOSFET gate driver outputs. Source 1.7 Ω, sink 1.0 Ω, SW-node referenced floating driver. Drive
voltage corresponds to VBST to SW voltage.
O
Low-side MOSFET gate driver outputs. Source 1.3 Ω, sink 0.7 Ω, and GND referenced driver.
I
VREF2 and VREG5 linear regulators enable pin. When turning on, apply greater than 1.2 V and less than 6
V. Connect to GND to disable.
I
Channel 1 and channel 2 SMPS Enable Pins. When turning on, apply greater than 0.55 V and less than 6 V.
Connect to GND to disable. Adjustable soft-start capacitance to be attached here.
–
Ground
O
Current monitor outputs for channel 1 and channel 2. Adding an RC filter is recommended.
O
Powergood window comparator outputs for channel 1 and channel 2. The recommended applied voltage
should be less than 6 V, and the recommended pull-up resistance value is from 100 kΩ to 1 MΩ.
I/O
Frequency setting pin. Connect a frequency setting resistor to (signal) GND. Connect to an external clock for
synchronization.
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PIN FUNCTIONS (continued)
PIN
NAME
NO.
SKIPSEL1
6
SKIPSEL2
19
SW2
25
SW1
32
V5SW
2
VBST1
31
VBST2
I/O
26
DESCRIPTION
Skip mode selection pin.
I
I/O
GND: Continuous conduction mode
VREF2: Auto Skip
VREG3: OOA Auto Skip, maximum 7 skips (suitable for fsw < 400kHz)
VREG5: OOA Auto Skip, maximum 15 skips (suitable for equal to or greater than 400kHz)
High-side MOSFET gate driver returns.
I
VREG5 switchover power supply input pin. When EN1 is high, PGOOD1 indicates GOOD and V5SW
voltage is higher than 4.8 V, switch-over function is enabled.
Note: When switch-over is enabled, VREG5 output voltage is approximately equal to the V5SW input
voltage.
I
Supply inputs for high-side N-channel FET driver (boot strap terminal). Connect a capacitor (0.1-µF or
greater is recommended) from this pin to respective SW terminal. Additional SB diode from VREG5 to this
pin is an optional.
I
SMPS voltage feedback Inputs. Connect the feedback resistors divider, and should be referred to (signal)
GND.
VFB1
9
VFB2
16
VIN
23
I
Supply input for 5-V and 3.3-V linear regulator. Typically connected to VBAT.
VREF2
13
O
2-V reference output. Bypass to (signal) GND with 0.22-µF of ceramic capacitance.
VREG3
22
O
Always alive 3.3 V, 10 mA low dropout linear regulator output. Bypass to (signal) GND with more than 1-µF
ceramic capacitance. Runs from VIN supply or from VREG5 when it is switched over to V5SW input.
O
5-V, 100-mA low dropout linear regulator output. Bypass to (power) GND using a 10-µF ceramic capacitor.
Runs from VIN supply. Internally connected to VBST and DRVL. Shuts off with EN. Switches over to V5SW
when 4.8 V or above is provided.
Note: When switch-over (see above V5SW) is enabled, VREG5 output voltage is approximately equal to
V5SW input voltage.
VREG5
8
29
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TYPICAL CHARACTERISTICS
INPUT VOLTAGE SHUTDOWN CURRENT
vs
INPUT VOLTAGE
INPUT VOLTAGE SHUTDOWN CURRENT
vs
JUNCTION TEMPERATURE
15
15
VI = 12 V
IVINSDN -– Shutdown Current – mA
IVINSDN -– Shutdown Current – mA
TA = 25°C
12
9
6
3
10
15
20
25
9
6
3
0
-50
0
5
12
30
100
TJ – Junction Temperature – °C
Figure 1.
Figure 2.
INPUT VOLTAGE STANDBY CURRENT
vs
JUNCTION TEMPERATURE
INPUT VOLTAGE STANDBY CURRENT
vs
INPUT VOLTAGE
150
150
TA = 25°C
IVINSTBY – Standby Current – mA
VI = 12 V
IVINSTBY – Standby Current – mA
50
VI – Input Voltage – V
150
120
90
60
30
0
-50
0
120
90
60
30
0
0
50
100
150
5
10
15
20
TJ – Junction Temperature – °C
VI – Input Voltage – V
Figure 3.
Figure 4.
25
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TYPICAL CHARACTERISTICS (continued)
NO LOAD BATTERY CURRENT
vs
INPUT VOLTAGE
NO LOAD BATTERY CURRENT
vs
INPUT VOLTAGE
1.0
1.0
EN = on
EN1 = off
EN2 = on
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0
5
10
15
20
25
5
10
15
20
VI – Input Voltage – V
VI – Input Voltage – V
Figure 5.
Figure 6.
BATTERY CURRENT
vs
INPUT VOLTAGE
VREF2 OUTPUT VOLTAGE
vs
OUTPUT CURRENT
1.0
25
2.02
EN = on
EN1 = on
EN2 = off
0.8
VI = 12 V
VVREF2 – VREF2 Output Voltage – V
0.9
IVBAT – Battery Current – mA
EN = on
EN1 = on
EN2 = on
0.9
IVBAT – Battery Current – mA
IVBAT – Battery Current – mA
0.9
2.01
0.7
0.6
0.5
2.00
0.4
0.3
1.99
0.2
0.1
0
5
10
15
20
25
1.98
–100
VI – Input Voltage – V
0
50
100
IVREF2 – VREF2 Output Current – mA
Figure 7.
10
–50
Figure 8.
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TYPICAL CHARACTERISTICS (continued)
VREG3 OUTPUT VOLTAGE
vs
OUTPUT CURRENT
VREG5 OUTPUT VOLTAGE
vs
OUTPUT CURRENT
5.10
VVREG5 – 5-V Linear Regulator Output Voltage – V
VVREG3 – 3.3-V Linear Regulator Output Voltage – V
3.40
VI = 12 V
5.05
3.35
5.00
3.3
4.95
3.25
4.90
3.20
0
2
4
6
8
0
10
20
40
60
80
100
IREG3 – 3.3-V Linear Regulator Output Current – mA
IREG5 – 5-V Linear Regulator Output Current – mA
Figure 9.
Figure 10.
SWITCHING FREQUENCY
vs
JUNCTION TEMPERATURE
FORWARD VOLTAGE OF BOOST SW
vs
JUNCTION TEMPERATURE
330
VFBST – Forward Voltage Boost Voltage – V
0.25
RRF = 330 kW
fSW – Switching Frequency – kHz
VI = 12 V
320
0.20
310
0.15
300
0.10
290
0.05
280
270
-50
0
50
100
150
0
-50
0
50
100
TJ – Junction Temperature – °C
TJ – Junction Temperature – °C
Figure 11.
Figure 12.
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TYPICAL CHARACTERISTICS (continued)
OVP/UVP THRESHOLD VOLTAGE
vs
JUNCTION TEMPERATURE
VBST LEAKAGE CURRENT
vs
JUNCTION TEMPERATURE
150
1.5
IBSTLK – VBST Leakage Current – mA
Voltage Protection Threshold – %
OVP
UVP
130
110
90
70
50
-50
0
50
100
0.9
0.6
0.3
0
-50
150
0
50
100
150
TJ – Junction Temperature – °C
TJ – Junction Temperature – °C
Figure 13.
Figure 14.
CURRENT LIMIT THRESHOLD
vs
JUNCTION TEMPERATURE
5-V OUTPUT VOLTAGE
vs
INPUT VOLTAGE
66
5.2
VCSN (V)
5.1
1
5
12
5.0
64
VO1 – 5-V Output Voltage – V
VOCL – Current Limit Threshold – mV
1.2
62
60
58
56
Auto-Skip Mode
fSW = 330 kHz
4.9
4.8
4.7
4.6
4.5
IO (A)
4.4
0
4
8
4.3
54
-50
12
0
50
100
150
4.2
4.5
5.0
5.5
6.0
TJ – Junction Temperature – °C
VI – Input Voltage – V
Figure 15.
Figure 16.
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TYPICAL CHARACTERISTICS (continued)
3.3-V OUTPUT VOLTAGE
vs
INPUT VOLTAGE
5-V EFFICIENCY
vs
OUTPUT CURRENT
100
3.40
Auto-Skip
Auto-Skip Mode
fSW = 330 kHz
VO2 – 3.3-V Output Voltage – V
80
h – Efficiency – %
3.35
3.30
3.25
IO (A)
5.0
5.5
6.5
6.0
40
0.01
0.1
1
VI – Input Voltage – V
IO1 – 5-V Output Current – A
Figure 17.
Figure 18.
5-V EFFICIENCY
vs
OUTPUT CURRENT
3.3-V EFFICIENCY
vs
OUTPUT CURRENT
10
100
VI = 8 V
Auto-Skip
80
90
VI = 12 V
VI = 20 V
h – Efficiency – %
h – Efficiency – %
Current Mode
VI = 12 V
RGV = 18 kW
0
0.001
7.0
100
80
70
0.01
0.1
1
60
CCM
OOA
40
VI = 12 V
Current Mode
RGV = 12 kW
5.0-V SMPS: ON
20
Auto-Skip
Current Mode
RGV = 18 kW
60
50
0.001
CCM
OOA
20
0
4
8
3.20
4.5
60
10
0
0.001
0.01
0.1
1
IO1 – 5-V Output Current – A
IO2 – 3.3-V Output Current – A
Figure 19.
Figure 20.
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TYPICAL CHARACTERISTICS (continued)
3.3-V EFFICIENCY
vs
OUTPUT CURRENT
5-V SWITCHING FREQUENCY
vs
OUTPUT CURRENT
400
100
CCM
VI = 8 V
350
h – Efficiency – %
VI = 12 V
fSW – Switching Frequency – kHz
90
VI = 20 V
80
70
60
VI = 12 V
Current Mode
RGV = 12 kW
5.0-V SMPS: ON
50
40
0.001
0.01
0.1
1
300
250
200
150
100
OOA
50
Auto-Skip
0
0.001
10
0.01
0.1
1
IO2 – 3.3-V Output Current – A
IO1 – 5-V Output Current – A
Figure 21.
Figure 22.
3.3-V SWITCHING FREQUENCY
vs
OUTPUT CURRENT
5-V OUTPUT VOLTAGE
vs
OUTPUT CURRENT
10
5.10
400
CCM
5.08
5.06
300
5.04
250
5.02
200
5.00
OOA
4.98
150
CCM
4.96
100
OOA
4.94
50
VI = 12 V
Current Mode
RGV = 18 kW
4.92
0
0.001
14
Auto-Skip
VO1 – 5.0-V Output Voltage – V
fSW – Switching Frequency – kHz
350
Auto-Skip
0.01
0.1
1
4.90
10
0
1
2
3
4
5
6
IO2 – 3.3-V Output Current – A
IO1 – 5-V Output Current – A
Figure 23.
Figure 24.
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TYPICAL CHARACTERISTICS (continued)
3.3-V OUTPUT VOLTAGE
vs
OUTPUT CURRENT
5-V OUTPUT VOLTAGE
vs
OUTPUT CURRENT
5.10
3.40
3.38
5.08
Auto-Skip
and
OOA
3.34
5.06
Auto-Skip
and
OOA
VO1 – 5.0-V Output Voltage – V
VO2 – 3.3-V Output Voltage – V
3.36
5.04
5.02
3.32
3.30
5.00
CCM
3.28
4.98
3.26
CCM
4.96
3.24
4.94
VI = 12 V
Current Mode
RGV = 12 kW
3.22
VI = 12 V
Current Mode
(Non-droop)
RGV = 1 kW
C = 1.8 nF
4.92
4.90
3.20
0
1
2
3
4
5
6
7
0
8
1
2
3
4
5
6
7
IO2 – 3.3-V Output Current – A
IO1 – 5-V Output Current – A
Figure 25.
Figure 26.
3.3-V OUTPUT VOLTAGE
vs
OUTPUT CURRENT
5.0-V BODE-PLOT – GAIN AND PHASE
vs
FREQUENCY
80
3.40
8
180
3.38
Auto-Skip
and
OOA
VO2 – 3.3-V Output Voltage – V
3.36
Gain – dB
3.34
3.32
3.30
60
135
40
90
20
45
Gain
0
0
–20
3.28
Phase – °
Phase
45
CCM
3.26
3.24
3.22
–90
–40
VI = 12 V
Current Mode
(Non-droop)
RGV = 9.1 kW
C = 1.8 nF
–60
VO= 5.0 V
VI = 12 V
IO = 8 A
–80
100
3.20
0
1
2
3
4
5
6
7
8
1k
–135
10 k
100 k
–180
1M
f – Frequency – Hz
IO2 – 3.3-V Output Current – A
Figure 27.
Figure 28.
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TYPICAL CHARACTERISTICS (continued)
3.3-V BODE-PLOT – GAIN AND PHASE
vs
FREQUENCY
80
5.0-V SWITCH-OVER WAVEFORMS
180
135
40
90
20
45
Gain
0
VREG5 (100 mV/div)
Phase – °
Gain – dB
Phase
60
0
–20
VO1 (100 mV/div)
45
–90
–40
VO= 3.3 V
VI = 12 V
IO = 8 A
–60
–80
100
1k
–135
10 k
2 ms/div
–180
1M
100 k
f – Frequency – Hz
Figure 29.
Figure 30.
CURRENT MONITOR VOLTAGE
vs
OUTPUT CURRENT
3.0
VIMONx – Output Voltage – V
2.5
2.0
VIMON1
1.5
1.0
VIMON2
0.5
0
0
2
4
6
8
10
12
IOUTx – Output Current – A
Figure 31.
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TYPICAL CHARACTERISTICS
5.0-V START-UP WAVEFORMS
3.3-V START-UP WAVEFORMS
EN2 (5V/div)
EN1 (5V/div)
Vout1 (2V/div)
Vout2 (2V/div)
PGOOD2 (5V/div)
1msec/div
PGOOD1 (5V/div)
1msec/div
Figure 32.
Figure 33.
5.0-V SOFT-STOP WAVEFORMS
3.3-V SOFT-STOP WAVEFORMS
EN2 (5V/div)
EN1 (5V/div)
Vout1 (2V/div)
Vout2 (2V/div)
PGOOD2 (5V/div)
PGOOD1 (5V/div)
1msec/div
1msec/div
Figure 34.
Figure 35.
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TYPICAL CHARACTERISTICS (continued)
5.0-V LOAD TRANSIENT RESPONSE
3.3-V LOAD TRANSIENT RESPONSE
VI =12V, Auto-skip
VI=12V, Auto-skip
VO1 (100mV/div)
VO2 (100mV/div)
SW1 (10V/div)
IO1 (5A/div)
100
100 mms/div
s/div
SW2 (10V/div)
Figure 36.
18
IO2 (5A/div)
100
100 mms/div
s/div
Figure 37.
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DETAILED DESCRIPTION
ENABLE AND SOFT START
When EN is Low, the TPS51222 is in the shutdown state. Only the 3.3-V LDO stays alive, and consumes 7 µA
(typically). When EN becomes High, the TPS51222 is in the standby state. The 2-V reference and the 5-V LDO
become enabled, and consume about 80 µA with no load condition, and are ready to turn on SMPS channels.
Each SMPS channel is turned on when ENx becomes High. After ENx is set to high, the TPS51222 begins the
softstart sequence, and ramps up the output voltage from zero to the target voltage in 0.96 ms. However, if a
slower soft-start is required, an external capacitor can be tied from the ENx pin to GND. In this case, the
TPS51222 charges the external capacitor with the integrated 2-µA current source. An approximate external
soft-start time would be tEX-SS = CEX / IEN12, which means the time from ENx = 1 V to ENx = 2 V. The recommend
capacitance is more than 2.2 nF.
1) Internal
Soft-start
EN1
Vout1
200ms
960ms
EN11V
2) External
Soft-start
EN1
External
Soft-start
time
Vout1
Figure 38. Enable and Soft-start Timing
Table 1. Enable Logic States
EN
EN1
EN2
VREG3
GND
Don’t Care
Don’t Care
ON
Hi
Lo
Lo
ON
Hi
Hi
Lo
ON
Hi
Lo
Hi
Hi
Hi
Hi
VREF2
VREG5
CH1
CH2
Off
Off
Off
Off
ON
ON
Off
Off
ON
ON
ON
Off
ON
ON
ON
Off
ON
ON
ON
ON
ON
ON
3.3-V, 10-mA LDO (VREG3)
A 3.3-V, 10-mA, linear regulator is integrated in the TPS51222. This LDO services some of the analog circuit in
the device and provides a handy standby supply for 3.3-V Always On voltage in the notebook system. Apply a
2.2-µF (at least 1-µF), high quality X5R or X7R ceramic capacitor from VREG3 to (signal) GND in adjacent to the
device.
2-V, 100-µA Sink/Source Reference (VREF2)
This voltage is used for the reference of the loop compensation network. Apply a 0.22-µF (at least 0.1-µF),
high-quality X5R or X7R ceramic capacitor from VREF2 to (signal) GND in adjacent to the device.
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5.0-V, 100-mA LDO (VREG5)
A 5.0-V, 100-mA, linear regulator is integrated in the TPS51222. This LDO services the main analog supply rail
and provides the current for gate drivers until switch-over function becomes enable. Apply a 10-µF (at least
4.7-µF), high-quality X5R or X7R ceramic capacitor from VREG5 to (power) GND in adjacent to the device.
VREG5 SWITCHOVER
When EN1 is high, PGOOD1 indicates GOOD and a voltage of more than 4.8 V is applied to V5SW, the internal
5V-LDO is shut off and the VREG5 is shorted to V5SW by an internal MOSFET after an 7.7-ms delay. When the
V5SW voltage becomes lower than 4.65 V, EN1 becomes low, or PGOOD1 indicates BAD, the internal switch is
turned off, and the internal 5V-LDO resumes immediately.
BASIC PWM OPERATIONS
The main control loop of the SMPS is designed as a fixed frequency, peak current mode, pulse width modulation
(PWM) controller. It achieves stable operation with any type of output capacitors, including low ESR capacitor(s)
such as ceramic or specialty polymer capacitors.
The current mode scheme uses the output voltage information and the inductor current information to regulate
the output voltage. The output voltage information is sensed by VFBx pin. The signal is compared with the
internal 1-V reference and the voltage difference is amplified by a transconductance amplifier (VFB-AMP). The
inductor current information is sensed by CSPx and CSNx pins. The voltage difference is amplified by another
transconductance amplifier (CS-AMP). The output of the VFB-AMP indicates the target peak inductor current. If
the output voltage decreases, the TPS51222 increases the target inductor current to raise the output voltage.
Alternatively, if the output voltage rises, the TPS51222 decreases the target inductor current to reduce the output
voltage.
At the beginning of each clock cycle, the high-side MOSFET is turned on, or becomes ‘ON’ state. The high-side
MOSFET is turned off, or becomes OFF state, after the inductor current becomes the target value which is
determined by the combination value of the output of the VFB-AMP and a ramp compensation signal. The ramp
compensation signal is used to prevent sub-harmonic oscillation of the inductor current control loop. The
high-side MOSFET is turned on again at the next clock cycle. By repeating the operation in this manner, the
controller regulates the output voltage. The synchronous low-side or the rectifying MOSFET is turned on each
OFF state to keep the conduction loss minimum.
20
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PWM FREQUENCY CONTROL
The TPS51222 has a fixed frequency control scheme with 180° phase shift. The switching frequency can be
determined by an external resistor which is connected between RF pin and GND, and can be calculated using
Equation 1.
1 × 105
fsw éëkHz ùû =
RF éëkΩ ùû
(1)
TPS51222 can also synchronize to more than 2.5 V amplitude external clock by applying the signal to the RF
pin. The set timing of channel 1 initiates at the raising edge (1.3 V typ) of the clock and channel 2 initiates at the
falling edge (1.1 V typ). Therefore, the 50% duty signal makes both channels 180° phase shift.
1000
900
fSW - Frequency - kHz
800
700
600
500
400
300
200
100
0
100
200
300
400
500
RF - Resistance - kW
Figure 39. Switching Frequency vs RF
LIGHT LOAD OPERATION
The TPS51222 automatically reduces switching frequency at light load conditions to maintain high efficiency if
Auto Skip or Out-of-Audio™ mode is selected by SKIPSELx. This reduction of frequency is achieved by skipping
pulses. As the output current decreases from heavy load condition, the inductor current is also reduced and
eventually comes to the point that its peak reaches a predetermined current, ILL(PEAK), which indicates the
boundary between heavy-load condditions and light-load conditions. Once the top MOSFET is turned on, the
TPS51222 does not allow it to be turned off until it reaches ILL(PEAK). This eventually causes an overvoltage
condition to the output and pulse skipping. From the next pulse after zero-crossing is detected, ILL(PEAK) is limited
by the ramp-down signal ILL(PEAK)RAMP, which starts from 25% of the overcurrent limit setting (IOCL(PEAK): (see the
Current Protection section) toward 5% of IOCL(PEAK) over one switching cycle to prevent causing large ripple. The
transition load point to the light load operation ILL(DC) can be calculated in Equation 2.
I LL(DC) + I LL(PEAK) * 0.5 I IND(RIPPLE)
(2)
(V - VOUT ) × VOUT
1
IIND(RIPPLE) =
× IN
L × fSW
VIN
(3)
where
•
fSW is the PWM switching frequency which is determined by RF resistor setting or external clock
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ILL(PEAK)RAMP = (0.2 - 0.13 ´ tON ´ fSW )´ t ´ IOCL(PEAK )
(4)
Switching frequency versus output current in the light load condition is a function of L, f, VIN and VOUT, but it
decreases almost proportionally to the output current from the ILL(DC), as described in Equation 2; while
maintaining the switching synchronization with the clock. Due to the synchronization, the switching waveform in
boundary load condition (close to ILL(DC)) appears as a sub-harmonic oscillation; however, it is the intended
operation.
If SKIPSELx is tied to GND, the TPS51222 works on a constant frequency of fSW regardless its load current.
Inductor
Current
ILL(PEAK)
ILL(DC)
IIND(RIPPLE)
0
Time
ILL(peak) – Inductor Current Limit – A
Figure 40. Boundary Between Pulse Skipping and CCM
20% of IOCL
ILL(PEAK) Ramp Signal
ILL(PEAK) at
Light Load
7% of IOCL
tON
1/fSW
t – Time
Figure 41. Inductor Current Limit at Pulse Skipping
Table 2. Skip Mode Selection
SKIPSELx
GND
VREF2
VREG3
VREG5
OPERATING MODE
Continuous Conduction
Auto Skip
OOA Skip (maximum 7
skips, for
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