SLUS571 − SEPTEMBER 2003
FEATURES
D High Efficiency − No Current Sense Resistor
D
D
D
D
D
D
D
D
DESCRIPTION
The TPS5124 is dual independent high efficiency
synchronous step-down controller. It supports a
low-voltage/high-current power supply applica−
tions that use either a 5-V or 12-V bus voltage.
Since both controllers of the TPS5124 operate
180 degree out-of-phase, the input current ripple
is minimized resulting in a smaller input
capacitance and reduced power supply cost.
Required, RDS(on) Overcurrent Detection with
Temperature Compensation
Adjustable Output Voltage Down to 0.9 V
Voltage-Mode PWM Control: Maximum
500-kHz Operation
180° Out-of-Phase Control
Individual Standby and Soft-Start for Each
Channel − Easy Power Sequencing
Overvoltage and Undervoltage Protection
Built-In Boot-Strap Diode
Built-In 5-V Linear Regulator
Accurate ± 1% 0.85-V Reference
The current protection circuit detects the
drain-to-source voltage drop across the high-side
and low-side power MOSFET while it is
conducting. Also, the current protection circuit has
a temperature coefficient to compensate for the
RDS(on) variation of the MOSFET. This
resistor-less current protection and built-in boost
diode simplify the system design and reduces the
external parts count. Other features such as
undervoltage lockout, overvoltage, undervoltage,
and programmable short-circuit protection
promote system reliability.
APPLICATIONS
D Consumer Game Systems
D DSP Applications
D Digital Set-Top Box
D VGA and Sound Cards
VIN
VO1
1
INV1
TPS5124
LH1 30
29
2 FB1
OUT1_U
3 SS1
LL1
4 N/C
OUT1_D
5
CT
6 N/C
OUTGND1
VIN
VO2
26
VCC 24
23
VIN
TRIP2
9 STBY1
VREF5
10 STBY2
VLSD
11 SCP
27
TRIP1 25
7 GND
8 REF
VO1
28
OUTGND2
12 N/C
OUT2_D
13 SS2
LL2
14 FB2
OUT2_U
15 INV2
LH2
22
21
20
19
18
VO2
17
16
VIN
UDG−03123
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
! " #$ %! " &$'(# ! ) !%*
)$#!" # ! "&%## ! " &% !+% !% " %, " "! $ %!"
"! ) ) - !.* )$#! & #%""/ ) %" ! %#%"" (. #($)%
!%"!/ (( & %!% "*
Copyright 2003, Texas Instruments Incorporated
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1
SLUS571 − SEPTEMBER 2003
ABSOLUTE MAXIMUM RATINGS
−40°C ≤ TA ≤ 85°C, all voltage values are with respect to the network ground terminal unless otherwise noted. (1)
TPS5124
Input voltage range
Ouput voltage range
VCC, STBY1, STBY2, TRIP1, TRIP2
−0.3 to 16
LH1, LH2 wrt GND
−0.3 to 22
LH1, LH2 (wrt the corresponding LL terminal)
−0.3 to 6
SS1, SS2, CT, INV1, INV2, SCP, VLSD
−0.3 to 6
OUT1_U, OUT2_U
−1 to 22
OUT1_U, OUT2_U (wrt the corresponding LL terminal)
−0.3 to 6
LL1, LL2
−1 to 16
OUT1_D, OUT2_D, VREF5, FB1, FB2
−0.3 to 6
OUTGND1, OUTGND2
V
−0.3 to 0.3
REF
Output current range
UNIT
−0.3 to 3
VREF5
50
VREF
5
Operating free-air temperature range, TA
−40 to 85
Storage temperature range, Tstg
−55 to 150
Junction temperature range, TJ
−40
mA
°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
300
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those indicated under ”recommended operating conditions” is
not implied. Exposure to Absolute Maximum Rated conditions for extended periods may affect device reliability
RECOMMENDED OPERATING CONDITIONS
MIN
Supply voltage, VCC
Input voltage range
MAX
15
(when VLSD is connected to VCC)
4.5
5.5
INV1, INV2, CT, SS1, SS2, SCP, FB1, FB2, OUT1_D, OUT2_D, VLSD
−0.1
5.9
OUT1_U, OUT2_U, LH1, LH2
−0.1
21
TRIP1, TRIP2, LL1, LL2, STBY1, STBY2
−0.1
15
Operating frequency, fOSC
300
Operating free-air temperature range, TA
2
NOM
6.5
−40
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UNIT
V
500
kHz
85
°C
SLUS571 − SEPTEMBER 2003
ELECTRICAL CHARACTERISTICS
TJ = −40°C to 85°C, VCC = 12 V (unless otherwise noted)
TEST CONDITIONS
PARAMETER
MIN
TYP
MAX
UNIT
SUPPLY CURRENTS
ICC
ICCS
Supply current
VVREF5
Output voltage
TA = 25°C,
7.5 V ≤ VCC ≤ 15 V,
0 mA ≤ IO ≤ 10 mA
VLN5
VLD5
Line regulation
7.5 V ≤ VCC ≤ 15 V,
Load regulation
1 mA ≤ IO ≤ 10 mA
IOS
VTHH
Short-circuit output current
VREF5 = 0 V,
high-to-low
VIN standby current
5-V REGULATOR
VTHL
VHYS
UVLO threshold voltage
TA = 25°C,
VCT = VINV1=VINV2 = 0 V
VSTBY1 = VSTBY2 = 0 V
4.8
1.1
1.5
mA
0.1
10.0
µA
5.0
5.2
V
IO =10 mA
20
40
TA = 25°C
65
low-to-high
Hysteresis
mV
mA
3.6
4.2
V
3.5
4.1
V
30
150
mV
REFERENCE VOLTAGE
VREF
VREF(tol)
Reference voltage
VREF(ln)
VREF(ld)
Line regulation
IREF = 50 µA,
6.5 V ≤ VCC ≤ 15 V,
Load regulation
0.1 µA ≤ IREF ≤ 1 mA
Reference voltage tolerance
0.85
TA = 25°C
IREF = 50 µA
-0.5%
V
0.5%
0.03
3.00
0.15
5.00
mV
CONTROL
VIH
VIL
High-level input voltage
STBY1, STBY2
Low-level input voltage
STBY1, STBY2
2.2
0.3
V
OUTPUT VOLTAGE MONITOR
OVP comparator threshold voltage
0.90
0.95
1.00
UVP comparator threshold voltage
0.58
0.66
0.74
Overvoltage protection
−4
−8
−12
Undervoltage protection
−1
−1.7
−2.3
Timer latch current source
V
µA
A
OSCILLATOR
fOSC
Frequency
VOSC(h)
High-level output voltage
VOSC(l)
Low-level output voltage
CT = 47 pF,
TA = 25°C
DC
300
1.0
fOSC = 300 kHz
DC
1.1
kHz
1.2
1.14
0.4
fOSC = 300 kHz
0.5
0.6
V
0.46
ERROR AMPLIFIER
VIO
Input offset voltage
TA = 25°C
2
Open-loop voltage gain
50
Unity gain bandwidth
ISINK
ISRC
Output sink current
Output source current
mV
dB
2.5
VO = 2.5 V
VO = 2.5 V
10
2
4
−2
−4
MHz
mA
DUTY CONTROL
Maximum duty cycle
fOSC = 300 kHz,
V(INV1) = V(INV2) = 0 V
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80%
3
SLUS571 − SEPTEMBER 2003
ELECTRICAL CHARACTERISTICS(continued)
TJ = −40°C to 85°C, VCC = 12 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OUTPUT DRIVER
OUT_U sink current
V(OUTx_U) − V(LLx) = 3 V
V(LHx) − V(OUTx_U) = 3 V
OUT_U source current
OUT_D sink current
1.2
−1.2
V(OUTx_D) = 3 V
V(OUTx_D) = 2 V
OUT_D source current
A
1.5
−1.5
SOFT START
ISOFT
Soft-start current
CURRENT PROTECTION
ITRIP
TC
TRIP current
TRIP current temperature coefficient
TA = 25°C
TA = 25°C
AVAILABLE OPTIONS
TA
−2.3
−2.9
µA
11
13
15
µA
3400
ppm/°C
DISSIPATION RATING TABLE
PACKAGED DEVICES(1)
PLASTIC TSSOP (DBT)
−40°C to 85°C
TPS5124DBT
(1) The DBT package is available taped and reeled.
Add an R suffix to the device type (e.g.
TPS5124DBTR) to order quantities of 2,000
devices per reel.
PACKAGE
TA < 25°C
POWER
RATING
DERATING
FACTOR ABOVE
TA = 25°C
TA = 85°C
POWER
RATING
30-pin DBT
874 mW
7.0 mW/°C
454 mW
DBT PACKAGE
(TOP VIEW)
INV1
FB1
SS1
NC
CT
NC
GND
REF
STBY1
STBY2
SCP
NC
SS2
FB2
INV2
4
−1.3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
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LH1
OUT1_U
LL1
OUT1_D
OUTGND1
TRIP1
VCC
TRIP2
VREG5
VLSD
OUTGND2
OUT2_D
LL2
OUT2_U
LH2
SLUS571 − SEPTEMBER 2003
TERMINAL FUNCTIONS
TERMINAL
NAME
NO.
I/O
DESCRIPTION
CT
5
I/O
External capacitor from CT to GND adjusts frequency of the triangle oscillator.
FB1
2
O
Feedback output of SBRC−Channel 1 error amplifier.
FB2
14
O
Feedback output of SBRC−Channel 2 error amplifier.
GND
7
−
Signal GND.
INV1
1
I
Inverting inputs of Channel 1 error amplifier and OVP1/UVP1 comparator.
INV2
15
I
Inverting inputs of Channel 2 error amplifier and OVP2/UVP2 comparator.
LH1
30
I/O
Bootstrap capacitor connection for Channel 1 high-side gate driver.
LH2
16
I/O
Bootstrap capacitor connection for Channel 2 high-side gate driver.
LL1
28
I/O
CH1 high-side gate driving return. Connect this pin to the junction of the high-side and low-side MOSFETs for
floating drive configuration. This pin is also an input terminal for current comparator.
LL2
18
I/O
CH2 high-side gate driving return. Connect this pin to the junction of the high-side and low-side MOSFETs for
floating drive configuration. This pin is also an input terminal for current comparator.
NC
4,6,12
−
No connection.
OUT1_D
27
O
Gate drive output for Channel 1 low-side MOSFETs.
OUT2_D
19
O
Gate drive output for Channel 2 low-side MOSFETs.
OUT1_U
29
O
Gate drive output for Channel 1 high-side MOSFETs.
OUT2_U
17
O
Gate drive output for Channel 2 high-side MOSFETs.
OUTGND1
26
−
Ground for Channel 1 MOSFET drivers.
OUTGND2
20
−
Ground for Channel 2 MOSFET drivers.
REF
8
O
0.85-V reference voltage output. This 0.85-V reference voltage is used to set the output voltage and the reference for the overvoltage and undervoltage protections. This reference voltage is dropped down from the internal 5-V regulator.
SCP
11
I/O
Fault latch timer pin. An external capacitor connected between SCP and GND sets SCP enable time up.
SS1
3
I/O
Soft start control for Channel 1. Connect an external capacitor between this pin and GND to specify SOFTSTART time.
SS2
13
I/O
Soft start control for Channel 2. Connect an external capacitor between this pin and GND to specify SOFTSTART time.
STBY1
9
I
Standby control input for Channel 1. It can be switched into standby mode by grounding the STBY1 pin.
STBY2
10
I
Standby control input for Channel 2. It can be switched into standby mode by grounding the STBY2 pin.
TRIP1
25
I
External resistor connection for Channel 1 output current protection control.
TRIP2
23
I
External resistor connection for Channel 2 output current protection control.
VCC
24
I
Supply voltage input
VLSD
21
I
Supply voltage input for low side driver. Typically connected to VREF5 with R-C filter when VVCC is between
6.5V and 15V and connected to VCC with filter when VVCC is between 4.5 V and 5.5 V.
VREF5
22
O
5V linear regulator output. When VVCC is between 4.5V and 5.5V should be connected to VCC.
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5
SLUS571 − SEPTEMBER 2003
FUNCTIONAL BLOCK DIAGRAM
VLSD
SS1
3
Soft−Start 1
30 LH1
Delay
SFT1
29 OUT1_U
FB1 2
INV1
+
+
+
28 LL1
PWM
COMP
+
E/A
1
21 VLSD
27 OUT1_D
Delay
0.85 V
26 OUTGND1
CT
5
Current
Comparator
Oscillator
OVP1
STBY1
SFT1
25 TRIP1
UVLO
+
+
+
0.85 V+12%
OVP2
SFT2
+
STBY2
+
Current
Protection
Trigger
24 VCC
0.85 V+12%
SCP
+
11
Timer
23 TRIP2
UVP1
Current
Comparator
+
+
0.85 V−22%
20 OUTGND2
UVP2
Delay
Phase
Inverter
+
19 OUT2_D
18 LL2
+
FB2 14
PWM
COMP
17 OUT2_U
SFT2
7
16 LH2
+
E/A
INV2 15
GND
Delay
0.85 V−22%
+
+
+
0.85 V
VLSD
UVLO
STBY1
22 VREF5
+
STBY2
SS2
13
Soft−Start 2
VCC
STBY1
UVLO
+
Comparator
9
STBY2
VREF
10
REF
5 VREG
0.85 V
8
UDG−03105
6
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SLUS571 − SEPTEMBER 2003
FUNCTIONAL DESCRIPTION
INPUT VOLTAGE RANGE
TPS5124 supports two input voltage ranges. When VVCC is between 6.5 V and 15 V, VLSD is connected to
VREF5 with R-C filter (see Figure 1). When VVCC is between 4.5 V and 5.5 V, VLSD is connected to VCC with
R-C filter and VREF5 is connected to VCC. (see Figure2).
REFERENCE VOLTAGE (0.85 V)
This 0.85-V reference voltage is used to set the output voltage and the reference for the overvoltage and
undervoltage protections. This reference voltage is dropped down from the internal 5V regulator.
PWM OPERATION
TPS5124 includes dual synchronous buck regulator controllers (SBRC) that operate 180_ out of phase and
same frequency. Both channels have individual standby and softstart controller.
5-V REGULATOR
An internal linear voltage regulator is used for the reference voltage and power supply of internal circuit. When
this regulator is connected to the VLSD pin, it is used for powering the low-side driver and powering the high-side
driver through the built-in bootstrap diode or external bootstrap circuit. It is active if either STBY1 or STBY2 is
HIGH and has a tolerance of 4 %.
ERROR AMPLIFIER
Each channel has its own error amplifier to regulate the output voltage of the synchronous buck converter. The
unity gain bandwidth is 2.5 MHz. This decreases the amplifier delay during fast load transients and contributes
to a fast transient response.
LOW-SIDE DRIVER
The low-side driver is designed to drive high current and low RDS(on) N-channel MOSFET(s). The maximum
drive voltage is 5 V from the VLSD pin. The current rating of the driver is typically 1.5 A at source and sink.
HIGH-SIDE DRIVER
The high-side driver is designed to drive high current and low RDS(on) N−channel MOSFET(s). The current rating
of the driver is 1.2 A (typ.) at source and sink. When configured as a floating driver a bias voltage is delivered
from the VSLD pin through built-in bootstrap diode or external bootstrap circuit. When the MOSFET needs high
gate threshold voltage, it is useful to add the external schottky diodes which provide a higher voltage for the gate
drive than using the built-in diodes. The instantaneous drive current is supplied by the flying capacitor between
the LH and LL pins since a bias power supply does not usually have low impedance. The maximum voltage
between the OUTx_U and LLx pins is about 5.5 V when the VSLD pin is connected to the VREF5 pin. The
maximum voltage that can be applied between the LH and OUTGND pins is 22 V.
DEAD-TIME
The internally defined dead-time prevents shoot-through current flowing through the main power MOSFETs
during switching transitions.
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7
SLUS571 − SEPTEMBER 2003
FUNCTIONAL DESCRIPTION
OVER CURRENT PROTECTION (OCP)
Over current protection (OCP) is achieved by comparing the drain-to-source voltage of the high-side and
low-side MOSFET to a set-point voltage, which is defined by both the internal current source, ITRIP, and the
external resistor connected between the VCC and TRIP pins. ITRIP has a typical value of 13 µA at 25°C. When
the low-side MOSFET’s drain-to-source voltage exceeds the set-point voltage during low-side conduction, the
high-side current comparator becomes active, and the low-side on pulse is extended until this voltage comes
back below the threshold. If the set-point voltage is exceeded during high-side conduction in the following cycle,
the current limit circuit terminates the high-side driver pulse. Together this action has the effect of decreasing
the output voltage until the under voltage protection circuit is activated to latch both the high-side and low-side
drivers OFF. In the TPS5124, trip current (ITRIP) has a temperature coefficient of 3400 ppm/_C in order to
compensate for temperature drift of the MOSFET on-resistance.
OVER VOLTAGE PROTECTION (OVP)
For over voltage protection (OVP), the TPS5124 monitors the INV pin voltage. When the INV pin voltage is
higher than 0.95 V (0.85 V +12%), the OVP comparator output goes low and the SCP timer starts to charge an
external capacitor connected to SCP pin. After a set time, the SCP circuit latches the high-side MOSFET driver
to OFF state and low-side MOSFET drivers to ON state. The timer source current for the OVP latch is 8 µA(typ.),
and the time−up voltage is 1.185 V (typ.). The OVP timer is designed to be five times faster than the under
voltage protection timer described below.
UNDER VOLTAGE PROTECTION (UVP)
For under voltage protection (UVP), the TPS5124 monitors the INV pin voltage. When the INV pin voltage is
lower than 0.66 V (0.85 V – 22%), the UVP comparator output goes low, and the SCP timer starts to charge the
external capacitor connected to SCP pin. Also, when the current comparator triggers the OCP, the UVP
comparator detects the under voltage output and starts the SCP capacitor charge, too. After a set time, the SCP
circuit latches both of the MOSFET drivers to the OFF state. The timer latch source current for UVP is 1.6 µA
(typ.), and the time-up voltage is also 1.185 V (typ.).
SCP (TIMER)
When an OVP or UVP comparator output goes low, the SCP circuit starts to charge the SCP capacitor. If the
SCP pin voltage goes beyond a constant level, the TPS5124 latches the MOSFET drivers. At this time, the state
of MOSFET is different depending on the OVP alert and the UVP alert. The enable time used to latch the
MOSFET drivers is decided by the value of the SCP capacitor. The charging constant current value depends
on whether it is an OVP alert or a UVP alert as shown in the following equation:
I SCP(ovp) + I SCP(uvp)
5
(1)
SOFT START
Soft-start ramp up of the SBRC is controlled by the SSx pin voltage. After the STBY pin is raised to a HIGH level,
an internal current source charges up an external capacitor connected between the SSx and GND pins. The
soft-start time is easily calculated by the supply current and the capacitance value.
8
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SLUS571 − SEPTEMBER 2003
FUNCTIONAL DESCRIPTION
STANDBY
The SBRC controller can be switched into standby mode separately by grounding STBY pin.
Table 1. Standby Logic
STBY1
STBY2
SBRC (CH1)
SBRC (CH2)
5-V REGULATOR
L
L
DISABLED
DISABLED
DISABLED
L
H
DISABLED
ENABLED
ENABLED
H
L
ENABLED
DISABLED
ENABLED
H
H
ENABLED
ENABLED
ENABLED
UNDERVOLTAGE LOCK OUT (UVLO)
For undervoltage lock out (UVLO), the TPS5124 monitors VREF5 voltage. When the VREF5 voltage decreases
below about 4.1 V, the output stages of both SBRC are turned off. This state is not latched and the operation
recovers immediately after the input voltage becomes higher than about 4.2 V again. The typical hysteresis
voltage is 40 mV.
PHASE INVERTER
The SBRC (CH2) of the TPS5124 operates in the same phase as the internal triangular oscillator output while
the SBRC (CH1) operates 180_ out of phase. When the SBRC (CH1) and the SBRC (CH2) share the same input
power supply, the TPS5124 reduces input current ripple and enables the input capacitor value smaller.
OSCILLATOR
TPS5124 has a triangle oscillator generator internal to the device. The oscillation frequency is set by the size
of the capacitor connected to the CT pin.
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9
VIN
10
GND
R27
GND
C01
R26
R17
C29
R16
C19
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R25
C28
C21
C04
C03
C02
C11
C18
R15
R23
Figure 1. Simplified Application Schematic (VIN = 12 V[typ])
R24
C27
1 INV1
2 FB1
3 SS1
4 NC
5 CT
6 NC
7 GND
8 REF
9 STBY1
10 STBY2
11 SCP
12 NC
13 SS2
14 FB2
15 INV2
C17
R13
TPS5124
R14
25
24
23
22
21
20
19
18
17
16
30
29
28
27
26
VIN
LH2
LH1
OUT1_U
LL1
OUT1_D
OUTGND1
TRIP1
VCC
TRIP2
VREF5
VLSD
OUTGND2
OUT2_D
LL2
OUT2_U
C6
GND
C12
R1
C22
R21
R11
C23
C13
GND
C05
Q21
Q22
R12
Q12
Q11
D21
R22
C14
C24
D11
L21
L11
C15
C25
C26
C16
GND
GND
VO2
VO1
SLUS571 − SEPTEMBER 2003
APPLICATION INFORMATION
VIN
GND
R27
GND
C01
R26
R17
C29
R16
C19
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R25
C28
C21
C04
C03
C02
C11
C18
R15
R23
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R24
C27
INV1
FB1
SS1
NC
CT
NC
GND
REF
STBY1
STBY2
SCP
NC
SS2
FB2
INV2
C17
R13
C6
GND
C12
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
VIN
LH2
LH1
OUT1_U
LL1
OUT1_D
OUTGND1
TRIP1
VCC
TRIP2
VREF5
VLSD
OUTGND2
OUT2_D
LL2
OUT2_U
TPS5124
R14
R1
C22
R21
R11
C23
C13
GND
C05
Q21
Q22
R12
Q12
Q11
D21
R22
C14
C24
D11
L21
L11
C15
C25
C26
C16
GND
GND
VO2
VO1
SLUS571 − SEPTEMBER 2003
APPLICATION INFORMATION
Figure 2. Simplified Application Schematic (VIN = 5 V[typ])
11
SLUS571 − SEPTEMBER 2003
APPLICATION INFORMATION
SHUTDOWN SUPPLY CURRENT
vs
JUNCTION TEMPERATURE
SUPPLY CURRENT
vs
JUNCTION TEMPERATURE
3.0
1000
VINV = VCT = 0 V
VVCC = 12 V
VINV = VCT = 0 V
VSTBY1 = VSTBY2 = 0 V
VVCC = 12 V
ICC − Supply Current − nA
ICC − Supply Current − mA
800
2.5
2.0
1.5
600
400
200
1.0
−50
0
50
100
0
−50
150
TJ − Junction Temperature − °C
150
Figure 4
Figure 3
TRIP CURRENT
vs
JUNCTION TEMPERATURE
SCP CURRENT
vs
JUNCTION TEMPERATURE
−10
25
VVCC = 12 V
VTRIPx = VVCC − 0.1 V
VVCC = 12 V
−8
20
ITRIP − Trip Current − µA
OVP
ISCP − SCP Current − µA
0
50
100
TJ − Junction Temperature − °C
−6
−4
−2
15
10
5
UVP
0
−50
0
50
100
150
TJ − Junction Temperature − °C
0
50
100
TJ − Junction Temperature − °C
Figure 6
Figure 5
12
0
−50
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150
SLUS571 − SEPTEMBER 2003
APPLICATION INFORMATION
UVP THRESHOLD VOLTAGE
vs
JUNCTION TEMPERATURE
OVP THRESHOLD VOLTAGE
vs
JUNCTION TEMPERATURE
1.0
VUVP − UVP Threshold Voltage − V
VOVP − OVP Threshold Voltage − V
1.0
0.8
0.6
0.4
0.2
VVCC = 12 V
0
−50
0
50
100
VVCC = 12 V
0.8
0.6
0.4
0.2
0
−50
150
0
TJ − Junction Temperature − °C
100
150
Figure 8
Figure 7
MAXIMUM DUTY CYCLE
vs
JUNCTION TEMPERATURE
OSCILLATOR FREQUENCY
vs
TIMING CAPACITANCE
100
1000
VVCC = 12 V
TJ = 25°C
VVCC = 12 V
90
Maximum Duty Cycle − %
fOSC − Oscillator Frequency − kHz
50
TJ − Junction Temperature − °C
100
80
70
60
10
0
50
100
150
200
250
300
350
CCT − TIMING CAPACITANCE − pF
50
−50
0
50
100
150
TJ − Junction Temperature − °C
Figure 9
Figure 10
www.ti.com
13
SLUS571 − SEPTEMBER 2003
APPLICATION INFORMATION
SOFT-START TIME
vs
SOFT-START CAPACITANCE
SCP DELAY TIME
vs
SCP CAPACITANCE
100 k
100 k
TJ = 25°C
VVCC = 12 V
10 k
10 k
tSS − Soft-Start Tmie − µs
tDELAY − SCP Delay Time − µs
TJ = 25°C
VVCC = 12 V
UVP
1000
1000
100
OVP
10
10
1
10
1
100
1000
10 k
100 k
10
100
1000
10 k
CSSx − Soft-Start Capacitance − pF
CSCP − SCP Capacitance − pF
Figure 12
Figure 11
14
100
www.ti.com
100 k
PACKAGE OPTION ADDENDUM
www.ti.com
13-Jul-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
TPS5124DBT
ACTIVE
TSSOP
DBT
30
60
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
PS5124
Samples
TPS5124DBTR
ACTIVE
TSSOP
DBT
30
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
PS5124
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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