TPS68000
(6,4 mm x 7,8 mm)
www.ti.com
SLVS524A – OCTOBER 2005 – REVISED FEBRUARY 2006
HIGHLY EFFICIENT PHASE SHIFT FULL BRIDGE CCFL CONTROLLER
Check for Samples: TPS68000
FEATURES
1
•
•
2
•
•
•
•
•
•
•
•
•
•
DESCRIPTION
8-V to 30-V Input Voltage Range
Full Bridge Topology With Integrated Gate
Drives for 4 NMOS Switches
Synchronizable Constant Frequency
Operation
Programmable Phase Delays of Operating
Frequency for Master-Slave Operation
Lamp Voltage and Lamp Current Regulation
Analog and Burst Dimming
Configurable Distributed Burst Dimming in
Multiple Controller Applications
Programmable Voltage Regulation Timeout for
Startup and Fault Conditions
Open-Lamp and Short-Circuit Protection
Internal Over-Temperature Protection
Undervoltage Lockout
30-pin TSSOP Package
The TPS68000 device provides a power supply
controller solution for CCFL backlight applications in a
large variety of applications. The wide input voltage
range of 8 V to 30 V makes it suitable to be powered
directly from regulated 12-V or 24-V rails, or any
other source with output voltages in this range. When
using a 10% accurate regulated 5-V rail, it also can
be used in notebook computers or other portable
battery-powered equipment having lower minimum
supply voltages. The controller is capable of driving
the gates of all 4 NMOS switches directly without the
need for any additional circuitry, like dedicated gate
drivers or gate-drive transformers. The wide input
voltage range also makes it easy to design CCFL
converters with higher input voltages like 120 V or
400 V available at the output of a power factor
correction unit. The TPS68000 also supports CCFL
converter circuits driving multi-lamp applications,
either by using higher power-rated switches and
transformers,
or
using
several
TPS68000s
synchronized. When synchronized, they can be
operated either at the same frequency and phase, or
phase shifted to minimize RMS input current. Already
implemented smart dimming features, such as
support of distributed dimming, also help to optimize
the performance of multi-controller applications.
(Continued on next page)
APPLICATIONS
•
•
CCFL Backlight Power Supplies for Desktop
Monitors and LCD TVs
CCFL Backlight Power Supplies for Notebook
Computers
C10
TPS68000
Supply Voltage
8V .. 30V
VCC
C1
VLOGIC
GA
SA
R2
Error Output
Synchronization
Synchronization Phase Shift
Operating Frequency
FAULT
0V
Burst Duty Cycle
(Burst Dimming Input)
C5
GC
SC
EN
STC
GB
GD
ABR
2V
0V
BBR
C6
Burst Frequency
Direct Burst Dimming Input
(Frequency + Duty Cycle)
BF
QC
3
C12
C14
C4
T1
QB
C2
V5
3.3 V
0V
QA
C
V5C
PH
SET
R1
Device Enable
Lamp current
(Analog Dimming Input)
SYNC
2.0 V
V5A
OCP
CSEN
CAO
QD
C13
R3
R4
C8
CA−
VSEN
BC
C7
VREF
GND
VAO
C9
VA−
PGND
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Distributed Dimming is a registered trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2005–2006, Texas Instruments Incorporated
TPS68000
SLVS524A – OCTOBER 2005 – REVISED FEBRUARY 2006
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
DESCRIPTION (CONTINUED)
To start the lamp, an automatic strike control is implemented. It smoothly increases the lamp voltage by
sweeping the operating frequency across the self resonance frequency of the transformer-series capacitor
resonant circuit. During this time the maximum lamp voltage is limited and regulated by a voltage control loop
until the lamp current increases to a value allowing the current control loop to take over control. The lamp current
is regulated over a wide current range. To set the lamp brightness, analog and PWM dimming circuits are
implemented. Analog and PWM dimming can be used independent of each other to control lamp brightness over
a wide range.
To protect the circuit during fault conditions, for example broken, disconnected, or shorted lamps, overvoltage
protection and overcurrent protection circuits are implemented. To protect the TPS68000 from overheating, an
internal temperature sensor is implemented that triggers controller turn-off at an excessive device temperature.
The device is packaged in a 30-pin TSSOP package measuring 6,4 mm x 7,8 mm (DBT).
AVAILABLE DEVICE OPTIONS
(1)
TA
PACKAGE
PART NUMBER (1)
–40°C to 85°C
30-Pin TSSOP
TPS68000DBT
The DBT package is available taped and reeled. Add R suffix to device type (e.g., TPS68000DBTR) to order quantities of 2000 devices
per reel.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
(1)
TPS68000
Input voltage range on VCC, EN, FAULT
–0.3 V to 33 V
Input voltage range on SYNC, SET, PH, STC, ABR, BBR, BF, BC, VREF, VA-, VAO, CA-, CAO
–0.3 V to 6 V
Input voltage range on VSEN, CSEN, OCP
–6 V to 6 V
Input voltage range on GD, GB, V5
–0.3 V to 6 V
maximum differential voltage between GA, V5A and SA
6V
maximum differential voltage between GC, V5C and SC
6V
maximum differential voltage between SA and PGND
35 V
maximum differential voltage between SC and PGND
35 V
Operating virtual junction temperature range, TJ
–40°C to 150°C
Storage temperature range Tstg
–65°C to 150°C
(1)
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated uner "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
DISSIPATION RATINGS
PACKAGE
THERMAL RESISTANCE
θJA
POWER RATING
TA ≤ 25°C
DERATING FACTOR
ABOVE TA = 25°C
POWER RATING
TA ≤ 70°C
POWER RATING
TA ≤ 85°C
DBT
63.9°C/W
1565 mW
16 mW/°C
860 mW
626 mW
RECOMMENDED OPERATING CONDITIONS
MIN
NOM
MAX
UNIT
VI
Supply voltage at VCC
8.0
30
V
TA
Operating free air temperature range
–40
85
°C
TJ
Operating virtual junction temperature range
–40
125
°C
2
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SLVS524A – OCTOBER 2005 – REVISED FEBRUARY 2006
ELECTRICAL CHARACTERISTICS
over recommended free-air temperature range and over recommended input voltage range (typical at an ambient temperature
range of 25°C) (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
4.5
5
5.5
V
25
mA
4.1
4.3
V
MAIN CONTROL
V5
Internal control supply regulator
IOUT-V5< 25 mA
IOUT-V5
Control supply output current
including internal current
consumption
VUVLO
Under voltage lockout threshold at V5
Voltage at V5 decreasing
4.0
VOL
FAULT output low voltage
IFAULT = 500 µA
0.2
0.4
V
Vlkg
FAULT output leakage current
VFAULT= 5 V
0.1
1
µA
VIL
EN input low voltage
0.4
V
VIH
EN input high voltage
0.1
µA
1.4
V
EN input current
VCC = 24 V
ISTC
STC source current
during strike
6
µA
ISTC
STC source current
during wait
2
µA
STC source and sink current
normal operation, VSTC =
1.25 V
10
µA
140
°C
ISTC
0.05
Overtemperature protection
Overtemperature hysteresis
20
°C
Quiescent current into VCC
VCC = 12 V, V5 = 5.5 V
30
50
µA
Quiescent current into VCC
VCC = V5 = 5.5 V
25
40
µA
Quiescent current into V5
VCC = V5 = 5.5 V
1000
1500
µA
Shutdown current into VCC
VCC = V5 = 5.5 V, EN = 0V
1
2
µA
Shutdown current into V5
VCC = V5 = 5.5 V, EN = 0V
1
2
µA
Shutdown current into VCC
VCC = 12 V, EN = 0V
2.5
5
µA
VREF
Reference Voltage
IOUT-VREF < 5 mA
3.3
3.33
IOUT-VREF
Reference output current
3.27
5
V
mA
GATE DRIVE
Ω
High side drive sink resistance
ID = 0.05 A
1.2
2.0
High side drive source resistance
ID = 0.05 A
1.5
2.5
Ω
High side drive rise time
CG = 4.7 nF, SA = SC = 0 V,
V5A = V5C = 5 V
35
50
ns
High side drive fall time
CG = 4.7 nF
15
25
ns
Time delay between high side off and
low side on
CG = 4.7 nF
100
ns
Time delay between low side off and
high side on
CG = 4.7 nF
100
ns
Low side drive sink resistance
ID = 0.05 A
1.2
2.0
Low side drive source resistance
ID = 0.05 A
1.5
2.5
Ω
Low side drive rise time
CG = 4.7 nF, V5 = 5 V
35
50
ns
Low side drive fall time
CG = 4.7 nF
15
25
ns
30
100
kHz
0.5 x f
2xf
Ω
MAIN OSCILLATOR
f
Oscillator frequency programming
range
fSYNC
Frequency capture range for
synchronization
VIL
SYNC low voltage
VIH
SYNC high voltage
0.4
1.4
ISYNC
SYNC input current
VPH ≤ V5 - 1.3 V, VSYNC = 3.3
V
ISYNC
SYNC drive current
VSYNC ≥ 1.4 V, VPH = 5 V
1000
V
0.5
1.5
µA
1250
1500
µA
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3
TPS68000
SLVS524A – OCTOBER 2005 – REVISED FEBRUARY 2006
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ELECTRICAL CHARACTERISTICS (continued)
over recommended free-air temperature range and over recommended input voltage range (typical at an ambient temperature
range of 25°C) (unless otherwise noted)
PARAMETER
ISYNC
SYNC sink current
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VSYNC ≤ 0.4 V, VPH = 5 V
1000
1250
1500
µA
Minimum pulse width for
synchronization
VSET
100
SET output voltage
ns
1.25
Phase shift of the main oscillator clock
VPH = 0.1 V .. 1.9 V
IPH
PH input current
VPH = 2.0 V
VPH
Threshold for programming device as
main oscillator frequency master
V
90
0.1
V5 – 1.3
V
° / VPH
1
µA
V5 – 0.7 V
V
VOLTAGE AND CURRENT CONTROL
RCSEN
Current sense input impedance
VCSEN = 3.3 V
35
kΩ
RCSEN
Current sense input impedance
VCSEN = –3.3 V
25
kΩ
RVSEN
Voltage sense input impedance
VVSEN = 3.3 V
25
kΩ
RVSEN
Voltage sense input impedance
VVSEN = –3.3 V
30
kΩ
ICAO, IVAO
Voltage and current amplifier output
source current
VCAO, VVAO = 2.5 V
55
µA
ICAO, IVAO
Voltage and current amplifier output
sink current
VCAO, VVAO = 2.5 V
VREFVREG
Voltage regulator reference voltage
VREFOVP
Overvoltage comparator threshold
VREFCREG
Current regulator reference voltage
IOCP
Overcurrent comparator input current
VOCP = 3.3V
0.1
IOCP
Overcurrent comparator input current
VOCP = –3.3V
50
µA
VREFOCP
Overcurrent comparator threshold
VREF
V
200
µA
(0.8 ×VREF) / π
V
VREF
V
VABR / π
V
1
µA
DIMMING
IABR
ABR input current
VABR = 3.3 V
VABR
ABR input voltage range for lamp
current programming
BC = V5
IBBR
BBR input current
VBBR = 2.0 V
0.1
Burst duty cycle
VBBR = 0 V .. 2 V
50
VBBR
BBR input voltage threshold for
selecting synchronized burst dimming
IBF
BF source current
fBurst
Internal burst frequency range
fBC
Frequency lock / capture range for
synchronized burst dimming
tr
Burst current pulse rise time
IBC
BC input current
VIL
BC input low voltage
VIH
BC input high voltage
4
0
V5 – 1.3
V
0.1
µA
3.3
V
1
V5 – 0.7 V
20
1000
1.5 x fBurst
400
0.1
1.4
VPH = 0 V .. 2 V, distributed
dimming selected
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V
µA
0.5 x
fBurst
VBC = 3.3V
µA
% / VBBR
10
minimum pulse width at BC
Phase shift of the dimming burst
compared to BC clock
0.01
Hz
µs
1
µA
0.4
V
V
100
ns
180
° / VPH
Copyright © 2005–2006, Texas Instruments Incorporated
Product Folder Links: TPS68000
TPS68000
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SLVS524A – OCTOBER 2005 – REVISED FEBRUARY 2006
PIN ASSIGNMENTS
DBT PACKAGE
(TOP VIEW)
SYNC
SET
STC
PH
BBR
BC
BF
ABR
VAO
VA−
VSEN
CA−
CAO
CSEN
OCP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
VREF
GND
SA
GA
V5A
GB
VCC
V5
PGND
GD
V5C
GC
SC
EN
FAULT
Terminal Functions
TERMINAL
NAME
NO.
I/O
DESCRIPTION
ABR
8
I
Analog brightness programming input. A DC voltage applied at that pin programs the lamp current
the current regulator regulates. 0 V means no current and 3.3 V means maximum current.
BBR
5
I
Burst brightness programming input. A DC voltage applied at that pin programs the duty cycle of the
burst pulses generated to dimm the brightness. 0 V means zero duty cycle and 2 V means
maximum duty cycle. Applying V5 (5 V) programs the device to operate in synchronized burst
dimming mode.
BC
6
I
Burst control. A PWM signal applied at that pin is directly used for burst dimming. Frequency and
duty cycle are used directly. This input has priority against the burst frequency programming with
BBR and BF
BF
7
I
Burst frequency programming. A capacitor at that pin programs the burst frequency.
CA-
12
I
Current amplifier negative input. This input is used to connect the compensation capacitor for
compensating the current loop.
CAO
13
O
Current amplifier output. This is the output for the current amplifier. It is used to connect the
compensation capacitor for the current loop.
CSEN
14
I
Current sense. Measuring input for the lamp current. The applied voltage (coming from a shunt
resistor) will be used for lamp current regulation. Sensed AC voltages can be applied directly. They
will be rectified internally.
EN
17
I
Enable input. Logic high enables the device.
FAULT
16
O
Error output, any detected malfunctioning of the application will be reported as error on this pin.
Error means the output is pulled low. The output is open drain to allow connecting multiple error
outputs of similar devices together.
GA
27
O
Gate drive output of switch A
GB
25
O
Gate drive output of switch B
GC
19
O
Gate drive output of switch C
GD
21
O
Gate drive output of switch D
GND
29
OCP
15
PGND
22
Analog ground pin. Reference ground for all control signals.
I
Over current protection. This input is used to monitor a voltage derived from a current sensor in any
part of the converter. This voltage is compared to an internal reference voltage. Exceeding the
internal reference voltage causes the device logic to turn the device off and report an error signal at
the fault pin.
Reference ground for the gate drivers and the gate drive supply.
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Terminal Functions (continued)
TERMINAL
NAME
NO.
I/O
DESCRIPTION
I
Phase delay programming input. A voltage between 0 V and 2 V applied to that pin programs the
phase delay of the operating frequency compared to the synchronizing frequency. Applying V5 (5.0
V) programs the device as a master regarding the main oscillator frequency (see SYNC). The
voltage applied to that pin is also used to determine the phase delay in a distributed dimming
configuration
PH
4
SA
28
Source connection of switch A
SC
18
Source connection of switch C
SET
2
I
Operating frequency programming input. A resistor connected to this pin programs the internal
operating frequency.
STC
3
I
Startup capacitor. A capacitor connected to that pin determines the the time the device waits in
voltage regulation for the lamp to strike.
SYNC
1
I/O
Synchronization input or operating frequency output. If the device is configured as master (see PH)
the pin is used to provide the synchronization frequency for the slaves. Otherwise the device works
as slave and uses the applied frequency at that pin for synchronizing the operating frequency.
V5
23
I/O
Input/Output of the internal 5 V regulator for gate drive supply and control supply. A capacitor must
be connected to that pin to decouple switching noise caused by the gate drivers.
V5A
26
O
Supply input for the gate driver of the high-side switch A. A capacitor must be connected to that pin
to supply the gate driver during switching (bootstrap).
V5C
20
O
Supply input for the gate driver of the high side switch C. A capacitor must be connected to that pin
to supply the gate driver during switching (bootstrap).
VA-
10
I
Voltage amplifier negative input. This input is used to connect the compensation capacitor for
compensating the voltage loop.
VAO
9
O
Voltage amplifier output. This is the output for the voltage amplifier. It is used to connect the
compensation capacitor for the voltage loop.
VCC
24
I
Device supply voltage input. VCC must be connected to V5 in case the device is powered directly
from a regulated 5 V rail.
VREF
30
O
Voltage reference. Output of the internal 3.3 V reference for use with all the analog control inputs.
VSEN
11
I
Voltage sense. Measuring input for the lamp voltage. This voltage is used for lamp voltage
regulation (open lamp regulation) and overvoltage protection. Sensed AC voltages can be applied
directly. They are rectified internally.
6
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SLVS524A – OCTOBER 2005 – REVISED FEBRUARY 2006
FUNCTIONAL BLOCK DIAGRAM (TPS68000)
V5A
GA
SA
V5
VCC
V5
Control Supply
GB
OVP
Gate
Control
Main Control
V5C
OCP
FAULT
GC
SC
V5
V5
GD
PGND
OCP
OCP
SYNC
VREF
SET
Oscillator
VREF_OCP
Phase Shift
Control
PH
CAO
CA−
EN
Startup
and Strike
Control
STC
Rectifier
CSEN
VAO
VA−
ABR
Analog
and
Burst
Dimming
BBR
BF
Rectifier
VREF_VREG
BC
OVP
VREF
VSEN
OVP
VREF_OVP
VREF
GND
PARAMETER MEASUREMENT INFORMATION
C10
TPS68000
Supply Voltage
8V .. 30V
VCC
C1
VLOGIC
GA
SA
R2
Error Output
Synchronization
Synchronization Phase Shift
Operating Frequency
FAULT
0V
Burst Duty Cycle
(Burst Dimming Input)
C5
GC
SC
EN
STC
GB
GD
ABR
2V
0V
BBR
C6
Burst Frequency
Direct Burst Dimming Input
(Frequency + Duty Cycle)
BF
QC
3
C12
C14
C4
T1
QB
C2
V5
3.3 V
0V
QA
C
V5C
PH
SET
R1
Device Enable
Lamp current
(Analog Dimming Input)
SYNC
2.0 V
V5A
OCP
CSEN
CAO
QD
C13
R3
R4
C8
CA−
VSEN
BC
C7
VREF
GND
VAO
C9
VA−
PGND
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TYPICAL CHARACTERISTICS
Table 1. Table of Graphs
Output voltage at V5
Output voltage at VREF
Operating frequency
Phase shift of operating frequency
Burst dimming duty cycle
Burst dimming phase shift
FIGURE
1
2
3
4
5
6
7
8
9
10
11
12
vs output current at V5
vs output current at VREF
vs resistance at SET
vs voltage at PH
vs voltage at BBR
vs voltage at PH
Startup of V5 (VCC = 12 V)
Startup of V5 (VCC = 24 V)
Startup of VREF (VCC = V5 = 5V)
Lamp current and lamp voltage at startup (VCC = 12 V)
Lamp current and lamp voltage at startup (VCC = 24 V)
Lamp current softstart at burst dimming
Waveforms
OUTPUT VOLTAGE AT V5
vs
OUTPUT CURRENT AT V5
5.5
3.35
5.4
3.34
5.3
3.33
OUTPUT VOLTAGE AT VREF
vs
OUTPUT CURRENT at VREF
VO − Output Voltage at VREF − V
VO − Output Voltage at V5 − V
V5 = 5 V
5.2
5.1
VCC = 24 V
5.0
4.9
4.8
VCC = 12 V
4.7
4.6
3.32
3.31
3.30
3.29
3.28
3.27
3.26
4.5
3.25
0
10
20
30
40
50
60
70
80
0
IO − Output Current at V5 − mA
Figure 1.
8
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2
4
6
8
10
12
14
16
IO − Output Current at VREF − mA
Figure 2.
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OPERATING FREQUENCY
vs
RESISTANCE AT SET
PHASE SHIFT OF OPERATING FREQUENCY
vs
VOLTAGE AT PH
140
180
V5 = 5 V
Phase Shift of Operating Frequency − °
V5 = 5 V
Operating Frequency − kHz
120
100
80
60
40
20
0
60
160
140
120
100
80
60
40
20
0
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
90 120 150 180 210 240 270 300 330 360
Resistance at SET − kΩ
Voltage at PH − V
Figure 4.
Figure 3.
BURST DIMMING DUTY CYCLE
vs
VOLTAGE AT BBR
BURST DIMMING PHASE SHIFT
vs
VOLTAGE AT PH
100
360
V5 = 5 V
V5 = 5 V
330
300
80
Burst Dimming Phase Shift − °
Burst Dimming Duty Cycle − %
90
70
60
50
40
30
20
270
240
210
180
150
120
90
60
10
30
0
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
0
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
Voltage at BBR − V
Figure 5.
Voltage at PH − V
Figure 6.
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STARTUP OF V5
VCC = 12 V
STARTUP OF V5
VCC = 24 V
VEN (5 V / div)
VEN (5 V / div)
V5 (2 V / div)
V5 (2 V / div)
Input Current (20 mA / div)
Input Current (20 mA / div)
VCC = 24 V, IOUT_V5 = 5 mA
VCC = 12 V, IOUT_V5 = 5 mA
Timebase (100 µs /div)
Timebase (100 µs /div)
Figure 7.
Figure 8.
STARTUP OF VREF
VCC = V5 = 5 V
VEN (5 V / div)
VREF (1 V / div)
Input Current (10 mA / div)
VCC = V5 = 5 V, IOUT_VREF = 2 mA
Timebase (100 µs /div)
Figure 9.
10
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SLVS524A – OCTOBER 2005 – REVISED FEBRUARY 2006
LAMP CURRENT AND
LAMP VOLTAGE AT STARTUP
VCC = 12 V
VCC = 12 V
Lamp Current (Voltage at CSEN) (5 V / div)
Lamp Voltage (Voltage at VSEN) (2 V / div)
Timebase (200 ms /div)
Figure 10.
LAMP CURRENT AND
LAMP VOLTAGE AT STARTUP
VCC = 24V
VCC = 24 V
Lamp Current (Voltage at CSEN) (5 V / div)
Lamp Voltage (Voltage at VSEN) (2 V / div)
Timebase (200 ms /div)
Figure 11.
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LAMP CURRENT SOFTSTART
AT BURST DIMMING
VCC = 12 V
Voltage at BC (2 V / div)
Lamp Current (Voltage at CSEN) (2 V / div)
Timebase (100 µs /div)
Figure 12.
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DETAILED DESCRIPTION
Supply Voltages
The TPS68000 and the connected H-bridge power stage can be completely supplied by a voltage connected to
VCC. This voltage must be between 8 V to 30 V. In this configuration an internal linear regulator generates the 5
V required for control supply and gate drive supply. It is available at the V5 pin. The external capacitors for
supplying the high side gate drivers during operation are charged using internal diodes during the time when the
low side switches are turned on. The 3.3-V reference voltage is generated with a precise linear regulator, which
is also supplied from the 5-V control supply.
Optionally, the device can be supplied using a regulated 5-V rail. This is done by connecting the external 5 V to
VCC and V5. This way the internal regulator is bypassed and the internal power dissipation is reduced. It also
makes it possible to use any voltage lower than 30 V to supply the H-bridge power stage. When using
appropriate means of isolating the gate drive outputs of the device from their respective gates of the H-bridge
switches, the device can control power stages with higher input voltages as well. An example for this
configuration is using the output voltage of the PFC directly as a supply for the H-bridge power stage.
Gate Driver
The TPS68000 is a controller for converters, built with a full bridge topology. To control the output power highside and low-side switches in each of the two half bridges are driven alternately with 50% duty cycle. By phase
shifting both half-bridge parts to each other, output power is controlled. Current can only flow into the transformer
if one of the high side switches is turned on the same time as the low-side switch on the other half-bridge is
turned on. Maximum output power can be achieved if the turn on time of the high-side switch on one half-bridge
exactly overlaps with the turn on time of the low side on the other half bridge. Zero output power will be if there is
no overlap.
To properly control the 4 switches required for this phase shift full bridge topology, 4 gate drivers are
implemented. To obtain maximum efficiency at lowest costs the gate drivers are designed to drive 4 N-Channel
MOSFETs. The gate drive outputs can be connected directly to the gates of the FETs. There is no gate drive
circuit required as long as the operating input voltage range does not exceed the isolation voltage of the high
side drivers or the drive capability is not sufficient for larger FETs. The nominal gate drive voltage is 5 V. This 5V rail is generated internally in the device and is used directly to supply the low side drivers. For the high side
drivers external capacitors are used to supply the drivers. They are charged up during the on time of the low-side
drivers.
Control Circuit
The device is able to control lamp current and lamp voltage directly. Lamp voltage and lamp current are sensed
with an appropriate feedback divider and a shunt resistor. By suitable designing feedback divider and shunt
resistor lamp current and maximum lamp voltage are programmed. Since the lamp needs to be operated with AC
current, the feedback signals in simple applications usually are AC voltages. To directly support this and to save
external components for rectification, internal half wave rectifiers are built in the device.
Regulating current and voltage is done by two independent error amplifiers. Both are compensated externally to
be flexible to meet the demands for a wide variety of CCFL backlight applications. Both error amplifier outputs
feed the phase shift modulator. Whichever error amplifier requires the lower duty cycle, takes over control of the
system. The control circuit also detects whether the device operates in voltage regulation or in current regulation.
If voltage regulation is detected a fault condition is assumed, for example a broken lamp. In this condition the
control circuit waits for a programmed wait time. If the current regulator does not take over control again during
this wait time, the device shuts down and sets the FAULT flag. The wait time is programmed with the size of the
capacitance at STC.
Protection
In addition to the voltage regulator other means of protection are implemented. To ensure that the secondary
voltage of the transformer does not exceed the isolation breakdown voltage of the transformer an overvoltage
comparator is implemented. This comparator monitors the rectified voltage at the VSEN input. If the peak voltage
level at VSEN rises 20% above the nominal regulation voltage, regulated by the voltage amplifier, the
overvoltage comparator trips and the device immediately enters FAULT condition. For detailed threshold values
please check the electrical characteristics table.
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For additional protection there is a standalone comparator implemented. It can be used to monitor any voltage in
the system. The switching threshold is set to the VREF voltage.
. This comparator monitors a voltage at its input and compares it with the internal reference voltage. As soon as
the input voltage of the comparator exceeds the reference voltage the comparator asserts FAULT at its output.
Negative voltages can be applied at that pin but there is no rectification. Since the input of the overcurrent
comparator is directly accessible at a pin it can be connected to any part of the circuit. It must not necessarily
use the shunt resistor used for current regulation. Monitoring the current in the secondary winding or any other
DC voltage in the system may be a desired approach as well.
Finally the device has an internal temperature sensor to monitor the IC temperature. If the temperature gets too
high FAULT is asserted as well. For detailed values for threshold and hysteresis of the thermal protection please
check the electrical characteristics table.
Oscillator
The device is operating at a fixed frequency which is generated by a built in PLL circuit. The frequency is
programmed with a resistor at SET. It also can be synchronized to an external frequency at SYNC. When
synchronizing to an external clock two modes are possible. One is to synchronize directly to the external clock,
the other is to synchronizeto the external clock but phase shifted. This helps to minimize the RMS input current
of the complete power converter application in a multi controller topology. This phase shift is programmed with a
DC voltage of 0 V to 2 V at PH for a phase shift of 0° to 180°.
Dimming
To dimm the lamp, two basic methods of dimming are supported. The first is to control the lamp current directly,
called analog dimming. The second is to turn the lamp on and off at a low frequency with a certain duty cycle,
called burst dimming. Analog dimming, is done by just providing a DC voltage at ABR. The lamp current will be
regulated propotional to that voltage. The maximum lamp current in burst dimming is also programmed with this
voltage at ABR.
Turning the lamp on and off, burst dimming, needs some more information. A low frequency must be generated
and duty cycle information for the on time needs to be provided. The simplest burst dimming mode, independent
burst dimming, is to program the low frequency with an external capacitor at BF. Applying a DC voltage at BBR
sets the duty cycle of the burst pulse. The burst duty cycle will be programmed proportional to the DC voltage at
BBR.
If the burst dimming frequency and duty cycle must be synchronized to an external PWM signal this external
signal can be connected to BC. The bursts follow the PWM signal directly. A PWM signal detected at BC has
priority to any internally generated burst signal. To force the device to take the BC PWM signal BBR can be tied
high (V5).
To minimize RMS input current in a multiple controller application the burst signal can be phase shifted to the
external PWM connected to BC, which is called Distributed Dimming®. Frequency and duty cycle stay the same.
The phase shift information is derived from the voltage at PH. Voltages of 0 V to 2 V at PH generate burst phase
shifts of 0° to 360°. For this mode of operation the internal low frequency oscillator is used. It is operated as a
PLL synchronized to the PWM frequency at BC and its center frequency has to be programmed at BF. The
compensation of the low frequency PLL is done with and R - C network connected at BBR.
Startup
When the device is enabled or the device is powered up with EN tied high, the device enters lamp strike mode.
In this mode no dimming and synchronization is possible. During the strike procedure the lamp current which
should flow when the lamp has turned on is programmed at ABR.
The device starts operating at double the programmed operating frequency and sweeps down to half of the
nominal frequency. During this sweep it can cross the self resonance frequency of the system with its maximum
voltage gain. As soon as the lamp current has reached its programmed value the device stops sweeping and
switches to the nominal operating frequency. The device will continue to regulate the lamp current and all other
control features like synchronization and burst dimming are enabled and will be used. If during this sweep the
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lamp voltage, which is programmed at the voltage regulator is reached, frequency sweeping is stopped and the
voltage regulator regulates the voltage at the programmed level. At that time a timer is started. If during this
waiting, the lamp current reaches its programmed value, the device will continue operating as described above. If
for any reason the timer reaches its programmed end, programmed by a capacitor at STC, the device stops
working and enters FAULT condition.
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APPLICATION INFORMATION
DESIGN PROCEDURE
This section describes the basic configuration and calculations which need to be done for getting the component
values necessary for configuring the device properly. Backlight inverters can be significantly more complex
especially when driving multiple lamps with one or more controllers. This will be described in seperate application
notes and documentation for reference designs and EVM's which are also available.
Decoupling and Filtering
For decoupling and filtering it is recommended to use capacitors with a low series resistance and inductance to
achieve optimum performance. Surface mount ceramic capacitors are a good choice. It is also recommended to
use short and wide traces to connect those decoupling capacitors to the controller.
For the high side gate drivers in typical applications at least a 1-μF supply capacitor is recommended. It should
be connected between SA to V5A and SC to V5C with connectio placed as close as possible to the respective
pins to make sure that the gate drive outputs have a low impedance power source.
The V5 control supply requires a decoupling capacitor as well. It should be similar in capacitance as used for
both of the high side gate drivers. Example if a typical 1uF capacitor is used at the high side drivers therefore 2.2
μF is recommended at V5.
If V5 is used as an input, which means the controller is supplied with regulated 5 V directly, V5 must be
connected to VCC to avoid reverse current flowing and malfunctioning of the control circuits directly powered
from VCC.
In case the V5 regulator is supplied via the VCC input it is recommended to use a decoupling capacitor at the
VCC pin. The capacitor should be at least 0.1 μF. For additional filtering a resistor in series can be used.
For all those capacitors the PGND pin at the IC should be the reference ground.
Connecting the Gates of the MOSFETs
The gates of the MOSFETs of the power stage should be connected with short and wide traces having a low
impedance. The respective ground connection should be similar in width and length. Special care should be
taken on the loop area formed by the gate drive trace and the respective ground return trace, that it is as small
as possible. Any vias in this traces should be avoided.
If there is a need to slow down the switching speed of the FETs to reduce EMI caused by switching transients,
gate resistors at the gate drive outputs can be used.
Voltage Reference
The internal reference voltage is available at the VREF pin. It is recommended to decouple it at this pin using a
minimum 0.22 μF capacitor to the analog ground reference pin GND. Short direct connections are
recommended.
Enabling the Controller
A logic high at the EN pin enables the controller. The enable thresholds are designed to meet requirements of
3.3 V and 1.8 V logic standards. Nevertheless it is also possible to connect EN directly to VCC to enable the
controller at power up, since the EN pin can withstand voltages as high as allowed at VCC.
If the device detects a fault it is automatically disabled. To allow the device to automatically restart after a fault,
FAULT and EN pins can be directly connected together using a common pull up resistor to VCC.
Fault Output
The fault output is open drain. It is low impedance to GND if the controller detected a fault. In normal operation it
is always high impedance. To make sure that a logic low at the FAULT pin has a lower voltage than 0.4 V the
pullup resistor should limit the current into the FAULT pin to a value lower than 0.5 mA. Equation 1 shows the
calculation:
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V
R FAULT + LOGIC
0.5 mA
(1)
RFAULT is the minimum resistance value of the pullup resistor, VLOGIC is the maximum supply voltage of the logic
connected to FAULT.
Main Oscillator
In normal operation the controller operates at the frequency of the main oscillator. It is programmed with a
resistor connecting the SET pin to GND. The resistor value is calculated using Equation 2:
R SET + 9720 kW kHz
fN
(2)
If the controller should be synchronized to an external clock the main oscillator frequency should be programmed
close to the synchronizing frequency. This avoids large variations in case external clock pulses are missing. It
also speeds up the locking to the external clock. The SET pin should never be left open.
Synchronization of the Main Oscillator
The main oscillator can be used in different modes of operation. The first and most important mode is using it as
a reference clock. This is also the mode of choice in a single controller application which is not synchronized to
an external clock. In this mode the SYNC pin is used as an output and should be left open if no circuit needs to
be synchronized to the device main oscillator clock. To force the device operating in this mode 5 V (V5) must be
connected to the PH pin.
Lower voltages applied at the PH pin configure the SYNC pin as an input. Detailed voltage levels for this can be
found in the electrical characteristics table. If the SYNC pin is configured as an input the device automatically
synchronizes the main oscillator to the frequency which must be applied at the SYNC pin. The compensation for
this main oscilator PLL circuit is done with a capacitor connected at the STC pin. Since this capacitor is used for
defining sweep and wait timing during startup and voltage regulation, synchronization is only possible when the
device has started and is regulating lamp current. Any capacitance value which makes sense for defining sweep
and wait time should offer a reasonable compensation for the main oscillator PLL. How to calculate the value for
the capacitor at STC to program the startup and wait timing is shown in the following paragraph. Typical values
are in a μF range.
Also a phase shifted synchronization can be programmed. For this a voltage in the range between 0 V and 2 V
must be applied at the PH pin. For calculating the phase shift of the main oscillator clock to the clock applied at
the SYNC pin Equation 3 can be used:
f N + VPH
90
o
V
(3)
In this equation φN is the main oscillator clock phase shift and VPH is the voltage applied at the PH pin.
Startup and Wait Timing
After enabling the device the device is starting at double the programmed main oscillator frequency and is
sweeping down to half the programmed main oscillator frequency. The timing for the sweep is programmed with
a capacitor connected between STC and GND. It can be calculated using Equation 4:
s
t SW + CSTC 0.42
mF
(4)
tSW is the sweep time and CSTC is the capacitance connected between the pins STC and GND.
If at any time the voltage regulator becomes active a wait timer is started. The timing is also programmed with a
capacitor connecting STC and GND. Open lamp condition will lead to shutdown after timeout. Equation 5 shows
how to calculate the wait time, tW:
s
t W + CSTC 0.63
mF
(5)
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Programming the Lamp Current
The lamp current which is an AC signal is sensed at the CSEN input. The AC signal is half-wave rectified
through internal circuits eliminating the need for external parts except for a current sense resistor. The error
amplifier will generate an average voltage from the half wave rectified input signal. This average voltage is
compared to the steering signal for the lamp current. This steering signal is always provided at the ABR input. It
is recommended to use the reference voltage as a maximum input voltage. For a sinusoidal feedback voltage at
CSEN the peak voltage matches the voltage applied at ABR. With this information the shunt resistor for a given
RMS lamp current can be calculated using Equation 6:
VABR
R Shunt +
Ǹ2
I
Lamp
(6)
Assuming that the reference voltage is connected to ABR the lamp current is calculated as shown in the
following Equation 7:
R Shunt + 3.3 V
I Lamp Ǹ2
(7)
RShunt is the value of the shunt resistor used for current sensing, VABR is the voltage applied at ABR and ILamp is
the RMS value of the lamp current which should be programmed.
Analog Dimming
By modifiying the voltage at ABR the lamp current steering signal is changed. With this the lamp current is
changed. The resulting lamp current for a certain voltage at ABR can be calculated as shown in Equation 8:
VABR
I Lamp +
Ǹ2
R
Shunt
(8)
ILamp is the RMS lamp current, VABR is the voltage at ABR and RShunt is the value of the resistor used for lamp
current sensing.
Programming the Voltage Regulation and Overvoltage Protection
The lamp voltage and the transformer secondary voltage are AC signals as is the lamp current. They are sensed
at the VSEN input. Circuits similar to the current amplifier (CSEN) half wave rectified input are eliminating the
requirement for rectification on VSEN. The error amplifier will generate an average voltage from the half wave
rectified input signal. This average voltage is compared to the steering signal for the voltage. This steering signal
is derived from the internal reference voltage VREF. The overvoltage comparator is monitoring the peak voltage at
VSEN. Its threshold is the internal reference voltage. The voltage divider ratio can be calculated using
Equation 9:
V
r V + REG
1.87 V
(9)
rV is the ratio of the voltage feedback divider and VREG is the maximum RMS voltage the regulator should
regulate at the lamp or transformer secondary.
The corresponding RMS voltage where the overvoltage protection comparator turns off can be calculated using
Equation 10:
V OVP + 2.33 V r V
(10)
To build the voltage feedback divider, resistive and capacitive dividers can be used. In case of a resistive divider
the ratio of the feedback divider is defined as shown in Equation 11:
R ) RL
rV + H
RL
(11)
RH is the upper resistor in the divider at the high voltage side, RL is the resistor to GND.
In case of a capacitive divider the ratio can be calculated as shown in Equation 12:
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rV +
SLVS524A – OCTOBER 2005 – REVISED FEBRUARY 2006
CH ) CL
CH
(12)
In this case CH is the upper capacitor in the divider at the high voltage side, CL is the capacitor to GND.
Protection
The overcurrent protection comparator (OCP) is typically used to monitor output current but can be configured to
monitor any voltage. The comparator uses the internal reference voltage VREF as a fixed threshold. Any voltage
above the internal reference voltage at OCP for more than 4 clock cycles of the main oscillator causes the
comparator to trip and generate a fault. The comparator only will trip with positive voltages above the internal
reference voltage at applied to OCP. Although the input can withstand higher negative voltages there is no
rectification implemented.
Compensating the Current and Voltage Regulators
The compensation networks for current and voltage regulators are connected between the negative inputs and
the outputs of the respecive amplifier. At the current amplifier the pins are CAM (input) and CAO (output). At the
voltage amplifier VAM (input) and VAO (output) are used. The compensation network must have a dominating
capacitive characteristic, since the error amplifiers are also used for smoothing the half wave rectified feedback
input signal. capacitors in parallel with resistor and capacitor in series or just capacitors are recommended. In
typical applications a 2200 pF capacitor at the current amplifier and a 0.022 μF capacitor at the voltage amplifier
can be used.
Synchronized Burst Dimming
To configure the device for synchronized burst dimming the dimming PWM signal must be connected directly to
the BC logic input pin. The controller will turn the lamp on and off, following directly the PWM pulses applied at
BC regarding frequency, phase and duty cycle. The slopes of the lamp current are controlled internally. The other
pins used for configuring burst dimming, BBR and BF should have a defined state as well. It is recommended to
connect BBR to 5 V (V5) and to connect BF to GND.
Independent Burst Dimming
In this configuration the device generates the low dimming frequency and the duty cycle internally. To use this
feature the BC pin should be connected to GND. A capacitor connected to BF is used to program the frequency
of the low frequency oscillator. The capacitance necessary to program a given burst dimming frequency can be
calculated using Equation 13:
C BF + 4.7 mF Hz
fD
(13)
CBF is the capacitor required to be connected between BF and GND and fD is the low frequency oscillator
frequency which should be programmed. For example a 0.047 μF capacitor is needed to program a burst
frequency of 100 Hz.
To program the burst duty cycle a voltage at BBR is used. The duty cycle can be calculated using Equation 14:
D B + VBBR 50 %
V
(14)
DB is the resulting burst duty cycle and VBBR is the voltage applied at the BBR pin. The operating voltage range
for duty cycle programming is 0 V to 2 V. 0 V at BBR will program 0% burst duty cycle and 2 V will program
100% burst duty cycle.
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Phase Shifted Burst Dimming
The device also supports phase shifted burst dimming. In this configuration a direct PWM burst signal is used
which must be connected to BC. The internal low frequency oscillator must be programmed as described in the
independent burst dimming section and in Equation 13. Since the internal low frequency oscillator will be
synchronized to the frequency connected to BC it is recommended to program the internal low frequency close to
the frequency at BC. The synchronization is done using a PLL circuit. This PLL circuit needs an external
compensation network connected at BBR. For a typical burst frequency in the 100 Hz range using a 0.68 μF
capacitor in series with a 100 kΩ resistor is recommended. This R - C network should be connected between
BBR and GND.
The phase shift of the dimming burst compared to the input signal at BC is programmed with a voltage applied at
PH. The resulting phase shift can be calculated using Equation 15:
f B + VPH
180
o
V
(15)
φB is the phase shift of the dimming burst and VPH is the voltage applied at the PH pin.
Layout Considerations
As for all switching power supplies, the layout is an important step in the design, especially at high peak currents
and high switching frequencies. If the layout is not carefully done, the regulator could show stability problems as
well as EMI problems. Therefore, use wide and short traces for the main current path and for the power ground
tracks. Use a common ground node for power ground and a different one for control ground to minimize the
effects of ground noise. Connect these ground nodes at any place close to one of the ground pins of the IC.
To layout the control ground, it is recommended to use short traces as well, separated from the power ground
traces. This avoids ground shift problems, which can occur due to superimposition of power ground current and
control ground current.
THERMAL INFORMATION
Implementation of integrated circuits in low-profile and fine-pitch surface-mount packages typically requires
special attention to power dissipation. Many system-dependent issues such as thermal coupling, airflow, added
heat sinks and convection surfaces, and the presence of other heat-generating components affect the powerdissipation limits of a given component.
Three basic approaches for enhancing thermal performance are listed below.
• Improving the power dissipation capability of the PCB design
• Improving the thermal coupling of the component to the PCB
• Introducing airflow in the system
The maximum recommended junction temperature (TJ) of the TPS68000 device is 125°C. The thermal resistance
of the 30-pin TSSOP package (PW) is RθJA = 63.9°C/W. Specified regulator operation is assured to a maximum
ambient temperature TA of 85°C. Therefore, the maximum power dissipation is about 626 mW. More power can
be dissipated if the maximum ambient temperature of the application is lower.
T J(MAX) * T A
o
o
P D(MAX) +
+ 125 C *o 85 C + 626 mW
R qJA
C
63.9
W
(16)
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PACKAGE OPTION ADDENDUM
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14-Oct-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS68000DBT
NRND
TSSOP
DBT
30
60
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TPS68000
TPS68000DBTR
NRND
TSSOP
DBT
30
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TPS68000
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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