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TPS51275B-1
SLVSCT3 – MARCH 2015
TPS51275B-1 Dual Synchronous, Step-Down Controller With 5-V and 3.3-V LDOs
1 Features
2 Applications
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Input Voltage Range: 5 V to 24 V
Output Voltages: 5 V and 3.3 V (Adjustable Range
±10%)
Built-in, 100-mA, 5-V, and 3.3-V LDOs
Clock Output for Charge-Pump
±1% Reference Accuracy
Adaptive On-Time D-CAP™ Mode Control
Architecture with 300-kHz and 355-kHz Frequency
Setting
Out-of-Audio™ (OOA) Light-Load Operation
Internal 3.2-ms Voltage Servo Soft-Start
Low-Side RDS(on) Current Sensing Scheme
Built-In Output Discharge Function
Separate Enable Input for Switchers
Dedicated OC Setting Terminals
Power Good Indicator
OVP, UVP, and OCP Protection
Non-Latch UVLO and OTP Protection
20-Pin, 3-mm × 3-mm, WQFN (RUK) Package
Notebook Computers
Tablet Computers
Desktop Computers
3 Description
The TPS51275B-1 device is a cost-effective, dualsynchronous buck controller targeted for notebook
system-power supply solutions. The device has 5-V
and 3.3-V low-dropout regulators (LDOs) and
requires few external components. The 260-kHz
VCLK output can be used to drive an external charge
pump, generating gate drive voltage for the load
switches without reducing the main converter
efficiency. The TPS51275B-1 device supports high
efficiency, fast transient response and provides a
combined power-good signal. Adaptive on-time, DCAP control provides convenient and efficient
operation. The device operates with a supply input
voltage ranging from 5 to 24 V and supports output
voltages of 5 V and 3.3 V. The TPS51275B-1 device
is available in a 20-pin, 3-mm × 3-mm, WQFN
package and is specified from –40°C to 85°C.
Device Information(1)
PART NUMBER
TPS51275B-1
SKIP MODE
OOA
ALWAYS ON-LDO
VREG3 and VREG5
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
4 Typical Application Diagram
VIN
TPS51275B-1
VIN
VOUT
5V
VBST1
VBST2
DRVH1
DRVH2
SW1
VOUT
3.3 V
SW2
DRVL1
DRVL2
VO1
VFB1
VFB2
CS1
CS2
VCLK
VOUT
15 V
5-V EN
5V
Always ON
EN1
VREG5
1 µF
PGOOD
PGOOD
EN2
3.3-V EN
3.3-V Always ON
VREG3
1 µF
UDG-12091
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS51275B-1
SLVSCT3 – MARCH 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Typical Application Diagram ................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
1
2
3
4
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
4
4
5
5
5
7
7
8
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Timing Requirements ................................................
Switching Characteristics ..........................................
Typical Characteristics ..............................................
8.2 Functional Block Diagram ....................................... 11
8.3 Feature Description................................................. 12
8.4 Device Functional Modes........................................ 16
9
Application and Implementation ........................ 17
9.1 Application Information............................................ 17
9.2 Typical Application ................................................. 17
10 Power Supply Recommendations ..................... 21
11 Layout................................................................... 21
11.1 Layout Guidelines ................................................. 21
11.2 Layout Example .................................................... 22
12 Device and Documentation Support ................. 22
12.1
12.2
12.3
12.4
Device Support......................................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
22
22
22
22
13 Mechanical, Packaging, and Orderable
Information ........................................................... 23
Detailed Description ............................................ 11
8.1 Overview ................................................................. 11
5 Revision History
2
DATE
REVISION
NOTES
March 2015
*
Initial release.
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6 Pin Configuration and Functions
EN1
VCLK
SW1
VBST1
DRVH1
20
19
18
17
16
RUK Package
20-Pin WQFN With Thermal Pad
Top View
CS1
1
15
DRVL1
VFB1
2
14
VO1
VREG3
3
13
VREG5
VIN
DRVL2
Thermal Pad
10
9
VBST2
DRVH2
8
SW2
11
7
5
PGOOD
CS2
6
4
12
EN2
VFB2
Pin Functions
PIN
NAME
CS1
NO.
I/O
DESCRIPTION
1
O
Sets the channel 1 OCL trip level
CS2
5
O
Sets the channel 2OCL trip level
DRVH1
16
O
High-side driver output
DRVH2
10
O
High-side driver output
DRVL1
15
O
Low-side driver output
DRVL2
11
O
Low-side driver output
EN1
20
I
Channel 1 enable
EN2
6
I
Channel 2 enable
PGOOD
7
O
Power good output flag. Open drain output. Pull up to external rail through a resistor
SW1
18
O
Switch-node connection
SW2
8
O
Switch-node connection
VBST1
17
I
VBST2
9
I
VCLK
19
O
VFB1
2
I
VFB2
4
I
VIN
12
I
Power conversion voltage input. Apply the same voltage as drain voltage of high-side MOSFETs of channel 1
and channel 2.
VO1
14
I
Output voltage input, 5-V input for switch-over
VREG3
3
O
3.3-V LDO output
VREG5
13
O
5-V LDO output
—
Ground (GND) terminal, solder to the ground plane
Thermal pad
Supply input for high-side MOSFET (bootstrap terminal). Connect a capacitor from this pin to the SWx pin.
Clock output for charge pump
Voltage feedback input
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7 Specifications
7.1 Absolute Maximum Ratings (1)
over operating free-air temperature range (unless otherwise noted)
Input voltage (2)
Output voltage (2)
MIN
MAX
VBST1, VBST2
–0.3
32
VBST1, VBST2 (3)
–0.3
6
SW1, SW2
–6.0
26
VIN
–0.3
26
EN1, EN2
–0.3
6
VFB1, VFB2
–0.3
3.6
VO1
–0.3
6
DRVH1, DRVH2
–6.0
32
DRVH1, DRVH2 (3)
–0.3
6
DRVH1, DRVH2 (3) (pulse width < 20 ns)
–2.5
6
DRVL1, DRVL2
–0.3
6
DRVL1, DRVL2 (pulse width < 20 ns)
–2.5
6
PGOOD, VCLK, VREG5
–0.3
6
VREG3, CS1, CS2
–0.3
3.6
Junction temperature, TJ
Storage temperature, Tstg
(1)
(2)
(3)
–55
UNIT
V
V
150
°C
150
°C
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to the network ground terminal unless otherwise noted
Voltage values are with respect to SW terminals.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
4
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1)
±2000
Charged device model (CDM), per JEDEC specification JESD22-C101, all
pins (2)
±1000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
Supply voltage
MAX
VIN
Input voltage (1)
Output voltage (1)
5
24
VBST1, VBST2
–0.1
30
VBST1, VBST2 (2)
–0.1
5.5
SW1, SW2
–5.5
24
EN1, EN2
–0.1
5.5
VFB1, VFB2
–0.1
3.5
VO1
–0.1
5.5
DRVH1, DRVH2
–5.5
30
DRVH1, DRVH2 (2)
–0.1
5.5
DRVL1, DRVL2
–0.1
5.5
PGOOD, VCLK, VREG5
–0.1
5.5
VREG3, CS1, CS2
–0.1
3.5
–40
85
Operating free-air temperature, TA
(1)
(2)
MIN
UNIT
V
V
V
°C
All voltage values are with respect to the network ground terminal unless otherwise noted.
Voltage values are with respect to the SW terminal.
7.4 Thermal Information
RUK (WQFN)
THERMAL METRIC (1)
RθJA
Junction-to-ambient thermal resistance
94.1
RθJC(top)
Junction-to-case (top) thermal resistance
58.1
RθJB
Junction-to-board thermal resistance
64.3
ψJT
Junction-to-top characterization parameter
31.8
ψJB
Junction-to-board characterization parameter
58.0
RθJC(bot)
Junction-to-case (bottom) thermal resistance
5.9
(1)
UNIT
20 PINS
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
7.5 Electrical Characteristics
over operating free-air temperature range, VVIN = 12 V, VVO1 = 5 V, VVFB1 = VVFB2 = 2 V, VEN1 = VEN2 = 3.3 V (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY CURRENT
860
μA
30
μA
TA = 25°C, No load, VVFB1 = VVFB2 = 2.05 V
900
μA
TA = 25°C, No load, VVO1 = 0 V, VEN1= VEN2 = 0 V
180
μA
IVIN1
VIN supply current-1
TA = 25°C, No load, VVO1 = 0 V
IVIN2
VIN supply current-2
TA = 25°C, No load
IVO1
VO1 supply current
IVIN(STBY)
VIN stand-by current
INTERNAL REFERENCE
VFBx
VFB regulation voltage
TA = 25°C
1.99
2
2.01
1.98
2
2.02
4.9
5
5.1
VVIN > 7 V , VVO1 = 0 V, IVREG5 < 100 mA
4.85
5
5.1
VVIN > 5.5 V , VVO1 = 0 V, IVREG5 < 35 mA
4.85
5
5.1
5.1
V
VREG5 OUTPUT
TA = 25°C, No load, VVO1 = 0 V
VVREG5
VREG5 output voltage
VVIN > 5 V, VVO1 = 0 V, IVREG5 < 20 mA
4.50
4.75
IVREG5
VREG5 current limit
VVO1 = 0 V, VVREG5 = 4.5 V, VVIN = 7 V
100
150
mA
RV5SW
5-V switch resistance
TA = 25°C, VVO1 = 5 V, IVREG5 = 50 mA
1.8
Ω
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5
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Electrical Characteristics (continued)
over operating free-air temperature range, VVIN = 12 V, VVO1 = 5 V, VVFB1 = VVFB2 = 2 V, VEN1 = VEN2 = 3.3 V (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
No load, VVO1= 0 V, TA = 25°C
3.267
3.3
3.333
VVIN > 7 V , VVO1= 0 V, IVREG3< 100 mA
3.217
3.3
3.383
5.5 V < VVIN , VVO1= 0 V, IVREG3< 35 mA
3.234
3.3
3.366
0°C ≤ TA ≤ 85°C, VVIN > 5.5 V, VVO1 = 0 V,
IVREG3< 35 mA
3.267
3.3
3.333
0°C ≤ TA ≤ 85°C, VVIN > 5.5 V, VVO1 = 5 V,
IVREG3 < 35 mA
3.267
3.3
3.333
VVIN > 5 V, VVO1 = 0 V, IVREG3< 35 mA
3.217
3.3
3.366
VVO1 = 0 V, VVREG3 = 3.0 V, VVIN= 7 V
100
150
UNIT
VREG3 OUTPUT
VVREG3
VREG3 output voltage
IVREG3
VREG3 current limit
V
mA
MOSFET DRIVERS
RDRVH
DRVH resistance
RDRVL
DRVL resistance
Source, (VVBST – VDRVH) = 0.25 V, (VVBST – VSW) = 5 V
3
Sink, (VDRVH – VSW) = 0.25 V, (VVBST – VSW) = 5 V
Ω
1.9
Source, (VVREG5 – VDRVL) = 0.25 V, VVREG5 = 5 V
3
Sink, VDRVL = 0.25 V, VVREG5= 5 V
0.9
Boost switch on-resistance
TA = 25°C, IVBST = 10 mA
13
VBST leakage current
TA = 25°C
Ω
INTERNAL BOOT STRAP SWITCH
RVBST
(ON)
IVBSTLK
Ω
1
µA
CLOCK OUTPUT
RVCLK
(PU)
VCLK on-resistance (pullup)
TA = 25°C
10
Ω
RVCLK
(PD)
VCLK on-resistance (pulldown)
TA = 25°C
10
Ω
OUTPUT DISCHARGE
RDIS1
CH1 discharge resistance
TA = 25°C, VVO1 = 0.5 V
VEN1 = VEN2 = 0 V
35
Ω
RDIS2
CH2 discharge resistance
TA = 25°C, VSW2 = 0.5 V, VEN1 = VEN2 = 0 V
70
Ω
POWER GOOD
Lower (rising edge of PG-in)
VPGTH
PG threshold
92.5%
Hysteresis
Upper (rising edge of PG-out)
95.0%
107.5% 110.0% 112.5%
Hysteresis
5%
6.5
IPGMAX
PG sink current
VPGOOD = 0.5 V
IPGLK
PG leakage current
VPGOOD = 5.5 V
97.5%
5%
mA
1
µA
CURRENT SENSING
ICS
CS source current
TA = 25°C, VCS= 0.4 V
TCCS
CS current temperature coefficient (1)
On the basis of 25°C
VCS
CS current-limit setting range
VZC
Zero cross detection offset
9
10
0.2
TA = 25°C
11
4500
–1
1
μA
ppm/°C
2
V
3
mV
LOGIC THRESHOLD
VENX(ON)
EN threshold high-level
SMPS on level
VENX(OFF)
EN threshold low-level
SMPS off level
0.3
IEN
EN input current
VENx= 3.3 V
–1
1.6
V
1
µA
V
OUTPUT OVERVOLTAGE PROTECTION
VOVP
OVP trip threshold
112.5% 115.0% 117.5%
OUTPUT UNDERVOLTAGE PROTECTION
VUVP
(1)
6
UVP trip threshold
55%
60%
65%
Ensured by design. Not production tested.
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Electrical Characteristics (continued)
over operating free-air temperature range, VVIN = 12 V, VVO1 = 5 V, VVFB1 = VVFB2 = 2 V, VEN1 = VEN2 = 3.3 V (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
UVLO
VUVL0VIN
VIN UVLO threshold
VUVLO5
VREG5 UVLO threshold
VUVLO3
VREG3 UVLO threshold
Wake up
4.58
Hysteresis
V
0.5
Wake up
4.38
Hysteresis
4.5
V
0.4
Wake up
3.15
Hysteresis
0.15
Shutdown temperature
155
V
OVERTEMPERATURE PROTECTION
OTP threshold (1)
TOTP
Hysteresis
°C
10
7.6 Timing Requirements
over operating free-air temperature range, VVIN = 12 V, VVO1 = 5 V, VVFB1 = VVFB2 = 2 V, VEN1 = VEN2 = 3.3 V (unless otherwise
noted)
MIN
NOM
MAX
UNIT
DUTY CYCLE AND FREQUENCY CONTROL
fsw1
CH1 frequency (1)
TA = 25°C, VVIN= 20 V
240
300
360
kHz
(1)
TA = 25°C, VVIN= 20 V
280
355
430
kHz
TA = 25°C
200
300
500
ns
fSW2
CH2 frequency
tOFF(MIN)
Minimum off-time
MOSFET DRIVERS
tD
(1)
Dead time
DRVH-off to DRVL-on
12
DRVL-off to DRVH-on
20
ns
Ensured by design. Not production tested.
7.7 Switching Characteristics
over operating free-air temperature range, VVIN = 12 V, VVO1 = 5 V, VVFB1 = VVFB2 = 2 V, VEN1 = VEN2 = 3.3 V (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
CLOCK OUTPUT
fCLK
Clock frequency
TA = 25°C
260
kHz
SOFT-START OPERATION
tSS
Soft-start time
From ENx = HI and VVREG5 >
VUVLO5 to VOUT = 95%
3.25
ms
tSSRAMP
Soft-start time (ramp-up)
VOUT= 0% to VOUT = 95%, VVREG5 =
5V
3.12
ms
From PG lower threshold (95% =
typical) to PG flag high
1.38
ms
0.5
µs
250
µs
4.3
ms
POWER GOOD
tPGDEL
PG delay
OUTPUT OVERVOLTAGE PROTECTION
tOVPDLY
OVP propagation delay
TA = 25°C
OUTPUT UNDERVOLTAGE PROTECTION
tUVPDLY
UVP propagation delay
tUVPENDLY
UVP enable delay
From ENx = HI and VVREG5 >
VUVLO5 to UV latch off
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7.8 Typical Characteristics
1.6
60
VIN Supply Current 2 (µA)
VIN Supply Current 1 (mA)
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
−40 −25 −10
5
20 35 50 65 80
Junction Temperature (°C)
95
20
10
250
1.4
225
1.2
1.0
0.8
0.6
0.4
0.0
−40 −25 −10
95
110 125
G002
200
175
150
125
100
75
50
25
5
20 35 50 65 80
Junction Temperature (°C)
95
0
−40 −25 −10
110 125
G003
310
18
300
16
290
VCLK Frequency (kHz)
20
14
12
10
8
6
4
2
5
20 35 50 65 80
Junction Temperature (°C)
95
110 125
G004
Figure 4. VIN Stand-By Current vs Junction Temperature
Figure 3. VO1 Supply Current 1 vs Junction Temperature
0
−40 −25 −10
5
20 35 50 65 80
Junction Temperature (°C)
Figure 2. VIN Supply Current 2 vs Junction Temperature
1.6
VIN Stand−By Current (µA)
VO1 Supply Current 1 (mA)
30
G001
0.2
CS Source Current (µA)
40
0
−40 −25 −10
110 125
Figure 1. VIN Supply Current 1 vs Junction Temperature
280
270
260
250
240
230
220
5
20 35 50 65 80
Junction Temperature (°C)
95
110 125
Figure 5. CS Source Current vs Junction Temperature
8
50
210
−40 −25 −10
G005
5
20 35 50 65 80
Junction Temperature (°C)
95
110 125
G006
Figure 6. Clock Frequency vs Junction Temperature
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Typical Characteristics (continued)
100
5.2
90
5.15
80
Output Voltage (V)
Efficiency (%)
70
60
50
40
30
VVIN = 7.4 V
VVIN = 11.1 V
VVIN = 14.8 V
VVIN = 20 V
20
10
0
0.001
0.01
0.1
Output Current (A)
1
5.1
5.05
5
4.95
VVIN = 7.4 V
VVIN = 11.1 V
VVIN = 14.8 V
VVIN = 20 V
4.9
4.85
0.001
10
0.01
D001
Out-of-Audio mode
VVOUT1 = 5 V
0.1
Output Current (A)
1
10
D003
Out-of-Audio mode
Figure 7. Efficiency vs Output Current
VVOUT1 = 5 V
Figure 8. Load Regulation
100
3.4
90
80
3.35
Output Voltage (V)
Efficiency (%)
70
60
50
40
30
3.25
VVIN = 7.4 V
VVIN = 11.1 V
VVIN = 14.8 V
VVIN = 20 V
20
10
0
0.001
0.01
0.1
Output Current (A)
1
3.3
VVIN = 7.4 V
VVIN = 11.1 V
VVIN = 14.8 V
VVIN = 20 V
3.2
0.001
10
0.01
D002
Out-of-Audio mode
VVOUT2 = 3.3 V
1
Figure 9. Efficiency vs Output Current
10
D004
Out-of-Audio mode
VVOUT2 = 3.3 V
Figure 10. Load Regulation
500
500
VVIN = 7.4 V
VVIN = 11.1 V
VVIN = 20 V
400
VVIN = 7.4 V
VVIN = 11.1 V
VVIN = 20 V
450
Switching Frequency (kHz)
450
Switching Frequency (kHz)
0.1
Output Current (A)
350
300
250
200
150
100
50
400
350
300
250
200
150
100
50
0
0.001
0.01
0.1
Output Current (A)
Out-of-Audio mode
1
10
0
0.001
D005
VVOUT1 = 5 V
Figure 11. Switching Frequency vs Output Current
0.01
0.1
Output Current (A)
Out-of-Audio mode
1
10
D006
VVOUT2 = 3.3 V
Figure 12. Switching Frequency vs Output Current
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500
500
450
450
Switching Frequency (kHz)
Switching Frequency (kHz)
Typical Characteristics (continued)
400
350
300
250
200
150
100
50
0
350
300
250
200
150
100
50
5
VOUT1 = 5 V
10
15
Input Voltage (V)
20
25
0
5
G000
IOUT1 = 6 A
VOUT2 = 3.3 V
Figure 13. Switching Frequency vs Input Voltage
10
400
10
15
Input Voltage (V)
20
25
G000
IOUT2 = 6 A
Figure 14. Switching Frequency vs Input Voltage
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8 Detailed Description
8.1 Overview
The TPS51275B-1 device is a cost-effective, dual-synchronous buck controller targeted for power-supply
solutions for notebook and desktop computer systems. The device has 5-V and 3.3-V low-dropout regulators
(LDOs) and requires few external components. With D-CAP control mode implemented, the compensation
network can be removed. The fast transient response also reduces the output capacitance.
8.2 Functional Block Diagram
TPS51275B-1
VIN
155°C
145°C
+
+
4.5 V
4V
VO1
+
VREG5
+
+
+
2V
+
VREG3
Osc
VCLK
EN1
VBST1
EN2
VDRV
VIN VDD VO_OK
SW1
DRVL 1
Switcher
Controller
(CH1)
VFB1
CS1
VDD VDRV
EN
DRVH 1
FAULT
REF
GND
REF
Switcher
Controller
(CH2)
PGOOD
DCHG
VBST2
DRVH 2
FAULT
PGOOD
PGND
VIN
EN
DCHG
SW2
DRVL 2
VFB2
GND
PGND
CS2
PGOOD
GND
(Thermal Pad )
UDG-12092
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Functional Block Diagram (continued)
TPS51275B-1
VDD
VREF –40%
+
UV
+
OV
VREF +15%
VREF +5%/10%
+
Control Logic
+
VREF –5%/10%
VFB
EN
PWM
+
+
REF
SS Ramp Comp
VO_OK
VBST
SKIP
HS
VIN
DRVH
SW
XCON
OC
CS
10 µA
VDRV
+
+
LS
NOC
One-Shot
+
Discharge
GND
+
ZC
DRVL
PGND
DCHG
PGOOD
PGOOD
FAULT
UDG-12093
Figure 15. Switcher Controller Block Diagram
8.3 Feature Description
8.3.1 PWM Operations
The main control loop of the switch-mode power supply (SMPS) is designed as an adaptive on-time pulse-widthmodulation (PWM) controller. The control loop supports a proprietary D-CAP mode. D-CAP mode does not
require an external conpensation circuit and is suitable for low external component-count configuration when
used with an appropriate amount of ESR at the output capacitors.
At the beginning of each cycle, the synchronous high-side MOSFET is turned on, or enters the ON state. After
the internal, one-shot timer expires, this MOSFET is turned off, or enters the OFF state. The MOSFET is turned
on again when the feedback point voltage, VVFB, decreases to match the internal 2-V reference. The inductor
current information is also monitored and should be below the overcurrent threshold to initiate this new cycle. By
repeating the operation in this manner, the controller regulates the output voltage. The synchronous low-side
(rectifying) MOSFET is turned on at the beginning of each OFF state to maintain a minimum of conduction loss.
The low-side MOSFET is turned off before the high-side MOSFET turns on at next switching cycle or when
inductor current information detects a zero level. When the low-side MOSFET is turned off when the inductor
current detects a zero level, a seamless transition to the reduced frequency operation during light-load conditions
is enabled so that high efficiency is maintained over a broad range of load current.
12
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Feature Description (continued)
8.3.2 Adaptive On-Time and PWM Frequency Control
Because the TPS51275B-1 device does not have a dedicated oscillator for the on-board control loop. The
switching cycle is controlled by the adaptive on-time circuit. The on-time is controlled to meet the target switching
frequency by feed-forwarding the input and output voltage into the on-time one-shot timer. The target switching
frequency is varied according to the input voltage to achieve higher duty operation for lower input voltage
application. The switching frequency of CH1 (5-V output) is 300 kHz during continuous-conduction-mode (CCM)
operation when VVIN = 20 V. The CH2 (3.3-V output) is 355 kHz during CCM when VVIN = 20 V (see Figure 13
and Figure 14).
To improve load transient performance and load regulation in lower input voltage conditions, the TPS51275B-1
device can extend the on-time. The maximum on-time extension for CH1 is 4 times and for CH2 is 3 times. To
maintain a reasonable inductor ripple current during on-time extension, the inductor ripple current should be set
to less than half of the OCL (valley) threshold (see the Step 2. Select the Inductor section). The on-time
extension function provides high duty-cycle operation and shows better DC (static) performance. AC
performance is determined mostly by the output LC filter and resistive factor in the loop.
8.3.3 Light-Load Condition in Out-of-Audio Operation
The TPS51275B-1 device automatically reduces switching frequency during light-load conditions to maintain high
efficiency. This reduction of frequency is achieved smoothly and without an increase in output voltage ripple. A
more detailed description of this operation follows. As the output current decreases from a heavy-load condition,
the inductor current is also reduced and eventually approaches valley zero current, which is the boundary
between continuous conduction mode and discontinuous conduction mode (DCM). The rectifying MOSFET is
turned off when this zero inductor current is detected. As the load current further decreases, the converter runs in
DCM and requires a longer and longer time to discharge the output capacitor to the level that requires the next
ON cycle. The ON time is maintained the same as that in the heavy-load condition. In reverse, when the output
current increases from light load to heavy load, the switching frequency increases to the preset value as the
inductor current reaches to the continuous conduction. Use Equation 1 to calculate the transition load point to the
light load operation IOUT(LL) (for example the threshold between continuous and discontinuous conduction mode).
IOUT(LL ) =
(VVIN - VOUT ) ´ VOUT
1
´
2 ´ L ´ fSW
VVIN
where
•
fSW is the PWM switching frequency
(1)
The switching frequency versus the output current during light-load conditions is a function of the inductance (L),
input voltage (VVIN) and output voltage (VOUT), but it decreases almost proportional to the output current from the
IOUT(LL). As the load current continues to decrease, the switching frequency can decrease into the acoustic
audible frequency range. To prevent this from happening, Out-of-Audio (OOA) light-load mode is implemented.
During Out-of-Audio operation, the OOA control circuit monitors the states of both the high-side and low-side
MOSFETs and forces them switching if both MOSFETs are off for more than 40 µs. When both high-side and
low-side MOSFETs are off for 40 µs during a light-load condition, the operation mode is changed to forced CCM
(FCCM). This mode change initiates one cycle of turning on both the low-side MOSFET and the high-side
MOSFET. Then, both MOSFETs remain turned off waiting for another 40 µs.
8.3.4 Enable and Power Good
The VREG3 and VREG5 pins are always-on regulators, when the input voltage is beyond the UVLO threshold it
turns ON. The VCLK signal initiates when the EN1 pin enters the ON state. Table 1 lists the enable states.
Table 1. Enabling and PGOOD State
EN1
EN2
VREG5
VREG3
CH1 (5 VOUT)
CH2 (3.3 VOUT)
VCLK
PGOOD
OFF
OFF
ON
ON
OFF
OFF
OFF
Low
Low
ON
OFF
ON
ON
ON
OFF
ON
OFF
ON
ON
ON
OFF
ON
OFF
Low
ON
ON
ON
ON
ON
ON
ON
High
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VIN-UVLO_threshold
VIN
2.4 V
VREG3
VREG5
EN_threshold
EN1
95% of
VOUT
Soft-Start Time (tSS)
Soft-Start Time
(tSS(ramp))
5-V VOUT
EN_threshold
EN2
95% of
VOUT
3.3-V VOUT
Soft-Start Time (tSS)
Soft-Start Time
(tSS(ramp))
PGOOD
PGOOD
Delay
tPGDEL
UDG-12015
Figure 16. Timing Diagram
8.3.5 Soft-Start and Discharge
The TPS51275B-1 device operates an internal, 3.2-ms, voltage servo soft-start for each channel. When the ENx
pin becomes higher than the enable threshold voltage, an internal DAC begins ramping up the reference voltage
to the PWM comparator. Smooth control of the output voltage is maintained during startup. When the ENx pin
becomes lower than the lower level of threshold voltage, the TPS51275B-1 device discharges the outputs using
internal MOSFETs through VO1 (CH1) and SW2 (CH2).
8.3.6 VREG5 and VREG3 Linear Regulators
The two sets of 100-mA standby linear regulators output 5 V and 3.3 V, respectively. The VREG5 pin provides
the current for the gate drivers. The VREG3 pin functions as the main power supply for the analog circuitry of the
device. Both the VREG5 and VREG3 regulators are always-ON LDOs (see Table 1).
To stabilize regulators, add ceramic capacitors with a value of 1 µF or larger (X5R grade or better) placed close
to the VREG5 and VREG3 pins.
The VREG5 pin switchover function is asserted when the following three conditions are present:
• CH1 internal PGOOD is high
• CH1 is not in overcurrent-limit (OCL) condition
• VO1 voltage is higher than VREG5-1V
In this switchover condition the following three things occur:
• The internal 5-V LDO regulator is shut off
• The VREG5 output is connected to VO1 by internal switchover MOSFET
• VREG3 input pass is changed from VIN to VO1
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8.3.7 VCLK for Charge Pump
The 260-kHz VCLK signal can be used in the charge pump circuit. The VCLK signal becomes available when the
EN1 pin is in the ON state. The VCLK driver is driven by the VO1 voltage. In a design that does not require
VCLK output, leave the VCLK pin open.
8.3.8 Overcurrent Protection
The TPS51275B-1 device has cycle-by-cycle overcurrent limiting control. The inductor current is monitored
during the OFF state and the controller maintains the OFF state during the inductor current is larger than the
overcurrent trip level. To provide both good accuracy and a cost effective solution, the TPS51275B-1 device
supports temperature-compensated MOSFET RDS(on) sensing. Connect the CSx pin to ground (GND) through the
CS voltage setting resistor, RCS. The CSx pin sources CS current (ICS) which is 10 µA typically at room
temperature, and the CSx terminal voltage (VCS= RCS × ICS) should be in the range of 0.2 to 2 V over all
operation temperatures. The trip level is set to the OCL trip voltage (VTRIP) as shown in Equation 2.
R ´I
VTRIP = CS CS + 1 mV
8
(2)
The inductor current is monitored by the voltage between the GND and the SWx pin so that SWx pin is
connected to the drain terminal of the low-side MOSFET properly. The CS pin current has a 4500 ppm/°C
temperature slope to compensate the temperature dependency of the RDS(on). GND is used as the positive
current sensing node so that GND should be connected to the source terminal of the low-side MOSFET.
As the comparison is done during the OFF state, VTRIP sets the valley level of the inductor current. Thus, the load
current at the overcurrent threshold, IOCP, can be calculated as shown in Equation 3.
IIND(ripple )
(VVIN - VOUT ) ´ VOUT
V
V
1
IOCP = TRIP +
= TRIP +
´
RDS(on )
2
RDS(on ) 2 ´ L ´ fSW
VVIN
(3)
In an overcurrent condition, the current to the load exceeds the current to the output capacitor and therefore the
output voltage tends to fall down. Eventually, the output voltage ends up crossing the undervoltage protection
threshold and both channels shut down.
8.3.9 Output Overvoltage and Undervoltage Protection
The TPS51275B-1 device asserts the overvoltage protection (OVP) when the VFBx voltage reaches the OVP-trip
threshold level. When an OVP event is detected, the controller changes the output target voltage to 0 V which
usually turns off the DRVHx pin and forces the DRVLx pin to turn on. When the inductor current begins to flow
through the low-side MOSFET and reaches the negative OCL, the DRVLx pin is turned off and the DRVHx pin is
turned on. After the on-time expires, the DRVHx pin is turned off and the DRVLx pin is turned on again. This
action minimizes the output node undershoot because of LC resonance. When the VFBx pin reaches 0 V, the
driver output is latched as the DRVHx pin turns off, the DRVLx pin turns on. The undervoltage protection (UVP)
latch is set when the VFBx voltage remains lower than UVP trip threshold voltage for 250 µs or longer. In this
fault condition, the controller latches the DRVHx and DRVLx pins low and discharges the outputs. The UVP
detection function is enabled after 4.3 ms of SMPS operation to ensure startup.
8.3.10 Undervoltage Lockout Protection
The TPS51275B-1 device has undervoltage lockout (UVLO) protection at the VIN, VREG5, and VREG3 pins.
When each voltage is lower than the respective UVLO threshold voltage, both SMPSs are shut-off. The UNVLO
is a non-latch protection.
8.3.11 Over-Temperature Protection (OTP)
The TPS51275B-1 device features an internal temperature monitor. If the temperature exceeds the threshold
value (typically 155°C), the TPS51275B-1 device, including the regulators, shuts off. The OTP is anon-latch
protection.
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8.4 Device Functional Modes
8.4.1 D-CAP Mode
From small-signal loop analysis, a buck converter using D-CAP mode can be simplified as shown in Figure 17.
TPS51275B-1
Switching Modulator
VIN
DRVH
R1
R2
L
VFB
PWM
+
+
Control
Logic
and
Divider
VOUT
DRVL
IIND
IC
IOUT
VREF
ESR
RLOAD
Voltage
Divider
VC
COUT
Output
Capacitor
UDG-12111
Figure 17. Simplifying the Modulator
The output voltage is compared with the internal reference voltage after the divider resistors, R1 and R2. The
PWM comparator determines the timing to turn on the high-side MOSFET. The gain and speed of the
comparator is high enough to keep the voltage at the beginning of each ON cycle substantially constant. For the
loop stability, the 0-dB frequency, ƒ0, defined in Equation 4 must be lower than 1/4 of the switching frequency.
f
1
f0 =
£ SW
2p ´ ESR ´ COUT
4
(4)
As ƒ0 is determined solely by the output capacitor characteristics, the loop stability during D-CAP mode is
determined by the capacitor chemistry. For example, specialty polymer capacitors have output capacitance in the
order of several hundred micro-Farads and ESR in range of 10 mΩ. These capacitors yield an f0 value on the
order of 100 kHz or less and the loop is stable. However, ceramic capacitors have ƒ0 at more than 700 kHz,
which is not suitable for this operational mode.
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The TPS51275B-1 device is typically used as a dual-synchronous buck controller, which converts an input
voltage ranging from 5 to 24 V, to output voltage of 5 V and 3.3 V (respectively). The device is targeted for
power-supply solutions for notebook and desktop computer systems.
9.2 Typical Application
VIN
0.1 µF
Q1
6.8 W
L1
3.3 µH
VOUT
5V
to
8A
10 µF × 2
U1
TPS51275B-1
10 µF × 2
12 VIN
0.1 µF
17 VBST1
VBST2
16 DRVH 1
DRVH 2 10
18 SW1
C1
SW2
9
8.2 W
L2
2.2 µH
8
C2
15 DRVL 1
15 kW
13 kW
DRVL 2 11
14 VO1
41.2 kW
10 kW
Q2
2
VFB1
VFB2
4
1
CS1
CS2
5
PGOOD
7
PGOOD
EN2
6
EN 3.3 V
VREG3
3
VREG
(3.3-V LDO)
19 VCLK
0.1 µF
0.1 µF
20 EN1
EN 5V
Charge-pump
Output
VREG5
(5-V LDO)
D1
41.2 kW
1 µF
0.1 µF
0.1 µF
13 VREG5
VOUT
3.3 V
to
8A
20 kW
1 µF
UDG-12094
GND
Figure 18. Detailed Application Schematic
9.2.1 Design Requirements
For this design example, use the parameters listed in Table 2.
Table 2. Design Parameters
PARAMETER
VALUE
Input voltage range
5.5 to 24 V
Channel 1 output voltage
5V
Channel 1 output voltage
8A
Channel 2 output voltage
3.3 V
Channel 2 output voltage
8A
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9.2.2 Detailed Design Procedure
9.2.2.1 External Components Selection
The external components selection is relatively simple for a design using D-CAP mode. Table 3 lists the key
external components that are recommended for this application design (see Figure 18).
Table 3. Key External Components
REFERENCE
DESIGNATOR
FUNCTION
L1
Output Inductor (5 VOUT)
MANUFACTURER
PART NUMBER
Alps
GLMC3R303A
L2
Output Inductor (3.3 VOUT)
Alps
GLMC2R203A
C1
Output Capacitor (5 VOUT)
SANYO
6TPE220MAZB × 2
C2
Output Capacitor (3.3 VOUT)
SANYO
6TPE220MAZB × 2
Q1
MOSFET (5 VOUT)
TI
CSD87330Q3D
Q2
MOSFET (3.3 VOUT)
TI
CSD87330Q3D
9.2.2.1.1 Step 1. Determine the Value of R1 and R2
The recommended value of R2 is between 10 kΩ and 20 kΩ. Use Equation 5 to calculate the value of R1.
R1 =
(VOUT - 0.5 ´ VRIPPLE - 2 ) ´ R2
2
(5)
9.2.2.1.2 Step 2. Select the Inductor
The inductance value should be determined to give the ripple current of approximately ½ to ¼ of maximum
output current and less than half of OCL (valley) threshold. A larger ripple current increases the output ripple
voltage, improves signal-to-noise ratio, and helps ensure stable operation.
(VVIN(max) - VOUT ) ´ VOUT
(VVIN(max) - VOUT ) ´ VOUT
1
2
L=
´
=
´
IIND(ripple) ´ fSW
VVIN(max)
IOUT(max) ´ fSW
VVIN(max)
(6)
The calculated inductance for channel1 and channel2 is 3.3 µH and 2 µH, respectively. For this design, select
the inductance values of 3.3 µH and 2.2 µH for these two channels.
The inductor must also have low DCR to achieve good efficiency, as well as enough room above the peak
inductor current before saturation. Use Equation 7 to calculate the peak inductor current.
(VVIN(max) - VOUT ) ´ VOUT
V
1
IIND(peak) = TRIP +
´
RDS(on) L ´ fSW
VVIN(max)
(7)
9.2.2.1.3 Step 3. Select Output Capacitors
Organic semiconductor capacitors or specialty polymer capacitors are recommended. Determine the ESR to
meet the required ripple voltage. Use Equation 8 to quickly calculate the ESR.
V
´ 20 mV ´ (1 - D) 20 mV ´ L ´ fSW
ESR = OUT
=
2 V ´ IIND(ripple )
2V
where
•
•
D as the duty-cycle factor
the required output ripple voltage slope is approximately 20 mV per tSW (switching period) in terms of the VFBx
pin
(8)
The calculated minimum-required ESR for channel1 and channel2 is 9.9 mΩ and 7.8 mΩ, respectively. For this
design, use two 220-µF, 35-mΩ polymer capacitors in parallel for each channel. The equivalent ESR is 17.5 mΩ
which meets the minimum ESR requirement. Using a value of 440 µF for the output capacitor and 17.5 mΩ of
ESR, the resulting value of the 0-dB frequency, f0 (see Equation 4), is approximately 21 kHz which is much less
than fSW / 4 for both channels.
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VVOUT
Slope (1)
Jitter
(2)
Slope (2)
Jitter
20 mV
(1)
VREF
VREF + Noise
tON
tOFF
UDG-12012
Figure 19. Ripple Voltage Slope and Jitter Performance
9.2.3 Application Curves
OUT1
2 V/div
OUT2
2 V/div
OUT2
2 V/div
OUT1
2 V/div
PGOOD
5 V/div
PGOOD
5 V/div
EN1 = EN2
5 V/div
EN1 = EN2
5 V/div
Time: 10 ms
Time: 1 ms
Figure 21. Shutdown
Figure 20. Startup
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OUT1
100 mV/div
OUT1
100 mV/div
OUT2
100 mV/div
OUT2
100 mV/div
SW1
10 V/div
SW2
10 V/div
IND1
5 A/div
IND2
5 A/div
Time: 100 µs
Time: 100 µs
IOUT1 = 0 to 3 A
IOUT2 = 0 A
VVIN = 7.4 V
IOUT1 = 0 A
Figure 22. 5-V Load Transient
VVIN = 7.4 V
Figure 23. 3.3-V Load Transient
VREG5
200 mV/div
VREG3
200 mV/div
VO1
1 V/div
VO1
1 V/div
Time: 100 ms
Time: 100 ms
Figure 24. 5-V Switch Over
20
IOUT2 = 0 to 3 A
Figure 25. 3.3-V Switch Over
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10 Power Supply Recommendations
The TPS51275B-1 device is designed to operate with an input supply-voltage range of 5 to 24 V. Ensure that the
power-supply voltage in this range.
11 Layout
11.1 Layout Guidelines
Good layout is essential for stable power-supply operation. Follow these guidelines for an efficient PCB layout.
11.1.1 Placement
• Place voltage setting resistors close to the device pins.
• Place bypass capacitors for the VREG5 and VREG3 regulators close to the device pins.
11.1.2 Routing (Sensitive Analog Portion)
• Use small copper space for the VFBx pins. Short and narrow traces are available to avoid noise coupling.
• Connect the VFB resistor trace to the positive node of the output capacitor. Routing the inner layer away from
power traces is recommended.
• Use short and wide trace from the VFB resistor to vias to GND (internal GND plane).
11.1.3 Routing (Power portion)
• Use wider and shorter traces of the DRVLx pin for the low-side gate drivers to reduce stray inductance.
• Use the parallel traces of the SWx and DRVHx pins for the high-side MOSFET gate drive in a same layer or
on adjoin layers, and keep these traces away from the DRVLx pin.
• Use wider and shorter traces between the source terminal of the high-side MOSFET and the drain terminal of
the low-side MOSFET
• The thermal pad is the GND terminal of this device. Five or more vias with 0.33-mm (13-mils) diameter
connected from the thermal pad to the internal GND plane should be used to have strong GND connection
and help heat dissipation.
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11.2 Layout Example
GND
VIN
input
capacitor
Output
capacitor
SW1
To enable
control
Route on
opposite side
VIN
CS1
SW
TG
SW
TGR
BG
VO1
GND
VIN
input
capacitor
VREG5
VREG3
VIN
VFB2
VBST2
DRVH2
SW2
EN2
PGOOD
CS2
Output
capacitor
DRVL2
SW2
Exposed
thermal pad
area
Connected to
power ground
on internal or
bottom layer
VIN
DRVL1
VFB1
Connected to
VOUT2
VOUT1
SW
DRVH1
SW1
VBST1
EN1
Connected to
VOUT1
VCLK
VIN
Output
inductor
To enable
control
VIN
SW
VIN
SW
TG
SW
TGR
BG
Output
inductor
VOUT2
VIA to Ground Plane
Figure 26. TPS51275B-Q1 Layout Example
12 Device and Documentation Support
12.1 Device Support
12.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
12.2 Trademarks
D-CAP, Out-of-Audio are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
12.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
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13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS51275B-1RUKR
ACTIVE
WQFN
RUK
20
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
1275B1
TPS51275B-1RUKT
ACTIVE
WQFN
RUK
20
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
1275B1
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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