TPS51716RUKT

Product Folder Sample & Buy Support & Community Tools & Software Technical Documents Reference Design TPS51716 SLUSB94A – OCTOBER 2012 – REVISED SEPTEMBER 2016 TPS51716 Complete DDR2, DDR3, DDR3L, LPDDR3, and DDR4 Memory Power Solution Synchronous Buck Controller, 2-A LDO, With Buffered Reference 1 Features 3 Description • The TPS51716 provides a complete power supply for DDR2, DDR3, DDR3L, LPDDR3, and DDR4 memory systems in the lowest total cost and minimum space. It integrates a synchronous buck regulator controller (VDDQ) with a 2-A sink/source tracking LDO (VTT) and buffered low noise reference (VTTREF). The TPS51716 employs D-CAP2 mode coupled with 500 kHz or 670 kHz operating frequencies that supports ceramic output capacitors without an external compensation circuit. The VTTREF tracks VDDQ/2 with excellent 0.8% accuracy. The VTT, which provides 2-A sink/source peak current capabilities, requires only 10 μF of ceramic capacitance. In addition, the device features a dedicated LDO supply input. 1 • • • Synchronous Buck Controller (VDDQ) – Conversion Voltage Range: 3 to 28 V – Output Voltage Range: 0.7 to 1.8 V – 0.8% VREF Accuracy – D-CAP2™ Mode for Ceramic Output Capacitors – Selectable 500-kHz/670-kHz Switching Frequencies – Optimized Efficiency at Light and Heavy Loads With Auto-Skip Function – Supports Soft-Off in S4/S5 States – OCL/OVP/UVP/UVLO Protections – Powergood Output 2-A LDO (VTT), Buffered Reference (VTTREF) – 2-A (Peak) Sink and Source Current – Requires Only 10-μF of Ceramic Output Capacitance – Buffered, Low Noise, 10-mA VTTREF Output – 0.8% VTTREF, 20-mV VTT Accuracy – Support High-Z in S3 and Soft-Off in S4/S5 Thermal Shutdown 20-Pin, 3 mm × 3 mm, WQFN Package 2 Applications • • DDR2, DDR3, DDR3L, LPDDR3, and DDR4 Memory Power Supplies SSTL_18, SSTL_15, SSTL_135, and HSTL Termination The TPS51716 provides rich, useful functions as well as excellent power supply performance. It supports flexible power state control, placing VTT at high-Z in S3 and discharging VDDQ, VTT and VTTREF (softoff) in S4/S5 state. It includes programmable OCL with low-side MOSFET RDS(on) sensing, OVP/UVP/UVLO and thermal shutdown protections. TI offers the TPS51716 in a 20-pin, 3 mm × 3 mm, WQFN package and specifies it for an ambient temperature range between –40°C and 85°C. Device Information(1) PART NUMBER PACKAGE TPS51716 WQFN (20) BODY SIZE (NOM) 3.00 mm × 3.00 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Block Diagram VIN 5VIN PGND PGND TPS51716 VBST 15 12 V5IN S3 17 S3 S5 16 S5 VDDQ DRVH 14 SW 13 DRVL 11 6 VREF PGND 10 PGOOD 20 8 REFIN 7 GND VDDQSNS 9 VLDOIN 2 VTT 3 19 MODE VTTSNS 1 18 TRIP VTTGND 4 VTTREF 5 Powergood VTT VTTREF UDG-12146 AGND PGND AGND PGND Copyright © 2016, Texas Instruments Incorporated 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TPS51716 SLUSB94A – OCTOBER 2012 – REVISED SEPTEMBER 2016 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 4 6.1 6.2 6.3 6.4 6.5 6.6 4 4 5 5 6 8 Absolute Maximum Ratings ...................................... ESD Ratings.............................................................. Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics........................................... Typical Characteristics .............................................. Detailed Description ............................................ 12 7.1 Overview ................................................................. 12 7.2 Functional Block Diagram ....................................... 12 7.3 Feature Description................................................. 13 7.4 Device Functional Modes........................................ 16 8 Application and Implementation ........................ 18 8.1 Application Information............................................ 18 8.2 Typical Application ................................................. 18 9 Power Supply Recommendations...................... 22 10 Layout................................................................... 23 10.1 Layout Guidelines ................................................. 23 10.2 Layout Example .................................................... 24 11 Device and Documentation Support ................. 25 11.1 11.2 11.3 11.4 11.5 Device Support...................................................... Documentation Support ........................................ Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 25 25 25 25 25 12 Mechanical, Packaging, and Orderable Information ........................................................... 25 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Original (October 2012) to Revision A Page • Added ESD Ratings table, Detailed Description section, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section ...................................................................................................................... 1 • Updated the Title From: Complete DDR2, DDR3, DDR3L, and LPDDR3 Memory Power Solution To: Complete DDR2, DDR3, DDR3L, LPDDR3, and DDR4 Memory Power ............................................................................................... 1 • Changed Applications list From: DDR2/DDR3/DDR3L/LPDDR3 Memory Power Supplies To: DDR2, DDR3, DDR3L, LPDDR3, and DDR4 Memory Power Supplies ...................................................................................................................... 1 2 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: TPS51716 TPS51716 www.ti.com SLUSB94A – OCTOBER 2012 – REVISED SEPTEMBER 2016 5 Pin Configuration and Functions PGOOD MODE TRIP S3 S5 RUK Package 20-Pin WQFN Top View 20 19 18 17 16 VTTSNS 1 15 VBST VLDOIN 2 14 DRVH VTT 3 13 SW Thermal Pad VTTREF 5 11 DRVL VREF 6 7 8 9 10 PGND V5IN VDDQSNS 12 REFIN 4 GND VTTGND Pin Functions PIN NAME NO. DRVH 14 DRVL GND I/O DESCRIPTION O High-side MOSFET gate driver output. 11 O Low-side MOSFET gate driver output. 7 — Signal ground. MODE 19 I PGND 10 — Gate driver power ground. RDS(on) current sensing input(+). PGOOD 20 O Powergood signal open drain output. PGOOD goes high when VDDQ output voltage is within the target range. REFIN 8 I Reference input for VDDQ. Connect to the midpoint of a resistor divider from VREF to GND. Add a capacitor for stable operation. SW 13 S3 17 I S3 signal input. (See Table 1) S5 16 I S5 signal input. (See Table 1) TRIP 18 I Connect resistor to GND to set OCL at VTRIP/8. Output 10-μA current at room temperature, TC = 4700 ppm/°C. VBST 15 I High-side MOSFET gate driver bootstrap voltage input. Connect a capacitor from the VBST pin to the SW pin. VDDQSNS 9 I VDDQ output voltage feedback. Reference input for VTTREF. Also serves as power supply for VTTREF. VLDOIN 2 I Power supply input for VTT LDO. Connect VDDQ in typical application. VREF 6 O 1.8-V reference output VTT 3 O VTT 2-A LDO output. Need to connect 10 μF or larger capacitance for stability. VTTGND 4 — Power ground for VTT LDO VTTREF 5 O Buffered VTT reference output. Need to connect 0.22 μF or larger capacitance for stability. VTTSNS 1 I VTT output voltage feedback. V5IN 12 I 5-V power supply input for internal circuits and MOSFET gate drivers. Thermal pad — — Thermal pad. Connect directly to system GND plane with multiple vias. Connect resistor to GND to configure switching frequency, control mode and discharge mode. (See Table 2) I/O High-side MOSFET gate driver return. RDS(on) current sensing input(–). Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: TPS51716 3 TPS51716 SLUSB94A – OCTOBER 2012 – REVISED SEPTEMBER 2016 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) MIN MAX VBST –0.3 36 VBST (3) –0.3 6 –5 30 VLDOIN, VDDQSNS, REFIN –0.3 3.6 VTTSNS –0.3 3.6 PGND, VTTGND –0.3 0.3 V5IN, S3, S5, TRIP, MODE –0.3 6 –5 36 SW Input voltage (2) DRVH Output voltage (2) DRVH (3) –0.3 6 VTTREF, VREF –0.3 3.6 VTT –0.3 3.6 DRVL –0.3 6 PGOOD –0.3 (1) (2) (3) V V 6 Junction temperature, TJ Storage temperature, Tstg UNIT –55 125 °C 150 °C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to the network ground terminal unless otherwise noted. Voltage values are with respect to the SW terminal. 6.2 ESD Ratings VALUE V(ESD) (1) (2) 4 Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±2000 Charged-device model (CDM), per JEDEC specification JESD22-C101 (2) ±500 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: TPS51716 TPS51716 www.ti.com SLUSB94A – OCTOBER 2012 – REVISED SEPTEMBER 2016 6.3 Recommended Operating Conditions MIN Supply voltage 5.5 VBST –0.1 33.5 VBST (1) –0.1 5.5 –3 28 SW (2) –4.5 28 VLDOIN, VDDQSNS, REFIN –0.1 3.5 VTTSNS –0.1 3.5 PGND, VTTGND –0.1 0.1 S3, S5, TRIP, MODE –0.1 5.5 –3 33.5 DRVH Output voltage range TA (1) (2) MAX 4.5 SW Input voltage range NOM V5IN DRVH (1) –0.1 5.5 DRVH (2) –4.5 33.5 VTTREF, VREF –0.1 3.5 VTT –0.1 3.5 DRVL –0.1 5.5 PGOOD –0.1 5.5 Operating free-air temperature –40 85 UNIT V V V °C Voltage values are with respect to the SW terminal. This voltage should be applied for less than 30% of the repetitive period. 6.4 Thermal Information TPS51716 THERMAL METRIC (1) RUK (WQFN) UNIT 20 PINS RθJA Junction-to-ambient thermal resistance 94.1 °C/W RθJC(top) Junction-to-case (top) thermal resistance 58.1 °C/W RθJB Junction-to-board thermal resistance 64.3 °C/W ψJT Junction-to-top characterization parameter 31.8 °C/W ψJB Junction-to-board characterization parameter 58.0 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 5.9 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: TPS51716 5 TPS51716 SLUSB94A – OCTOBER 2012 – REVISED SEPTEMBER 2016 www.ti.com 6.5 Electrical Characteristics over operating free-air temperature range, VV5IN = 5 V, VLDOIN is connected to VDDQ output, VMODE= 0 V, VS3= VS5= 5 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY CURRENT IV5IN(S0) V5IN supply current, in S0 TA = 25°C, No load, VS3 = VS5 = 5 V 590 IV5IN(S3) V5IN supply current, in S3 TA = 25°C, No load, VS3 = 0 V, VS5 = 5 V 500 IV5INSDN V5IN shutdown current TA = 25°C, No load, VS3 = VS5 = 0 V 1 μA IVLDOIN(S0) VLDOIN supply current, in S0 TA = 25°C, No load, VS3 = VS5 = 5 V 5 μA IVLDOIN(S3) VLDOIN supply current, in S3 TA = 25°C, No load, VS3 = 0 V, VS5 = 5 V 5 μA IVLDOINSDN VLDOIN shutdown current TA = 25°C, No load, VS3 = VS5 = 0 V 5 μA V μA μA VREF OUTPUT IVREF = 30 μA, TA = 25°C VVREF Output voltage IVREFOCL Current limit 1.8000 0 μA ≤ IVREF