TPS53219ARGTR

Order Now Product Folder Support & Community Tools & Software Technical Documents Reference Design TPS53219A SLUSAU4B – DECEMBER 2011 – REVISED FEBRUARY 2019 TPS53219A 3-V to 28-V Input, D-CAP, Eco-Mode™, synchronous buck controller 1 Features 2 Applications • • • • • • • • • • • • • 1 • • • • • • • • • Conversion input voltage range: 3 V to 28 V VDD input voltage range: 4.5 V to 25 V Output voltage range: 0.6 V to 5.5 V Wide output load range: 0 A to > 20 A Built-in 0.6-V (±0.8%) reference Built-in LDO linear voltage regulator Auto-skip Eco-Mode™ for light-load efficiency D-CAP™ mode with 100-ns load-step response Adaptive ON-time control architecture with 8 selectable frequency settings 4700ppm/°C RDS(on) current sensing 0.7-ms, 1.4-ms, 2.8-ms and 5.6-ms selectable internal voltage servo soft start Pre-charged start-up capability Built-in output discharge Open-drain power-good output Integrated boost switch Built-In OVP/UVP/OCP Thermal shutdown (non-latch) 3-mm × 3-mm QFN, 16-Pin (RGT) package Storage computers Server computers Multi-function printers Embedded computing 3 Description The TPS53219A device is a small-sized single buck controller with adaptive ON-time D-CAP mode control. The device is suitable for low output voltage, high current, PC system power rail and similar pointof-load (POL) power supplies in digital consumer products. The small package and minimal pin-count save space on the PCB, while the dedicated EN pin and pre-set frequency selections simplify the power supply design. The skip mode at light load conditions, strong gate drivers, and low-side FET RDS(on) current sensing supports low-loss and high efficiency, over a broad load range. The conversion input voltage (highside FET drain voltage) range is between 4.5 V and 25 V, and the output voltage range is between 0.6 V and 5.5 V. The TPS53219A is available in a 16-pin, QFN package specified from –40°C to +85°C. Device Information(1) PART NUMBER TPS53219A PACKAGE QFN (16) BODY SIZE (NOM) 3.00 mm × 3.00 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Simplified Schematic VIN VOUT VREG VIN 16 EN 1 TRIP 2 EN 15 14 VIN SW DRVL 11 TG SW TGR BG VDRV 10 VFB VREG 4 SW PGOOD NC VBST DRVH SW 12 TPS53219A 3 CSD86350 13 9 RF Pad MODE VDD 5 6 VDD GND PGND 7 PGND 8 UDG-11273 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TPS53219A SLUSAU4B – DECEMBER 2011 – REVISED FEBRUARY 2019 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 4 6.1 6.2 6.3 6.4 6.5 6.6 4 4 4 5 5 7 Absolute Maximum Ratings ...................................... ESD Ratings.............................................................. Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics........................................... Typical Characteristics .............................................. Detailed Description ............................................ 10 7.1 Overview ................................................................. 10 7.2 Functional Block Diagram ....................................... 11 7.3 Feature Description................................................. 11 7.4 Device Functional Modes........................................ 16 8 Application and Implementation ........................ 17 8.1 Application Information............................................ 17 8.2 Typical Applications ................................................ 17 9 Power Supply Recommendations...................... 22 10 Layout................................................................... 22 10.1 Layout Guidelines ................................................. 22 10.2 Layout Example .................................................... 23 11 Device and Documentation Support ................. 27 11.1 11.2 11.3 11.4 11.5 Receiving Notification of Documentation Updates Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 27 27 27 27 27 12 Mechanical, Packaging, and Orderable Information ........................................................... 27 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision A (December 2015) to Revision B • Page Editorial changes only, no technical changes ....................................................................................................................... 1 Changes from Original (December 2011) to Revision A Page • Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1 • Added more complete pin descriptions. ................................................................................................................................. 3 2 Submit Documentation Feedback Copyright © 2011–2019, Texas Instruments Incorporated Product Folder Links: TPS53219A TPS53219A www.ti.com SLUSAU4B – DECEMBER 2011 – REVISED FEBRUARY 2019 5 Pin Configuration and Functions TRIP 1 EN 2 PGOOD N/C VBST DRVH RGT Package 16-Pin QFN With Exposed Thermal Pad Top View 16 15 14 13 12 SW 11 DVRL TPS53219A RF 4 9 VREG 5 6 7 8 PGND VDRV GND 10 VDD 3 MODE VFB Pin Functions PIN TYPE (1) DESCRIPTION NAME NO. DRVH 13 O High-side MOSFET driver output. The SW node referenced floating driver. The gate drive voltage is defined by the voltage across VBST to SW node bootstrap flying capacitor. DRVL 11 O Synchronous MOSFET driver output. The PGND referenced driver. The gate drive voltage is defined by VDRV voltage. EN 2 I Enable pin. Place a 1-kΩ resistor in series with this pin if the source voltage is higher than 5.5 V. GND 7 G Ground pin. This is the ground of internal analog circuitry. Connect to GND plane at single point. MODE 5 I Soft-start and skip/CCM selection. Connect a resistor to select soft-start time using Table 1. The softstart time is detected and stored into internal register during start-up. NC 15 – No connection. PAD – – Thermal pad. Use five vias to connect to GND plane. PGOOD 16 O Open-drain power good flag. Provides 1-ms start-up delay after the VFB pin voltage falls within specified limits. When VFB goes out specified limits PGOOD goes low after a 2-µs delay. PGND 8 G Power ground. Connect to GND plane. RF 4 I Switching frequency selection. Connect a resistor to GND or VREG to select switching frequency using Table 2. The switching frequency is detected and stored during the start-up. SW 12 P Output of converted power. Connect this pin to the output inductor. TRIP 1 I OCL detection threshold setting pin. 10 µA at room temp, 4700 ppm/°C current is sourced and set the OCL trip voltage as follows. VOCL = VTRIP/8 spacer ( VTRIP ≤ 3 V, VOCL ≤ 375 mV) VBST 14 P Supply input for high-side FET gate driver (boost terminal). Connect a capacitor from this pin to SWnode. Internally connected to VREG through bootstrap MOSFET switch. VDD 6 P Controller power supply input. The input range is from 4.5 V to 25 V. VDRV 10 I Gate drive supply voltage input. Connect to VREG if using LDO output as gate drive supply. VFB 3 I Output feedback input. Connect this pin to VOUT through a resistor divider. VREG 9 O 6.2-V LDO output. This is the supply of internal analog circuitry and driver circuitry. (1) I=Input, O=Output, P=Power, G=Ground Submit Documentation Feedback Copyright © 2011–2019, Texas Instruments Incorporated Product Folder Links: TPS53219A 3 TPS53219A SLUSAU4B – DECEMBER 2011 – REVISED FEBRUARY 2019 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) Input voltage MIN MAX VBST –0.3 37 VBST (2) –0.3 7 VDD –0.3 28 –2 30 DC SW Pulse