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TPS62134ARGTR

TPS62134ARGTR

  • 厂商:

    BURR-BROWN(德州仪器)

  • 封装:

    VQFN-16_3X3MM-EP

  • 描述:

    IC REG BUCK PROG 3.2A 16QFN

  • 数据手册
  • 价格&库存
TPS62134ARGTR 数据手册
Sample & Buy Product Folder Support & Community Tools & Software Technical Documents TPS62134A, TPS62134B, TPS62134C, TPS62134D SLVSC20E – JANUARY 2015 – REVISED OCTOBER 2016 TPS62134x, 17-V Input, Step-down Converter With Low-Power Mode Input for Intel Skylake Platform 1 Features • • 1 • • • • • • • • • • • • DCS-Control™ Architecture Supports Low-Power Mode for System Standby Mode Power Save Mode for Light Load Efficiency Selectable Fixed Output Voltage (0.7 V to 1.05 V) Low Power Mode Logic Input Quiescent Current of 20 µA Input Voltage Range: 3 V to 17 V Output Current: up to 3.2 A Programmable Soft Start Power Good Output Short Circuit Protection Single-ended Remote Sense Thermal Shutdown Protection Available in a 3-mm × 3-mm, VQFN-16 Package With a wide operating input-voltage range of 3 to 17 V, the devices are ideally suited for systems powered from either a Li-Ion or other batteries as well as from 12-V intermediate power rails. The devices have a low-power mode where the output voltage is reduced by using the LPM pin. In addition, the devices support dynamic output-voltage change by using the VIDx pins. The LPM and VIDx pins help the system minimize power consumption in different operating modes. The output-voltage startup ramp is controlled by the SS pin. The power sequencing is configurable by the enable (EN) and power good (PG) pins. In powersave mode, the devices show quiescent current of approximately 20 μA which maintains high efficiency over the entire load range. Short circuit protection and thermal shutdown protect the IC and external components from heavy current when the output is shorted to ground. The device is available in a 3-mm × 3-mm 16-pin VQFN package with thermal pad. Device Information(1) 2 Applications • • • • • Intel Skylake™ Platform Ultrabook, Notebook, PC Standard 12-V Rail Supply POL Supply from 1 to 4 Cells Li-Ion Battery Solid-State Disk Drive Embedded System 3 Description PART NUMBER PACKAGE BODY SIZE (NOM) TPS62134A TPS62134B TPS62134C VQFN 3.00mm x 3.00mm TPS62134D (1) For all available packages, see the orderable addendum at the end of the data sheet. The TPS62134x family of devices is an easy-to-use, synchronous step-down DC-DC converter, compatible with Intel Skylake platform applications such as Ultrabooks™ and notebooks. The high performance DCS-Control™ architecture provides fast transient response as well as high output voltage accuracy. spacer spacer Typical Application Circuit VI 3 to 17 V C1 22 µF PVIN SW AVIN VOS EN FBS VID0 Host SS C3 470 pF C2 47 µF PG AGND PGND 100 VO 0.95 V, 3 A 90 VDD R3 499 kΩ VID1 LPM TPS62134A Efficiency L1 1 µH V(PG) Efficiency (%) TPS62134A 80 70 VI = 5 V VI = 6 V VI = 7.2 V VI = 8.4 V VI = 10.8 V VI = 12 V 60 50 VO = 0.95 V 40 0.001 0.01 0.02 0.05 0.1 0.2 Load (A) 0.5 1 2 3 45 D002 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TPS62134A, TPS62134B, TPS62134C, TPS62134D SLVSC20E – JANUARY 2015 – REVISED OCTOBER 2016 www.ti.com Table of Contents 1 2 3 4 5 6 7 8 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Device Comparison Table..................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 3 4 7.1 7.2 7.3 7.4 7.5 7.6 4 4 4 4 5 6 Absolute Maximum Ratings ..................................... ESD Ratings.............................................................. Recommend Operating Conditions........................... Thermal Information .................................................. Electrical Characteristic............................................. Typical Characteristics .............................................. Detailed Description .............................................. 7 8.1 8.2 8.3 8.4 Overview ................................................................... 7 Functional Block Diagram ......................................... 7 Feature Description................................................... 8 Device Functional Modes........................................ 11 9 Application and Implementation ........................ 12 9.1 Application Information............................................ 12 9.2 Typical Application .................................................. 12 10 Power Supply Recommendations ..................... 17 11 Layout................................................................... 18 11.1 Layout Guidelines ................................................. 18 11.2 Layout Example .................................................... 18 11.3 Thermal Considerations ........................................ 19 12 Device and Documentation Support ................. 20 12.1 12.2 12.3 12.4 12.5 12.6 12.7 12.8 Device Support...................................................... Documentation Support ........................................ Related Links ........................................................ Receiving Notification of Documentation Updates Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 20 20 20 20 20 20 20 21 13 Mechanical, Packaging, and Orderable Information ........................................................... 21 4 Revision History Changes from Revision D (April 2015) to Revision E • Page Added Note to Power-Good Output (PG). PG blanking time condition for TPS62134A and TPS62134C ........................... 9 Changes from Revision C (January 2015) to Revision D • Page Added the Program Output Voltage with External Resistor Divider section......................................................................... 14 Changes from Revision B (August 2014) to Revision C Page • Changed the Device Information table .................................................................................................................................. 1 • Added the Device Comparison Table .................................................................................................................................... 3 • Moved the Storage temperature From the Handling Ratings table to the Absolute Maximum Ratings (1) table..................... 4 • Changed the Handling Ratings table to the ESD Ratings table ............................................................................................. 4 • Changed the Output voltage accuracy, PSM mode MAX value From: 2% To: 3%, Add test condition: LPM = High. .......... 5 Changes from Revision A (August 2014) to Revision B Page • Add new device to Device Comparison Table ....................................................................................................................... 3 • Updated the Functional Block Diagram image ....................................................................................................................... 7 • Add new device to Table 1 ..................................................................................................................................................... 9 • Updated the Figure 16 in the Application Curves section .................................................................................................... 15 • Updated Equation 8 ............................................................................................................................................................. 17 Changes from Original (August 2014) to Revision A • 2 Page Switched the pin names of pin 8 and 9 in the Pin Functions table ........................................................................................ 3 Submit Documentation Feedback Copyright © 2015–2016, Texas Instruments Incorporated Product Folder Links: TPS62134A TPS62134B TPS62134C TPS62134D TPS62134A, TPS62134B, TPS62134C, TPS62134D www.ti.com SLVSC20E – JANUARY 2015 – REVISED OCTOBER 2016 5 Device Comparison Table PART NUMBER PACKAGE MARKING TPS62134A 134A TPS62134B 134B TPS62134C 134C TPS62134D 134D OUTPUT VOLTAGE See Table 1 6 Pin Configuration and Functions SS 7 VID1 8 SW SW VOS 1 16 PGND 15 PGND Exposed Thermal PAD 14 LPM 13 EN 9 10 11 12 PVIN 6 2 PVIN AGND 3 AVIN 5 4 VID0 FBS PG RGT Package 16-Pin VQFN With Thermal Pad Top View Pin Functions PIN TYPE DESCRIPTION NO. NAME 1 VOS I SW PWR 4 PG O Output power-good pin. The PG pin is an open drain and requires a pullup resistor. If this pin is not in use, leave it floating. 5 FBS I Output-voltage feedback pin. This pin is used for a positive remote sense of the load voltage. The FBS pin must be connected close to the load-supply node on the output bus. 6 AGND — Analog ground pin. The AGND pin must be connected directly to the exposed thermal pad and common ground plane. 7 SS O Soft-start pin. An external capacitor connected to this pin sets the soft-start time. 8 VID1 9 VID0 I Output-voltage selection pins (VIDx). 10 AVIN I Supply-voltage pin for the internal control circuitry. Connect the AVIN pin to the same source as the PVIN pin. PVIN PWR 13 EN I Enable and disable input pin. An internal pulldown resistor maintains logic-level low if the pin is floating. 14 LPM I Low-power-mode input pin. PGND — Power ground. The PGND pin must be connected directly to the exposed thermal pad and common ground plane. Exposed Thermal Pad — The exposed thermal pad must be connected to the AGND (6) pin, PGND (15 and 16) pins, and common ground plane. The thermal pad must be soldered to achieve appropriate power dissipation and mechanical reliability. 2 3 11 12 15 16 — Output voltage sense pin and connection for the control loop circuitry. The VOS pin must be connected directly at the output capacitor. This pin is a switch node and is connected to the internal MOSFET switches. Connect an inductor between the SW pin and output capacitor. Supply-voltage pins for the internal power stage. Copyright © 2015–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS62134A TPS62134B TPS62134C TPS62134D 3 TPS62134A, TPS62134B, TPS62134C, TPS62134D SLVSC20E – JANUARY 2015 – REVISED OCTOBER 2016 www.ti.com 7 Specifications 7.1 Absolute Maximum Ratings (1) over operating junction temperature range (unless otherwise noted) MIN MAX AVIN, PVIN –0.3 20 EN, SW –0.3 VI + 0.3 SS, PG, VOS, VID0, VID1, LPM –0.3 7 FBS –0.3 3 PG 0 2 mA Operating junction temperature, TJ –40 150 °C Storage temperature, Tstg –65 150 °C Voltage at pins (2) Sink current (1) (2) UNIT V Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to network ground pin. 7.2 ESD Ratings VALUE Human body model (HBM), per ANSI/ESDA/JEDEC JS–001 V(ESD) (1) (2) Electrostatic discharge (1) UNIT ±2000 Charged device model (CDM), per JEDEC specification JESD22C101 (2) V ±500 JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 7.3 Recommend Operating Conditions over operating junction temperature range, unless otherwise noted. VI Input voltage (AVIN, PVIN) V(PG) PG pin pullup resistor voltage IO Output current TJ Operating junction temperature MIN MAX UNIT 3 17 V V 0 6 3 V ≤ VI < 5 V 0 3 5 V ≤ VI ≤ 17 V 0 3.2 –40 125 A °C 7.4 Thermal Information TPS62134x THERMAL METRIC (1) RGT (VQFN) UNIT 16 PINS RθJA Junction-to-ambient thermal resistance 44.2 RθJC(top) Junction-to-case (top) thermal resistance 51.0 RθJB Junction-to-board thermal resistance 16.6 ψJT Junction-to-top characterization parameter 0.9 ψJB Junction-to-board characterization parameter 16.6 RθJC(bot) Junction-to-case (bottom) thermal resistance 3.7 (1) 4 °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report. Submit Documentation Feedback Copyright © 2015–2016, Texas Instruments Incorporated Product Folder Links: TPS62134A TPS62134B TPS62134C TPS62134D TPS62134A, TPS62134B, TPS62134C, TPS62134D www.ti.com SLVSC20E – JANUARY 2015 – REVISED OCTOBER 2016 7.5 Electrical Characteristic TJ = –40 °C to 125 °C and VI = 3 V to 17 V. Typical values at VI = 12 V and TJ = 25 °C, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX 3 17 UNIT SUPPLY VI Input voltage range IQ Operating quiescent current EN = High, no load, device not switching TJ = –40 °C to 85 °C 20 TJ = 125 °C ISD Shutdown current into AVIN and PVIN 35 V µA 58 EN = Low TJ = –40 °C to +85 °C 2 TJ = 125 °C 9 µA 18 VI falling 2.6 2.7 2.8 VI rising 2.8 2.9 3 V(UVLO) Undervoltage lockout threshold TSD(th) Thermal shutdown threshold TJ rising 160 TSD(hys) Thermal shutdown hysteresis TJ falling 20 V °C CONTROL (EN, SS, PG, VIDx, LPM) VIH High-level input threshold voltage (EN, VIDx, LPM) VIL Low-level input threshold voltage (EN, VIDx, LPM) R(PD) Pull down resistor at EN, VIDx, LPM EN, VIDx, LPM = low R(DIS) Output discharge resistor EN = Low, VO = 1 V Ilkg Input leakage current at EN, VIDx, LPM EN, VIDx, LPM = 3.3 V 0.8 0.54 0.47 V 0.3 400 V kΩ 20 kΩ 0.01 1 VO rising 736 760 784 VO falling 696 720 752 µA VTH(PG) Power good threshold DC voltage VOL(PG) Power good output low voltage I(PG) = –2 mA 0.07 0.3 V Ilkg(PG) Input leakage current at PG V(PG) = 1.8 V 1 400 nA td(PG) Power good delay time I(SS) SS pin source current PG rising 140 PG falling 20 2.3 mV µs 2.5 2.7 µA POWER SWITCH rDS(on_H) High-side MOSFET on-resistance VI ≥ 6 V 90 170 rDS(on_L) Low-side MOSFET on-resistance VI ≥ 6 V 40 70 IL High-side MOSFET DC current-limit VI ≥ 5 V, TJ = 25 °C 4.4 5.4 IL(LOW) High-side MOSFET DC current-limit at low output voltage VO ≤ 0.3 V Ilkg(FBS) Input leakage current at FBS V(FBS)= 1.1 V VO(A) Output voltage accuracy ΔVO(ΔIO) Load regulation (2) 3.6 mΩ A 1.6 OUTPUT ΔVO(ΔVI) (1) (2) Line regulation 1 PWM mode –1% PSM mode, LPM = High (1) –1% VI = 7.2 V, IO = 0.5 A to 3.2 A (2) 3 V ≤ VI ≤ 17 V, IO = 1 A 100 nA 1% 3% 0.01 %/A 0.003 %/V This is the accuracy provided by the device itself (line and load regulation effects are not included). External components effective value: L = 1 µH and C(OUT) = 47 µF. Line and load regulation depend on external component selection and layout. Copyright © 2015–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS62134A TPS62134B TPS62134C TPS62134D 5 TPS62134A, TPS62134B, TPS62134C, TPS62134D SLVSC20E – JANUARY 2015 – REVISED OCTOBER 2016 www.ti.com 7.6 Typical Characteristics 40 10 TJ = 40qC TJ = 0qC TJ = 25qC TJ = 85qC TJ = 125qC Shutdown Current (PA) Quiescent Current (PA) 8 30 20 TJ = 40qC TJ = 0qC TJ = 25qC TJ = 85qC TJ = 125qC 10 4 2 0 0 3 5 7 9 11 Input Voltage (V) 13 15 17 D005 Figure 1. Quiescent Current into PVIN and AVIN 6 6 Submit Documentation Feedback 3 5 7 9 11 Input Voltage (V) 13 15 17 D006 Figure 2. Shutdown Current into PVIN and AVIN Copyright © 2015–2016, Texas Instruments Incorporated Product Folder Links: TPS62134A TPS62134B TPS62134C TPS62134D TPS62134A, TPS62134B, TPS62134C, TPS62134D www.ti.com SLVSC20E – JANUARY 2015 – REVISED OCTOBER 2016 8 Detailed Description 8.1 Overview The TPS62134x synchronous switched-mode power converters are based on DCS-Control™ (direct control with seamless transition into power-save mode), an advanced regulation topology that combines the advantages of hysteretic, voltage-mode, and current-mode control including an AC loop that is directly associated to the output voltage. This control loop uses information about output voltage changes and feeds the information directly to a fast comparator stage. The control loop provides immediate response to dynamic load changes. For accurate DC load regulation, a voltage feedback loop is used. The internally compensated regulation network achieves fast and stable operation with small external components and low ESR capacitors. The DCS-Control™ topology supports PWM (pulse width modulation) mode for medium and heavy load conditions and a power-save mode (PSM) at light loads. During PWM mode, the devices operate at the nominal switching frequency in continuous conduction mode (CCM). This frequency is approximately 1 MHz (typical) with a controlled frequency variation depending on the input voltage. If the load current decreases, the converter enters PSM to sustain high efficiency down to very light loads. In PSM, the switching frequency decreases linearly with the load current. Because DCS-Control™ supports both operation modes within one single building block, the transition from PWM to PSM is seamless without effects on the output voltage. 8.2 Functional Block Diagram AVIN Thermal shutdown PVIN PG FBS UVLO PVIN PG Control High-side limit Comparator EN Control logic SW LPM Power control VID0 Gate drive Reference voltage control logic Vref VID1 SW Soft start SS Comparator Direct control and compensation VOS R(DIS) FBS EN Output discharge Vref Error amplifier + Low-side limit Ramp Comparator ton DCS-ControlŒ AGND Copyright © 2015–2016, Texas Instruments Incorporated PGND PGND Submit Documentation Feedback Product Folder Links: TPS62134A TPS62134B TPS62134C TPS62134D 7 TPS62134A, TPS62134B, TPS62134C, TPS62134D SLVSC20E – JANUARY 2015 – REVISED OCTOBER 2016 www.ti.com 8.3 Feature Description 8.3.1 Enable and Shutdown (EN) When the EN pin is set high, the device begins operation. The EN pin allows sequencing from a host or powergood output of another device. The devices enter shutdown mode if the EN pin is pulled low with a shutdown current of 2 µA (typical). During shutdown, the internal power MOSFETs as well as the entire control circuitry are turned off. The output capacitor is smoothly discharged by a 20-kΩ internal resistor through the VOS pin. An internal pulldown resistor of approximately 400 kΩ is connected and maintains EN logic low, if the pin is floating. The pulldown resistor is disconnected if the EN pin is high. 8.3.2 Undervoltage Lockout (UVLO) If the input voltage drops, the undervoltage lockout prevents misoperation of the device by switching off both power MOSFETs. The UVLO threshold is set to 2.7 V (typical). The device is fully operational for voltages above the UVLO threshold and turns off if the input voltage trips the threshold. The converter begins operation again when the input voltage exceeds the threshold by a hysteresis of 200 mV (typical). 8.3.3 Soft-Start (SS) Circuitry The internal soft-start circuitry controls the output-voltage slope during startup. This control avoids excessive inrush current and ensures a controlled output-voltage rise time. The control also prevents unwanted voltage drops from high-impedance power sources or batteries. When the EN pin is set high to begin device operation, the device begins switching after a delay of approximately 50 µs and VO rises up to the nominal value set by the VIDx pins with a slope controlled by an external capacitor connected to the SS pin. Leave the SS pin floating for the fastest startup. The device can startup into a pre-biased output. During monotonic pre-biased startup, both power MOSFETs are not allowed to turn on until the internal ramp of the device sets an output voltage above the pre-bias voltage. If the device is in shutdown mode, undervoltage lockout, or thermal shutdown, an internal resistor pulls the SS pin down to ensure a proper low level. Returning from those states causes a new startup sequence. 8.3.4 Switch Current-Limit and Short Circuit Protection The TPS62134x family of devices is protected against heavy load and short circuit events. If an output short circuit is detected (VO drops below 0.3 V), the switch current limit is reduced to 1.6 A (typical). If the output voltage rises above 0.4 V, the device operates in normal operation again. At heavy loads, the current-limit determines the maximum output current. The current-limit supports output currents of 3 A with input voltages below 5 V and 3.2 A with higher input voltages. If the peak current-limit (IL) is reached, the high-side MOSFET is turned off. Avoiding shoot-through current, the low-side MOSFET is switched on to sink the inductor current. The high-side MOSFET turns on again, only if the current in the low-side MOSFET has decreased below the low-side current-limit threshold of 3.2 A (typical). Because of the internal propagation delay, the actual peak current of the high-side switch typically occurs above the DC value listed in the Electrical Characteristic table, especially in low duty-cycle applications. Use Equation 1 to calculate the dynamic current-limit. V - VO ´ 30 ns IL(dynamic) = IL + I (1) L 8.3.5 Output Voltage and LPM Logic Selection (VIDx and LPM) The output voltage of the TPS62134x family of devices is selected by two VIDx pins and one LPM pin as listed in Table 1. A pulldown resistor of 400 kΩ is internally connected to the VIDx pins and LPM pin to ensure a proper logic level if the pin is high impedance or floating. The pulldown resistors are disconnected if the pins are pulled High. 8 Submit Documentation Feedback Copyright © 2015–2016, Texas Instruments Incorporated Product Folder Links: TPS62134A TPS62134B TPS62134C TPS62134D TPS62134A, TPS62134B, TPS62134C, TPS62134D www.ti.com SLVSC20E – JANUARY 2015 – REVISED OCTOBER 2016 Feature Description (continued) The device has a low power mode (LPM) where the output voltage is reduced or disabled by using the LPM pin. While the LPM pin is asserted, the PG output remains high impedance. The device also achieves a dynamic output-voltage change by using the VIDx pins. This feature helps the system to minimize power consumption in standby or idle mode. The TPS62134B/D devices provide the full current even if the output voltage is set at 0.7 V in LPM mode. Table 1. Output Voltage Selection PART NUMBER (INTEL SKYLAKE VRs) TPS62134A (VCC(IO) Rail) TPS62134B (VCC(PRIM_CORE) Rail) TPS62134C (VCC(EDRAM) / VCC(EOPIO) Rail) TPS62134D (VCC(PRIM_CORE) Rail) LPM LOGIC VID1 LOGIC VID0 LOGIC OUTPUT VOLTAGE (V) 0 x x 0 (LPM) 1 0 0 0.850 1 0 1 0.875 1 1 0 0.950 1 1 1 0.975 0 x x 0.7 (LPM) 1 0 0 0.80 1 0 1 0.85 1 1 0 0.90 1 1 1 0.95 0 x x 0 (LPM) 1 0 0 0.80 1 0 1 0.95 1 1 0 1.00 1 1 1 1.05 0 x x 0.7 (LPM) 1 0 0 0.85 1 0 1 0.90 1 1 0 0.95 1 1 1 1.00 8.3.6 Power-Good Output (PG) The TPS62134x family of devices has a built-in power-good indicator. The PG signal can be used for startup sequencing of multiple rails. The PG pin is an open-drain output that requires a pullup resistor to any voltage below 6 V. The device has a fixed power-good threshold of 760 mV (rising edge) and 720 mV (falling edge). The PG rising edge has a delay time of 140 µs (typical) and a falling edge has a delay time of 20 µs (typical). The PG pin can sink 2-mA of current and maintain the specified logic low level. Table 2 lists the PG logic status in different operation conditions. The PG pin can be left floating if not used. In LPM, the PG signal is latched as high impedance. When the device exits LPM, the PG has a 500-µs blanking time to ensure that the output voltage returns to the nominal value. NOTE For the TPS62134A and TPS62134C, if LPM is exited when the output voltage is between 0.5 V to 0.75 V, the PG pin may not have its 500-µs blanking time and may go briefly low as the output voltage returns to its set-point. To avoid this behavior, do not enter LPM or adjust the load and/or output capacitance or add an extra output discharge circuit to avoid this output voltage range when LPM is exited. The TPS62134A and TPS62134C are not recommended for new Skylake or KabyLake, Intel designs. The TPS62134B or TPS62134D should be used in their place. These parts are pin to pin compatible facilitating a simple replacement. See Table 1 for VID related changes. Copyright © 2015–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS62134A TPS62134B TPS62134C TPS62134D 9 TPS62134A, TPS62134B, TPS62134C, TPS62134D SLVSC20E – JANUARY 2015 – REVISED OCTOBER 2016 www.ti.com Table 2. Power Good Logic PG LOGIC STATUS CONDITIONS HIGH IMPEDANCE √ EN = high, LPM = high, VO > 760 mV Enable LOW √ EN = high, LPM = high, VO < 720 mV √ LPM EN = high, LPM = low LPM, TPS62134B/D EN = high, LPM = Low, VO < 0.3 V √ Shutdown EN = Low √ √ Thermal shutdown UVLO 0.5 V < V(AVIN) < V(UVLO) Power supply removal V(AVIN) < 0.5 V √ √ 8.3.7 Single-Ended Remote Sense (FBS) The devices allow a single-ended remote sense by connecting the FBS pin at the load. This function overcomes the parasitic resistance of the PCB traces and achieves an improved output-voltage regulation at the load. Avoid any noise coupled into the FBS trace. Use a solid ground plane to connect the ground return of the load with the AGND and PGND pins of the device. Connect the AGND and PGND pins directly to exposed thermal pad of the device. Figure 3 shows an example. TPS62134x SW VOS FBS L1 1 µH C2 47 µF C(LOAD) Load Ground Plane Connection AGND PGND Figure 3. Remote Sense Connection 8.3.8 Thermal Shutdown The junction temperature (TJ) of the device is monitored by an internal temperature sensor. If TJ exceeds 160°C (typical), the device goes into thermal shutdown. Both the high-side and low-side power MOSFETs are turned off. When TJ decreases below the hysteresis of 20°C, the converter resumes normal operation, beginning with a soft start. 10 Submit Documentation Feedback Copyright © 2015–2016, Texas Instruments Incorporated Product Folder Links: TPS62134A TPS62134B TPS62134C TPS62134D TPS62134A, TPS62134B, TPS62134C, TPS62134D www.ti.com SLVSC20E – JANUARY 2015 – REVISED OCTOBER 2016 8.4 Device Functional Modes 8.4.1 PWM Operation and Power Save Mode The device operates with pulse width modulation (PWM) in medium and heavy load with a fixed on-time circuitry (ton). Use Equation 2 to calculate the on-time in steady-state operation. V t on = 1 ms ´ O VI (2) The typical PWM switching frequency is 1 MHz. The frequency variation in PWM is controlled and depends on VI, VO, and the inductance. The switching frequency decreases with the input voltage to improve the efficiency in small duty-cycle applications. To maintain high efficiency at light loads, the device enters PSM at the boundary to discontinuous conduction mode (DCM). In PSM, the switching frequency decreases linearly with the load current maintaining high efficiency. Use Equation 3 to calculate the switching frequency in PSM mode. 2 ´ IO ƒS(PSM) = V - VO V t on2 ´ I ´ I VO L (3) See Figure 12 for the switching frequency variation over load and input voltage. Copyright © 2015–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS62134A TPS62134B TPS62134C TPS62134D 11 TPS62134A, TPS62134B, TPS62134C, TPS62134D SLVSC20E – JANUARY 2015 – REVISED OCTOBER 2016 www.ti.com 9 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 9.1 Application Information The TPS62134x family of devices are synchronous step-down converters based on the DCS-Control™ topology. The following section discusses the design of the external components to complete the power-supply design for power rails in the Intel Skylake platform. 9.2 Typical Application TPS62134A VI 3 to 17 V C1 22 µF PVIN SW AVIN VOS EN FBS L1 1 µH VID0 Host C2 47 µF VO 0.95 V, 3 A VDD R3 499 kΩ VID1 PG LPM SS V(PG) AGND C3 470 pF PGND Figure 4. TPS62134A Typical Application 9.2.1 Design Requirements The design guideline provides component selection to operate the device within the values listed in the Recommend Operating Conditions section. Meanwhile, the design meets the time and slew rate requirements of the Intel Skylake platform for VCC(IO), VCC(PRIM_CORE), VCC(EDRAM), and VCC(EOPIO) rails. Table 3 lists the components used for the curves in the Application Curves section. Table 3. List of Components REFERENCE TPS62134x DESCRIPTION MANUFACTURER High efficiency step down converter TI L1 Inductor, 1 µH, XFL4020-102ME Coilcraft C1 Ceramic capacitor, 22 µF, GRM21BR61E226ME44L Murata C2 Ceramic capacitor, 47 µF, GRM21BR60J476ME15L Murata C3 Ceramic capactor, 470 pF, GRM188R71H471KA01D Murata R3 Resistor, 499 kΩ Standard 9.2.2 Detailed Design Procedure 9.2.2.1 Output Filter Selection The first step of the design procedure is the selection of the output-filter components. The combinations listed in Table 4 are used to simplify the output filter component selection. 12 Submit Documentation Feedback Copyright © 2015–2016, Texas Instruments Incorporated Product Folder Links: TPS62134A TPS62134B TPS62134C TPS62134D TPS62134A, TPS62134B, TPS62134C, TPS62134D www.ti.com SLVSC20E – JANUARY 2015 – REVISED OCTOBER 2016 Table 4. Recommended LC Output Filter Combinations (1) OUTPUT CAPACITOR INDUCTOR 22 µF 47 µF 100 µF 200 µF √ (2) √ √ 400 µF 0.47 µH 1 µH 2.2 µH (1) (2) The values in the table are nominal values, including device tolerances. This LC combination is the standard value and recommended for most applications. 9.2.2.2 Inductor Selection The inductor selection is affected by several effects such as inductor-ripple current, output-ripple voltage, PWMto-PSM transition point, and efficiency. In addition, the selected inductor must be rated for appropriate saturation current and DC resistance (DCR). Use Equation 4 to calculate the maximum inductor current under static load conditions. ΔI(L)max I(L)max = IOmax + 2 æ VO V ö DI(L)max = ´ ç1 - O ÷ Lmin ´ ƒS è VI ø where • • • • I(L)max is the maximum inductor current ΔI(L)max is the maximum peak-to-peak inductor ripple current Lmin is the minimum effective inductor value ƒS is the actual PWM switching frequency (4) Calculating the maximum inductor current using the actual operating conditions gives the minimum saturation current. A margin of approximately 20% is recommended to be added. The inductor value also determines the load current at which power save mode is entered: DI(L) IO(PSM) = (5) 2 Table 5 lists inductors that are recommended to use with the TPS62134x device. Table 5. List of Inductors TYPE INDUCTANCE (µH) CURRENT (A) DIMENSIONS (L × B × H, mm) MANUFACTURER XFL4020-102ME 1 µH DFE252012F 1 µH 4.7 4×4×2 Coilcraft 5.0 2.5 × 2 × 1.2 DFE201612E Toko 1 µH 4.1 2 × 1.6 × 1.2 Toko PISB25201T 1 µH 3.9 2.5 × 2 × 1 Cyntec PIME031B 1 µH 5.4 3.1 × 3.4 × 1.2 Cyntec 9.2.2.3 Output Capacitor The recommended value for the output capacitor is 47 µF. The architecture of the TPS62134x family of devices allows the use of tiny ceramic output capacitors which have low equivalent series resistance (ESR). These capacitors provide low output-voltage ripple and are recommended. Using an X7R or X5R dielectric is recommended to maintain low resistance up to high frequencies and to achieve narrow capacitance variation with temperature. Using a higher value can have some advantages such as smaller voltage ripple and a tighter DC output accuracy in PWM. See Optimizing the TPS62130/40/50/60/70 Output Filter, SLVA463 for additional information. Note that in power save mode, the output voltage ripple depends on the output capacitance, ESR, and peak inductor current. Using ceramic capacitors provides small ESR and low ripple. Copyright © 2015–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS62134A TPS62134B TPS62134C TPS62134D 13 TPS62134A, TPS62134B, TPS62134C, TPS62134D SLVSC20E – JANUARY 2015 – REVISED OCTOBER 2016 www.ti.com 9.2.2.4 Input Capacitor For most applications, using a capacitor with a value of 22 µF is a recommended. Larger values further reduce input-current ripple. The input capacitor buffers the input voltage for transient events and also decouples the converter from the supply. A ceramic capacitor which has low ESR is recommended for best filtering and should be placed between the PVIN and PGND pins and as close as possible to those pins. 9.2.2.5 Soft-Start Capacitor A capacitor connected between the SS pin and the AGND pin allows a user programmable startup slope of the output voltage. A constant current source supports 2.5 µA to charge the external capacitance. Use Equation 6 to calculate the capacitor value required for a given soft-start time. 2.5 mA C(SS) = t(SS) ´ VO where • • C(SS) is the capacitance (F) required at the SS pin t(SS) is the desired soft-start time (s) (6) Leave the SS pin floating for fastest startup. 9.2.2.6 Program Output Voltage with External Resistor Divider The TPS62134x family of devices extends the output voltage range by an external resistor divider, shown in Figure 5. The output voltage is then set by Equation 7. R1 ö æ VO = VFBS ´ ç1 + ÷ R2 è ø where • VFBS is the FBS pin voltage setting by the VIDx pins, as shown in Table 1 (7) The maximum output voltage must be less than 1.9 V. The required feed forward capacitor, C4, improves the loop stability performance. 5 pF is sufficient for most of applications with the R1 and R2 values shown. R1, R2 and C4 must be located close to the IC. TPS62134C VI 3V to 17V PVIN C1 22µF AVIN L1 1µH VO SW VOS 1.1V/3A C2 47µF R1 49.9k C4 5pF EN Logic L VID0 Logic H VID1 Logic H LPM SS C3 470pF FBS R2 499k PG AGND PGND Figure 5. TPS62134C 1.1-V Output 14 Submit Documentation Feedback Copyright © 2015–2016, Texas Instruments Incorporated Product Folder Links: TPS62134A TPS62134B TPS62134C TPS62134D TPS62134A, TPS62134B, TPS62134C, TPS62134D www.ti.com SLVSC20E – JANUARY 2015 – REVISED OCTOBER 2016 9.2.3 Application Curves 100 100 90 90 80 80 Efficiency (%) Efficiency (%) TA = 25°C and VI = 7.2 V, unless otherwise noted. 70 VI = 5 V VI = 6 V VI = 7.2 V VI = 8.4 V VI = 10.8 V VI = 12 V 60 50 40 0.001 0.01 0.02 0.05 0.1 0.2 Load (A) 0.5 1 70 VI = 5 V VI = 6 V VI = 7.2 V VI = 8.4 V VI = 10.8 V VI = 12 V 60 50 40 0.001 2 3 45 0.01 0.02 0.05 0.1 0.2 Load (A) D001 VO = 0.975 V 90 90 80 80 Efficiency (%) Efficiency (%) 100 70 VI = 5 V VI = 6 V VI = 7.2 V VI = 8.4 V VI = 10.8 V VI = 12 V 60 50 D016 0.01 0.02 0.05 0.1 0.2 Load (A) 0.5 1 70 VI = 5 V VI = 6 V VI = 7.2 V VI = 8.4 V VI = 10.8 V VI = 12 V 60 50 40 0.001 2 3 45 0.01 0.02 0.05 0.1 0.2 Load (A) D003 VO = 1 V 0.5 1 2 3 45 D004 VO = 0.8 V Figure 8. TPS62134C Efficiency Figure 9. TPS62134C Efficiency 0.8 0.8 0.6 0.6 Output Voltage Accuracy (%) Output Voltage Accuracy (%) 2 3 45 Figure 7. TPS62134B Efficiency 100 0.4 0.2 0 -0.2 -0.4 TA = 40qC TA = 25qC TA = 85qC -0.6 -0.8 0.001 1 VO = 0.95 V Figure 6. TPS62134A Efficiency 40 0.001 0.5 0.4 0.2 0 -0.2 -0.4 TA = 40qC TA = 25qC TA = 85qC -0.6 -0.8 0.01 0.02 0.05 0.1 0.2 Load (A) VO = 0.95 V 0.5 1 2 3 45 VI = 7.2 V Figure 10. TPS62134A Load Regulation Copyright © 2015–2016, Texas Instruments Incorporated 3 5 D008 7 9 11 Input Voltage (V) VO = 0.95 V 13 15 17 D009 IO = 1 A Figure 11. TPS62134A Line Regulation Submit Documentation Feedback Product Folder Links: TPS62134A TPS62134B TPS62134C TPS62134D 15 TPS62134A, TPS62134B, TPS62134C, TPS62134D SLVSC20E – JANUARY 2015 – REVISED OCTOBER 2016 www.ti.com TA = 25°C and VI = 7.2 V, unless otherwise noted. 5x106 Switching Frequency (Hz) 2x106 V(SW) = 10 V/div 1x106 5 5x10 2x105 VO = 20 mV/div, AC 1x105 4 5x10 2x104 I(COIL) = 1 A/div 1x104 VI = 3 V VI = 8 V VI = 12 V VI = 17 V 3 5x10 2x103 1x103 0.001 0.01 0.02 0.05 0.1 0.2 Load (A) 0.5 1 2 3 45 D007 VO = 0.95 V Time = 5 µs/div IO = 50 mA VO = 0.975 V Figure 13. TPS62134A Output Ripple Figure 12. TPS62134A Switching Frequency V(EN) = 2 V/div V(SW) = 10 V/div V(PG) = 2 V/div VO = 20 mV/div, AC VO = 0.5 V/div I(COIL) = 2 A/div I(COIL) = 2 A/div Time = 1 µs/div IO = 2 A VO = 0.95 V Figure 14. TPS62134A Output Ripple Load = 0.75 A to 3 A VO = 0.95 V Time = 100 µs/div R(LOAD) = 0.47 Ω Figure 15. TPS62134A Startup and Shutdown V(LPM) = 2 V/div V(PG) = 2 V/div VO = 50 mV/div, AC VO = 0.5 V/div I(COIL) = 2 A/div I(LOAD) = 2 A/div Time = 50 µs/div Time = 10 µs/div VO = 0.95 V R(LOAD) = 0.47 Ω Figure 16. TPS62134A Load Transient 16 Submit Documentation Feedback Figure 17. TPS62134C LPM Entry and Exit Copyright © 2015–2016, Texas Instruments Incorporated Product Folder Links: TPS62134A TPS62134B TPS62134C TPS62134D TPS62134A, TPS62134B, TPS62134C, TPS62134D www.ti.com SLVSC20E – JANUARY 2015 – REVISED OCTOBER 2016 TA = 25°C and VI = 7.2 V, unless otherwise noted. V(VID1) = 2 V/div V(PG) = 2 V/div VO = 0.8 to 1 V I(COIL) = 2 A/div Time = 10 µs/div R(LOAD) = 0.47 Ω Figure 18. TPS62134C Minimum Speed Mode (MSM) Entry and Exit 10 Power Supply Recommendations The device is designed to operate from an input voltage supply range between 3 V and 17 V. Use Equation 8 to calculate the average input current of the TPS62134x device. 1 V ´I II = ´ O O VI h (8) Ensure that the input power supply has a sufficient current rating for the application. Copyright © 2015–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS62134A TPS62134B TPS62134C TPS62134D 17 TPS62134A, TPS62134B, TPS62134C, TPS62134D SLVSC20E – JANUARY 2015 – REVISED OCTOBER 2016 www.ti.com 11 Layout 11.1 Layout Guidelines • • • • • • • • TI recommends to place all components as close as possible to the device. Ensure that the input capacitor placement is as close as possible to the PVIN and PGND pins of the device. The VOS pin is noise sensitive and must be routed short and directly to the output of the output capacitor. This routing minimizes switch node jitter and ensures reliability. The direct common-ground connection of the AGND and PGND pins to the exposed thermal pad and the system ground (ground plane) is mandatory. To enhance heat dissipation of the device, the exposed thermal pad should be connected to bottom or internal layer ground planes using vias. Use wide and short traces for the main current paths to reduce the parasitic inductance and resistance. The capacitor on the SS pin should be placed close to the device and connected directly to those pins and the AGND pin. The inductor should be placed close to the SW pins, keeping this area small. Finally, the ground of the output capacitor should be located close to the PGND pins of the device. See Figure 19 for an example of component placement, routing, and thermal design. 11.2 Layout Example VIN AGND SS L1 FBS VID1 PVIN VOS PGND SW EN PG SW PVIN /LPM VID0 AVIN PGND C1 AGND C3 C2 VOUT GND Figure 19. TPS62134x Layout Example 18 Submit Documentation Feedback Copyright © 2015–2016, Texas Instruments Incorporated Product Folder Links: TPS62134A TPS62134B TPS62134C TPS62134D TPS62134A, TPS62134B, TPS62134C, TPS62134D www.ti.com SLVSC20E – JANUARY 2015 – REVISED OCTOBER 2016 11.3 Thermal Considerations Implementation of integrated circuits in low-profile and fine-pitch surface-mount packages typically requires special attention to power dissipation. Many system-dependent issues such as thermal coupling, airflow, added heat sinks and convection surfaces, and the presence of other heat-generating components affect the powerdissipation limits of a given component. The following lists three basic approaches for enhancing thermal performance: • Improving the power dissipation capability of the PCB design • Improving the thermal coupling of the component to the PCB by soldering the exposed thermal pad • Introducing airflow in the system For more details on how to use the thermal parameters, see the application notes, Thermal Characteristics of Linear and Logic Packages Using JEDEC PCB Designs (SZZA017), and Semiconductor and IC Package Thermal Metrics (SPRA953). Copyright © 2015–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS62134A TPS62134B TPS62134C TPS62134D 19 TPS62134A, TPS62134B, TPS62134C, TPS62134D SLVSC20E – JANUARY 2015 – REVISED OCTOBER 2016 www.ti.com 12 Device and Documentation Support 12.1 Device Support 12.1.1 Third-Party Products Disclaimer TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE. 12.2 Documentation Support 12.2.1 Related Documentation • • • Optimizing the TPS62130/40/50/60/70 Output Filter, SLVA463 Semiconductor and IC Package Thermal Metrics, SPRA953 Thermal Characteristics of Linear and Logic Packages Using JEDEC PCB Designs, SZZA017 12.3 Related Links The table below lists quick access links. Categories include technical documents, support and community resources, tools and software, and quick access to sample or buy. Table 6. Related Links PARTS PRODUCT FOLDER TECHNICAL DOCUMENTS TOOLS & SOFTWARE SUPPORT & COMMUNITY TPS62134A Click here Click here Click here Click here TPS62134B Click here Click here Click here Click here TPS62134C Click here Click here Click here Click here TPS62134D Click here Click here Click here Click here 12.4 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 12.5 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 12.6 Trademarks DCS-Control, the DCS-Control, E2E are trademarks of Texas Instruments. Skylake, Ultrabooks are trademarks of Intel. All other trademarks are the property of their respective owners. 12.7 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 20 Submit Documentation Feedback Copyright © 2015–2016, Texas Instruments Incorporated Product Folder Links: TPS62134A TPS62134B TPS62134C TPS62134D TPS62134A, TPS62134B, TPS62134C, TPS62134D www.ti.com SLVSC20E – JANUARY 2015 – REVISED OCTOBER 2016 12.8 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Copyright © 2015–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS62134A TPS62134B TPS62134C TPS62134D 21 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) TPS62134ARGTR ACTIVE VQFN RGT 16 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 134A TPS62134ARGTT ACTIVE VQFN RGT 16 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 134A TPS62134BRGTR ACTIVE VQFN RGT 16 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 134B TPS62134BRGTT ACTIVE VQFN RGT 16 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 134B TPS62134CRGTR ACTIVE VQFN RGT 16 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 134C TPS62134CRGTT ACTIVE VQFN RGT 16 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 134C TPS62134DRGTR ACTIVE VQFN RGT 16 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 134D TPS62134DRGTT ACTIVE VQFN RGT 16 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 134D (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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