TPS54202H
TPS54202H
SLVSDG7A – APRIL 2016 – REVISED
APRIL 2021
SLVSDG7A – APRIL 2016 – REVISED APRIL 2021
www.ti.com
TPS54202H 4.5-V to 28-V Input, 2-A Output,
SWIFT™ Synchronous Step Down Voltage Converter
1 Features
3 Description
•
•
The TPS54202H is a 4.5-V to 28-V input voltage
range, 2-A synchronous buck converter. The device
includes two integrated switching FETs, internal loop
compensation and 5-ms internal soft start to reduce
component count.
•
•
•
•
•
•
•
•
•
•
4.5-V to 28-V wide input voltage range
Integrated 148-mΩ and 78-mΩ MOSFETs for 2-A,
continuous output current
Low 2-μA shutdown, 45-μA quiescent current
Internal 5-mS soft start
Fixed 500-kHz switching frequency
Advanced Eco-mode™ pulse skip
Peak current mode control
Internal loop compensation
Overcurrent protection for both MOSFETs with
hiccup mode protection
Overvoltage protection
Thermal shutdown
SOT-23 (6) package
2 Applications
•
•
•
12-V, 24-V distributed power-bus supply
Industry application
– White goods
Consumer application
– Audio
– STB, DTV
– Printer
By integrating the MOSFETs and employing the
SOT-23 package, the TPS54202H achieves the high
power density and offers a small footprint on the PCB.
Advanced Eco-mode implementation maximizes the
light load efficiency and reduces the power loss.
Cycle-by-cycle current limit in both high-side MOSFET
protects the converter in an overload condition and
is enhanced by a low-side MOSFET freewheeling
current limit which prevents current runaway. Hiccup
mode protection is triggered if the overcurrent
condition has persisted for longer than the present
time.
Device Information
TPS54202H
(1)
TPS54202H
1.60 mm × 2.90 mm
For all available packages, see the orderable addendum at
the end of the data sheet.
6
VIN
BOOT
90
Cin
Cboot
Lo
80
2
GND
VOUT
SW
70
Rfb1
5
4
EN
FB
Co
Rfb2
Copyright © 2016, Texas Instruments Incorporated
Simplified Schematic
Efficiency (%)
1
EN
SOT-23 (6)
BODY SIZE (NOM)
100
3
VIN
PACKAGE(1)
PART NUMBER
60
50
40
30
VIN = 12 V, VOUT = 5 V
VIN = 12 V, VOUT = 3.3 V
VIN = 24 V, VOUT = 5 V
VIN = 24 V, VOUT = 3.3 V
20
10
0
0.001
0.01
0.1
Output Current (A)
1
D100
Efficiency vs Output Current
An©IMPORTANT
NOTICEIncorporated
at the end of this data sheet addresses availability, warranty, changes, use in
safety-critical
applications,
Copyright
2021 Texas Instruments
Submit
Document
Feedback
intellectual property matters and other important disclaimers. PRODUCTION DATA.
Product Folder Links: TPS54202H
1
TPS54202H
www.ti.com
SLVSDG7A – APRIL 2016 – REVISED APRIL 2021
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................4
6.4 Thermal Information....................................................4
6.5 Electrical Characteristics.............................................5
6.6 Timing Requirements.................................................. 5
7 Detailed Description........................................................8
7.1 Overview..................................................................... 8
7.2 Functional Block Diagram........................................... 8
7.3 Feature Description.....................................................9
7.4 Device Functional Modes..........................................12
8 Application and Implementation.................................. 13
8.1 Application Information............................................. 13
8.2 Typical Application.................................................... 13
9 Power Supply Recommendations................................20
10 Layout...........................................................................21
10.1 Layout Guidelines................................................... 21
10.2 Layout Example...................................................... 21
11 Device and Documentation Support..........................22
11.1 Device Support........................................................22
11.2 Receiving Notification of Documentation Updates.. 22
11.3 Support Resources................................................. 22
11.4 Trademarks............................................................. 22
11.5 Electrostatic Discharge Caution.............................. 22
11.6 Glossary.................................................................. 22
12 Mechanical, Packaging, and Orderable
Information.................................................................... 22
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision * (April 2016) to Revision A (April 2021)
Page
• Updated the numbering format for tables, figures, and cross-references throughout the document. ................1
• Changed the max centre switching frequency from 590 kHz to 630 kHz........................................................... 5
• Changed the max low-side source current limit from 4 A to 4.3 A......................................................................5
2
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TPS54202H
TPS54202H
www.ti.com
SLVSDG7A – APRIL 2016 – REVISED APRIL 2021
5 Pin Configuration and Functions
GND
1
6
BOOT
SW
2
5
EN
VIN
3
4
FB
Figure 5-1. 6-Pin SOT-23 DDC Package (Top View)
Table 5-1. Pin Functions
PIN
NAME
NO.
BOOT
6
(1)
TYPE(1)
O
DESCRIPTION
Supply input for the high-side NFET gate drive circuit. Connect a 0.1-μF capacitor between BOOT and
SW pins.
EN
5
I
This pin is the enable pin. Float the EN pin to disable.
FB
4
I
Converter feedback input. Connect to output voltage with feedback resistor divider.
GND
1
–
Ground pin. Source terminal of low-side power NFET as well as the ground terminal for controller circuit.
Connect sensitive VFB to this GND at a single point.
SW
2
O
Switch node connection between high-side NFET and low-side NFET.
VIN
3
–
Input voltage supply pin. The drain terminal of high-side power NFET.
O = Output; I = Input
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TPS54202H
3
TPS54202H
www.ti.com
SLVSDG7A – APRIL 2016 – REVISED APRIL 2021
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
Input voltage range, VI
Output voltage range, VO
MIN
MAX
UNIT
VIN
–0.3
30
V
EN
–0.3
7
V
FB
–0.3
7
V
BOOT-SW
–0.3
7
V
SW
–0.3
30
V
–5
30
V
Operating junction temperature, TJ
SW (20 ns transient)
–40
150
°C
Storage temperature range, Tstg
–65
150
°C
(1)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic
discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±4000
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
±1500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
VI
Input voltage range
MIN
MAX
VIN
4.5
28
V
EN
–0.1
7
V
FB
–0.1
7
V
BOOT-SW
–0.1
7
V
SW
–0.1
28
V
–40
125
°C
VO
Output voltage range
TJ
Operating junction temperature
UNIT
6.4 Thermal Information
TPS54202H
THERMAL METRIC(1)
DDC ( SOT23)
UNIT
6 PINS
RθJA
Junction-to-ambient thermal resistance
89.2
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
39.5
°C/W
RθJB
Junction-to-board thermal resistance
14.7
°C/W
ψJT
Junction-to-top characterization parameter
1.2
°C/W
ψJB
Junction-to-board characterization parameter
14.7
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, .
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TPS54202H
TPS54202H
www.ti.com
SLVSDG7A – APRIL 2016 – REVISED APRIL 2021
6.5 Electrical Characteristics
The electrical ratings specified in this section apply to all specifications in this document, unless otherwise noted. These
specifications are interpreted as conditions that do not degrade the device parametric or functional specifications for the life
of the product containing it. TJ = –40°C to +125°C, VIN = 4.5 V to 28 V, (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INPUT SUPPLY
VIN
Input voltage range
IQ
Non switching quiescent current
EN =5 V, VFB = 1 V
IOFF
Shut down current
EN = GND
VIN(UVLO)
4.5
VIN under voltage lockout
28
V
45
µA
2
µA
Rising VIN
3.9
4.2
4.4
V
Falling VIN
3.4
3.7
3.9
V
400
480
560
mV
1.28
1.35
V
Hysteresis
ENABLE (EN PIN)
V(EN_RISING)
V(EN_FALLING)
I(EN_HYS)
Rising
Enable threshold
Falling
Hysteresis current
1.16
VEN = 1.5 V
1.25
V
1
μA
FEEDBACK AND ERROR AMPLIFIER
VFB
Feedback Voltage
VIN = 12 V
0.581
0.596
0.611
V
PULSE SKIP MODE
I(SKIP) (1)
Pulse skip mode peak inductor current threshold
VIN = 24 V, VOUT = 5 V, L = 15 µH
300
mA
148
mΩ
78
mΩ
POWER STAGE
R(HSD)
High-side FET on resistance
TA = 25°C, VBST – SW = 6 V
R(LSD)
Low-side FET on resistance
TA = 25°C, VIN = 12
CURRENT LIMIT
I(LIM_HS)
High side current limit
Inductor peak current
I(LIM_LS)
Low side source current limit
Inductor valley current
2.5
3.2
3.9
A
2
3
4.3
A
390
500
630
kHz
OSCILLATOR
Fsw
Centre switching frequency
OVER TEMPERATURE PROTECTION
Rising temperature
Thermal
Shutdown(1)
Hysteresis
Hiccup time
(1)
155
°C
10
°C
32768
Cycles
Not production tested
6.6 Timing Requirements
MIN
TYP
MAX
UNIT
OVER CURRENT PROTECTION
tHIC_WAIT
Hiccup up wait time
tHIC_RESTART
Hiccup up time before restart
tSS
Soft-start time
512
Cycles
16384
Cycles
5
mS
110
ns
ON TIME CONTROL
tMIN_ON (1)
Minimum on time, measured at 90% to 90% and 1-A loading
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TPS54202H
5
TPS54202H
www.ti.com
SLVSDG7A – APRIL 2016 – REVISED APRIL 2021
Typical Characteristics
Shutdown Quiescent Current (PA)
2.5
2
1.5
1
0.5
0
-50
-25
0
25
50
75
Junction Temperature (qC)
100
125
D001
Figure 6-1. Shutdown Quiescent Current vs
Junction Temperature
Non-Switching Operating Quiescent Current (PA)
VIN = 12, unless otherwise specified
80
60
40
20
-50
-25
0
25
50
75
Junction Temperature (qC)
100
125
D002
Figure 6-2. Non-Switching Operating Quiescent
Current vs Junction Temperature
240
130
Low side FET Rds(on) (m:)
High side FET Rds(on) (m:)
220
200
180
160
140
110
90
70
120
100
-50
-25
0
25
50
75
Junction Temperature (qC)
100
50
-50
125
-25
D003
0
25
50
75
Junction Temperature (qC)
100
125
D004
Figure 6-4. Low-Side FET On Resistance vs
Junction Temperature
Figure 6-3. High-Side Resistance vs Junction
Temperature
520
0.600
Switching Frequency (kHz)
Reference Voltage (mV)
515
0.598
0.596
0.594
0.592
510
505
500
495
490
485
0.590
-50
-25
0
25
50
75
Junction Temperature (qC)
100
125
D005
Figure 6-5. Reference Voltage vs Junction
Temperature
6
480
-50
-25
0
25
50
75
Junction Temperature (qC)
100
125
D006
Figure 6-6. Centre Switching Frequency vs
Junction Temperature
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TPS54202H
TPS54202H
SLVSDG7A – APRIL 2016 – REVISED APRIL 2021
3.5
3.3
3.4
3.2
Low Side Current Limit (A)
High Side Current Limit (A)
www.ti.com
3.3
3.2
3.1
3.0
2.9
2.8
-50
3.0
2.9
2.8
2.7
-25
0
25
50
75
Junction Temperature (qC)
100
2.6
-50
125
0
25
50
75
Junction Temperature (qC)
100
125
D008
Figure 6-8. Low-Side Current Limit Threshold vs
Junction Temperature
4.5
2.20
VIN UVLO Threshold (V)
4.3
2.15
2.10
2.05
4.1
3.9
3.7
3.5
2.00
-50
-25
0
25
50
75
Junction Temperature (qC)
100
3.3
-50
125
1.08
1.07
1.36
1.06
EN Hysteresis Current (PA)
1.4
1.34
1.32
1.3
1.28
1.26
1.24
1.22
L->H
H->L
1.2
-25
0
25
50
75
Junction Temperature (oC)
-25
100
0
25
50
75
Junction Temperature (qC)
100
125
D010
Figure 6-10. VIN UVLO Threshold vs Junction
Temperature
1.38
1.18
-50
L->H
H->L
D009
Figure 6-9. BOOT-SW UVLO Threshold vs Junction
Temperature
EN UVLO Threshold (V)
-25
D007
Figure 6-7. High-Side Current Limit Threshold vs
Junction Temperature
BOOT UVLO Threshold (V)
3.1
1.05
1.04
1.03
1.02
1.01
1
0.99
125
0.98
-50
D001
Figure 6-11. EN UVLO Threshold vs Junction
Temperature
-25
0
25
50
75
Junction Temperature (oC)
100
125
D001
Figure 6-12. EN Hysteresis Current vs Junction
Temperature
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TPS54202H
7
TPS54202H
www.ti.com
SLVSDG7A – APRIL 2016 – REVISED APRIL 2021
7 Detailed Description
7.1 Overview
The TPS54202H device is a 28-V, 2-A, synchronous step-down (buck) converter with two integrated n-channel
MOSFETs. To improve performance during line and load transients the device implements a constant-frequency,
peak current mode control which reduces output capacitance. The optimized internal compensation network
minimizes the external component counts and simplifies the control loop design.
The switching frequency is fixed to 500 kHz.
The device begins switching at VIN equal to 4.5 V. The operating current is 45 μA typically when not switching
and under no load. When the device is disabled, the supply current is 2 µA typically.
The integrated 148-mΩ high-side MOSFET and 78-mΩ allow for high efficiency power supply designs with
continuous output currents up to 2 A.
The device reduces the external component count by integrating the boot recharge diode. The bias voltage
for the integrated high-side MOSFET is supplied by an external capacitor on the BOOT to PH pins. The boot
capacitor voltage is monitored by an UVLO circuit and will turn the high-side MOSFET off when the voltage falls
below a preset threshold of 2.1 V typically.
The device minimizes excessive output overvoltage transients by taking advantage of the overvoltage
comparator. When the regulated output voltage is greater than 108% of the nominal voltage, the overvoltage
comparator is activated, and the high-side MOSFET is turned off and masked from turning on until the output
voltage is lower than 104%.
The device has internal 5-ms soft-start time to minimize inrush currents.
7.2 Functional Block Diagram
EN
VIN
Thermal
Hiccup
Ih
-
UVLO
OV comparator
Shutdown
Logic
+
Hiccup
Shutdown
EN Compatator
Boot Charge
Minimum Clamp
Pulse Skip
FB
Current
Sense
BOOT
Boot UVLO
-
+ ERROR AMPLIFIER
HS MOSFET
Current
Comparator
+
0.6V
Power Stage
And
Dead time
Control
Logic
30kohm
2pF
Voltage
Reference
SW
VIN
Regulator
2.2nF
Slope
Compensation
Soft Start
Hiccup
Shutdown
Overload
Recovery
Maximum
Clamp
Current
Sense
Oscillator
LS MOSFET
Current Limit
GND
8
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TPS54202H
TPS54202H
www.ti.com
SLVSDG7A – APRIL 2016 – REVISED APRIL 2021
7.3 Feature Description
7.3.1 Fixed-Frequency PWM Control
The device uses a fixed-frequency, peak current-mode control. The output voltage is compared through external
resistors on the FB pin to an internal voltage reference by an error amplifier. An internal oscillator initiates the
turn on of the high-side power switch. The error amplifier output is compared to the current of the high-side
power switch. When the power-switch current reaches the error amplifier output voltage level, the high side
power switch is turned off and the low-side power switch is turned on. The error amplifier output voltage
increases and decreases as the output current increases and decreases. The device implements a current-limit
by clamping the error amplifier voltage to a maximum level and also implements a minimum clamp for improved
transient-response performance.
7.3.2 Pulse Skip Mode
The TPS54202H is designed to operate in pulse skipping mode at light load currents to boost light load
efficiency. When the peak inductor current is lower than 300 mA typically, the device enters pulse skipping mode.
When the device is in pulse skipping mode, the error amplifier output voltage is clamped which prevents the high
side integrated MOSFET from switching. The peak inductor current must rise above 300 mA and exit pulse skip
mode. Since the integrated current comparator catches the peak inductor current only, the average load current
entering pulse skipping mode varies with the applications and external output filters.
7.3.3 Error Amplifier
The device has a trans-conductance amplifier as the error amplifier. The error amplifier compares the FB voltage
to the lower of the internal soft-start voltage or the internal 0.596-V voltage reference. The transconductance of
the error amplifier is 240 µA/V typically. The frequency compensation components are placed internal between
the output of the error amplifier and ground.
7.3.4 Slope Compensation and Output Current
The device adds a compensating ramp to the signal of the switch current. This slope compensation prevents
sub-harmonic oscillations as the duty cycle increases. The available peak inductor current remains constant over
the full duty-cycle range.
7.3.5 Device Enable
The EN pin provides electrical on and off control of the device. When the EN pin voltage exceeds the threshold
voltage, the device begins operation. If the EN pin voltage is pulled below the threshold voltage, the regulator
stops switching and enters the low-quiescent (IQ) state.
The EN pin has an internal pull down resistance Rpd (typical 1 MΩ) which allows the user to float the EN pin to
disable the device, a Zener diode (typical break down voltage 6.9 V) is used to clamp the EN input voltage. To
enable the device, connect a pull up resistor R4 (typical 510 KΩ) between EN and VIN, R4 is used to limit the
quiet scent current of the device for light load efficiency improvement.
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TPS54202H
9
TPS54202H
www.ti.com
SLVSDG7A – APRIL 2016 – REVISED APRIL 2021
VIN
Device
R4
Ih
EN
R5
Rpd
Figure 7-1. Adjustable VIN Undervoltage Lockout
7.3.6 Adjusting Under Voltage Lockout
The device implements internal under voltage-lockout (UVLO) circuitry on the VIN pin. The device is disabled
when the VIN pin voltage falls below the internal VIN UVLO threshold. The internal VIN UVLO threshold has a
hysteresis of 480 mV. To enable the device, connect a pull-up resistor R4 (typical 510 KΩ to limit the quiescent
current) to the VIN pin.
If an application requires a higher UVLO threshold on the VIN pin, then the EN pin can be configured as shown
in Figure 7-1. When using the external UVLO function, setting the hysteresis at a value greater than 500 mV is
recommended.
The EN pin has a pull-down resistance Rpd (typical 1 MΩ), which sets the default state of the pin to disable
when no external components are connected. Use Equation 1 and Equation 2 to calculate the values of R4 and
R5 for a specified UVLO threshold.
æ VENfalling
ö
´ VSTART - VSTOP ÷ / Ih
R4 = ç
ç VENri sin g
÷
è
ø
(1)
R4 ´ Rpd
æ VSTART
ö
- 1÷ ´ Rpd - R4
ç
ç VENri sin g
÷
è
ø
(2)
R5 =
Where:
Ih = 1 µA
VENrising = 1.28 V
VENfalling = 1.25 V
7.3.7 Safe Startup into Pre-Biased Outputs
The device has been designed to prevent the low-side MOSFET from discharging a pre-biased output. During
monotonic pre-biased startup, both high-side and low-side MOSFETs are not allowed to be turned on until the
internal soft-start voltage is higher than FB pin voltage.
7.3.8 Voltage Reference
The voltage reference system produces a precise ±2.5% voltage-reference over temperature by scaling the
output of a temperature stable bandgap circuit. The typical voltage reference is designed at 0.596 V.
10
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TPS54202H
TPS54202H
www.ti.com
SLVSDG7A – APRIL 2016 – REVISED APRIL 2021
7.3.9 Adjusting Output Voltage
The output voltage is set with a resistor divider from the output node to the FB pin. It is recommended to use
divider resistors with 1% tolerance or better. Start with a 100 kΩ for the upper resistor divider, use Equation 3
to calculate the output voltage. To improve efficiency at light loads consider using larger value resistors. If the
values are too high the regulator is more susceptible to noise and voltage errors from the FB input current are
noticeable.
VOUT
ª R2 º
Vref u «
1»
¬ R3 ¼
(3)
7.3.10 Internal Soft-Start
The TTPS54202H device uses the internal soft-start function. The internal soft start time is set to 5 ms typically.
7.3.11 Bootstrap Voltage (BOOT)
The TPS54202H has an integrated boot regulator and requires a 0.1-µF ceramic capacitor between the BOOT
and SW pins to provide the gate drive voltage for the high-side MOSFET. A ceramic capacitor with an X7R or
X5R grade dielectric is recommended because of the stable characteristics over temperature and voltage. To
improve drop out, the device is designed to operate at 100% duty cycle as long as the BOOT to SW pin voltage
is greater than 2.1 V typically.
7.3.12 Overcurrent Protection
The device is protected from overcurrent conditions by cycle-by-cycle current limiting on both the high-side
MOSFET and the low-side MOSFET.
7.3.12.1 High-Side MOSFET Overcurrent Protection
The device implements current mode control which uses the internal COMP voltage to control the turn off of the
high-side MOSFET and the turn on of the low-side MOSFET on a cycle-by-cycle basis. During each cycle, the
switch current and the current reference generated by the internal COMP voltage are compared. When the peak
switch current intersects the current reference the high-side switch turns off.
7.3.12.2 Low-Side MOSFET Overcurrent Protection
While the low-side MOSFET is turned on, the conduction current is monitored by the internal circuitry. During
normal operation the low-side MOSFET sources current to the load. At the end of every clock cycle, the low-side
MOSFET sourcing current is compared to the internally set low-side sourcing current-limit. If the low-side
sourcing current-limit is exceeded, the high-side MOSFET does not turn on and the low-side MOSFET stays
on for the next cycle. The high-side MOSFET turns on again when the low-side current is below the low-side
sourcing current-limit at the start of a cycle which is the inductor current valley value.
Furthermore, if an output overload condition occurs for more than the hiccup wait time, which is programmed for
512 switching cycles, the device shuts down and restarts after the hiccup time of 16384 cycles. The hiccup mode
helps to reduce the device power dissipation under severe overcurrent conditions.
7.3.13 Output Overvoltage Protection (OVP)
The TPS54202H incorporates an overvoltage transient protection (OVTP) circuit to minimize output voltage
overshoot when recovering from output fault conditions or strong unload transients. The OVTP circuit includes
an overvoltage comparator to compare the FB pin voltage and internal thresholds. When the FB pin voltage goes
above 108% × Vref, the high-side MOSFET will be forced off. When the FB pin voltage falls below 104% × Vref,
the high-side MOSFET will be enabled again.
7.3.14 Thermal Shutdown
The internal thermal-shutdown circuitry forces the device to stop switching if the junction temperature exceeds
155°C typically. When the junction temperature drops below 145°C typically, the internal thermal-hiccup timer
begins to count. The device reinitiates the power-up sequence after the built-in thermal-shutdown hiccup time
(32768 cycles) is over.
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TPS54202H
11
TPS54202H
www.ti.com
SLVSDG7A – APRIL 2016 – REVISED APRIL 2021
7.4 Device Functional Modes
7.4.1 Normal Operation
When the input voltage is above the UVLO threshold, the TPS54202H can operate in their normal switching
modes. Normal continuous conduction mode (CCM) occurs when inductor peak current is above 0 A. In CCM,
the device operates at a fixed frequency.
7.4.2 Eco-mode™ Operation
The devices are designed to operate in high-efficiency pulse-skipping mode under light load conditions. Pulse
skipping initiates when the switch current falls to 0 A. During pulse skipping, the low-side FET turns off when
the switch current falls to 0 A. The switching node (the SW pin) waveform takes on the characteristics of
discontinuous conduction mode (DCM) operation and the apparent switching frequency decreases. As the
output current decreases, the perceived time between switching pulses increases.
12
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TPS54202H
TPS54202H
www.ti.com
SLVSDG7A – APRIL 2016 – REVISED APRIL 2021
8 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
8.1 Application Information
The TPS54202H device is typically used as a step down converter, which convert an input voltage from 8 V to 28
V to fixed output voltage 5 V.
8.2 Typical Application
8.2.1 TPS54202H 8-V to 28-V Input, 5-V Output Converter
U1
TPS54202H
VIN
VIN = 8V ~ 28V
C1
10PF
C2
0.1PF
3 VIN
R4
510Kohm
BOOT
6
C3
0.1PF
1
GND
SW
L1 15PH
FB 4
5 EN
VOUT = 5V,2A
2
C4
22PF
C5
22PF
C6
75pF
VOUT
R1
49.9 Q
R2
100lQ
R3
13.3lQ
Copyright © 2016, Texas Instruments Incorporated
Figure 8-1. 5-V, 2-A Reference Design
8.2.2 Design Requirements
For this design example, use the parameters in Table 8-1.
Table 8-1. Design Parameters
PARAMETER
VALUE
Input voltage range
8 V to 28 V
Output voltage
5V
Output current
2A
Transient response, 1.5 A load step
ΔVOUT = ±5 %
Input ripple voltage
400 mV
Output voltage ripple
30 mVpp
Switching frequency
500 kHz
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TPS54202H
13
TPS54202H
www.ti.com
SLVSDG7A – APRIL 2016 – REVISED APRIL 2021
8.2.3 Detailed Design Procedure
8.2.3.1 Input Capacitor Selection
The device requires an input decoupling capacitor and a bulk capacitor is needed depending on the application.
A ceramic capacitor over 10 µF is recommended for the decoupling capacitor. An additional 0.1 µF capacitor
(C2) from VIN to GND is optional to provide additional high frequency filtering. The capacitor voltage rating
needs to be greater than the maximum input voltage.
Use Equation 4 to calculate the input ripple voltage (ΔVIN).
DVIN =
IOUT(MAX ) ´0.25
CBULK ´ fsw
(
+ IOUT(MAX ) ´ ESRMAX
)
(4)
where:
•
•
•
•
CBULK is the bulk capacitor value
fSW is the switching frequency
IOUT(MAX) is the maximum loading current
ESRMAX is maximum series resistance of the bulk capacitor
The maximum RMS (root mean square) ripple current must also be checked. For worst case conditions, use
Equation 5 to calculate ICIN(RMS).
ICIN(RMS)
IOUT(MAX)
(5)
2
The actual input-voltage ripple is greatly affected by parasitic associated with the layout and the output
impedance of the voltage source. Design Requirements show the actual input voltage ripple for this circuit which
is larger than the calculated value. This measured value is still below the specified input limit of 400 mV. The
maximum voltage across the input capacitors is VIN (MAX) + ΔVIN/2. The selected bypass capacitor is rated
for 35 V and the ripple current capacity is greater than 2 A. Both values provide ample margin. The maximum
ratings for voltage and current must not be exceeded under any circumstance.
8.2.3.2 Bootstrap Capacitor Selection
A 0.1 µF ceramic capacitor must be connected between the BOOT to SW pin for proper operation. It is
recommended to use a ceramic capacitor.
8.2.3.3 Output Voltage Set Point
The output voltage of the TPS54202H device is externally adjustable using a resistor divider network. In the
application circuit of , this divider network is comprised of R2 and R3. Use Equation 6 and Equation 7 to
calculate the relationship of the output voltage to the resistor divider.
R3 =
VOUT
R2 ´ Vref
VOUT - Vref
(6)
ª R2 º
Vref u «
1»
¬ R3 ¼
(7)
Select a value of R2 to be approximately 100 kΩ. Slightly increasing or decreasing R3 can result in closer output
voltage matching when using standard value resistors. In this design, R2 = 100 kΩ and R3 = 13.3 kΩ which
results in a 5-V output voltage. The 49.9-Ω resistor, R1, is provided as a convenient location to break the control
loop for stability testing.
14
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TPS54202H
TPS54202H
www.ti.com
SLVSDG7A – APRIL 2016 – REVISED APRIL 2021
8.2.3.4 Enable Pin Setup
To enable the chip, a pull-up resistor R4 (typical 511 KΩ) connecting between VIN and EN R4 is used to limit the
quiet scent current which should be less than 50 µA.
8.2.3.5 Output Filter Components
Two components must be selected for the output filter, the output inductor (LO) and CO.
8.2.3.5.1 Inductor Selection
Use Equation 8 to calculate the minimum value of the output inductor (LMIN).
LMIN =
(
VOUT ´ VIN(MAX ) - VOUT
)
VIN(MAX ) ´ KIND ´ IOUT ´ fsw
(8)
Where:
KIND is a coefficient that represents the amount of inductor ripple current relative to the maximum output current.
In general, the value of KIND is at the discretion of the designer; however, the following guidelines may be used.
For designs using low-ESR output capacitors, such as ceramics, a value as high as KIND = 0.3 can be used.
When using higher ESR output capacitors, KIND = 0.2 yields better results.
For this design example, use KIND = 0.3. The minimum inductor value is calculated as 13.7 μH. For this design, a
close standard value of 15 μH was selected for LMIN.
For the output filter inductor, the RMS current and saturation current ratings must not be exceeded. Use
Equation 9 to calculate the RMS inductor current (IL(RMS)).
IL(MAX )
2
IOUT
MAX
§
1 ¨ VOUT u VIN MAX VOUT
u
12 ¨¨ VIN MAX u LO u fSW u 0.8
©
·
¸
¸
¸
¹
2
(9)
Use Equation 10 to calculate the peak inductor current (IL(PK)).
IL(PK)
IOUT MAX
VOUT u VIN MAX
VOUT
1.6 u VIN MAX u LO u fSW
(10)
Smaller or larger inductor values can be used depending on the amount of ripple current the designer wants to
allow so long as the other design requirements are met. Larger value inductors have lower AC current and result
in lower output voltage ripple. Smaller inductor values increase AC current and output voltage ripple.
8.2.3.5.2 Output Capacitor Selection
Consider three primary factors when selecting the value of the output capacitor. The output capacitor determines
the modulator pole, the output voltage ripple, and how the regulator responds to a large change in load current.
The output capacitance must be selected based on the more stringent of these three criteria.
The desired response to a large change in the load current is the first criterion. The output capacitor must supply
the load with current when the regulator cannot. This situation occurs if the desired hold-up times are present for
the regulator. In this case, the output capacitor must hold the output voltage above a certain level for a specified
amount of time after the input power is removed. The regulator is also temporarily unable to supply sufficient
output current if a large, fast increase occurs affecting the current requirements of the load, such as a transition
from no load to full load. The regulator usually requires two or more clock cycles for the control loop to notice
the change in load current and output voltage and to adjust the duty cycle to react to the change. The output
capacitor must be sized to supply the extra current to the load until the control loop responds to the load change.
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TPS54202H
15
TPS54202H
www.ti.com
SLVSDG7A – APRIL 2016 – REVISED APRIL 2021
The output capacitance must be large enough to supply the difference in current for 2 clock cycles while only
allowing a tolerable amount of drop in the output voltage. Use Equation 11 to calculate the minimum required
output capacitance.
CO !
2 u 'IOUT
fsw u 'VOUT
(11)
where:
•
•
•
∆IOUT is the change in output current
ƒSW is the switching frequency of the regulator
∆V(OUT )b is the allowable change in the output voltage
For this example, the transient load response is specified as a 5% change in the output voltage, VOUT, for a load
step of 1.5 A. For this example, ΔIOUT = 1.5 A and ΔVOUT = 0.05 × 5 = 0.25 V. Using these values results in
a minimum capacitance of 24 μF. This value does not consider the ESR of the output capacitor in the output
voltage change. For ceramic capacitors, the ESR is usually small enough to ignore in this calculation.
Equation 12 calculates the minimum output capacitance required to meet the output voltage ripple specification.
In this case, the maximum output voltage ripple is 30 mV. Under this requirement, Equation 12 yields 4.56 μF.
CO >
1
1
´
8 ´ fSW VOUTripple
Iripple
(12)
where:
•
•
•
ƒSW is the switching frequency
V(OUTripple) is the maximum allowable output voltage ripple
I(ripple) is the inductor ripple current
Use Equation 13 to calculate the maximum ESR an output capacitor can have to meet the output-voltage ripple
specification. Equation 13 indicates the ESR should be less than 54.8 mΩ. In this case, the ESR of the ceramic
capacitor is much smaller than 54.8 mΩ.
RESR <
VOUTripple
Iripple
(13)
The output capacitor can affect the crossover frequency ƒo. Considering to the loop stability and effect of the
internal parasitic parameters, choose the crossover frequency less than 40 kHz without considering the feed
forward capacitor. A simple estimation for the crossover frequency without feed forward capacitor C6 is shown in
Equation 14, assuming COUT has small ESR.
fo =
3.95
VOUT u COUT
(14)
Additional capacitance deratings for aging, temperature, and DC bias should be considered which increases
this minimum value. For this example, two 22-uF 25-V, X7R ceramic capacitors are used. Capacitors generally
have limits to the amount of ripple current they can handle without failing or producing excess heat. An output
capacitor that can support the inductor ripple current must be specified. Some capacitor data sheets specify the
RMS value of the maximum ripple current. Use Equation 15 to calculate the RMS ripple current that the output
capacitor must support. For this application, Equation 15 yields 79 mA for each capacitor.
16
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TPS54202H
TPS54202H
www.ti.com
ICOUT RMS
SLVSDG7A – APRIL 2016 – REVISED APRIL 2021
§V
¨ OUT u VIN MAX VOUT
u¨
12 ¨ VIN MAX u LO u fSW u NC
©
1
·
¸
¸
¸
¹
(15)
8.2.3.5.3 Feed-Forward Capacitor
The TPS54202H device is internally compensated and the internal compensation network is composed of two
capacitors and one resister shown on the block diagram. Depending on the VOUT, if the output capacitor COUT
is dominated by low ESR (ceramic types) capacitors, it could result in low phase margin. To improve the phase
boost an external feedforward capacitor C6 can be added in parallel with R2. C6 is chosen such that phase
margin is boosted at the crossover frequency.
Equation 16 for C6 was tested:
C6 =
1
1
u
2Sfo R2
(16)
For this design, C6 = 75 pF. C6 is not needed when COUT has high ESR, and C6 calculated from Equation 16
should be reduced with medium ESR. Table 8-2 can be used as a starting point.
Table 8-2. Recommended Component Values
VOUT (V)
L (µH)
COUT(µF)
R2 (kΩ)
R3 (kΩ)
C6 (pF)
1.8
5.6
66
100
49.9
47
2.5
8.2
44
100
31.6
33
3.3
10
44
100
22.1
56
5
15
44
100
13.3
75
12
22
44
100
5.23
100
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TPS54202H
17
TPS54202H
www.ti.com
SLVSDG7A – APRIL 2016 – REVISED APRIL 2021
8.2.4 Application Curves
0.5
90
0.4
80
0.3
Line Regulation (%)
100
Efficiency (%)
70
60
50
40
30
0.2
0.1
0
-0.1
-0.2
-0.3
20
VIN = 24 V, VOUT = 5 V
VIN = 12 V, VOUT = 5 V
10
0
0.001
0.01
-0.4
-0.5
0.1
Output Current (A)
6
1
8
10
D013
12
14 16 18 20
Input Voltage (V)
22
24
26
28
D014
Figure 8-3. Line Regulation
Figure 8-2. Efficiency
0.5
0.4
VOUT = 200 mV/div (ac coupled)
Load Regulation (%)
0.3
0.2
0.1
0
PH = 10 V/div
-0.1
-0.2
-0.3
VIN = 24 V
VIN = 12 V
-0.4
-0.5
0.1
0.6
1.1
Output Current (A)
1.6
2.1
Time - 2 ms/div
D015
Figure 8-4. Load Regulation
IOUT = 2 A
Figure 8-5. Input Voltage Ripple
VOUT = 20 mV/div (ac coupled)
VOUT = 20 mV/div (ac coupled)
PH = 10 V/div
PH = 10 V/div
Time - 40 ms/div
Time - 4 ms/div
IOUT = 0 A
IOUT = 10 mA
Figure 8-6. Output Voltage Ripple
18
Figure 8-7. Output Voltage Ripple
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TPS54202H
TPS54202H
www.ti.com
SLVSDG7A – APRIL 2016 – REVISED APRIL 2021
VOUT = 20 mV/div (ac coupled)
VOUT = 10 mV/div (ac coupled)
PH = 10 V/div
PH = 10 V/div
Time - 4 ms/div
Time - 2 ms/div
IOUT = 100 mA
IOUT = 2 A
Figure 8-8. Output Voltage Ripple
Figure 8-9. Output Voltage Ripple
VOUT = 100 mV/div (ac coupled)
VOUT = 100 mV/div (ac coupled)
IOUT = 0.5 A/div
IOUT = 0.5 A/div
0.5 A to 1.5 A Load Step,
Slew Rate = 250 mA/msec
0.1 A to 1 A Load Step,
Slew Rate = 250 mA/msec
Time - 200 ms/div
Time - 200 ms/div
0.5 to 1.5 A
0.1 to 1 A
Figure 8-10. Transient Response
Figure 8-11. Transient Response
VIN = 10 V/div
VIN = 10 V/div
EN = 2 V/div
EN = 2 V/div
VOUT = 2 V/div
VOUT = 2 V/div
Time - 2 ms/div
Time - 2 ms/div
Figure 8-12. Start-Up Relative to VIN
Figure 8-13. Shutdown Relative to VIN
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TPS54202H
19
TPS54202H
www.ti.com
SLVSDG7A – APRIL 2016 – REVISED APRIL 2021
VIN = 10 V/div
VIN = 10 V/div
EN = 2 V/div
EN = 2 V/div
VOUT = 2 V/div
VOUT = 2 V/div
Time - 2 ms/div
Time - 2 ms/div
Figure 8-14. Start-Up Relative to EN
Figure 8-15. Shutdown Relative to EN
9 Power Supply Recommendations
The devices are designed to operate from an input voltage supply range between 4.5 V and 28 V. This
input supply must be well regulated. If the input supply is located more than a few inches from the device
or converter, additional bulk capacitance may be required in addition to the ceramic bypass capacitors. An
electrolytic capacitor with a value of 47 µF is a typical choice.
20
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TPS54202H
TPS54202H
www.ti.com
SLVSDG7A – APRIL 2016 – REVISED APRIL 2021
10 Layout
10.1 Layout Guidelines
•
•
•
•
•
•
•
•
•
•
VIN and GND traces should be as wide as possible to reduce trace impedance. The wide areas are also of
advantage from the view point of heat dissipation.
The input capacitor and output capacitor should be placed as close to the device as possible to minimize
trace impedance.
Provide sufficient vias for the input capacitor and output capacitor.
Keep the SW trace as physically short and wide as practical to minimize radiated emissions.
Do not allow switching current to flow under the device.
A separate VOUT path should be connected to the upper feedback resistor.
Make a Kelvin connection to the GND pin for the feedback path.
Voltage feedback loop should be placed away from the high-voltage switching trace, and preferably has
ground shield.
The trace of the VFB node should be as small as possible to avoid noise coupling.
The GND trace between the output capacitor and the GND pin should be as wide as possible to minimize its
trace impedance.
10.2 Layout Example
VOUT
GND
Additional
Vias to the
GND plane
OUTPUT
CAPACITOR
Vias to the
internal SW
node copper
BOOST
CAPACITOR
OUTPUT
INDUCTOR
Vias to the
internal SW
node copper
VIN
GND
VBST
SW
EN
VIN
TO ENABLE
CONTROL
FEEDBACK
RESISTORS
VFB
INPUT BYPAS
CAPACITOR
SW node copper
pour area on internal
or bottom layer
Figure 10-1. Board Layout
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TPS54202H
21
TPS54202H
www.ti.com
SLVSDG7A – APRIL 2016 – REVISED APRIL 2021
11 Device and Documentation Support
11.1 Device Support
11.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
11.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.4 Trademarks
Eco-mode™ and TI E2E™ are trademarks of Texas Instruments.
All trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.6 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
22
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TPS54202H
PACKAGE OPTION ADDENDUM
www.ti.com
31-Mar-2021
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS54202HDDCR
ACTIVE
SOT-23-THIN
DDC
6
3000
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
202H
TPS54202HDDCT
ACTIVE
SOT-23-THIN
DDC
6
250
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
202H
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
工商网监
湘ICP备2023018690号
