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TPS54310
SLVS412F – DECEMBER 2001 – REVISED APRIL 2019
TPS54310 3-V to 6-V Input, 3-A Output Synchronous-Buck PWM Switcher
With Integrated FETs
1 Features
3 Description
•
As a member of one of TI's families of dc/dc
regulators, the TPS54310 low-input-voltage highoutput-current synchronous-buck PWM converter
integrates all required active components. Included
on the substrate with the listed features are a true,
high performance, voltage error amplifier that
provides high performance under transient conditions;
an undervoltage-lockout circuit to prevent start-up
until the input voltage reaches 3 V; an internally and
externally set slow-start circuit to limit in-rush
currents; and a power good output useful for
processor/logic reset, fault signaling, and supply
sequencing.
1
•
•
•
•
•
•
60-mΩ MOSFET switches for high efficiency at 3A continuous output source or sink current
Adjustable output voltage down to 0.9 V With 1%
accuracy
Externally compensated for design flexibility
Fast transient response
Wide PWM frequency: fixed 350 kHz, 550 kHz, or
adjustable 280 kHz to 700 kHz
Load protected by peak current limit and thermal
shutdown
Integrated solution reduces board area and total
cost
2 Applications
•
•
•
•
Low-voltage, high-density systems with power
distributed at 5 V or 3.3 V
Point-of-load regulation for high
performance DSPs, FPGAs, ASICs, and
microprocessors
Broadband, networking and optical
communications infrastructure
Portable computing/notebook PCs
The TPS54310 device is available in a thermally
enhanced 20-pin HTSSOP (PWP) PowerPAD™
package, which eliminates bulky heatsinks. TI
provides evaluation modules to aid in quickly
achieving high- performance power supply designs to
meet aggressive equipment development cycles.
Device Information(1)
PART NUMBER
TPS54310
PACKAGE
BODY SIZE (NOM)
HTSSOP
PowerPAD (20)
6.40 mm × 6.30 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Efficiency vs Load Current
Simplified Schematic
Input
96
Output
VIN
PH
94
TPS54310
BOOT
VBIAS VSENSE
AGND COMP
92
Efficiency − %
PGND
90
88
86
84
TA = 25°C
VI = 5 V
VO = 3.3 V
82
80
0
0.5
1
1.5
2
2.5
3
Load Current − A
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS54310
SLVS412F – DECEMBER 2001 – REVISED APRIL 2019
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
3
4
7.1
7.2
7.3
7.4
7.5
7.6
7.7
4
4
4
4
5
5
7
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Dissipation Ratings ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Detailed Description .............................................. 9
8.1 Overview ................................................................... 9
8.2 Functional Block Diagram ......................................... 9
8.3 Feature Description................................................... 9
8.4 Device Functional Modes........................................ 12
9
Application and Implementation ........................ 13
9.1 Application Information............................................ 13
9.2 Typical Application ................................................. 13
10 Power Supply Recommendations ..................... 18
11 Layout................................................................... 18
11.1 Layout Guidelines ................................................. 18
11.2 Layout Example .................................................... 19
12 Device and Documentation Support ................. 20
12.1
12.2
12.3
12.4
12.5
12.6
Related DC/DC Products ......................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
20
20
20
20
20
20
13 Mechanical, Packaging, and Orderable
Information ........................................................... 20
4 Revision History
Changes from Revision E (November 2014) to Revision F
•
Editorial updates only; no technical changes ........................................................................................................................ 1
Changes from Revision D (February 2007) to Revision E
•
2
Page
Page
Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1
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SLVS412F – DECEMBER 2001 – REVISED APRIL 2019
5 Device Comparison Table
DEVICE
OUTPUT VOLTAGE
DEVICE
OUTPUT VOLTAGE
DEVICE
TPS54311
0.9 V
TPS54314
1.8 V
TPS54372
OUTPUT VOLTAGE
DDR/Adjustable
TPS54312
1.2 V
TPS54315
2.5 V
TPS54373
Prebias/Adjustable
TPS54313
1.5 V
TPS54316
3.3 V
TPS54380
Sequencing/Adjustable
6 Pin Configuration and Functions
PWP PACKAGE
20-PINs
Top View
AGND
VSENSE
COMP
PWRGD
BOOT
PH
PH
PH
PH
PH
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
RT
SYNC
SS/ENA
VBIAS
VIN
VIN
VIN
PGND
PGND
PGND
Pin Functions
PIN
DESCRIPTION
NAME
NO.
AGND
1
Analog ground. Return for compensation network/output divider, slow-start capacitor, VBIAS capacitor, RT resistor
and SYNC pin. Make PowerPAD connection to AGND.
BOOT
5
Bootstrap input. 0.022-µF to 0.1-µF low-ESR capacitor connected from BOOT to PH generates floating drive for the
high-side FET driver.
COMP
3
Error amplifier output. Connect compensation network from COMP to VSENSE.
PGND
11–13
Power ground. High current return for the low-side driver and power MOSFET. Connect PGND with large copper
areas to the input and output supply returns, and negative terminals of the input and output capacitors.
PH
6–10
Phase input/output. Junction of the internal high and low-side power MOSFETs, and output inductor.
PWRGD
4
Power good open drain output. High when VSENSE ≥ 90% Vref, otherwise PWRGD is low. Note that output is low
when SS/ENA is low or internal shutdown signal active.
RT
20
Frequency setting resistor input. Connect a resistor from RT to AGND to set the switching frequency, fs.
SS/ENA
18
Slow-start/enable input/output. Dual function pin which provides logic input to enable/disable device operation and
capacitor input to externally set the start-up time.
SYNC
19
Synchronization input. Dual function pin which provides logic input to synchronize to an external oscillator or pin
select between two internally set switching frequencies. When used to synchronize to an external signal, a resistor
must be connected to the RT pin.
VBIAS
17
Internal bias regulator output. Supplies regulated voltage to internal circuitry. Bypass VBIAS pin to AGND pin with a
high quality, low ESR 0.1-µF to 1.0-µF ceramic capacitor.
VIN
VSENSE
14–16
2
Input supply for the power MOSFET switches and internal bias regulator. Bypass VIN pins to PGND pins close to
device package with a high quality, low ESR 1-µF to 10-µF ceramic capacitor.
Error amplifier inverting input.
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SLVS412F – DECEMBER 2001 – REVISED APRIL 2019
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
VI
Input voltage
VO
Output voltage
IO
Output voltage
Sink current
Voltage differential
TJ
MIN
MAX
UNIT
VIN, SS/ENA, SYNC
–0.3
7
V
RT
–0.3
6
V
VSENSE
–0.3
4
V
BOOT
–0.3
17
V
VBIAS, PWRGD, COMP
–0.3
7
V
PH
–0.6
10
V
PH
Internally Limited
COMP, VBIAS
6
PH
6
A
COMP
6
mA
SS/ENA, PWRGD
10
mA
0.3
V
AGND to PGND
–0.3
Continuous power dissipation
See Dissipation
Ratings
Operating virtual junction temperature
–40
150
°C
–65
150
°C
Tstg Storage temperature
(1)
mA
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
±1500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
VI
Input voltage range
TJ
Operating junction temperature
MIN
MAX
3
6
UNIT
V
–40
125
°C
7.4 Thermal Information (1)
TPS54310
THERMAL METRIC
(2)
PWP
UNIT
20 PINS
RθJA
Junction-to-ambient thermal resistance
RθJA
Junction-to-ambient thermal resistance (without solder coverage on PowerPad)
(1)
(2)
4
26
°C/W
57.5
°C/W
Test board conditions:
(a) 3 inch × 3 inch, 2 layers, Thickness: 0.062 inch
(b) 1.5 oz copper traces located on the top of the PCB
(c) 1.5 oz copper ground plane on the bottom of the PCB
(d) Ten thermal vias (see recommended land pattern in application section of this data sheet)
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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7.5 Dissipation Ratings
over operating free-air temperature range (unless otherwise noted) (1)
(1)
(2)
(3)
(2)
PACKAGE
TA = 25°C
POWER RATING
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
20-Pin PWP with solder
3.85 W (3)
2.12 W
1.54 W
20-Pin PWP without solder
1.73 W
0.96 W
0.69 W
For more information on the PWP package, refer to TI technical brief, literature number SLMA002.
Test board conditions:
(a) 3 inch × 3 inch, 2 layers, Thickness: 0.062 inch
(b) 1.5 oz copper traces located on the top of the PCB
(c) 1.5 oz copper ground plane on the bottom of the PCB
(d) Ten thermal vias (see recommended land pattern in application section of this data sheet)
Maximum power dissipation may be limited by overcurrent protection.
7.6 Electrical Characteristics
TJ = –40°C to 125°C, VIN = 3 V to 6 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
fs = 350 kHz, SYNC = 0.8 V, RT open
6.2
9.6
fs = 550 kHz, SYNC ≥ 2.5 V, RT open, phase pin
open
8.4
12.8
1
1.4
2.95
3
UNIT
SUPPLY VOLTAGE, VIN
VIN input voltage range
3
Quiescent current
Shutdown, SS/ENA = 0 V
6
V
mA
UNDERVOLTAGE LOCK OUT
Start threshold voltage, UVLO
Stop threshold voltage, UVLO
Hysteresis voltage, UVLO
Rising and falling edge deglitch, UVLO
V
2.70
2.80
0.14
0.16
V
2.5
µs
(1)
BIAS VOLTAGE
VO
Output voltage, VBIAS
Output current, VBIAS
I(VBIAS) = 0
2.70
2.80
(2)
2.90
V
100
µA
0.900
V
CUMULATIVE REFERENCE
Vref
Accuracy
0.882
0.891
REGULATION
Line regulation (1)
Load regulation (1)
(3)
(3)
IL = 1.5 A, fs = 350 kHz, TJ = 85°C
0.07
IL = 1.5 A, fs = 550 kHz, TJ = 85°C
0.07
IL = 0 A to 3 A, fs = 350 kHz, TJ = 85°C
0.03
IL = 0 A to 3 A, fs = 550 kHz, TJ = 85°C
0.03
%/V
%/A
OSCILLATOR
Internally set free-running frequency range
Externally set free-running frequency range
SYNC ≤ 0.8 V, RT open
280
350
420
SYNC ≥ 2.5 V, RT open
440
550
660
RT = 180 kΩ (1% resistor to AGND) (1)
252
280
308
RT = 100 kΩ (1% resistor to AGND)
460
500
540
RT = 68 kΩ (1% resistor to AGND) (1)
663
700
762
High-level threshold voltage, SYNC
2.5
0.8
V
700
kHz
50
Frequency range, SYNC (1)
330
Ramp valley (1)
(1)
(2)
(3)
kHz
V
Low-level threshold voltage, SYNC
Pulse duration, SYNC (1)
kHz
0.75
V
Specified by the circuit used in Figure 10.
Static resistive loads only
Specified by design
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Electrical Characteristics (continued)
TJ = –40°C to 125°C, VIN = 3 V to 6 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
Ramp amplitude (peak-to-peak)
MIN
(1)
TYP
MAX
UNIT
200
ns
1
Minimum controllable on time (1)
Maximum duty cycle
V
90%
ERROR AMPLIFIER
Error amplifier open loop voltage gain
1 kΩ COMP to AGND (1)
90
110
Error amplifier unity gain bandwidth
Parallel 10 kΩ, 160 pF COMP to AGND (1)
3
5
Error amplifier common-mode input voltage
range
Powered by internal LDO (1)
0
IIB
Input bias current, VSENSE
VSENSE = Vref
VO
Output voltage slew rate (symmetric), COMP
VBIAS
60
1
dB
MHz
250
1.4
V
nA
V/µs
PWM COMPARATOR
PWM comparator propagation delay time,
PWM comparator input to PH pin (excluding
dead time)
10 mV overdrive (1)
70
85
ns
1.20
1.40
V
SLOW-START/ENABLE
Enable threshold voltage, SS/ENA
0.82
Enable hysteresis voltage, SS/ENA (1)
Falling edge deglitch, SS/ENA
0.03
(1)
V
2.5
Internal slow-start time
2.6
Charge current, SS/ENA
SS/ENA = 0 V
Discharge current, SS/ENA
SS/ENA = 0.2 V, VI = 2.7 V
µs
3.35
4.1
ms
3
5
8
µA
1.5
2.3
4
mA
POWER GOOD
Power good threshold voltage
VSENSE falling
Power good hysteresis voltage(4)
(4)
Power good falling edge deglitch
90
%Vref
3
%Vref
35
Output saturation voltage, PWRGD
I(sink) = 2.5 mA
Leakage current, PWRGD
VI = 5.5 V
0.18
µs
0.30
V
1
µA
CURRENT LIMIT
Current limit trip point
VI = 3 V, output shorted(4)
4
6.5
VI = 6 V, output shorted(4)
4.5
7.5
Current limit leading edge blanking time(4)
Current limit total response time
(4)
A
100
ns
200
ns
THERMAL SHUTDOWN
Thermal shutdown trip point(4)
135
(4)
Thermal shutdown hysteresis
150
165
10
°C
°C
OUTPUT POWER MOSFETS
rDS(o
Power MOSFET switches
n)
(4)
(5)
6
IO = 3 A, VI = 6 V
(4)
59
88
IO = 3 A, VI = 3 V
(5)
85
136
mΩ
Matched MOSFETs, low side rDS(on) production tested, high side rDS(on) specified by design.
Matched MOSFETs, low side rDS(on) production tested, high side rDS(on) specified by design.
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7.7 Typical Characteristics
100
Drain-Source On-State Resistance − W
Drain-Source On-State Resistance − W
120
VI = 3.3 V
IO = 3 A
100
80
60
40
20
0
25
85
IO = 3 A
60
40
20
0
−40
0
−40
VI = 5 V
80
125
0
25
85
125
TJ − Junction Temperature − °C
Figure 1. Drain-Source On-State Resistance vs Junction
Temperature
Figure 2. Drain-Source On-State Resistance vs Junction
Temperature
750
f − Externally Set Oscillator Frequency − kHz
f − Internally Set Oscillator Frequency −kHz
TJ − Junction Temperature − °C
650
SYNC ≥ 2.5 V
550
450
SYNC ≤ 0.8 V
350
250
−40
0
25
85
125
800
RT = 68 k
700
600
RT = 100 k
500
400
RT = 180 k
300
200
−40
0
25
85
125
TJ − Junction Temperature − °C
TJ − Junction Temperature − °C
Figure 3. Internally Set Oscillator Frequency vs Junction
Temperature
Figure 4. Externally Set Oscillator Frequency vs Junction
Temperature
0.8950
0.895
VO − Output Voltage Regulation − V
Vref − Voltage Reference − V
TA = 85°C
0.893
0.891
0.889
0.887
0.885
−40
0.8930
0.8910
0.8890
f = 350 kHz
0.8870
0.8850
0
25
85
125
3
TJ − Junction Temperature − °C
Figure 5. Voltage Reference vs Junction Temperature
4
5
VI − Input Voltage − V
6
Figure 6. Output Voltage Regulation vs Input Voltage
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Typical Characteristics (continued)
0
140
RL= 10 kW,
CL = 160 pF,
TA = 25°C
Gain − dB
100
−60
80
Phase
−80
−100
60
−120
40
Internal Slow-Start Time − ms
−40
Gain
−140
20
Phase − Degrees
120
3.80
−20
−160
0
−180
−20
−200
10 k 100 k 1 M 10 M
0
10
100
1k
3.65
3.50
3.35
3.20
3.05
2.90
2.75
−40
f − Frequency − Hz
0
25
85
TJ − Junction Temperature − °C
125
Figure 8. Internal Slow-Start Time vs Junction Temperature
Figure 7. Error Amplifier Open Loop Response
2.25
TJ − 125°C
fs = 700 kHz
Device Power Losses − W
2
1.75
1.5
VI = 3.3 V
1.25
1
VI = 5 V
0.75
0.5
0.25
0
0
1
2
3
IL − Load Current − A
4
Figure 9. Device Power Losses vs Load Current
8
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8 Detailed Description
8.1 Overview
The TPS54310 low-input-voltage high- output-current synchronous-buck PWM converter integrates all required
active components. Included on the substrate with the listed features are a true, high performance, voltage error
amplifier that provides high performance under transient conditions; an undervoltage-lockout circuit to prevent
start-up until the input voltage reaches 3 V; an internally and externally set slow-start circuit to limit in-rush
currents; and a power good output useful for processor/logic reset, fault signaling, and supply sequencing.
8.2 Functional Block Diagram
VBIAS
AGND
VIN
Enable
Comparator
SS/ENA
Falling
Edge
Deglitch
1.2 V
Hysteresis: 0.03
V
2.5 ms
VIN UVLO
Comparator
VIN
2.95 V
Hysteresis: 0.16
V
REG
VBIAS
SHUTDOWN
VIN
ILIM
Comparator
Thermal
Shutdown
150°C
3−6V
Leading
Edge
Blanking
Falling
and
Rising
Edge
Deglitch
100 ns
BOOT
30 mW
2.5 ms
SS_DIS
SHUTDOWN
Internal/External
Slow-start
(Internal Slow-start Time = 3.35 ms
PH
+
−
R Q
S
Error
Amplifier
Reference
VREF = 0.891 V
PWM
Comparator
LOUT
VO
CO
Adaptive Dead-Time
and
Control Logic
VIN
30 mW
OSC
PGND
Powergood
Comparator
PWRGD
VSENSE
Falling
Edge
Deglitch
0.90 Vref
TPS54610
Hysteresis: 0.03 Vref
VSENSE
COMP
RT
SHUTDOWN
35 ms
SYNC
8.3 Feature Description
8.3.1 Undervoltage Lockout (UVLO)
The TPS54310 incorporates an undervoltage lockout circuit to keep the device disabled when the input voltage
(VIN) is insufficient. During power up, internal circuits are held inactive until VIN exceeds the nominal UVLO
threshold voltage of 2.95 V. Once the UVLO start threshold is reached, device start-up begins. The device
operates until VIN falls below the nominal UVLO stop threshold of 2.8 V. Hysteresis in the UVLO comparator,
and a 2.5-µs rising and falling edge deglitch circuit reduce the likelihood of shutting the device down due to noise
on VIN.
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Feature Description (continued)
8.3.2 Slow Start and Enable (SS/ENA)
The slow-start and enable pin provide two functions; first, the pin act as an enable (shutdown) control by keeping
the device turned off until the voltage exceeds the start threshold voltage of approximately 1.2 V. When SS/ENA
exceeds the enable threshold, device start-up begins. The reference voltage fed to the error amplifier is linearly
ramped up from 0 V to 0.891 V in 3.35 ms. Similarly, the converter output voltage reaches regulation in
approximately 3.35 ms. Voltage hysteresis and a 2.5-µs falling edge deglitch circuit reduce the likelihood of
triggering the enable due to noise.
The second function of the SS/ENA pin provides an external means of extending the slow-start time with a lowvalue capacitor connected between SS/ENA and AGND. Adding a capacitor to the SS/ENA pin has two effects
on start-up. First, a delay occurs between release of the SS/ENA pin and start up of the output. The delay is
proportional to the slow-start capacitor value and lasts until the SS/ENA pin reaches the enable threshold. The
start-up delay is approximately:
1.2 V
t =C
d
(SS) × 5 µA
(1)
Second, as the output becomes active, a brief ramp-up at the internal slow-start rate may be observed before the
externally set slow-start rate takes control and the output rises at a rate proportional to the slow-start capacitor.
The slow-start time set by the capacitor is approximately:
0.7 V
= C
t
(SS)
(SS) × 5 µA
(2)
The actual slow-start is likely to be less than the above approximation due to the brief ramp-up at the internal
rate.
8.3.3 VBIAS Regulator (VBIAS)
The VBIAS regulator provides internal analog and digital blocks with a stable supply voltage over variations in
junction temperature and input voltage. A high quality, low-ESR, ceramic bypass capacitor is required on the
VBIAS pin. X7R or X5R grade dielectrics are recommended because their values are more stable over
temperature. The bypass capacitor should be placed close to the BVIAS pin and returned to AGND. External
loading on VBIAS is allowed, with the caution that internal circuits require a minimum BVIAS of 2.7 V, and
external loads on VBIAS with ac or digital switching noise may degrade performance. The VBIAS pin may be
useful as a reference voltage for external circuits.
8.3.4 Voltage Reference
The voltage reference system produces a precise Vref signal by scaling the output of a temperature stable
bandgap circuit. During manufacture, the bandgap and scaling circuits are trimmed to produce 0.891 V at the
output of the error amplifier, with the amplifier connected as a voltage follower. The trim procedure adds to the
high precision regulation of the TPS54310, because it cancels offset errors in the scale and error amplifier
circuits
8.3.5 Oscillator and PWM Ramp
The oscillator frequency can be set to internally fixed values of 350 kHz or 550 kHz using the SYNC pin as a
static digital input. If a different frequency of operation is required for the application, the oscillator frequency can
be externally adjusted from 280 kHz to 700 kHz by connecting a resistor to the RT pin to ground and floating the
SYNC pin. The switching frequency is approximated by the following equation, where R is the resistance from RT
to AGND:
SWITCHING FREQUENCY = 100 kΩ × 500 kHz
R
(3)
External synchronization of the PWM ramp is possible over the frequency range of 330 kHz to 700 kHz by driving
a synchronization signal into SYNC and connecting a resistor from RT to AGND. Choose an RT resistor that sets
the free-running frequency to 80% of the synchronization signal. Table 1 summarizes the frequency selection
configurations.
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Feature Description (continued)
Table 1. Summary of the Frequency Selection Configurations
SWITCHING FREQUENCY
SYNC PIN
RT PIN
350 kHz, internally set
Float or AGND
Float
550 kHz, internally set
≥ 2.5 V
Float
Externally set 280 kHz to 700 kHz
Float
R = 68 k to 180 k
Externally synchronized frequency
Synchronization signal
R = RT value for 80% of external synchronization frequency
8.3.6 Error Amplifier
The high performance, wide bandwidth, voltage error amplifier sets the TPS54310 apart from most dc/dc
converters. The user is given the flexibility to use a wide range of output L and C filter components to suit the
particular needs of the application. Type 2 or type 3 compensation can be employed using external
compensation components.
8.3.7 PWM Control
Signals from the error amplifier output, oscillator, and current limit circuit are processed by the PWM control logic.
Referring to the internal block diagram, the control logic includes the PWM comparator, OR gate, PWM latch,
and portions of the adaptive dead-time and control logic block. During steady-state operation below the current
limit threshold, the PWM comparator output and oscillator pulse train alternately reset and set the PWM latch.
Once the PWM latch is set, the low-side FET remains on for a minimum duration set by the oscillator pulse
duration. During this period, the PWM ramp discharges rapidly to its valley voltage. When the ramp begins to
charge back up, the low-side FET turns off and high-side FET turns on. As the PWM ramp voltage exceeds the
error amplifier output voltage, the PWM comparator resets the latch, thus turning off the high-side FET and
turning on the low-side FET. The low-side FET remains on until the next oscillator pulse discharges the PWM
ramp.
During transient conditions, the error amplifier output could be below the PWM ramp valley voltage or above the
PWM peak voltage. If the error amplifier is high, the PWM latch is never reset and the high-side FET remains on
until the oscillator pulse signals the control logic to turn the high-side FET off and the low-side FET on. The
device operates at its maximum duty cycle until the output voltage rises to the regulation set-point, setting
VSENSE to approximately the same voltage as Vref. If the error amplifier output is low, the PWM latch is
continually reset and the high-side FET does not turn on. The low-side FET remains on until the VSENSE
voltage decreases to a range that allows the PWM comparator to change states. The TPS54310 is capable of
sinking current continuously until the output reaches the regulation set-point.
If the current limit comparator trips for longer than 100 ns, the PWM latch resets before the PWM ramp exceeds
the error amplifier output. The high-side FET turns off and low-side FET turns on to decrease the energy in the
output inductor and consequently the output current. This process is repeated each cycle in which the current
limit comparator is tripped.
8.3.8 Dead-Time Control and MOSFET Drivers
Adaptive dead-time control prevents shoot-through current from flowing in both N-channel power MOSFETs
during the switching transitions by actively controlling the turn-on times of the MOSFET drivers. The high-side
driver does not turn on until the gate drive voltage to the low-side FET is below 2 V. The low-side driver does not
turn on until the voltage at the gate of the high-side MOSFETs is below 2 V. The high-side and low-side drivers
are designed with 300-mA source and sink capability to quickly drive the power MOSFETs gates. The low-side
driver is supplied from VIN, while the high-side drive is supplied from the BOOT pin. A bootstrap circuit uses an
external BOOT capacitor and an internal 2.5-Ω bootstrap switch connected between the VIN and BOOT pins.
The integrated bootstrap switch improves drive efficiency and reduces external component count.
8.3.9 Overcurrent Protection
The cycle by cycle current limiting is achieved by sensing the current flowing through the high-side MOSFET and
differential amplifier and comparing it to the preset overcurrent threshold. The high-side MOSFET is turned off
within 200 ns of reaching the current limit threshold. A 100-ns leading edge blanking circuit prevents false
tripping of the current limit. Current limit detection occurs only when current flows from VIN to PH when sourcing
current to the output filter. Load protection during current sink operation is provided by thermal shutdown.
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8.3.10 Thermal Shutdown
The device uses the thermal shutdown to turn off the power MOSFETs and disable the controller if the junction
temperature exceeds 150°C. The device is released from shutdown when the junction temperature decreases to
10°C below the thermal shutdown trip point and starts up under control of the slow-start circuit. Thermal
shutdown provides protection when an overload condition is sustained for several milliseconds. With a persistent
fault condition, the device cycles continuously; starting up by control of the soft-start circuit, heating up due to the
fault, and then shutting down upon reaching the thermal shutdown point.
8.3.11 Powergood (PWRGD)
The powergood circuit monitors for undervoltage conditions on VSENSE. If the voltage on VSENSE is 10%
below the reference voltage, the open-drain PWRGD output is pulled low. PWRGD is also pulled low if VIN is
less than the UVLO threshold, or SS/ENA is low, or thermal shutdown is asserted. When VIN = UVLO threshold,
SS/ENA = enable threshold, and VSENSE > 90% of Vref, the open-drain output of the PWRGD pin is high. A
hysteresis voltage equal to 3% of Vref and a 35-µs falling edge deglitch circuit prevent tripping of the powergood
comparator due to high-frequency noise.
8.4 Device Functional Modes
8.4.1 Continuous Conduction Mode
The TPS54310 operates in continuous conduction mode, that is, the low-side MOSFET runs fully complimentary
to the high-side MOSFET regardless of output current.
8.4.2 Switching Frequency Configuration
Depending on the configuration of the RT and SYNC pins, the TPS54310 can be configured to switch at 350
kHz, or 550 kHz without external components, or any frequency between 280 kHz and 700 kHz as configured by
a resistor from the RT pin to ground. The TPS54310 can also be synchronized to an external clock using the
SYNC pin. See Table 1 for more information.
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The TPS54310 is a 3-V to 6-V integrated FET synchronous buck converter. It is used to convert a DC input
voltage on the VIN pins to a lower output voltage at 3 A maximum output current.
9.2 Typical Application
Figure 10 shows the schematic diagram for a typical TPS54310 application. The TPS54310 (U1) can provide up
to 3 A of output current at a nominal output voltage of 3.3 V. For proper thermal performance, the power pad
underneath the TPS54310 integrated circuit needs to be soldered well to the printed-circuit board.
J1
VI
GND
VIN
2
1
C2
+
R3
1
R1
10 kW
71.5 kW
U1
TPS54310PWP
20
19
18
17
C3
0.1 mF
4
PWRGD
RT
VIN
SS/ENA
9
PH
3 COMP
2
PH
6
5
BOOT
13
PGND
AGND
C6
GND
C11
1000 pF
C7
0.047 mF
R6
2700 pF
R5
VO
11
PGND
PwrPAD
R4
3.74 kW
C9
180 mF
4V
J3
12
PGND
C5
3900 pF
C4
100 pF
R2
3.74 kW
2
+
8
7
PH
VSENSE
1
10
PH
VBIAS
PWRGD
L1
1.2 mH
14
VIN
PH
1
15
VIN
SYNC
C8
10 mF
16
732 W
R7
49.9 W
10 kW
1
Optional
Figure 10. TPS54310 Schematic
9.2.1 Design Requirements
Design requirements for this example are as follows:
• DC input voltage: 3 V – 6 V
• DC output current: 0 A – 3 A
• Load regulation: ±0.5%
• Output voltage ripple: 30 mV
• Input voltage ripple: 150 mV
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Typical Application (continued)
9.2.2 Detailed Design Procedure
9.2.2.1 Input Voltage
The input to the circuit is a nominal 5 VDC, applied at J1. The optional input filter (C2) is a 220-µF POSCAP
capacitor, with a maximum allowable ripple current of 3 A. C8 is the decoupling capacitor for the TPS54310 and
must be located as close to the device as possible.
9.2.2.2 Feedback Circuit
The resistor divider network of R5 and R4 sets the output voltage for the circuit at 3.3 V. R5, along with R2, R6,
C4, C5, and C6 forms the loop compensation network for the circuit. For this design, a Type 3 topology is used.
9.2.2.3 Setting the Output Voltage
The output voltage of the TPS54310 can be set by feeding back a portion of the output to the VSENSE pin using
a resistor divider network. In the application circuit of Figure 10, this divider network is comprised of resistors R5
and R4. To calculate the resistor values to generate the required output voltage use Equation 4.
R5 x 0.891
R4 =
VO - 0.891
(4)
Start with a fixed value of R5 and calculate the required R4 value. Assuming a fixed value of 10 kΩ for R5, the
following table gives the appropriate R4 value for several common output voltages:
Table 2. R4 Values for Common Output Voltages
OUTPUT VOLTAGE (V)
R4 VALUE (KΩ)
1.2
28.7
1.5
14.7
1.8
9.76
2.5
5.49
3.3
3.74
9.2.2.4 Operating Frequency
In the application circuit, the 350-kHz operation is selected by leaving RT and SYNC open. Connecting a 68-kΩ
to 180-kΩ resistor between RT (pin 20) and analog ground can be used to set the switching frequency from
280 kHz to 700 kHz. To calculate the RT resistor, use the Equation 5:
R = 100 kΩ × 500 kHz
ƒ
SW
(5)
9.2.2.5 Output Filter
The output filter is composed of a 1.2-µH inductor and 180-µF capacitor. The inductor is a low dc resistance
(0.017 Ω) type, Coilcraft DO1813P-122HC. The capacitor used is a 4-V special polymer type with a maximum
ESR of 0.015 Ω. The feedback loop is compensated so that the unity gain frequency is approximately 75 kHz.
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9.2.3 Application Curves
Figure 11. Efficiency vs. Load Current
Figure 12. Power Loss vs. Load Current
Figure 13. Junction Temperature vs. Load Current
Figure 14. Load Regulation
Figure 15. Output Voltage Ripple
Figure 16. Input Voltage Ripple
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Figure 17. Start-Up From VIN
Figure 18. System Bode Plot
3.4
100
VI = 5 V
VI = 4 V
VO − Output Voltage − %
95
90
VI = 6 V
Efficiency − %
TA = 25°C
VI = 5 V
3.38
85
80
75
70
3.36
3.34
3.32
3.3
3.28
3.26
3.24
65
0
1
2
3
4
5
0
1
2
3
4
5
IO − Output Current − A
IL − Load Current − A
Figure 19. Efficiency vs Output Current
Figure 20. Output Voltage vs Load Current
135
Phase
Gain − dB
40
45
20
Gain
0
0
VO (AC)
10 mV/div
90
TA = 25°C
Phase − Degrees
60
−45
−20
−40
100
1k
10 k
100 k
VI = 5 V
IO = 3 A
400 ns/div
−90
1M
f − Frequency − Hz
Figure 22. Output Ripple Voltage
Figure 21. Loop Response
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VI = 5 V
40 ms/div
VO (AC)
50 mV/div
VI 2 V/div
VO 2 V/div
VPWRGD 5 V/div
IO
2 A/div
1 ms/div
Figure 24. Slow-Start Timing
Figure 23. Load Transient Response
125
T A − Ambient Temperature − ° C
115
VI = 5 V
105
95
85
VI = 3.3 V
75
Safe Operating Area †
65
55
45
35
25
0
†
1
2
3
IL − Load Current − A
4
Safe operating area is applicableto the test board conditions
listed in the dissipation rating table section of this data sheet.
Figure 25. Ambient Temperature vs Load Current
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10 Power Supply Recommendations
The TPS54310 is designed to operate from an input supply from 3 V to 6 V on the VIN pins. This supply must be
well regulated and properly bypassed for proper operation of the TPS54310. Additionally, the VBIAS pin must
have good local bypassing for noise performance. See the recommendations in Pin Configuration and Functions
and Layout Guidelines for more information.
11 Layout
11.1 Layout Guidelines
Figure 26 shows a generalized PCB layout guide for the TPS54310.
The VIN pins should be connected together on the printed circuit board (PCB) and bypassed with a low ESR
ceramic bypass capacitor. Care should be taken to minimize the loop area formed by the bypass capacitor
connections, the VIN pins, and the TPS54X10 ground pins. The minimum recommended bypass capacitance is
10-µF ceramic with a X5R or X7R dielectric and the optimum placement is closest to the VIN pins and the PGND
pins.
The TPS54310 has two internal grounds (analog and power). Inside the TPS54310, the analog ground ties to all
of the noise sensitive signals, while the power ground ties to the noisier power signals. Noise injected between
the two grounds can degrade the performance of the TPS54310, particularly at higher output currents. Ground
noise on an analog ground plane can also cause problems with some of the control and bias signals. For these
reasons, separate analog and power ground traces are recommended. There should be an area of ground one
the top layer directly under the IC, with an exposed area for connection to the PowerPAD. Use vias to connect
this ground area to any internal ground planes. Use additional vias at the ground side of the input and output
filter capacitors as well. The AGND and PGND pins should be tied to the PCB ground by connecting them to the
ground area under the device as shown. The only components that should tie directly to the power ground plane
are the input capacitors, the output capacitors, the input voltage decoupling capacitor, and the PGND pins of the
TPS54310. Use a separate wide trace for the analog ground signal path. This analog ground should be used for
the voltage set point divider, timing resistor RT, slow start capacitor and bias capacitor grounds. Connect this
trace directly to AGND (pin 1).
The PH pins should be tied together and routed to the output inductor. Since the PH connection is the switching
node, inductor should be located very close to the PH pins and the area of the PCB conductor minimized to
prevent excessive capacitive coupling.
Connect the boot capacitor between the phase node and the BOOT pin as shown. Keep the boot capacitor close
to the IC and minimize the conductor trace lengths.
Connect the output filter capacitor(s) as shown between the VOUT trace and PGND. It is important to keep the
loop formed by the PH pins, Lout, Cout and PGND as small as practical.
Place the compensation components from the VOUT trace to the VSENSE and COMP pins. Do not place these
components too close to the PH trace. Due to the size of the IC package and the device pinout, they will have to
be routed somewhat close, but maintain as much separation as possible while still keeping the layout compact.
Connect the bias capacitor from the VBIAS pin to analog ground using the isolated analog ground trace. If a
slow-start capacitor or RT resistor is used, or if the SYNC pin is used to select 350-kHz operating frequency,
connect them to this trace as well.
For operation at full rated load current, the analog ground plane must provide adequate heat dissipating area. A
3 inch by 3 inch plane of 1 ounce copper is recommended, though not mandatory, depending on ambient
temperature and airflow. Most applications have larger areas of internal ground plane available, and the
PowerPAD should be connected to the largest area available. Additional areas on the top or bottom layers also
help dissipate heat, and any area available should be used when 3 A or greater operation is desired. Connection
from the exposed area of the PowerPAD to the analog ground plane layer should be made using 0.013 inch
diameter vias to avoid solder wicking through the vias. Six vias should be in the PowerPAD area with four
additional vias located under the device package. The size of the vias under the package, but not in the exposed
thermal pad area, can be increased to 0.018. Additional vias beyond the ten recommended that enhance thermal
performance should be included in areas not under the device package.
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11.2 Layout Example
ANALOG GROUND TRACE
FREQUENCY SET RESISTOR
AGND
RT
COMPENSATION
NETWORK
COMP
SS/ENA
PWRGD
BOOT
CAPACITOR
BOOT
SLOW START
CAPACITOR
SYNC
VSENSE
VBIAS
BIAS CAPACITOR
EXPOSED
POWERPAD
AREA
VIN
PH
VIN
PH
VIN
PH
PGND
PH
PGND
PH
PGND
Vin
VOUT
OUTPUT INDUCTOR
PH
INPUT
BYPASS
CAPACITOR
OUTPUT
FILTER
CAPACITOR
INPUT
BULK
FILTER
TOPSIDE GROUND AREA
VIA to Ground Plane
Figure 26. TPS54310 PCB Layout
6 PL ∅ 0.0130
4 PL ∅ 0.0180
Connect Pin 1 to Analog Ground Plane
in This Area for Optimum Performance
Minimum Recommended Thermal Vias: 6 × .013 dia.
Inside Powerpad Area 4 × .018 dia. Under Device as Shown.
Additional .018 dia. Vias May be Used if Top Side Analog
Ground Area is Extended.
0.0150
0.06
0.0227
0.0600
0.0400
0.2560
0.2454
0.1010
0.0400
0.0600
0.0256
Minimum Recommended Top
Side Analog Ground Area
0.1700
0.1340
0.0620
0.0400
Minimum Recommended Exposed
Copper Area For Powerpad. 5mm
Stencils may Require 10 Percent
Larger Area
Figure 27. Recommended Land Pattern for 20-Pin PWP PowerPAD
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12 Device and Documentation Support
12.1 Related DC/DC Products
•
•
•
TPS40000—dc/dc controller
PT5500 series—3-A plug-in modules
TPS757XX—3-A low dropout regulator
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.4 Trademarks
PowerPAD, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS54310PWP
ACTIVE
HTSSOP
PWP
20
70
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
TPS54310
TPS54310PWPG4
ACTIVE
HTSSOP
PWP
20
70
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
TPS54310
TPS54310PWPR
ACTIVE
HTSSOP
PWP
20
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
TPS54310
TPS54310PWPRG4
ACTIVE
HTSSOP
PWP
20
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
TPS54310
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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