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TPS54311, TPS54312, TPS54313
TPS54314, TPS54315, TPS54316
SLVS416C – FEBRUARY 2002 – REVISED JANUARY 2015
TPS5431x 3-V to 6-V Input, 3-A Output Synchronous Buck PWM Switcher With Integrated
FETs (SWIFT™)
1 Features
3 Description
•
As members of the SWIFT™ family of DC - DC
regulators, the TPS54311, TPS54312, TPS54313,
TPS54314, TPS54315 and TPS54316 low-inputvoltage high-outputcurrent synchronous-buck PWM
converters integrate all required active components.
Included on the substrate with the listed features are
a true, high performance, voltage error amplifier that
provides high performance under transient conditions;
an undervoltage-lockout circuit to prevent start-up
until the input voltage reaches 3 V; an internally and
externally set slow-start circuit to limit in-rush
currents; and a powergood output useful for
processor/logic reset, fault signaling, and supply
sequencing.
1
•
•
•
•
•
•
60-mΩ, MOSFET Switches for High Efficiency at
3-A Continuous Output Source and Sink Current
0.9-V, 1.2-V, 1.5-V, 1.8-V, 2.5-V, and 3.3-V Fixed
Output Voltage Devices With 1.0% Initial Accuracy
Internally Compensated for Low Parts Count
Fast Transient Response
Wide PWM Frequency − Fixed 350 kHz, 550 kHz
or Adjustable 280 kHz to 700 kHz
Load Protected by Peak Current Limit and
Thermal Shutdown
Integrated Solution Reduces Board Area and
Total Cost
2 Applications
•
•
•
•
Low-Voltage, High-Density Systems With Power
Distributed at 5 V or 3.3 V
Point of Load Regulation for High Performance
DSPs, FPGAs, ASICs and Microprocessors
Broadband, Networking and Optical
Communications Infrastructure
Portable Computing/Notebook PCs
The TPS54311, TPS54312, TPS54313, TPS54314,
TPS54315 and TPS54316 devices are available in a
thermally enhanced 20-pin HTSSOP (PWP)
PowerPAD™ package, which eliminates bulky
heatsinks. TI provides evaluation modules and the
SWIFT designer software tool to aid in quickly
achieving high-performance power supply designs to
meet aggressive equipment development cycles.
Device Information(1)
PART NUMBER
PACKAGE
OUTPUT VOLTAGE
TPS54311
0.9 V
TPS54312
1.2 V
TPS54313
1.5 V
HTSSOP (20)
TPS54314
1.8 V
TPS54315
2.5 V
TPS54316
3.3 V
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Simplified Schematic
Input
VIN
PH
Efficiency vs Load Current
Output
96
TPS54316
94
BOOT
92
VSENSE
GND
Efficiency − %
PGND
VBIAS
90
88
86
84
TA = 25°C
VI = 5 V
VO = 3.3 V
82
80
0
0.5
1
1.5
2
2.5
3
Load Current − A
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS54311, TPS54312, TPS54313
TPS54314, TPS54315, TPS54316
SLVS416C – FEBRUARY 2002 – REVISED JANUARY 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
4
4
4
4
5
7
Absolute Maximum Ratings ......................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Dissipation Ratings ...................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Detailed Description .............................................. 9
7.1 Overview ................................................................... 9
7.2 Functional Block Diagram ......................................... 9
7.3 Feature Description................................................... 9
7.4 Device Functional Modes........................................ 12
8
Application and Implementation ........................ 13
8.1 Application Information............................................ 13
8.2 Typical Application ................................................. 13
9 Power Supply Recommendations...................... 16
10 Layout................................................................... 16
10.1 Layout Guidelines ................................................. 16
10.2 Layout Example .................................................... 17
10.3 Thermal Considerations ........................................ 17
11 Device and Documentation Support ................. 18
11.1
11.2
11.3
11.4
11.5
Documentation Support ........................................
Related Links ........................................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
18
18
18
18
18
12 Mechanical, Packaging, and Orderable
Information ........................................................... 18
4 Revision History
Changes from Revision B (April 2005) to Revision C
•
2
Page
Added Feature Description section, Device Functional Modes, Application and Implementation section, Power
Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical,
Packaging, and Orderable Information section. .................................................................................................................... 1
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Copyright © 2002–2015, Texas Instruments Incorporated
Product Folder Links: TPS54311 TPS54312 TPS54313 TPS54314 TPS54315 TPS54316
TPS54311, TPS54312, TPS54313
TPS54314, TPS54315, TPS54316
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SLVS416C – FEBRUARY 2002 – REVISED JANUARY 2015
5 Pin Configuration and Functions
PWP Package
20-Pin HTSSOP
Top View
AGND
VSENSE
NC
PWRGD
BOOT
PH
PH
PH
PH
PH
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
RT
FSEL
SS/ENA
VBIAS
VIN
VIN
VIN
PGND
PGND
PGND
NC – No internal connection
Pin Functions
PIN
DESCRIPTION
NAME
NO.
AGND
1
Analog ground. Return for compensation network/output divider, slow-start capacitor, VBIAS capacitor, RT resistor and FSEL pin. Make
PowerPAD connection to AGND.
BOOT
5
Bootstrap input. 0.022-µF to 0.1-µF low-ESR capacitor connected from BOOT to PH generates floating drive for the high-side FET driver.
FSEL
19
Frequency select input. Provides logic input to select between two internally set switching frequencies.
NC
3
No connection
PGND
11−13
Power ground. High current return for the low-side driver and power MOSFET. Connect PGND with large copper areas to the input and
output supply returns, and negative terminals of the input and output capacitors.
PH
6−10
Phase input/output. Junction of the internal high and low-side power MOSFETs, and output inductor.
PWRGD
4
Powergood open-drain output. Hi-Z when VSENSE ≥ 90% Vref, otherwise PWRGD is low. Note that output is low when SS/ENA is low or
internal shutdown signal active.
RT
20
Frequency setting resistor input. Connect a resistor from RT to AGND to set the switching frequency, fs.
SS/ENA
18
Slow-start/enable input/output. Dual function pin which provides logic input to enable/disable device operation and capacitor input to
externally set the start-up time.
VBIAS
17
Internal bias regulator output. Supplies regulated voltage to internal circuitry. Bypass VBIAS pin to AGND pin with a high quality, low
ESR 0.1-µF to 1.0-µF ceramic capacitor.
VIN
VSENSE
14−16
2
Input supply for the power MOSFET switches and internal bias regulator. Bypass VIN pins to PGND pins close to device package with a
high quality, low ESR 1-µF to 10-µF ceramic capacitor.
Error amplifier inverting input. Connect directly to output voltage sense point.
Copyright © 2002–2015, Texas Instruments Incorporated
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3
TPS54311, TPS54312, TPS54313
TPS54314, TPS54315, TPS54316
SLVS416C – FEBRUARY 2002 – REVISED JANUARY 2015
www.ti.com
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
VI
Input voltage
VO
Output voltage
IO
Source current
IS
Sink current
Voltage differential
MIN
MAX
UNIT
VIN, SS/ENA, SYNC
−0.3
7
V
RT
−0.3
6
V
VSENSE
−0.3
4
V
BOOT
−0.3
17
V
VBIAS, PWRGD, COMP
−0.3
7
V
PH
−0.6
10
V
PH
Internally Limited
V
COMP, VBIAS
6
PH
6
A
COMP
6
mA
SS/ENA, PWRGD
10
mA
±0.3
V
TJ
Operating virtual junction temperature
–40
125
°C
Tstg
Storage temperature
−65
150
°C
(1)
AGND to PGND
mA
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
VI
Input voltage range
TJ
Operating junction temperature
MIN
MAX
3
6
UNIT
V
–40
125
°C
6.3 Thermal Information (1)
TPS5431x
THERMAL METRIC (2)
RθJA
(1)
(2)
PWP (28 PINS)
Junction-to-ambient thermal resistance
26.0
Junction-to-ambient thermal resistance (without solder on PowerPad)
57.5
UNIT
°C/W
Test board conditions:
(a) 3 inches × 3 inches, 2 layers, Thickness 0.062 inch
(b) 1.5 oz copper traces located on the top of the PCB
(c) 1.5 oz copper plane on the bottom of the PCB
(d) Ten thermal vias (see recommended land pattern)
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
6.4 Dissipation Ratings (1) (2)
TA = 25 °C
POWER RATING
PACKAGE
20-Pin PWP with solder
20-pin PWP without solder
(1)
(2)
(3)
4
3.85
(3)
1.73
TA = 70 °C
POWER RATING
TA = 85 °C
POWER RATING
UNIT
2.12
1.54
W
0.96
0.69
W
For more information on the PWP package, refer to TI technical brief, SLMA002
Test board conditions:
(a) 3 inches × 3 inches, 2 layers, Thickness 0.062 inch
(b) 1.5 oz copper traces located on the top of the PCB
(c) 1.5 oz copper plane on the bottom of the PCB
(d) Ten thermal vias (see recommended land pattern)
Maximum power dissipation may be limited by overcurrent protection
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Product Folder Links: TPS54311 TPS54312 TPS54313 TPS54314 TPS54315 TPS54316
TPS54311, TPS54312, TPS54313
TPS54314, TPS54315, TPS54316
www.ti.com
SLVS416C – FEBRUARY 2002 – REVISED JANUARY 2015
6.5 Electrical Characteristics
TJ = –40°C to 125°C, VIN = 3 V to 6 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
fs = 350 kHz, FSEL ≤ 0.8 V, RT open
6.2
9.6
fs = 550 kHz, FSEL ≤ 2.5 V, RT open, Phase pin open
8.4
12.8
1
1.4
2.95
3.0
UNIT
SUPPLY VOLTAGE, VIN
VIN
Input voltage range
I(Q)
3
Quiescent current
Shutdown, SS/ENA = 0 V
6
V
mA
UNDERVOLTAGE LOCK OUT
Start threshold voltage
UVLO
V
Stop threshold voltage
2.70
2.80
Hysteresis voltage
0.14
0.16
V
2.5
µs
Rising and falling edge deglitch
(1)
V
BIAS VOLTAGE
VBIAS
Output voltage
I(VBIAS) = 0
2.70
2.80
Output current (2)
2.90
V
100
µA
OUTPUT VOLTAGE
TPS54311
TPS54312
TPS54313
VO
Output voltage
TPS54314
TPS54315
TPS54316
TJ = 25°C, VIN = 5 V
0.9
3 V ≤ VIN ≤ 6 V, 0 ≤ IL ≤ 3 A, −40°C ≤ TJ ≤ 125°C
–2.5%
TJ = 25°C, VIN = 5 V
2.5%
1.2
3 V ≤ VIN ≤ 6 V, 0 ≤ IL ≤ 3 A, −40°C ≤ TJ ≤ 125°C
–2.5%
TJ = 25°C, VIN = 5 V
2.5%
1.5
3 V ≤ VIN ≤ 6 V, 0 ≤ IL ≤ 3 A, −40°C ≤ TJ ≤ 125°C
–2.5%
TJ = 25°C, VIN = 5 V
2.5%
1.8
3 V ≤ VIN ≤ 6 V, 0 ≤ IL ≤ 3 A, −40°C ≤ TJ ≤ 125°C
–2.5%
TJ = 25°C, VIN = 5 V
2.5%
2.5
3 V ≤ VIN ≤ 6 V, 0 ≤ IL ≤ 3 A, −40° ≤ TJ ≤ 125°C
–2.5%
TJ = 25°C, VIN = 5 V
2.5%
3.3
4 V ≤ VIN ≤ 6 V, 0 ≤ IL ≤ 3 A, −40° ≤ TJ ≤ 125°C
−2.5%
2.5%
V
V
V
V
V
V
REGULATION
Line regulation (1) (3)
IL = 3 A, 350 ≤ fs ≤ 550 kHz, TJ = 85°C
0.21
%/V
Load regulation (1) (3)
IL = 0 A to 3 A, 350 ≤ fs ≤ 550 kHz, TJ = 85°C
0.21
%/A
OSCILLATOR
Internally set-free running frequency
Externally set-free running
frequency range
FSEL ≤ 0.8 V, RT open
280
350
420
FSEL ≥ 2.5 V, RT open
440
550
660
RT = 180 kΩ (1% resistor to AGND) (1)
252
280
308
RT = 100 kΩ (1% resistor to AGND)
460
500
540
663
700
762
RT = 68 kΩ (1% resistor to AGND)
High level threshold voltage at
FSEL
(1)
2.5
0.8
0.75
Ramp amplitude (peak-to-peak) (1)
Maximum duty cycle (1)
(1)
(2)
(3)
V
V
1
Minimum controllable on time (1)
kHz
V
Low level threshold voltage at FSEL
Ramp valley (1)
kHz
V
200
ns
90%
Specified by design
Static resistive loads only
Specified by the circuit used in Figure 10.
Copyright © 2002–2015, Texas Instruments Incorporated
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TPS54311, TPS54312, TPS54313
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SLVS416C – FEBRUARY 2002 – REVISED JANUARY 2015
www.ti.com
Electrical Characteristics (continued)
TJ = –40°C to 125°C, VIN = 3 V to 6 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ERROR AMPLIFIER
Error amplifier open loop voltage
gain (4)
Error amplifier unity gain
bandwidth (4)
3
26
dB
5
MHz
PWM COMPARATOR
PWM comparator propagation delay
time, PWM comparator input to PH 10-mV overdrive (4)
pin (excluding dead time)
70
85
ns
1.20
1.40
V
SLOW-START/ENABLE
Enable threshold voltage, SS/ENA
0.82
Enable hysteresis voltage,
SS/ENA (4)
Falling edge deglitch, SS/ENA
Internal slow-start
time (4)
(4)
0.03
V
2.5
µs
TPS54311
2.6
3.3
4.1
TPS54312
3.5
4.5
5.4
TPS54313
4.4
5.6
6.7
TPS54314
2.6
3.3
4.1
TPS54315
3.6
4.7
5.6
TPS54316
4.7
6.1
7.6
3
5
8
µA
1.5
2.3
4
mA
Charge current, SS/ENA
SS/ENA = 0V
Discharge current, SS/ENA
SS/ENA = 0.2 V, VI = 1.5 V
ms
POWERGOOD
Powergood threshold voltage
Powergood hysteresis voltage
VSENSE falling
(4)
Powergood falling edge deglitch (4)
90
%Vref
3
%Vref
35
Output saturation voltage, PWRGD
I(sink) = 2.5 mA
Leakage current, PWRGD
VI = 5.5 V
0.18
µs
0.30
V
1
µA
CURRENT LIMIT
Current limit
VI = 3 V, output shorted (4)
42
6.5
VI = 6 V, output shorted (4)
4.5
7.5
Current limit leading edge blanking
time (4)
Current limit total response time
(4)
A
100
ns
200
ns
THERMAL SHUTDOWN
Thermal shutdown trip point (4)
135
Thermal shutdown hysteresis (4)
150
165
10
°C
OUTPUT POWER MOSFETS
rDS(on)
(4)
(5)
6
Power MOSFET switches
VI = 6 V (5)
IO = 3 A, VI = 3 V (5)
59
88
856
136
mΩ
Specified by design
Matched MOSFETs, low side rDS(on) production tested, high side rDS(on) specified by design.
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Product Folder Links: TPS54311 TPS54312 TPS54313 TPS54314 TPS54315 TPS54316
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TPS54314, TPS54315, TPS54316
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SLVS416C – FEBRUARY 2002 – REVISED JANUARY 2015
6.6 Typical Characteristics
100
Drain-Source On-State Resistance − Ω
Drain-Source On-State Resistance − Ω
120
VI = 3.3 V
IO = 3 A
100
80
60
40
20
0
25
85
IO = 3 A
60
40
20
0
−40
0
−40
VI = 5 V
80
125
0
25
85
125
Figure 1. Drain-source On-state Resistance
vs Junction Temperature
Figure 2. Drain-source On-state Resistance
vs Junction Temperature
750
650
FSEL ≥ 2.5 V
550
450
FSEL ≤ 0.8 V
350
250
−40
0
25
85
125
f – Externally Set Oscillator Frequency – kHz
TJ − Junction Temperature − °C
f – Internally Set Oscillator Frequency – kHz
TJ − Junction Temperature − °C
800
RT = 68 k
700
600
RT = 100 k
500
400
RT = 180 k
300
200
−40
0
85
25
125
TJ − Junction Temperature − °C
TJ − Junction Temperature − °C
Figure 3. Internally Set Oscillator Frequency
vs Junction Temperature
Figure 4. Externally Set Oscillator Frequency
vs Junction Temperature
0.8950
0.895
VO − Output Voltage Regulation − V
Vref − Voltage Reference – V
TA = 85°C
0.893
0.891
0.889
0.887
0.885
−40
0.8930
0.8910
0.8890
f = 350 kHz
0.8870
0.8850
0
25
85
125
TJ − Junction Temperature − °C
Figure 5. Voltage Reference vs Junction Temperature
Copyright © 2002–2015, Texas Instruments Incorporated
3
4
5
VI − Input Voltage − V
6
Figure 6. Output Voltage Regulation vs Input Voltage
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SLVS416C – FEBRUARY 2002 – REVISED JANUARY 2015
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Typical Characteristics (continued)
RL= 10 kΩ,
CL = 160 pF,
TA = 25°C
−40
100
−60
80
Phase
−80
−100
60
−120
40
Internal Slow-Start Time − ms
−20
Gain
−140
20
Phase − Degrees
120
Gain − dB
3.80
0
140
−160
0
−180
−20
−200
10 k 100 k 1 M 10 M
0
10
100
1k
3.65
3.50
3.35
3.20
3.05
2.90
2.75
−40
f − Frequency − Hz
Figure 7. Error Amplifier Open Loop Response
0
25
85
TJ − Junction Temperature − °C
125
Figure 8. Internal Slow-start Time vs Junction Temperature
2.25
TJ − 125°C,
fs = 700 kHz
Device Power Losses − W
2
1.75
1.5
VI = 3.3 V
1.25
1
VI = 5 V
0.75
0.5
0.25
0
0
1
2
3
IL − Load Current − A
4
Figure 9. Device Power Losses vs Load Current
8
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Product Folder Links: TPS54311 TPS54312 TPS54313 TPS54314 TPS54315 TPS54316
TPS54311, TPS54312, TPS54313
TPS54314, TPS54315, TPS54316
www.ti.com
SLVS416C – FEBRUARY 2002 – REVISED JANUARY 2015
7 Detailed Description
7.1 Overview
As members of the SWIFT™ family of DC - DC regulators, the TPS54311, TPS54312, TPS54313, TPS54314,
TPS54315, and TPS54316 low-input-voltage high-outputcurrent synchronous-buck PWM converters integrate all
required active components. Included on the substrate with the listed features are a true, high performance,
voltage error amplifier that provides high performance under transient conditions; an undervoltage-lockout circuit
to prevent start-up until the input voltage reaches 3 V; an internally and externally set slow-start circuit to limit inrush currents; and a powergood output useful for processor/logic reset, fault signaling, and supply sequencing.
7.2 Functional Block Diagram
AGND
VBIAS
VIN
Enable
5 µA Comparator
SS/ENA
Falling
Edge
Deglitch
1.2 V
Hysteresis: 0.03 V
VIN UVLO
Comparator
VIN
2.95 V
Hysteresis: 0.16 V
VIN
ILIM
Comparator
Thermal
Shutdown
145°C
2.5 µs
REG
VBIAS
SHUTDOWN
VIN
Leading
Edge
Blanking
Falling
and
Rising
Edge
Deglitch
100 ns
BOOT
2.5 µs
SS_DIS
SHUTDOWN
Internal/External
Slow-Start
(Internal Slow-Start Time =
3.3 ms to 6.6 ms)
VI
PH
+
−
S
40 kΩ
Error
Amplifier
VI
Feed-Forward
Compensation
PWM
Comparator
25 ns Adaptive
Deadtime
VO
CO
Adaptive Dead-Time
and
Control Logic
R Q
2 kΩ
LOUT
VIN
OSC
PGND
Power good
Comparator
Reference/
DAC
Falling
Edge
Deglitch
VSENSE
0.90 Vref
TPS5431x
Hysteresis: 0.03 Vref
VSENSE
RT
SHUTDOWN
PWRGD
35 µs
FSEL
7.3 Feature Description
7.3.1 Undervoltage Lock Out (UVLO)
The TPS5431x incorporates an UVLO circuit to keep the device disabled when the input voltage (VIN) is
insufficient. During power up, internal circuits are held inactive until VIN exceeds the nominal UVLO threshold
voltage of 2.95 V. Once the UVLO start threshold is reached, device start-up begins. The device operates until
VIN falls below the nominal UVLO stop threshold of 2.8 V. Hysteresis in the UVLO comparator, and a 2.5-µs
rising and falling edge deglitch circuit reduce the likelihood of shutting the device down due to noise on VIN.
Copyright © 2002–2015, Texas Instruments Incorporated
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Feature Description (continued)
7.3.2 Slow-Start/Enable (SS/ENA)
The slow-start/enable pin provides two functions; first, the pin acts as an enable (shutdown) control by keeping
the device turned off until the voltage exceeds the start threshold voltage of approximately 1.2 V. When SS/ENA
exceeds the enable threshold, device start up begins. The reference voltage fed to the error amplifier is linearly
ramped up from 0 V to 0.891 V in 3.35 ms. Similarly, the converter output voltage reaches regulation in
approximately 3.35 ms. Voltage hysteresis and a 2.5-µs falling edge deglitch circuit reduce the likelihood of
triggering the enable due to noise.
Table 1. Device Startup Times
DEVICE
OUTPUT VOLTAGE
SLOW-START
TPS54311
0.9 V
3.3 ms
TPS54312
1.2 V
4.5 ms
TPS54313
1.5 V
5.6 ms
TPS54314
1.8 V
3.3 ms
TPS54315
2.5 V
4.7 ms
TPS54316
3.3 V
6.1 ms
The second function of the SS/ENA pin provides an external means of extending the slow-start time with a lowvalue capacitor connected between SS/ENA and AGND. Adding a capacitor to the SS/ENA pin has two effects
on start-up. First, a delay occurs between release of the SS/ENA pin and start up of the output. The delay is
proportional to the slow-start capacitor value and lasts until the SS/ENA pin reaches the enable threshold. The
start-up delay is approximately:
1.2 V
t d = C(SS) ´
5 mA
(1)
Second, as the output becomes active, a brief ramp up at the internal slow-start rate may be observed before the
externally set slow-start rate takes control and the output rises at a rate proportional to the slow-start capacitor.
The slow-start time set by the capacitor is approximately:
0.7 V
t(SS) = C(SS) ´
5 mA
(2)
The actual slow-start time is likely to be less than the above approximation due to the brief ramp up at the
internal rate
7.3.3 VBIAS Regulator (VBIAS)
The VBIAS regulator provides internal analog and digital blocks with a stable supply voltage over variations in
junction temperature and input voltage. A high quality, low-ESR, ceramic bypass capacitor is required on the
VBIAS pin. X7R or X5R grade dielectrics are recommended because their values are more stable over
temperature. The bypass capacitor should be placed close to the VBIAS pin and returned to AGND. External
loading on VBIAS is allowed, with the caution that internal circuits require a minimum VBIAS of 2.70 V, and
external loads on VBIAS with ac or digital switching noise may degrade performance. The VBIAS pin may be
useful as a reference voltage for external circuits.
7.3.4 Voltage Reference
The voltage reference system produces a precise Vref signal by scaling the output of a temperature stable
bandgap circuit. During manufacture, the bandgap and scaling circuits are trimmed to produce 0.891 V at the
output of the error amplifier, with the amplifier connected as a voltage follower. The trim procedure adds to the
high precision regulation of the TPS5431x, since it cancels offset errors in the scale and error amplifier circuits.
10
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SLVS416C – FEBRUARY 2002 – REVISED JANUARY 2015
7.3.5 Oscillator and PWM Ramp
The oscillator frequency can be set to internally fixed values of 350 kHz or 550 kHz using the FSEL pin as a
static digital input. If a different frequency of operation is required for the application, the oscillator frequency can
be externally adjusted from 280 kHz to 700 kHz by connecting a resistor to the RT pin to ground and floating the
FSEL pin. The switching frequency is approximated by the following equation, where R is the resistance from RT
to AGND:
100 kW
´ 500 [kHz]
Switching Frequency =
(3)
R
Table 2. Summary of the Frequency Selection Configurations
SWITCHING FREQUENCY
FSEL PIN
RT PIN
350 kHz, internally set
Float or AGND
Float
550 kHz, internally set
≥2.5 V
Float
Externally set 280 kHz to 700 kHz
Float
R = 68 kΩ to 180 kΩ
7.3.6 Error Amplifier
The high performance, wide bandwidth, voltage error amplifier is gain limited to provide internal compensation of
the control loop. The user is given limited flexibility in choosing output L and C filter components. Inductance
values of 4.7 µH to 10 µH are typical and available from several vendors. The resulting designs exhibit good
noise and ripple characteristics, along with exceptional transient response. Transient recovery times are typically
in the range of 10 to 20 µs.
7.3.7 PWM Control
Signals from the error amplifier output, oscillator, and current limit circuit are processed by the PWM control logic.
Referring to the internal block diagram, the control logic includes the PWM comparator, OR gate, PWM latch,
and portions of the adaptive dead-time and control logic block. During steady-state operation below the current
limit threshold, the PWM comparator output and oscillator pulse train alternately reset and set the PWM latch.
Once the PWM latch is set, the low-side FET remains on for a minimum duration set by the oscillator pulse
duration. During this period, the PWM ramp discharges rapidly to its valley voltage. When the ramp begins to
charge back up, the low-side FET turns off and high-side FET turns on. As the PWM ramp voltage exceeds the
error amplifier output voltage, the PWM comparator resets the latch, thus turning off the high-side FET and
turning on the low-side FET. The low-side FET remains on until the next oscillator pulse discharges the PWM
ramp
During transient conditions, the error amplifier output could be below the PWM ramp valley voltage or above the
PWM peak voltage. If the error amplifier is high, the PWM latch is never reset and the high-side FET remains on
until the oscillator pulse signals the control logic to turn the high-side FET off and the low-side FET on. The
device operates at its maximum duty cycle until the output voltage rises to the regulation set-point, setting
VSENSE to approximately the same voltage as Vref. If the error amplifier output is low, the PWM latch is
continually reset and the high-side FET does not turn on. The low-side FET remains on until the VSENSE
voltage decreases to a range that allows the PWM comparator to change states. The TPS5431x is capable of
sinking current continuously until the output reaches the regulation set-point.
If the current limit comparator trips for longer than 100 ns, the PWM latch resets before the PWM ramp exceeds
the error amplifier output. The high-side FET turns off and low-side FET turns on to decrease the energy in the
output inductor and consequently the output current. This process is repeated each cycle in which the current
limit comparator is tripped.
7.3.8 Dead-Time Control and MOSFET Drivers
Adaptive dead-time control prevents shoot-through current from flowing in both N-channel power MOSFETs
during the switching transitions by actively controlling the turnon times of the MOSFET drivers. The high-side
driver does not turn on until the voltage at the gate of the low-side FET is below 2 V. The high-side and low-side
drivers are designed with 300 mA source and sink capability to quickly drive the power MOSFETs gates. The
low-side driver is supplied from VIN, while the high-side drive is supplied from the BOOT pin. A bootstrap circuit
uses an external BOOT capacitor and internal 2.5-Ω bootstrap switch connected between the VIN and BOOT
pins. The integrated bootstrap switch improves drive efficiency and reduces external component count.
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7.3.9 Overcurrent Protection
The cycle by cycle current limiting is achieved by sensing the current flowing through the high-side MOSFET and
differential amplifier and comparing it to the preset overcurrent threshold. The high-side MOSFET is turned off
within 200 ns of reaching the current limit threshold. A 100-ns leading edge blanking circuit prevents false
tripping of the current limit. Current limit detection occurs only when current flows from VIN to PH when sourcing
current to the output filter. Load protection during current sink operation is provided by thermal shutdown.
7.3.10 Thermal Shutdown
The device uses the thermal shutdown to turn off the power MOSFETs and disable the controller if the junction
temperature exceeds 150°C. The device is released from shutdown when the junction temperature decreases to
10°C below the thermal shutdown trip point and starts up under control of the slow-start circuit. Thermal
shutdown provides protection when an overload condition is sustained for several milliseconds. With a persistent
fault condition, the device cycles continuously; starting up by control of the soft-start circuit, heating up due to the
fault, and then shutting down upon reaching the thermal shutdown point.
7.3.11 Powergood (PWRGD)
The powergood circuit monitors for undervoltage conditions on VSENSE. If the voltage on VSENSE is 10%
below the reference voltage, the open-drain PWRGD output is pulled low. PWRGD is also pulled low if VIN is
less than the UVLO threshold, or SS/ENA is low, or thermal shutdown is asserted. When VIN = UVLO threshold,
SS/ENA = enable threshold, and VSENSE > 90% of Vref, the open-drain output of the PWRGD pin is high. A
hysteresis voltage equal to 3% of Vref and a 35-µs falling edge deglitch circuit prevent tripping of the powergood
comparator due to high frequency noise.
7.4 Device Functional Modes
7.4.1 Continuous Conduction Mode
The TPS5431x devices operate in continuous conduction mode, i.e. the low-side MOSFET runs fully
complimentary to the high-side MOSFET regardless of output current.
7.4.2 Switching Frequency Selection/Synchronization
Depending on the configuration of the RT and SYNC pins, the TPS5431x can be configured to switch at 350
kHz, or 550 kHz without external components, or any frequency between 280 kHz and 700 kHz as configured by
a resistor from the RT pin to ground. The TPS54310 can also be synchronized to an external clock using the
SYNC pin. See Table 2 for more information.
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SLVS416C – FEBRUARY 2002 – REVISED JANUARY 2015
8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TPS5431x devices are 3-V to 6-V integrated FET synchronous buck converters. They are used to convert a
DC input voltage on the VIN pins to a lower output voltage at 3 A maximum output current.
8.2 Typical Application
Figure 10 shows the schematic diagram for a typical TPS54314 application. The TPS54314 (U1) can provide up
to 3 A of output current at a nominal output voltage of 1.8 V. For proper thermal performance, the PowerPAD
underneath the TPS54314 integrated circuit needs to be soldered to the printed circuit board.
J1
VI
2
+
1
GND
C2
R1
10 kΩ
1
PWRGD
J3
VO
GND
1
L1
5.2 µH
C7
0.047 µF
1
2
+ C9
470 µF
4V
C11
1000 pF
U1
TPS54314PWP
1
AGND
RT
2 VSENSE
FSEL
3
NC
SS/ENA
4 PWRGD
VBIAS
5 BOOT
VIN
6 PH
VIN
7
PH
VIN
8
PH
PGND
9
PGND
PH
10
PH
PGND
PwrPAD
20
R7
19
71.5 kΩ
18
17
16
15
14
13
C8
10 µF
C3
0.1 µF
12
11
Optional
Figure 10. TPS54314 Schematic
8.2.1 Design Requirements
The design requirements for this example are listed in Table 3.
Table 3. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
DC Input Voltage Range
3V–6V
DC Output Voltage
1.8 V
DC Output Current Range
0–3A
Output Voltage Ripple
20 mV
Load Transient Output Deviation
±80 mV
8.2.2 Detailed Design Procedure
8.2.2.1 Component Selection
The values for the components used in this design example were selected using the SWIFT designer software
tool. SWIFT designer provides a complete design environment for developing dc-dc converters using the
TPS54314, or other devices in the SWIFT product family. Additional design information is available at
www.ti.com.
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8.2.2.2 Input Voltage
The input to the circuit is a nominal 5 VDC, applied at J1. The optional input filter (C2) is a 220-µF POSCAP
capacitor, with a maximum allowable ripple current of 3 A. C8 is the decoupling capacitor for the TPS54314 and
must be located as close to the device as possible.
8.2.2.3 Feedback Circuit
The output voltage of the converter is fed directly into the VSENSE pin of the TPS54314. The TPS54314 is
internally compensated to provide stability of the output under varying line and load conditions.
8.2.2.4 Operating Frequency
In the application circuit, a 700 kHz operating frequency is selected by leaving FSEL open and connecting a 71.5
kΩ resistor between the RT pin and AGND. Different operating frequencies may be selected by varying the value
of R3 using Equation 4:
500 kHz
R=
´ 100 kW
SwitchingFrequency
(4)
Alternately, a preset operating frequency of 350 kHz or 550 kHz can be selected by leaving RT open and
connecting the FSEL pin to AGND or VIN respectively.
8.2.2.5 Output Filter
The output filter is composed of a 5.2-µH inductor and 470-µF capacitor. The inductor is a low-DC resistance
(16-mΩ) type, Sumida CDRH104R−5R2. The capacitor used is a 4-V POSCAP with a maximum ESR of 40 mΩ.
The output filter components work with the internal compensation network to provide a stable closed loop
response for the converter.
8.2.3 Application Curves
1.9
100
Efficiency at 700 kHz
5 VI
VO − Output Voltage − %
90
Efficiency − %
3.3 VI
80
70
1.85
3.3 VI
1.8
5 VI
1.75
60
1.7
50
0
1
2
3
4
0
5
1
2
3
4
5
Load Current − A
IL − Load Current − A
Figure 11. Efficiency vs Load Current
Figure 12. Output Voltage vs Load Current
60
180
135
45
Gain − dB
45
Gain
15
0
0
1k
10 k
100 k
f − Frequency − Hz
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VI = 5 V
IO = 3 A
400 ns/div
−90
1M
Figure 13. Loop Response
14
VO (AC)
10 mV/div
−45
−15
−30
100
Amplitude − 10 mV/div
90
30
Phase − Degrees
Phase
Time − 100 µs/div
Figure 14. Output Ripple Voltage
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Start Up Waveforms – V
SLVS416C – FEBRUARY 2002 – REVISED JANUARY 2015
Load Transient Response − mV
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VO 50 mV/div
IO 2 A/div
VI 2 V/div
VO 2 V/div
VPWRGD 5 V/div
VI = 5 V
Time − 10 µs/div
Time − 2 ms/div
Figure 16. Start-Up Waveforms
Figure 15. Load Transient Response
125
T A − Ambient Temperature − ° C
115
105
†
95
85
Safe Operating Area †
Safe operating area is applicable to the test
board conditions listed in the Dissipation Rating
Table section of this data sheet.
75
65
55
45
35
25
0
1
2
3
4
IL − Load Current − A
Figure 17. Ambient Temperature vs Load Current
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9 Power Supply Recommendations
The TPS5431x devices are designed to operate from an input supply from 3 V to 6 V on the VIN pins. This
supply must be well regulated and properly bypassed for proper operation of the TPS5431x converter.
Additionally, the VBIAS pin must have good local bypassing for noise performance. See the recommendations in
Layout and Pin Configuration and Functions for more information.
10 Layout
10.1 Layout Guidelines
Figure 18 shows a generalized PCB layout guide for the TPS5431x.
• The VIN pins should be connected together on the printed circuit board (PCB) and bypassed with a low ESR
ceramic bypass capacitor. Care should be taken to minimize the loop area formed by the bypass capacitor
connections, the VIN pins, and the TPS5431x ground pins. The minimum recommended bypass capacitance
is 10-µF ceramic with a X5R or X7R dielectric and the optimum placement is closest to the VIN pins and the
PGND pins.
• The TPS5431x has two internal grounds (analog and power). Inside the TPS5431x, the analog ground ties to
all of the noise sensitive signals, while the power ground ties to the noisier power signals. Noise injected
between the two grounds can degrade the performance of the TPS5431x, particularly at higher output
currents. Ground noise on an analog ground plane can also cause problems with some of the control and
bias signals. For these reasons, separate analog and power ground traces are recommended. There should
be an area of ground one the top layer directly under the IC, with an exposed area for connection to the
PowerPAD. Use vias to connect this ground area to any internal ground planes. Use additional vias at the
ground side of the input and output filter capacitors as well. The AGND and PGND pins should be tied to the
PCB ground by connecting them to the ground area under the device as shown. The only components that
should tie directly to the power ground plane are the input capacitors, the output capacitors, the input voltage
decoupling capacitor, and the PGND pins of the TPS5431x. Use a separate wide trace for the analog ground
signal path. This analog ground should be used for the timing resistor RT, slow-start capacitor and bias
capacitor grounds. Connect this trace directly to AGND (pin 1).
• The PH pins should be tied together and routed to the output inductor. Since the PH connection is the
switching node, inductor should be located very close to the PH pins and the area of the PCB conductor
minimized to prevent excessive capacitive coupling.
• Connect the boot capacitor between the phase node and the BOOT pin as shown. Keep the boot capacitor
close to the IC and minimize the conductor trace lengths.
• Connect the output filter capacitor(s) as shown between the VOUT trace and PGND. It is important to keep
the loop formed by the PH pins, Lout, Cout and PGND as small as practical.
• Connect the output of the circuit directly to the VSENSE pin. Do not place this trace too close to the PH trace.
Do to the size of the IC package and the device pinout, they will have to be routed somewhat close, but
maintain as much separation as possible while still keeping the layout compact.
• Connect the bias capacitor from the VBIAS pin to analog ground using the isolated analog ground trace. If a
slow-start capacitor or RT resistor is used, or if the SYNC pin is used to select 350-kHz operating frequency,
connect them to this trace as well.
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SLVS416C – FEBRUARY 2002 – REVISED JANUARY 2015
10.2 Layout Example
ANALOG GROUND TRACE
FREQUENCY SET RESISTOR
AGND
RT
NC
SS/ENA
PWRGD
BOOT
CAPACITOR
BOOT
SLOW START
CAPACITOR
FSEL
VSENSE
VBIAS
EXPOSED
POWERPAD
AREA
BIAS CAPACITOR
VIN
PH
VIN
PH
VIN
PH
PGND
PH
PGND
PH
PGND
Vin
VOUT
OUTPUT INDUCTOR
PH
INPUT
BYPASS
CAPACITOR
OUTPUT
FILTER
CAPACITOR
INPUT
BULK
FILTER
TOPSIDE GROUND AREA
VIA to Ground Plane
Figure 18. TPS5431x PCB Layout
10.3 Thermal Considerations
For operation at full rated load current, the analog ground plane must provide adequate heat dissipating area. A
3 inch by 3 inch plane of 1 ounce copper is recommended, though not mandatory, depending on ambient
temperature and airflow. Most applications have larger areas of internal ground plane available, and the
PowerPAD should be connected to the largest area available. Additional areas on the top or bottom layers also
help dissipate heat, and any area available should be used when 3 A or greater operation is desired. Connection
from the exposed area of the PowerPAD to the analog ground plane layer should be made using 0.013 inch
diameter vias to avoid solder wicking through the vias. Six vias should be in the PowerPAD area with four
additional vias located under the device package. The size of the vias under the package, but not in the exposed
thermal pad area, can be increased to 0.018. Additional vias beyond the ten recommended that enhance thermal
performance should be included in areas not under the device package.
6 PL ∅ 0.0130
4 PL ∅ 0.0180
Connect Pin 1 to Analog Ground Plane
in This Area for Optimum Performance
Minimum Recommended Thermal Vias: 6 × .013 dia.
Inside Powerpad Area 4 × .018 dia. Under Device as Shown.
Additional .018 dia. Vias May be Used if Top Side Analog
Ground Area is Extended.
0.0150
0.06
0.0227
0.0600
0.0400
0.2560
0.2454
0.1010
0.0400
0.0600
0.0256
Minimum Recommended Top
Side Analog Ground Area
0.1700
0.1340
0.0620
0.0400
Minimum Recommended Exposed
Copper Area For Powerpad. 5mm
Stencils may Require 10 Percent
Larger Area
Figure 19. Recommended Land Pattern for 20-Pin PWP PowerPAD
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11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
11.1.1.1 Related DC - DC Products
• TPS40000—Low-input, voltage-mode synchronous buck controller
• TPS759xx—7.5-A low dropout regulator
• PT6440 series—6-A plugin modules
11.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 4. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
TPS54311
Click here
Click here
Click here
Click here
Click here
TPS54312
Click here
Click here
Click here
Click here
Click here
TPS54313
Click here
Click here
Click here
Click here
Click here
TPS54314
Click here
Click here
Click here
Click here
Click here
TPS54315
Click here
Click here
Click here
Click here
Click here
TPS54316
Click here
Click here
Click here
Click here
Click here
11.3 Trademarks
SWIFT, PowerPAD are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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13-Aug-2021
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS54311PWP
ACTIVE
HTSSOP
PWP
20
70
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
TPS54311
TPS54312PWP
ACTIVE
HTSSOP
PWP
20
70
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
TPS54312
TPS54312PWPG4
ACTIVE
HTSSOP
PWP
20
70
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
TPS54312
TPS54312PWPR
ACTIVE
HTSSOP
PWP
20
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
TPS54312
TPS54312PWPRG4
ACTIVE
HTSSOP
PWP
20
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
TPS54312
TPS54313PWP
ACTIVE
HTSSOP
PWP
20
70
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
TPS54313
TPS54313PWPG4
ACTIVE
HTSSOP
PWP
20
70
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
TPS54313
TPS54313PWPR
ACTIVE
HTSSOP
PWP
20
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
TPS54313
TPS54314PWP
ACTIVE
HTSSOP
PWP
20
70
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
TPS54314
TPS54314PWPG4
ACTIVE
HTSSOP
PWP
20
70
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
TPS54314
TPS54314PWPR
ACTIVE
HTSSOP
PWP
20
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
TPS54314
TPS54314PWPRG4
ACTIVE
HTSSOP
PWP
20
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
TPS54314
TPS54315PWP
ACTIVE
HTSSOP
PWP
20
70
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
TPS54315
TPS54315PWPR
ACTIVE
HTSSOP
PWP
20
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
TPS54315
TPS54316PWP
ACTIVE
HTSSOP
PWP
20
70
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TPS54316
TPS54316PWPG4
ACTIVE
HTSSOP
PWP
20
70
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TPS54316
TPS54316PWPR
ACTIVE
HTSSOP
PWP
20
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TPS54316
TPS54316PWPRG4
ACTIVE
HTSSOP
PWP
20
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TPS54316
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
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13-Aug-2021
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
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RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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