Obsolete Devices:
TPS54314-Q1 and TPS54315-Q1
Typical Size
(6,3 mm x 6,4 mm)
TPS54311-Q1, TPS54312-Q1
TPS54313-Q1, TPS54314-Q1
TPS54315-Q1, TPS54316-Q1
www.ti.com
SGLS242G − OCTOBER 2004 − REVISED SEPTEMBER 2008
3-V TO 6-V INPUT, 3-A OUTPUT SYNCHRONOUS-BUCK PWM
SWITCHER WITH INTEGRATED FETs (SWIFT)
FEATURES
D Qualified for Automotive Applications
D 60-mΩ MOSFET Switches for High Efficiency
D
D
D
D
D
D
at 3-A Continuous Output Source or Sink
Current
0.9-V, 1.2-V, 1.5-V, 1.8-V, 2.5-V, and 3.3-V Fixed
Output Voltage Devices With 1% Initial
Accuracy
Internally Compensated for Low Parts Count
Fast Transient Response
Wide PWM Frequency: Fixed 350 kHz,
550 kHz, or Adjustable 280 kHz to 700 kHz
Load Protected by Peak Current Limit and
Thermal Shutdown
Integrated Solution Reduces Board Area and
Total Cost
APPLICATIONS
D Low-Voltage, High-Density Systems With
D
D
D
Power Distributed at 5 V or 3.3 V
Point of Load Regulation for High
Performance DSPs, FPGAs, ASICs, and
Microprocessors
Broadband, Networking and Optical
Communications Infrastructure
Automotive Telematics
DESCRIPTION
As members of the SWIFT family of dc/dc regulators, the
TPS54311,
TPS54312,
TPS54313,
TPS54314,
TPS54315, and TPS54316 low-input-voltage high-output
current synchronous-buck PWM converters integrate all
required active components. Included on the substrate
with the listed features are a true, high performance,
voltage error amplifier that provides high performance
under transient conditions; an undervoltage-lockout circuit
to prevent start-up until the input voltage reaches 3 V; an
internally and externally set slow-start circuit to limit
in-rush currents; and a power good output useful for
processor/logic reset, fault signaling, and supply
sequencing.
The TPS54311, TPS54312, TPS54313, TPS54314,
TPS54315, and TPS54316 devices are available in a
thermally enhanced 20-pin TSSOP (PWP) PowerPAD
package, which eliminates bulky heatsinks. Texas
Instruments provides evaluation modules and the SWIFT
designer software tool to aid in quickly achieving
high-performance power supply designs to meet
aggressive equipment development cycles.
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during
storage or handling to prevent electrostatic damage to the MOS gates.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD and SWIFT are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date. Products
conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters.
Copyright 2008, Texas Instruments Incorporated
Obsolete Devices:
TPS54314-Q1 and TPS54315-Q1
TPS54311-Q1, TPS54312-Q1
TPS54313-Q1, TPS54314-Q1
TPS54315-Q1, TPS54316-Q1
www.ti.com
SGLS242G − OCTOBER 2004 − REVISED SEPTEMBER 2008
EFFICIENCY
vs
LOAD CURRENT
Simplified Schematic
Input
VIN
96
94
Output
PH
92
Efficiency − %
TPS54316
BOOT
PGND
VBIAS
VSENSE
GND
90
88
86
84
TA = 25°C
VI = 5 V
VO = 3.3 V
82
80
0
0.5
1
1.5
2
2.5
3
Load Current − A
ORDERING INFORMATION(1)
TJ
OUTPUT
VOLTAGE
PACKAGED DEVICES
PLASTIC HTSSOP (PWP)(2)
0.9 V
TPS54311QPWPRQ1(3)
−40°C
40 C to 125°C
125 C
1.2 V
TPS54312QPWPRQ1
1.5 V
TPS54313QPWPRQ1(3)
TJ
−40°C
40 C to 125°C
125 C
OUTPUT
VOLTAGE
PACKAGED DEVICES
PLASTIC HTSSOP (PWP)(2)
1.8 V
TPS54314QPWPRQ1(3)
2.5 V
TPS54315QPWPRQ1
3.3 V
TPS54316QPWPRQ1(3)
(1)
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site
at www.ti.com.
(2) The PWP package is taped and reeled as indicated by the R suffix. See application section of data sheet for PowerPAD drawing and layout
information.
(3) Product Preview
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted(1)
Input voltage range,
range VI
Output voltage range
range, VO
Source current
current, IO
VIN, SS/ENA, FSEL
−0.3 V to 7 V
RT
−0.3 V to 6 V
VSENSE
−0.3 V to 4 V
BOOT
−0.3 V to 17 V
VBIAS, PWRGD, COMP
−0.3 V to 7 V
PH
−0.6 V to 10 V
PH
Internally Limited
COMP, VBIAS
6 mA
PH
Sink current
Voltage differential
6A
COMP
6 mA
SS/ENA,PWRGD
10 mA
±0.3 V
AGND to PGND
Operating virtual junction temperature range, TJ
−40°C to 150°C
Storage temperature, Tstg
−65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
(1)
300°C
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
MIN
Input voltage range, VI
Operating junction temperature, TJ
2
NOM
MAX
UNIT
3
6
V
−40
125
°C
Obsolete Devices:
TPS54314-Q1 and TPS54315-Q1
TPS54311-Q1, TPS54312-Q1
TPS54313-Q1, TPS54314-Q1
TPS54315-Q1, TPS54316-Q1
www.ti.com
SGLS242G − OCTOBER 2004 − REVISED SEPTEMBER 2008
PACKAGE DISSIPATION RATINGS(1) (2)
PACKAGE
THERMAL IMPEDANCE
JUNCTION-TO-AMBIENT
TA = 25°C
POWER RATING
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
20-Pin PWP with solder
26°C/W
3.85 W(3)
2.12 W
1.54 W
20-Pin PWP without solder
57.5°C/W
1.73 W
0.96 W
0.69 W
(1)
For more information on the PWP package, see the Texas Instruments technical brief (SLMA002).
(2) Test board conditions:
1. 3” × 3”, 2 layers, Thickness: 0.062”
2. 1.5 oz copper traces located on the top of the PCB
3. 1.5 oz copper ground plane on the bottom of the PCB
4. Ten thermal vias (see the recommended land pattern in the Applications section of this data sheet)
(3) Maximum power dissipation may be limited by overcurrent protection.
ELECTRICAL CHARACTERISTICS
TJ = −40°C to 125°C, VIN = 3 V to 6 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
6.2
9.6
8.4
12.8
1
1.4
2.95
3
UNIT
SUPPLY VOLTAGE, VIN
VIN
Input voltage range
3
Quiescent current
fs = 350 kHz,
FSEL ≤ 0.8 V,
RT open
fs = 550 kHz,
Phase pin open
FSEL ≥ 2.5 V,
RT open,
Shutdown,
SS/ENA = 0 V
6
V
mA
UNDER VOLTAGE LOCK OUT
Start threshold voltage, UVLO
Stop threshold voltage, UVLO
2.7
Hysteresis voltage, UVLO
Rising and falling edge deglitch,
UVLO(1)
2.8
V
0.14
V
2.5
µs
BIAS VOLTAGE
Output voltage, VBIAS
I(VBIAS) = 0
2.7
2.8
Output current, VBIAS(2)
2.95
V
100
µA
OUTPUT VOLTAGE
TJ = 25°C,
VIN = 5 V
3 ≤ VIN ≤ 6 V,
0 ≤ IL ≤ 3 A,
TJ = 25°C,
VIN = 5 V
3 ≤ VIN ≤ 6 V,
0 ≤ IL ≤ 3 A,
TJ = 25°C,
VIN = 5 V
3 ≤ VIN ≤ 6 V,
0 ≤ IL ≤ 3 A,
TJ = 25°C,
VIN = 5 V
3 ≤ VIN ≤ 6 V,
0 ≤ IL ≤ 3 A,
TJ = 25°C,
VIN = 5 V
3.2 ≤ VIN ≤ 6 V,
0 ≤ IL ≤ 3 A,
TJ = 25°C,
VIN = 5 V
4 ≤ VIN ≤ 6 V,
0 ≤ IL ≤ 3 A,
−40 ≤ TJ ≤ 125
Line regulation(1) (3)
IL = 1.5 A,
350 ≤ fs ≤ 550 kHz,
TJ = 85°C
0.21
%/V
Load regulation(1) (3)
IL = 0 A to 3 A,
350 ≤ fs ≤ 550 kHz,
TJ = 85°C
0.21
%/A
TPS54311
TPS54312
TPS54313
VO
Output voltage
TPS54314
TPS54315
TPS54316
0.9
−40 ≤ TJ ≤ 125
−2.5%
V
2.5%
1.2
−40 ≤ TJ ≤ 125
−2.5%
V
2.5%
1.5
−40 ≤ TJ ≤ 125
−2.5%
−40 ≤ TJ ≤ 125
−2.5%
−40 ≤ TJ ≤ 125
−2.5%
V
2.5%
1.8
V
2.5%
2.5
V
2.5%
3.3
−2.5%
V
2.5%
REGULATION
(1)
Specified by design
(2) Static resistive loads only
(3) Specified by the circuit used in Figure 10.
3
TPS54311-Q1, TPS54312-Q1
TPS54313-Q1, TPS54314-Q1
TPS54315-Q1, TPS54316-Q1
Obsolete Devices:
TPS54314-Q1 and TPS54315-Q1
www.ti.com
SGLS242G − OCTOBER 2004 − REVISED SEPTEMBER 2008
ELECTRICAL CHARACTERISTICS (continued)
TJ = −40°C to 125°C, VIN = 3 V to 6 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
FSEL ≤ 0.8 V,
RT open
265
350
440
FSEL ≥ 2.5 V,
RT open
440
550
680
RT = 180 kΩ (1% resistor to AGND)(1)
252
280
308
RT = 160 kΩ (1% resistor to AGND)
290
312
350
RT = 68 kΩ (1% resistor to AGND)(1)
663
700
762
UNIT
OSCILLATOR
Internally set free-running
free running frequency
range
Externally
E
t
ll sett ffree-running
i ffrequency
range
High-level threshold voltage at FSEL
2.5
Frequency range, FSEL(1) (4)
0.8
50
Maximum duty cycle(1)
V
200
90%
Specified by design
Static resistive loads only
(3) Specified by the circuit used in Figure 10.
(4) To ensure proper operation when RC filter is used between external clock and FSEL pin, the recommended values are R ≤ 1kΩ and
C ≤ 68 pF.
(2)
4
kHz
V
1
Minimum controllable on time(1)
(1)
700
0.75
Ramp amplitude (peak-to-peak)(1)
V
ns
330
Ramp valley(1)
kHz
V
Low-level threshold voltage at FSEL
Pulse duration, FSEL(1)
kHz
ns
Obsolete Devices:
TPS54314-Q1 and TPS54315-Q1
www.ti.com
TPS54311-Q1, TPS54312-Q1
TPS54313-Q1, TPS54314-Q1
TPS54315-Q1, TPS54316-Q1
SGLS242G − OCTOBER 2004 − REVISED SEPTEMBER 2008
ELECTRICAL CHARACTERISTICS (continued)
TJ = −40°C to 125°C, VIN = 3 V to 6 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ERROR AMPLIFIER
Error amplifier open loop voltage gain(1)
Error amplifier unity gain bandwidth(1)
3
26
dB
5
MHz
PWM COMPARATOR
PWM comparator propagation delay time,
PWM comparator input to PH pin
(excluding dead time)
10-mV overdrive(1)
70
85
ns
1.2
1.4
V
SLOW-START/ENABLE
Enable threshold voltage, SS/ENA
0.82
Enable hysteresis voltage, SS/ENA(1)
Falling edge deglitch, SS/ENA(1)
Internal slow-start
slow start time(1)
0.03
V
2.5
µs
TPS54311
2.6
3.3
4.1
TPS54312
3.5
4.5
5.4
TPS54313
4.4
5.6
6.7
TPS54314
2.6
3.3
4.1
TPS54315
3.6
4.7
5.6
TPS54316
4.7
6.1
7.6
2.5
5
8
µA
1.2
2.3
4
mA
Charge current, SS/ENA
SS/ENA = 0 V
Discharge current, SS/ENA
SS/ENA = 0.2 V,
VI = 2.7 V
ms
POWER GOOD
Power good threshold voltage
Power good hysteresis
VSENSE falling
voltage(1)
Power good falling edge deglitch(1)
90
%Vref
3
%Vref
µs
35
Output saturation voltage, PWRGD
I(sink) = 2.5 mA
Leakage current, PWRGD
VI = 5.5 V
0.18
0.3
1
V
µA
CURRENT LIMIT
Current limit trip point
VI = 3 V, output shorted
4
6.5
VI = 6 V, output shorted
4.5
7.5
A
Current limit leading edge blanking time
See (1)
100
ns
Current limit total response time
See (1)
200
ns
THERMAL SHUTDOWN
Thermal shutdown trip point(1)
135
Thermal shutdown hysteresis(1)
150
165
°C
°C
10
OUTPUT POWER MOSFETS
rDS(on)
(1)
(2)
Power MOSFET switches
VI = 6 V(2)
59
88
V(2)
85
136
VI = 3
mΩ
Specified by design
Matched MOSFETs, low side rDS(on) production tested, high side rDS(on) specified by design.
5
TPS54311-Q1, TPS54312-Q1
TPS54313-Q1, TPS54314-Q1
TPS54315-Q1, TPS54316-Q1
Obsolete Devices:
TPS54314-Q1 and TPS54315-Q1
www.ti.com
SGLS242G − OCTOBER 2004 − REVISED SEPTEMBER 2008
PIN ASSIGNMENTS
PWP PACKAGE
(TOP VIEW)
AGND
VSENSE
NC
PWRGD
BOOT
PH
PH
PH
PH
PH
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
RT
FSEL
SS/ENA
VBIAS
VIN
VIN
VIN
PGND
PGND
PGND
NC − No internal connection
Terminal Functions
TERMINAL
NAME
DESCRIPTION
NO.
AGND
1
Analog ground. Return for compensation network/output divider, slow-start capacitor, VBIAS capacitor, RT resistor and
FSEL pin. Make PowerPAD connection to AGND.
BOOT
5
Bootstrap input. 0.022-µF to 0.1-µF low-ESR capacitor connected from BOOT to PH generates floating drive for the
high-side FET driver.
FSEL
19
Frequency select input. Provides logic input to select between two internally set switching frequencies.
3
No connection
NC
PGND
11−13
Power ground. High current return for the low-side driver and power MOSFET. Connect PGND with large copper areas to the
input and output supply returns, and negative terminals of the input and output capacitors.
PH
6−10
Phase input/output. Junction of the internal high and low-side power MOSFETs, and output inductor.
PWRGD
4
Power good open drain output. Hi-Z when VSENSE ≥ 90% Vref, otherwise PWRGD is low. Note that output is low when
SS/ENA is low or internal shutdown signal active.
RT
20
Frequency setting resistor input. Connect a resistor from RT to AGND to set the switching frequency, fs.
SS/ENA
18
Slow-start/enable input/output. Dual function pin which provides logic input to enable/disable device operation and capacitor
input to externally set the start-up time.
VBIAS
17
Internal bias regulator output. Supplies regulated voltage to internal circuitry. Bypass VBIAS pin to AGND pin with a high
quality, low ESR 0.1-µF to 1-µF ceramic capacitor.
14−16
Input supply for the power MOSFET switches and internal bias regulator. Bypass VIN pins to PGND pins close to device
package with a high quality, low ESR 1-µF to 10-µF ceramic capacitor.
VIN
VSENSE
6
2
Error amplifier inverting input. Connect directly to output voltage sense point.
Obsolete Devices:
TPS54314-Q1 and TPS54315-Q1
TPS54311-Q1, TPS54312-Q1
TPS54313-Q1, TPS54314-Q1
TPS54315-Q1, TPS54316-Q1
www.ti.com
SGLS242G − OCTOBER 2004 − REVISED SEPTEMBER 2008
FUNCTIONAL BLOCK DIAGRAM
AGND
VBIAS
VIN
Enable
5 µA Comparator
SS/ENA
Falling
Edge
Deglitch
1.2 V
Hysteresis: 0.03 V
VIN UVLO
Comparator
VIN
2.95 V
Hysteresis: 0.16 V
VIN
ILIM
Comparator
Thermal
Shutdown
145°C
2.5 µs
REG
VBIAS
SHUTDOWN
VIN
Leading
Edge
Blanking
Falling
and
Rising
Edge
Deglitch
100 ns
BOOT
2.5 µs
SS_DIS
SHUTDOWN
Internal/External
Slow-Start
(Internal Slow-Start Time =
3.3 ms to 6.6 ms)
VI
PH
+
−
S
40 kΩ
Error
Amplifier
VI
Feed-Forward
Compensation
PWM
Comparator
25 ns Adaptive
Deadtime
VO
CO
Adaptive Dead-Time
and
Control Logic
R Q
2 kΩ
LOUT
VIN
OSC
PGND
Power good
Comparator
Reference/
DAC
Falling
Edge
Deglitch
VSENSE
0.90 Vref
TPS5431x
Hysteresis: 0.03 Vref
VSENSE
RT
SHUTDOWN
PWRGD
35 µs
FSEL
7
Obsolete Devices:
TPS54314-Q1 and TPS54315-Q1
TPS54311-Q1, TPS54312-Q1
TPS54313-Q1, TPS54314-Q1
TPS54315-Q1, TPS54316-Q1
www.ti.com
SGLS242G − OCTOBER 2004 − REVISED SEPTEMBER 2008
TYPICAL CHARACTERISTICS
DRAIN-SOURCE ON-STATE RESISTANCE
vs
JUNCTION TEMPERATURE
100
IO = 3 A
80
60
40
20
VI = 5 V
0
25
85
IO = 3 A
80
60
40
20
0
−40
0
−40
125
TJ − Junction Temperature − °C
0
25
800
600
RT = 100 k
500
400
RT = 180 k
300
0.893
0.891
0.889
0.887
−80
−120
40
Gain
20
−140
−160
0
−180
−20
−200
10 k 100 k 1 M 10 M
0
10
100
1k
f − Frequency − Hz
Figure 7
Internal Slow-Start Time − ms
−40
−100
60
f = 350 kHz
0.8870
0
25
85
3
125
4
5
VI − Input Voltage − V
6
Figure 6
DEVICE POWER LOSSES
vs
LOAD CURRENT
3.80
2.25
3.65
2
−20
−60
Phase
0.8890
INTERNAL SLOW-START TIME
vs
JUNCTION TEMPERATURE
Phase − Degrees
RL= 10 kΩ,
CL = 160 pF,
TA = 25°C
125
0.8910
Figure 5
0
140
85
0.8930
TJ − Junction Temperature − °C
ERROR AMPLIFIER
OPEN LOOP RESPONSE
25
0.8850
0.885
−40
125
Figure 4
80
0
TA = 85°C
Device Power Losses − W
85
100
250
−40
0.8950
TJ − Junction Temperature − °C
120
350
OUTPUT VOLTAGE REGULATION
vs
INPUT VOLTAGE
VO − Output Voltage Regulation − V
700
25
FSEL ≤ 0.8 V
Figure 3
0.895
0
450
TJ − Junction Temperature − °C
RT = 68 k
200
−40
FSEL ≥ 2.5 V
550
VOLTAGE REFERENCE
vs
JUNCTION TEMPERATURE
Vref − Voltage Reference − V
f − Externally Set Oscillator Frequency − kHz
125
650
Figure 2
EXTERNALLY SET OSCILLATOR
FREQUENCY
vs
JUNCTION TEMPERATURE
Gain − dB
85
750
TJ − Junction Temperature − °C
Figure 1
8
f − Internally Set Oscillator Frequency −kHz
100
Drain-Source On-State Resistance − Ω
Drain-Source On-State Resistance − Ω
120
VI = 3.3 V
INTERNALLY SET OSCILLATOR
FREQUENCY
vs
JUNCTION TEMPERATURE
DRAIN-SOURCE ON-STATE RESISTANCE
vs
JUNCTION TEMPERATURE
3.50
3.35
3.20
3.05
TJ − 125°C,
fs = 700 kHz
1.75
1.5
VI = 3.3 V
1.25
1
VI = 5 V
0.75
0.5
2.90
0.25
2.75
−40
0
25
85
TJ − Junction Temperature − °C
Figure 8
125
0
0
1
2
3
IL − Load Current − A
Figure 9
4
Obsolete Devices:
TPS54314-Q1 and TPS54315-Q1
TPS54311-Q1, TPS54312-Q1
TPS54313-Q1, TPS54314-Q1
TPS54315-Q1, TPS54316-Q1
www.ti.com
SGLS242G − OCTOBER 2004 − REVISED SEPTEMBER 2008
APPLICATION INFORMATION
Figure 10 shows the schematic diagram for a typical
TPS54314 application. The TPS54314 (U1) can provide
up to 3 A of output current at a nominal output voltage of
J1
VI
2
+
1
GND
C2
R1
10 kΩ
1
PWRGD
L1
5.2 µH
J3
2
GND
C11
1000 pF
1
C7
0.047 µF
1
VO
1.8 V. For proper thermal performance, the PowerPAD
underneath the TPS54314 integrated circuit needs to be
soldered to the printed circuit board.
+ C9
470 µF
4V
U1
TPS54314PWP
1
AGND
RT
2 VSENSE
FSEL
3
NC
SS/ENA
4 PWRGD
VBIAS
5 BOOT
VIN
6 PH
VIN
7
PH
VIN
8
PH
PGND
9
PGND
PH
10
PH
PGND
PwrPAD
20
R7
19
71.5 kΩ
18
17
16
15
14
13
C8
10 µF
C3
0.1 µF
12
11
Optional
Figure 10. TPS54314 Schematic
INPUT VOLTAGE
OUTPUT FILTER
The input to the circuit is a nominal 5 VDC, applied at J1.
The optional input filter (C2) is a 220-µF POSCAP
capacitor, with a maximum allowable ripple current of 3 A.
C8 is the decoupling capacitor for the TPS54314 and must
be located as close to the device as possible.
The output filter is composed of a 5.2-µH inductor and
470-µF capacitor. The inductor is a low dc resistance
(16-mΩ) type, Sumida CDRH104R−5R2. The capacitor
used is a 4-V POSCAP with a maximum ESR of 40 mΩ.
The output filter components work with the internal
compensation network to provide a stable closed loop
response for the converter.
FEEDBACK CIRCUIT
GROUNDING AND PowerPAD LAYOUT
The output voltage of the converter is fed directly into the
VSENSE pin of the TPS54314. The TPS54314 is
internally compensated to provide stability of the output
under varying line and load conditions.
OPERATING FREQUENCY
In the application circuit, a 700 kHz operating frequency is
selected by leaving FSEL open and connecting a 71.5 kΩ
resistor between the RT pin and AGND. Different
operating frequencies may be selected by varying the
value of R3 using equation 1:
R+
500 kHz
Switching Frequency
100 kW
(1)
Alternately, preset operating frequencies of 350 kHz or
550 kHz my be selected by leaving RT open and
connecting the FSEL pin to AGND or VIN respectively.
The TPS54311−16 have two internal grounds (analog and
power). Inside the TPS54311−16, the analog ground ties
to all of the noise sensitive signals, while the power ground
ties to the noisier power signals. The PowerPAD must be
connected directly to AGND. Noise injected between the
two grounds can degrade the performance of the
TPS54311−16, particularly at higher output currents.
However, ground noise on an analog ground plane can
also cause problems with some of the control and bias
signals. For these reasons, separate analog and power
ground planes are recommended. These two planes
should tie together directly at the IC to reduce noise
between the two grounds. The only components that
should tie directly to the power ground plane are the input
capacitor, the output capacitor, the input voltage
decoupling capacitor, and the PGND pins of the
TPS54311−16. The layout of the TPS54314 evaluation
module is representative of a recommended layout for a
4-layer board. Documentation for the TPS54314
evaluation module can be found on the Texas Instruments
9
Obsolete Devices:
TPS54314-Q1 and TPS54315-Q1
TPS54311-Q1, TPS54312-Q1
TPS54313-Q1, TPS54314-Q1
TPS54315-Q1, TPS54316-Q1
www.ti.com
SGLS242G − OCTOBER 2004 − REVISED SEPTEMBER 2008
web site under the TPS54314 product folder and in the
application note, Texas Instruments literature number
SLVA111.
LAYOUT CONSIDERATIONS FOR THERMAL
PERFORMANCE
For operation at full rated load current, the analog ground
plane must provide adequate heat dissipating area. A
3 inch by 3 inch plane of 1 ounce copper is recommended,
though not mandatory, depending on ambient temperature
and airflow. Most applications have larger areas of internal
ground plane available, and the PowerPAD should be
6 PL ∅ 0.0130
4 PL ∅ 0.0180
Connect Pin 1 to Analog Ground Plane
in This Area for Optimum Performance
0.0227
0.0600
0.0400
0.2560
0.2454
0.0400
0.0600
Minimum Recommended Top
Side Analog Ground Area
connected to the largest area available. Additional areas
on the top or bottom layers also help dissipate heat, and
any area available should be used when 3 A or greater
operation is desired. Connection from the exposed area of
the PowerPAD to the analog ground plane layer should be
made using 0.013 inch diameter vias to avoid solder
wicking through the vias. Six vias should be in the
PowerPAD area with four additional vias located under the
device package. The size of the vias under the package,
but not in the exposed thermal pad area, can be increased
to 0.018. Additional vias beyond the ten recommended
that enhance thermal performance should be included in
areas not under the device package.
Minimum Recommended Thermal Vias: 6 × .013 dia.
Inside Powerpad Area 4 × .018 dia. Under Device as Shown.
Additional .018 dia. Vias May be Used if Top Side Analog
Ground Area is Extended.
ÓÓÓ
ÓÓÓ
ÓÓÓ
ÓÓÓ
ÓÓÓ
ÓÓÓ
ÓÓÓ
0.0150
0.06
0.1010
0.0256
0.1700
0.1340
0.0620
0.0400
Minimum Recommended Exposed
Copper Area For Powerpad. 5mm
Stencils may Require 10 Percent
Larger Area
Figure 11. Recommended Land Pattern for 20-Pin PWP PowerPAD
10
Obsolete Devices:
TPS54314-Q1 and TPS54315-Q1
TPS54311-Q1, TPS54312-Q1
TPS54313-Q1, TPS54314-Q1
TPS54315-Q1, TPS54316-Q1
www.ti.com
SGLS242G − OCTOBER 2004 − REVISED SEPTEMBER 2008
PERFORMANCE GRAPHS
OUTPUT VOLTAGE
vs
LOAD CURRENT
EFFICIENCY
vs
LOAD CURRENT
LOOP RESPONSE
60
1.9
100
180
Efficiency at 700 kHz
135
45
80
70
1.85
90
30
3.3 VI
1.8
5 VI
45
Gain
15
0
0
1.75
−45
−15
60
1.7
50
1
2
3
4
0
5
1
2
4
5
−30
100
Figure 12
LOAD TRANSIENT RESPONSE
Load Transient Response − mV
VO (AC)
10 mV/div
VI = 5 V
IO = 3 A
400 ns/div
10 k
100 k
−90
1M
Figure 14
Figure 13
OUTPUT RIPPLE VOLTAGE
1k
f − Frequency − Hz
IL − Load Current − A
Load Current − A
Amplitude − 10 mV/div
3
VO 50 mV/div
IO 2 A/div
START-UP WAVEFORMS
Start Up Waveforms − V
0
Phase − Degrees
3.3 VI
Phase
Gain − dB
5 VI
VO − Output Voltage − %
Efficiency − %
90
VI 2 V/div
VO 2 V/div
VPWRGD 5 V/div
VI = 5 V
Time − 100 µs/div
Time − 10 µs/div
Figure 15
Time − 2 ms/div
Figure 17
Figure 16
AMBIENT TEMPERATURE
vs
LOAD CURRENT
125
T A − Ambient Temperature − ° C
115
105
†
95
85
Safe Operating Area†
Safe operating area is applicable to the test
board conditions listed in the Dissipation Rating
Table section of this data sheet.
75
65
55
45
35
25
0
1
2
3
4
IL − Load Current − A
Figure 18
11
TPS54311-Q1, TPS54312-Q1
TPS54313-Q1, TPS54314-Q1
TPS54315-Q1, TPS54316-Q1
Obsolete Devices:
TPS54314-Q1 and TPS54315-Q1
www.ti.com
SGLS242G − OCTOBER 2004 − REVISED SEPTEMBER 2008
DETAILED DESCRIPTION
t
Under Voltage Lock Out (UVLO)
The TPS54311 through TPS54316 incorporate an under
voltage lockout circuit to keep the device disabled when
the input voltage (VIN) is insufficient. During power up,
internal circuits are held inactive until VIN exceeds the
nominal UVLO threshold voltage of 2.95 V. Once the
UVLO start threshold is reached, device start-up begins.
The device operates until VIN falls below the nominal
UVLO stop threshold of 2.8 V. Hysteresis in the UVLO
comparator, and a 2.5-µs rising and falling edge deglitch
circuit reduce the likelihood of shutting the device down
due to noise on VIN.
Slow-Start/Enable (SS/ENA)
The slow-start/enable pin provides two functions; first, the
pin acts as an enable (shutdown) control by keeping the
device turned off until the voltage exceeds the start
threshold voltage of approximately 1.2 V. When SS/ENA
exceeds the enable threshold, device start up begins. The
reference voltage fed to the error amplifier is linearly
ramped up from 0 V to 0.891 V in 3.35 ms. Similarly, the
converter output voltage reaches regulation in
approximately 3.35 ms. Voltage hysteresis and a 2.5-µs
falling edge deglitch circuit reduce the likelihood of
triggering the enable due to noise.
OUTPUT
VOLTAGE
SLOW START
TPS54311
0.9 V
3.3 ms
TPS54312
1.2 V
4.5 ms
TPS54313
1.5 V
5.6 ms
TPS54314
1.8 V
3.3 ms
TPS54315
2.5 V
4.7 ms
TPS54316
3.3 V
6.1 ms
DEVICE
td + C
(SS)
(2)
Second, as the output becomes active, a brief ramp-up at
the internal slow-start rate may be observed before the
externally set slow-start rate takes control and the output
rises at a rate proportional to the slow-start capacitor. The
slow-start time set by the capacitor is approximately:
12
+C
(SS)
0.7 V
5 mA
(3)
The actual slow-start is likely to be less than the above
approximation due to the brief ramp-up at the internal rate.
VBIAS Regulator (VBIAS)
The VBIAS regulator provides internal analog and digital
blocks with a stable supply voltage over variations in
junction temperature and input voltage. A high quality,
low-ESR, ceramic bypass capacitor is required on the
VBIAS pin. X7R or X5R grade dielectrics are
recommended because their values are more stable over
temperature. The bypass capacitor should be placed close
to the VBIAS pin and returned to AGND. External loading
on VBIAS is allowed, with the caution that internal circuits
require a minimum VBIAS of 2.7 V and external loads on
VBIAS with ac or digital switching noise may degrade
performance. The VBIAS pin may be useful as a reference
voltage for external circuits.
Voltage Reference
The voltage reference system produces a precise Vref
signal by scaling the output of a temperature stable
bandgap circuit. During manufacture, the bandgap and
scaling circuits are trimmed to produce 0.891 V at the
output of the error amplifier, with the amplifier connected
as a voltage follower. The trim procedure adds to the high
precision regulation of the TPS54311 through TPS54316,
since it cancels offset errors in the scale and error amplifier
circuits.
Oscillator and PWM Ramp
The second function of the SS/ENA pin provides an
external means of extending the slow-start time with a
low-value capacitor connected between SS/ENA and
AGND. Adding a capacitor to the SS/ENA pin has two
effects on start-up. First, a delay occurs between release
of the SS/ENA pin and start up of the output. The delay is
proportional to the slow-start capacitor value and lasts until
the SS/ENA pin reaches the enable threshold. The
start-up delay is approximately:
1.2 V
5 mA
(SS)
The oscillator frequency can be set to internally fixed
values of 350 kHz or 550 kHz using the FSEL pin as a static
digital input. If a different frequency of operation is required
for the application, the oscillator frequency can be
externally adjusted from 280 kHz to 700 kHz by connecting
a resistor to the RT pin to ground and floating the FSEL pin.
The switching frequency is approximated by the following
equation, where R is the resistance from RT to AGND:
SWITCHING FREQUENCY + 100 kW
R
500 kHz
(4)
External synchronization of the PWM ramp is possible
over the frequency range of 330 kHz to 700 kHz by driving
a synchronization signal into FSEL and connecting a
resistor from RT to AGND. Choose an RT resistor that sets
the free-running frequency to 80% of the synchronization
signal. Table 1 summarizes the frequency selection
configurations.
Obsolete Devices:
TPS54314-Q1 and TPS54315-Q1
www.ti.com
TPS54311-Q1, TPS54312-Q1
TPS54313-Q1, TPS54314-Q1
TPS54315-Q1, TPS54316-Q1
SGLS242G − OCTOBER 2004 − REVISED SEPTEMBER 2008
Table 1. Summary of the Frequency Selection
Configurations
SWITCHING
FREQUENCY
FSEL PIN
RT PIN
350 kHz, internally
set
Float or AGND
Float
550 kHz, internally
set
≥ 2.5 V
Float
Externally set 280
kHz to 700 kHz
Float
R = 68 k to 180 k
Externally
synchronized
frequency(1)
Synchronization
signal
R = RT value for 80% of
external synchronization
frequency
(1)
To ensure proper operation when RC filter is used between external
clock and FSEL pin, the recommended values are R ≤ 1kΩ and
C ≤ 68 pF.
Error Amplifier
The high performance, wide bandwidth, voltage error
amplifier is gain limited to provide internal compensation
of the control loop. The user is given limited flexibility in
choosing output L and C filter components. Inductance
values of 4.7 µH to 10 µH are typical and available from
several vendors. The resulting designs exhibit good noise
and ripple characteristics, along with exceptional transient
response. Transient recovery times are typically in the
range of 10 to 20 µs.
PWM Control
Signals from the error amplifier output, oscillator, and
current limit circuit are processed by the PWM control
logic. Referring to the internal block diagram, the control
logic includes the PWM comparator, OR gate, PWM latch,
and portions of the adaptive dead-time and control logic
block. During steady-state operation below the current
limit threshold, the PWM comparator output and oscillator
pulse train alternately reset and set the PWM latch. Once
the PWM latch is set, the low-side FET remains on for a
minimum duration set by the oscillator pulse duration.
During this period, the PWM ramp discharges rapidly to its
valley voltage. When the ramp begins to charge back up,
the low-side FET turns off and high-side FET turns on. As
the PWM ramp voltage exceeds the error amplifier output
voltage, the PWM comparator resets the latch, thus
turning off the high-side FET and turning on the low-side
FET. The low-side FET remains on until the next oscillator
pulse discharges the PWM ramp.
During transient conditions, the error amplifier output
could be below the PWM ramp valley voltage or above the
PWM peak voltage. If the error amplifier is high, the PWM
latch is never reset and the high-side FET remains on until
the oscillator pulse signals the control logic to turn the
high-side FET off and the low-side FET on. The device
operates at its maximum duty cycle until the output voltage
rises to the regulation set-point, setting VSENSE to
approximately the same voltage as Vref. If the error
amplifier output is low, the PWM latch is continually reset
and the high-side FET does not turn on. The low-side FET
remains on until the VSENSE voltage decreases to a
range that allows the PWM comparator to change states.
The TPS54311 through TPS54316 are capable of sinking
current continuously until the output reaches the
regulation set-point.
If the current limit comparator trips for longer than 100 ns,
the PWM latch resets before the PWM ramp exceeds the
error amplifier output. The high-side FET turns off and
low-side FET turns on to decrease the energy in the output
inductor and consequently the output current. This
process is repeated each cycle in which the current limit
comparator is tripped.
Dead-Time Control and MOSFET Drivers
Adaptive dead-time control prevents shoot-through
current from flowing in both N-channel power MOSFETs
during the switching transitions by actively controlling the
turn-on times of the MOSFET drivers. The high-side driver
does not turn on until the gate drive voltage to the low-side
FET is below 2 V. The low-side driver does not turn on until
the voltage at the gate of the high-side MOSFETs is below
2 V. The high-side and low-side drivers are designed with
300-mA source and sink capability to quickly drive the
power MOSFETs gates. The low-side driver is supplied
from VIN, while the high-side drive is supplied from the
BOOT pin. A bootstrap circuit uses an external BOOT
capacitor and an internal 2.5-Ω bootstrap switch
connected between the VIN and BOOT pins. The
integrated bootstrap switch improves drive efficiency and
reduces external component count.
Overcurrent Protection
The cycle by cycle current limiting is achieved by sensing
the current flowing through the high-side MOSFET and
differential amplifier and comparing it to the preset
overcurrent threshold. The high-side MOSFET is turned
off within 200 ns of reaching the current limit threshold. A
100-ns leading edge blanking circuit prevents false
tripping of the current limit. Current limit detection occurs
only when current flows from VIN to PH when sourcing
current to the output filter. Load protection during current
sink operation is provided by thermal shutdown.
Thermal Shutdown
The device uses the thermal shutdown to turn off the power
MOSFETs and disable the controller if the junction
temperature exceeds 150°C. The device is released from
shutdown when the junction temperature decreases to
10°C below the thermal shutdown trip point and starts up
under control of the slow-start circuit. Thermal shutdown
provides protection when an overload condition is
sustained for several milliseconds. With a persistent fault
13
TPS54311-Q1, TPS54312-Q1
TPS54313-Q1, TPS54314-Q1
TPS54315-Q1, TPS54316-Q1
Obsolete Devices:
TPS54314-Q1 and TPS54315-Q1
www.ti.com
SGLS242G − OCTOBER 2004 − REVISED SEPTEMBER 2008
condition, the device cycles continuously; starting up by
control of the soft-start circuit, heating up due to the fault,
and then shutting down upon reaching the thermal
shutdown point.
Power Good (PWRGD)
The power good circuit monitors for under voltage
conditions on VSENSE. If the voltage on VSENSE is 10%
below the reference voltage, the open-drain PWRGD
14
output is pulled low. PWRGD is also pulled low if VIN is
less than the UVLO threshold, or SS/ENA is low, or
thermal shutdown is asserted. When VIN = UVLO
threshold, SS/ENA = enable threshold, and VSENSE >
90% of Vref, the open drain output of the PWRGD pin is
high. A hysteresis voltage equal to 3% of Vref and a 35-µs
falling edge deglitch circuit prevent tripping of the power
good comparator due to high frequency noise.
PACKAGE OPTION ADDENDUM
www.ti.com
17-Mar-2017
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TPS54312QPWPRQ1
ACTIVE
HTSSOP
PWP
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
P54312Q1
TPS54316QPWPRQ1
ACTIVE
HTSSOP
PWP
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
P54316Q1
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
17-Mar-2017
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TPS54312-Q1, TPS54316-Q1 :
• Catalog: TPS54312, TPS54316
• Enhanced Product: TPS54312-EP, TPS54316-EP
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
• Enhanced Product - Supports Defense, Aerospace and Medical Applications
Addendum-Page 2
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