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TPS543C20
SLUSCD4B – MARCH 2017 – REVISED MAY 2018
TPS543C20 4-VIN to 14-VIN, 40-A Stackable, Synchronous Step-Down SWIFT™ Converter
With Adaptive Internal Compensation
1 Features
2 Applications
•
•
1
•
•
•
•
•
•
•
•
•
•
•
•
•
Internally-Compensated Advanced Current Mode
Control 40-A POL
Input Voltage Range: 4 V to 14 V
Output Voltage Range: 0.6 V to 5.5 V
Integrated 3/0.9-mΩ Stacked NexFET™ Power
Stage With Lossless Low-Side Current Sensing
Fixed Frequency - Synchronization to an External
Clock and/or Sync Out
Pin Strapping Programmable Switching Frequency
– 300 kHz to 2 MHz for Standalone
– 300 kHz to 1 MHz for Stackable
Stack 2× for up to 80 A With Current Share,
Voltage Share, and CLK Sync
Pin Strapping Programmable Reference from 0.6
V to 1.1 V With 0.5% Accuracy
Differential Remote Sensing
Safe Start-Up into Prebiased Output
High-Accuracy Hiccup Current Limit
Asynchronous Pulse Injection (API) and Body
Braking
40-pin, 5-mm × 7-mm LQFN Package with 0.5mm Pitch and Single Thermal Pad
Create a Custom Design Using the TPS543C20
With the WEBENCH® Power Designer
•
•
•
Wireless and Wired Communications
Infrastructure Equipment
Enterprise Servers, Switches, and Routers
Enterprise Storage, SSD
ASIC, SoC, FPGA, DSP Core, and I/O Rails
3 Description
The TPS543C20 employs an internally compensated
emulated peak-current-mode control, with a clock
synchronizable, fixed-frequency modulator for EMIsensitive POL. The internal integrator and directly
amplifying ramp tracking loop eliminate the need for
external compensation over a wide range of
frequencies thereby making the system design
flexible, dense, and simple. Optional API and body
braking help improve transient performance by
significantly reducing undershoot and overshoot,
respectively. Integrated NexFET™ MOSFETs with
low-loss switching facilitate high efficiency and deliver
up to 40 A in a 5-mm × 7-mm PowerStack™ package
with a layout friendly thermal pad. Two TPS543C20
devices can be stacked together to provide up to 80A point-of-load.
Device Information(1)
PART NUMBER
TPS543C20
PACKAGE
BODY SIZE (NOM)
LQFN-CLIP (40)
5.00 mm × 7.00 mm
1. For all available packages, see the orderable
addendum at the end of the data sheet.
Simplified Schematic
VIN
PVIN
EN
ILIM
VDD
VOUT
RAMP
RSN
RT
BOOT
SW
TPS543C20
VSEL
BP
SYNC
PGD
VSHARE
AGND
ISHARE
SS
MODE
RSP
+
LOAD
t
PGND
GND
Copyright © 2017, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS543C20
SLUSCD4B – MARCH 2017 – REVISED MAY 2018
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
7.1
7.2
7.3
7.4
7.5
7.6
8
Absolute Maximum Ratings ...................................... 5
ESD Ratings ............................................................ 5
Recommended Operating Conditions....................... 6
Thermal Information ................................................. 6
Electrical Characteristics........................................... 7
Typical Characteristics ............................................ 11
Detailed Description ............................................ 14
8.1
8.2
8.3
8.4
9
1
1
1
2
3
3
5
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
14
14
15
15
9.1 Application Information............................................ 24
9.2 Typical Application: TPS543C20 Stand-alone
Device ...................................................................... 24
9.3 System Example ..................................................... 30
10 Power Supply Recommendations ..................... 32
11 Layout................................................................... 33
11.1 Layout Guidelines ................................................. 33
11.2 Layout Example .................................................... 34
11.3 Package Size, Efficiency and Thermal
Performance............................................................. 35
12 Device and Documentation Support ................. 37
12.1
12.2
12.3
12.4
12.5
12.6
Device Support......................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
37
37
37
37
37
38
13 Mechanical, Packaging, and Orderable
Information ........................................................... 38
Application and Implementation ........................ 24
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (September 2017) to Revision B
Page
•
Changed "16 Vin" and "16 V" input voltage to "14 Vin" and "14 V" ...................................................................................... 1
•
Changed Absolute Maximum Ratings VIN row MAX from "20" to "16"; add VIN to SW row................................................. 5
•
Added Absolute Maximum Ratings new footnote 1; delete "VIN < 2-ms transient" row ........................................................ 5
•
Changed Absolute Maximum Ratings VDD row MAX from "22" to "16" ............................................................................... 5
•
Changed Absolute Maximum Ratings "SW" rows to "SW to PGND" and "< 10 ns" MAX from "23" to "20" ......................... 5
•
Changed Recommended Operating Conditions VIN maximum from "16" to "14" V; added VIN to SW specs ..................... 6
•
Changed Recommended Operating Conditions BOOT maximum from "19.5" to "23.5" V.................................................... 6
•
Added in Recommended Operating Conditions " to PGND" after SW row; changed DC maximum from "16" to "18" V
and < 10 ns from "21" to "18" V; added new note 1............................................................................................................... 6
•
Changed Electrical Characteristics INPUT SUPPLY and CURRENT Power stage voltage MAX value irom "16" to
"14" and VDD supply voltage MAX value from "22" to "16" V ............................................................................................... 7
•
Added statement re: mandatory requirement for VIN to GND capacitor ............................................................................. 15
•
Added sentence after " is valid for VDD ≥ 5 V." ................................................................................................................... 21
•
Changed Table 6 Input voltage MAX from "16" to "14 V"; add new footnote 1 ................................................................... 25
•
Changed Table 6 Line regulation TEST CONDITION from "5 V ≤ VIN ≤ 16 V" to "5 V ≤ VIN ≤ 14 V" .................................. 25
•
Added "Place a 10-nF to 100-nF capacitor close to IC from Pin 25 VIN to Pin 27 GND." to Layout Guidelines ............... 33
•
Changed Condition for Figure 43 from "VOUT = 1 V" to "VOUT = 5 V" and Figure 44 from "VOUT = 5 V" to "VOUT = 1 V"...... 35
Changes from Original (March 2017) to Revision A
Page
•
Added links for WEBENCH ................................................................................................................................................... 1
•
Changed from "DART" to "ACM" in the Detailed Description and Functional Block Diagram ............................................ 14
•
Replace figures 42 through 49 with new "Example Layout" ................................................................................................ 34
2
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SLUSCD4B – MARCH 2017 – REVISED MAY 2018
5 Device Comparison Table
DEVICE
OUTPUT CURRENT
TPS543B20
25 A
TPS543C20
40 A
6 Pin Configuration and Functions
RVF Package
40-Pin LQFN
Top View
20
19
18
17
SS
PGND
16
RT
PGND
15
MODE
PGND
14
RAMP
PGND
13
21 PVIN
22 PVIN
PGND
40
23 PVIN
VSEL
39
24 PVIN
PGND
38
25 PVIN
26 VDD
SYNC
37
27 GND
28 BP
PGND
36
29 AGND
30 ILIM
PGD
35
31 ISHARE
PGND
34
32 VSHARE
33
EN
Thermal Tab
SW 12
SW 11
SW 10
9
6
SW
NC
5
8
NC
4
SW
NC
3
BOOT 7
NC
RSN 2
RSP 1
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SLUSCD4B – MARCH 2017 – REVISED MAY 2018
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Pin Functions
PIN
NO.
NAME
I/O/P (1)
DESCRIPTION
1
RSP
I
The positive input of the remote sense amplifier. Connect RSP pin to the output voltage at the
load. For multi-phase configuration, the remote sense amplifier is not needed for slave devices.
2
RSN
I
The negative input of the remote sense amplifier. Connect RSN pin to the ground at load side.
For multi-phase configuration, the remote sense amplifier is not needed for slave devices.
3–6
7
NC
BOOT
Not connected
I
Bootstrap pin for the internal flying high-side driver. Connect a typical 100-nF capacitor from this
pin to SW. To reduce the voltage spike at SW, a BOOT resistor with a value between 1 Ω to 10
Ω may be placed in series with the BOOT capacitor to slow down turnon of the high-side FET.
8 – 12
SW
B
Output of converted power. Connect this pin to the output Inductor.
13 – 20
PGND
G
These ground pins are connected to the return of the internal low-side MOSFET
21 – 25
PVIN
I
Input power to the power stage. Low impedance bypassing of these pins to PGND is critical. A
10-nF to 100-nF capacitor from PVIN to PGND close to IC is required.
26
VDD
I
Controller power supply input
27
GND
G
Ground return for the controller. This pin should be directly connected to the thermal pad on the
PCB board. A 10-nF to 100-nF capacitor from PVIN to GND close to IC is required.
28
BP
O
Output of the 5 V on board regulator. This regulator powers the driver stage of the controller
and must be bypassed with a minimum of 2.2 µF to the thermal pad (power stage ground, that
is, GND). Low impedance bypassing of this pin to PGND is critical.
29
AGND
G
GND return for internal analog circuits.
30
ILIM
O
Current protection pin; connect a resistor from this pin to AGND sets current limit level.
31
ISHARE
I
Current sharing signal for multi-phase operation. Float this pin for single phase
32
VSHARE
B
Voltage sharing signal for multi-phase operation. Float this pin for single phase.
33
EN
I
The enable pin turns on the switcher.
34
PGD
O
Open-drain power-good status signal which provides start-up delay after the FB voltage falls
within the specified limits. After the FB voltage moves outside the specified limits, PGOOD goes
low.
35
SYNC
B
For frequency synchronization. This pin can be configured as sync in or sync out by MODE pin
and RT pin for master and slave devices.
36
VSEL
I
Connect a resistor from this pin to AGND to select internal reference voltage.
37
SS
O
Connect a resistor from this pin to AGND to select soft-start time.
38
RT
O
Frequency setting pin. Connect a resistor from this pin to AGND to program the switching
frequency. This pin also selects sync point for devices in stackable applications
39
MODE
B
Enable or disable API or body brake function, choose API threshold, also selects the operation
mode in stackable applications
40
RAMP
B
Ramp level selection, with a resistor to AGND to adjust internal loop.
–
Thermal Tab
–
Package thermal tab, internally connected to PGND. The thermal tab must have adequate
solder coverage for proper operation.
(1)
4
I = Input, O = Output, B = Bidirectional, P = Supply, G = Ground
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SLUSCD4B – MARCH 2017 – REVISED MAY 2018
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1) (2)
VIN
MIN
MAX
–0.3
16
VIN to SW (3)
20
VDD
–0.3
16
BOOT
–0.3
34.5
DC
–0.3
6.5
< 10 ns
–0.3
7
VSEL, SS, MODE, RT, SYNC, EN, ISHARE, ILIM
–0.3
7
RSP
–0.3
3.6
RSN
–0.3
0.3
PGND, GND
–0.3
0.3
–0.3
20
BOOT to SW
Input voltage (1)
DC
SW to PGND (3)
Output voltage
UNIT
< 10 ns
V
–5
20
BP, RAMP
–0.3
7
PGD
–0.3
7
VSHARE
V
–0.3
3.6
Junction temperature, TJ
–55
150
°C
Storage temperature, Tstg
–55
150
°C
(1)
(2)
(3)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to the network ground terminal unless otherwise noted.
VIN to SW and SW to PGND must not exceed 20 V.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
(1)
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±2500
±1500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 500-V HBM is possible with the necessary precautions.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 250-V CDM is possible with the necessary precautions.
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7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
4
14
–0.1
18
VIN
DC
VIN to SW (3)
< 10 ns
UNIT
18
VDD
BOOT
4
16
–0.1
23.5
DC
–0.1
5.5
< 10 ns
–0.1
6
VSEL, SS, MODE, RT, SYNC, EN, ISHARE,
ILIM
–0.1
5.5
RSP
–0.1
1.7
RSN
–0.1
0.1
–0.1
0.1
–0.1
18
–5
18
BP, RAMP
–0.3
7
PGD
–0.3
7
VSHARE
–0.3
3.6
Junction temperature, TJ
–40
125
°C
Storage temperature, Tstg
–55
125
°C
BOOT to SW
Input voltage (2)
PGND, GND
DC
SW to PGND
Output
voltage (2)
(1)
(2)
(3)
< 10 ns
V
V
Stresses beyond those listed under may cause permanent damage to the device.
All voltage values are with respect to the network ground terminal unless otherwise noted.
See Layout Guidelines for VIN capacitor placement requirement to reduce MOSFET voltage stress.
7.4 Thermal Information
TPS543C20
THERMAL METRIC (1)
RVF (LQFN)
UNIT
40 PINS
RθJA
Junction-to-ambient thermal resistance
28.9
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
18.9
°C/W
RθJB
Junction-to-board thermal resistance
4.1
°C/W
ψJT
Junction-to-top characterization parameter
1.3
°C/W
ψJB
Junction-to-board characterization parameter
4.1
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
1
°C/W
(1)
6
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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SLUSCD4B – MARCH 2017 – REVISED MAY 2018
7.5 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
MOSFET RDS(ON)
RDS(on)HS
HS FET
VBST – VSW = 5 V, ID = 20 A, Tj = 25°C
3.0
mΩ
RDS(on)LS
LS FET
VDD = 5 V, ID = 20 A, Tj = 25°C
0.9
mΩ
tDEAD(LtoH)
Power stage driver dead-time
from Low-side off to High-side
on (1)
VDD ≥ 12 V, TJ = 25°C
12
ns
tDEAD(HtoL)
Power stage driver dead-time
from High-side off to Low-side
on (1)
VDDN ≥ 12 V, TJ = 25°C
15
ns
INPUT SUPPLY and CURRENT
VVIN
Power stage voltage
VVDD
VDD supply voltage
IVDD
VDD bias current
TA = 25°C, no load, power conversion enabled (no
switching)
IVDDSTBY
VDD standby current
TA = 25°C, no load, power conversion disabled
4
14
4
16
4.3
mA
4.3
mA
UNDERVOLTAGE LOCKOUT
VVDD_UVLO
3.8
V
VVDD_UVLO_HYS VDD UVLO hysteresis
VDD UVLO rising threshold
0.2
v
VVIN_UVLO
VIN UVLO rising threshold
3.2
V
VVIN_UVLO_HYS
VIN UVLO hysteresis
0.2
VEN_ON_TH
EN on threshold
1.45
1.6
1.75
V
VHYS
EN hysteresis
270
300
330
mV
IEN_LKG
EN input leakage current
–1
0
1
µA
v
INTERNAL REFERENCE VOLTAGE
VINTREF
Internal REF voltage
RVSEL = OPEN
1000
mV
VINTREFTOL
Internal REF voltage tolerance
TJ = -40°C to 125°C
–0.5%
+0.5%
VINTREF_VSEL
Internal REF voltage range
Programable by VSEL (pin 36)
0.6
1.1
V
VRSP= 600 mV
–1
1
µA
OUTPUT VOLTAGE
IRSP
RSP input current
DIFFERENTIAL REMOTE SENSE AMPLIFIER
fUGBW
Unity gain bandwidth (1)
A0
Open loop gain
SR
SLew rate (1)
VICM
Input common mode range (1)
VOFFSET
(1)
5
(1)
Input offset voltage (1)
8.5
MHz
±10
V/µs
75
VRSN-VGND = 0 mV
VRSN-VGND = ±100 mV
dB
–0.2
1.7
–1
1
–1.9
1.9
V
mV
Specified by design. Not production tested.
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Electrical Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SWITCHING FREQUENCY
VIN = 12 V, VVO= 1 V, RT = 66.5 kΩ
300
VIN = 12 V, VVO = 1 V, RT = 48.7 kΩ
400
VIN
VO switching frequency maximum V
IN
frequency for multi-phase is
V
IN
1MHz
VIN
FSW
tON(min)
tOFF(min)
= 12 V, VVO = 1 V, RT = 39.2 kΩ
500
= 12 V, VVO= 1 V, RT = 28.0 kΩ
700
= 12 V, VVO= 1 V, RT = 22.6 kΩ
850
= 12 V, VVO = 1 V, RT = 19.1 kΩ
1000
VIN = 12 V, VVO = 1 V, RT = 15.4 kΩ
1200
VIN = 12 V, VVO = 1 V, RT = 8.06 kΩ
2000
kHz
Minimum on-time (1)
DRVH rising to falling
30
ns
(1)
DRVH falling to rising
250
ns
VBP-VBST, TA= 25°C, IF= 5 mA
0.1
RVSEL= 0 kΩ
0.6
Minimum off-time
INTERNAL BOOTSTRAP SWITCH
VF
Forward voltage
0.2
V
VSEL
VSEL
Internal reference voltage
RVSEL= 8.66 kΩ
0.7
RVSEL= 15.4 kΩ
0.75
RVSEL= 23.7 kΩ
0.8
RVSEL= 34.8 kΩ
0.85
RVSEL= 51.1 kΩ
0.9
RVSEL= 78.7 kΩ
0.95
RVSEL= OPEN
V
1
RVSEL= 121 kΩ
1.05
RVSEL= 187 kΩ
1.1
SOFT START
RSS = 0 kΩ
tSS
Soft-start time
0.5
RSS = 8.66 kΩ
1
RSS = 15.4 kΩ
2
RSS = Open
4
VO rising from 0 V RSS = 23.7 kΩ
to 95% of final set
RSS = 34.8 kΩ
point
RSS = 51.1 kΩ
12
RSS = 78.7 kΩ
16
RSS = 121 kΩ
24
RSS = 187 kΩ
32
5
8
ms
POWER ON DELAY
tPODLY
8
Power-on delay time
Delay from enable to switching
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512
µs
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Electrical Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
108
112
116
UNIT
PGOOD COMPARATOR
OV warning threshold on RSP
pin, PGOOD fault threshold on
rising
VREF = 600 mV
UV warning threshold on RSP
pin, PGOOD fault threshold on
falling
VREF = 600 mV
VPGD(rise)
PGOOD threshold on rising and
UV warning threshold deassertion threshold at RSP pin
VREF = 600 mV
95
%VREF
VPGD(fall)
PGOOD threshold on falling and
OV warning threshold deassertion threshold at RSP pin
VREF = 600 mV
105
%VREF
RPGD
PGOOD pulldown resistance
IPGOOD = 5 mA, VRSP = 0 V
VPG(thresh)
tPGDLY
PGOOD delay time
VPGD(OL)
PGOOD output low level voltage
at no supply voltage
IPGLK
PGOOD leakage current
%VREF
84
30
Delay for PGOOD going in
88
45
92
60
1.024
Delay for PGOOD coming out
Ω
ms
2
µs
VDD=0, IPGOOD = 80 µA
0.8
V
VPGOOD = 5 V
15
µA
CURRENT SHARE ACCURACY
ISHARE(acc)
Output current sharing accuracy
IOUT ≥ 20 A/phase
among stackable devices, defined
as the ratio of the current
IOUT ≤ 20 A/phase
difference between devices to
total current(sensing error only) (1)
–15%
15%
±3
A
CURRENT DETECTION
VILIM
VTRIP voltage range
Rdson sensing
IOCP
Low-side FET current protection
threshold and tolerance
RILIM= 33.2 kΩ
IOCP
Low-Side FET Current protection
threshold and tolerance
RILIM= 23.7 kΩ
IOCP_N
Negative current limit threshold
Valley-point current sense
ICLMP_LO
Clamp current at VTRIP clamp at
lowest
25°C, VTRIP = 0.1 V
0.1
1.2
35
OC tolerance
A
±10%
25
OC tolerance
A
±15%
–23
5.5
6.5
A
7.5
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A
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Electrical Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
HIGH-SIDE SHORT-CIRCUIT PROTECTION
High-side short circuit protection
fault threshold (1)
IHSOC
60
A
OV / UV PROTECTION
VOVP
OVP threshold voltage
OVP detect voltage
tOVPDLY
OVP response time (1)
OVP response time with 100-mV overdrive
VUVP
UVP threshold voltage
UVP detect voltage
tUVPDLY
UVP delay (1)
UVP delay
tHICDLY
Hiccup delay time
Regular tSS setting
113
117
121 %VREF
79
83
87 %VREF
1
1.5
7 × tSS
µs
µs
ms
BP LDO REGULATOR
BP
LDO output voltage
VIN = 12 V, ILOAD = 0 to 10 mA
4.5
5
Wakeup
3.32
Shutdown
3.11
VBPUVLO
BP UVLO threshold voltage
VLDOBP
LDO low dropout voltage
VIN= 4.5 V, ILOAD= 30 mA, TA = 25°C
ILDOMAX
LDO overcurrent limit
VIN= 12 V, TA = 25°C
5.5
V
V
365
100
mV
mA
SYNCHRONIZATION
VIH(SYNC)
High-level input voltage
VIL(SYNC)
Low-level input voltage
tPSW(SYNC)
Sync input minimum pulse width
FSYNC
2
0.8
100
Synchronization frequency
300
2000
Dual-phase
300
1000
tSYNC to SW
Sync to SW delay tolerance,
percentage from phase-tophase (1)
FSYNC = 300 kHz to 1 MHz,
tLose_SYNC_delay
Delay when lose sync clock (1)
FSYNC = 300 kHz
V
ns
kHz
10%
5
µs
THERMAL SHUTDOWN
TSDN
10
Built-in thermal shutdown
threshold (1)
Shutdown temperature
Hysteresis
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155
165
30
°C
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7.6 Typical Characteristics
VIN = VDD = 12 V, TA = 25°C, RRT = 40.2 kΩ, TA= 25°C (unless otherwise specified)
100%
10
95%
9
3.3 VOUT
2.5 VOUT
1.5 VOUT
1 VOUT
0.6 VOUT
8
Power Loss (W)
Efficiency (%)
90%
85%
80%
75%
7
6
5
4
3
70%
2
65%
3.3 VOUT
2.5 VOUT
1.5 VOUT
1 VOUT
0.6 VOUT
1
0
60%
0
5
10
15
20
25
Output Current (A)
VIN = 5 V
30
35
0
40
500 kHz
25°C
15
20
25
Output Current (A)
30
35
40
D013
500 kHz
25°C
Figure 2. Power Loss vs Output Current
100%
9
95%
8
90%
7
Power Loss (W)
Efficiency (%)
10
VIN = 5 V
Figure 1. Efficiency vs Output Current
85%
80%
75%
70%
5 VOUT
3.3 VOUT
2.5 VOUT
1.5 VOUT
1 VOUT
0.6 VOUT
6
5
4
3
2
65%
5 VOUT
3.3 VOUT
2.5 VOUT
1.5 VOUT
1 VOUT
0.6 VOUT
1
60%
0
0
5
10
VIN = 12 V
15
20
25
Output Current (A)
30
35
40
0
5
10
D016
500 kHz
25°C
VIN = 12 V
Figure 3. Efficiency vs Output Current
15
20
25
Output Current (A)
30
35
40
D017
500 kHz
25°C
Figure 4. Power Loss vs Output Current
9
100%
14 VIN
12 VIN
9 VIN
5 VIN
4 VIN
8
7
Power Loss (W)
90%
Efficiency (%)
5
D012
80%
14 VIN
12 VIN
9 VIN
5 VIN
4 VIN
70%
6
5
4
3
2
1
0
60%
0
5
VOUT = 1 V
10
15
20
25
Output Current (A)
30
35
40
0
5
D020
1 MHz
25°C
Figure 5. Efficiency vs Output Current
VOUT = 1 V
10
15
20
25
Output Current (A)
30
35
40
1 MHz
D021
25°C
Figure 6. Power Loss vs Output Current
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Typical Characteristics (continued)
VIN = VDD = 12 V, TA = 25°C, RRT = 40.2 kΩ, TA= 25°C (unless otherwise specified)
800
6
0.6 VOUT
1 VOUT
1.5 VOUT
2.5 VOUT
3.3 VOUT
5 VOUT
Frequency (KHz)
Output Voltage (V)
0.6 VOUT
1 VOUT
1.5 VOUT
2.5 VOUT
3.3 VOUT
5 VOUT
700
5
4
3
2
600
500
400
300
1
200
0
0
5
10
VIN = 12 V
15
20
25
Output Current (A)
30
35
0
40
5
10
D007
500 kHz
25°C
Figure 7. Output Voltage vs Output Current
VIN = 12 V
15
20
25
Output Current (A)
30
500 kHz
35
40
D010
25°C
Figure 8. Switching Frequency vs Output Current
Output Voltage (V)
1.05
14 VIN
12 VIN
9 VIN
5 VIN
4 VIN
1
0.95
0
5
VOUT = 1 V
10
15
20
25
Output Current (A)
30
35
40
D019
1 MHz
25°C
Figure 9. Output Voltage vs Output Current
Figure 11. Output Voltage Start-Up and Shutdown
12
Figure 10. Start-Up From EN
Figure 12. Output Voltage Ripple at Steady State
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Typical Characteristics (continued)
VIN = VDD = 12 V, TA = 25°C, RRT = 40.2 kΩ, TA= 25°C (unless otherwise specified)
15 A to 25 A to 15 A, 10-A Step at 40 A/µs
Figure 13. Output Voltage Transient Response
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8 Detailed Description
8.1 Overview
The TPS543C20 device is 40-A, high-performance, synchronous buck converter with two integrated N-channel
NexFET™ power MOSFETs. These devices implement the fixed frequency non-compensation mode control.
Safe pre-bias capability eliminates concerns about damaging sensitive loads. Two TPS543C20 devices can be
paralleled together to provide up to 80-A load. Current sensing for over-current protection and current sharing
between devices is done by sampling a small portion of the power stage current providing accurate information
independent on the device temperature.
Advanced Current Mode (ACM) is an emulated peak current control topology. It supports stable static and
transient operation without complex external compensation design. This control architecture includes an internal
ramp generation network that emulates inductor current information, enabling the use of low ESR output
capacitors such as multi-layered ceramic capacitors (MLCC). The internal ramp also creates a high signal to
noise ratio for good noise immunity. The TPS543C20 has 10 ramp options (see Ramp Selections for detail) to
optimize internal loop for various inductor and output capacitor combinations with only a simple resistor to GND.
The TPS543C20 is easy to use and allows low external component count with fast load transient response.
Fixed-frequency modulation also provides ease-of-filter design to overcome EMI noise.
8.2 Functional Block Diagram
VDD
BP
PVIN
BOOT
BP
Linear Regulators
BP3
MODE
API
SW
SYNC
Phase Managment
S Q PWM
Oscillator
RT
R
Driver
Control:
Anti-CrossConduction ,
Prebias
BP
Stacked NexFET
Power Stage
PGND
ACM Controller
Overcurrent
Detection ,
Current sensing
OC Event
Average Iout
ISHARE
Phase
Balance
AGND
Fault
EN
Fault
Control
OC Threshold
Reference
VSHARE
RSP
RSN
Start and Reference
SS
GND
VSEL
PGD
ILIM
RAMP
REMOTE SENSE AMP
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8.3 Feature Description
The TPS543C20 device is a high-performance, integrated FET converter supporting current rating up to 40-A
thermally. It integrates two N-channel NexFET™ power MOSFETs, enabling high power density and small PCB
layout area. The drain-to-source breakdown voltage for these FETs is 20 V DC and transient. Avalanche
breakdown occurs if the absolute maximum voltage rating exceeds 20 V. In order to limit the switch node ringing
of the device, TI recommends adding a R-C snubber from the SW node to the PGND pins. Also a 10~100nF
capacitor from VIN (Pin 25) to GND (Pin2 7) is mandatory to reduce high side FET stress. Refer to Layout
Guidelines for the detailed recommendations.
The typical on-resistance (RDS(on)) for the high-side MOSFET is 3 mΩ and typical on-resistance for the low-side
MOSFET is 0.9 mΩ with a nominal gate voltage (VGS) of 5 V.
8.4 Device Functional Modes
8.4.1 Soft-Start Operation
In the TPS543C20 device, the soft-start time controls the inrush current required to charge the output capacitor
bank during start-up. The device offers 10 selectable soft-start options ranging from 0.5 ms to 32 ms. When the
device is enabled the reference voltage ramps from 0 V to the final level defined by VSEL pin strap configuration,
in a given soft-start time, which can be selected by SS pin. See Table 1 for details.
Table 1. SS Pin Configuration
(1)
SS TIME (ms)
RESISTOR VALUE (kΩ) (1)
0.5
0
1
8.66
2
15.4
5
23.7
4
OPEN
8
34.8
12
51.1
16
78.7
24
121
32
187
The E48 series resistors with no more than 1% tolerance are recommended.
8.4.2 Input and VDD Undervoltage Lockout (UVLO) Protection
The TPS543C20 provides fixed VIN and VDD undervoltage lockout threshold and hysteresis. The typical VIN
turnon threshold is 3.2 V and hysteresis is 0.2 V. The typical VDD turnon threshold is 3.8 V and hysteresis is
0.2 V. No specific power-up sequence is required.
8.4.3 Power Good and Enable
The TPS543C20 has power-good output that indicates logic high when output voltage is within the target. The
power-good function is activated after soft-start has finished. When the soft-start ramp reaches 90% of setpoint,
PGOOD detection function will be enabled. If the output voltage becomes within ±8% of the target value, internal
comparators detect power-good state and the power good signal becomes high after a delay. If the output
voltage goes outside of ±12% of the target value, the power good signal becomes low after an internal delay.
The power-good output is an open-drain output and must be pulled up externally.
This part has internal pull up for EN. EN is internally pulled up to BP when EN pin is floating. EN can be pulled
low through external grounding. When EN pin voltage is below its threshold, TPS543C20 enters into shutdown
operation, and the minimum time for toggle EN to reset is 5 µs.
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8.4.4 Voltage Reference
VSEL pin strap is used to program initial boot voltage value from 0.6 V to 1.1 V by the resistor connected from
VSEL to AGND. The initial boot voltage is used to program the main loop voltage reference point. VSEL voltage
settings provide TI designated discrete internal reference voltages. Table 2 lists internal reference voltage
selections.
Table 2. VSEL Pin Configuration
DEFAULT Vref (V)
(1)
RESISTOR VALUE (kΩ) (1)
0.6
0
0.7
8.66
0.75
15.4
0.8
23.7
0.85
34.8
0.9
51.1
0.95
78.7
1.0
OPEN
1.05
121
1.1
187
The E48 series resistors with no worse than 1% tolerance are
recommended
8.4.5 Prebiased Output Start-up
The device prevent current from being discharged from the output during start-up, when a pre-biased output
condition exists. No SW pulses occur until the internal soft-start voltage rises above the error amplifier input
voltage, if the output is pre-biased. As soon as the soft-start voltage exceeds the error amplifier input, and SW
pulses start, the device limits synchronous rectification after each SW pulse with a narrow on-time. The low-side
MOSFET on-time slowly increases on a cycle-by-cycle basis until 128 pulses have been generated and the
synchronous rectifier runs fully complementary to the high-side MOSFET. This approach prevents the sinking of
current from a pre-biased output, and ensures the output voltage start-up and ramp-to regulation sequences are
smooth and monotonic.
8.4.6 Internal Ramp Generator
Internal ramp voltage is generated from duty cycle that contains emulated inductor ripple current information and
then feed it back for control loop regulation and optimization according to required output power stage, duty ratio
and switching frequency. Internal ramp amplitude is set by RAMP pin by adjusting an internal ramp generation
capacitor CRAMP, selected by the resistor connected from MODE pin to GND. For best performance, we
recommend ramp signal to be no more than 4 times of output ripple signal for all Low ESR output capacitor
(MLCC) applications, or no more than 2 times larger than output ripple signal for regular ESR output capacitor
(Pos-cap) applications. For design recommendation, please find the design tool at www.ti.com/WEBENCH.
RAMP
Duty Cycle
RRAMP
SLOPE
Slope
Compensation
RAMP
10 Selections
CRAMP
Figure 14. Internal Ramp Generator
16
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8.4.6.1 Ramp Selections
RAMP pin sets internal ramp amplitude for the control loop. RAMP amplitude is determined by internal RC,
selected by the resistor connected from MODE pin to GND, to optimize the control loop. See Table 3.
Table 3. RAMP Pin-strapping Selection
RESISTOR VALUE (kΩ) (1)
CRAMP (pF)
(1)
1
0
1.42
8.66
1.94
15.4
2.58
23.7
3.43
34.8
4.57
51.1
6.23
78.7
8.91
121
14.1
187
29.1
Open
The E48 series resistors with tolerance of 1% or less are
recommended.
8.4.7 Switching Frequency
The converter supports analog frequency selections from 300 kHz to 2 MHz, for stand alone device and sync
frequency from 300 kHz to 1 MHz for stackable configuration. The RT pin also sets clock sync point (SP) for the
slave device.
Switching Frequency Configuration for Stand-alone and Master Device in Stackable Configuration
Master
MODE
TPS543C20
RT
SYNC
Figure 15. Standalone: RT Pin Sets the Switching Frequency
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Master
Slave
VSHARE
VSHARE
ISHARE
ISHARE
MODE
MODE
RT
SYNC
SYNC
RT
Figure 16. Stackable: Master (as Clock Master) RT Pin Sets Switching Frequency, and passes it to Slave
Resistor RRT sets the continuous switching frequence selection by
RRT =
20 ´ 109 ¦ SW ´ 2
2000
¦ SW
where
•
•
R is the resistor from RT pin to GND, in Ω
ƒSW is the desired switching frequency, in Hz
(1)
8.4.8 Clock Sync Point Selection
The TPS543C20 device implements an unique clock sync scheme for phase interleaving during stackable
configuration. The device will receive the clock through sync pin and generate sync points for another
TPS543C20 device to sync to one of them to achieve phase interleaving. Sync point options can be selected
through RT pin when 1) device is configurated as master sync in, 2) device is configured as slave. See Table 5
for Control Mode Selection.
System Clock
or
Master Clock
0
1/2
0
Slave clock
1/2
Figure 17. 2-Phase Stackable with 180° Clock Phase Shift
18
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Table 4. RT Pin Sync Point Selection
CLOCK SYNC OPTIONS
RESISTOR VALUE (kΩ)
0 (0° Interleaving)
0
1/4 (90° Interleaving)
8.66
1/3 (120° Interleaving)
15.4
2/3 (240° Interleaving)
23.7
3/4 (270° Interleaving)
34.8
1/2 (180° Interleaving)
OPEN
8.4.9 Synchronization and Stackable Configuration
The TPS543C20 device can synchronize to an external clock which must be equal to or higher than internal
frequency setting. For stand alone device, the external clock should be applied to the SYNC pin. A sudden
change in synchronization clock frequency causes an associated control loop response, resulting in an overshoot
or undershoot on the output voltage.
In dual phase stackable configuration:
1. when there is no external system clock applied, the master device will be configured as clock master,
sending out pre-set switching frequency clock to slave device through SYNC pin. Slave will receive this clock
as switching clock with phase interleaving.
2. when a system clock is applied, both master and slave devices will be configured as clock slave, they will
sync to the external system clock as switching frequency with proper phase shift
8.4.10 Dual-Phase Stackable Configurations
8.4.10.1 Configuration 1: Master Sync Out Clock-to-Slave
• Direct SYNC, VSHARE and ISHARE connections between Master and Slave.
• Switching frequency is set by RT pin of Master, and pass to slave through SYNC pin. SYNC pin of master will
be configured as sync out by it’s MODE pin.
• Slave receives clock from SYNC pin. It’s RT pin determines the sync point for clock phase shift.
Master
Slave
VSHARE
VSHARE
ISHARE
ISHARE
MODE
MODE
23.7 k
51.1 k
RT
SYNC
SYNC
RT
Open
Sync Point
F_SW
Figure 18. 2-Phase Stackable with 180° Phase Shift: Master Sync Out Clock-to-Slave
8.4.10.2 Configuration 2: Master and Slave Sync to External System Clock
• Direct connection between external clock and SYNC pin of Master and Slave.
• Direct VSHARE and ISHARE connections between Master and Slave.
• SYNC pin of master will be configured as sync in by it’s MODE pin.
• Master and Slave receive external system clock from SYNC pin. Their RT pin determine the sync point for
clock phase shift.
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Master
Slave
VSHARE
VSHARE
ISHARE
ISHARE
MODE
MODE
34.8 k
51.1 k
RT
SYNC
0k
Sync Point
RT
SYNC
Open
Sync Point
System Clock
Figure 19. 2-Phase Stackable with 180° Phase Shift: Master and Slave Sync to External System Clock
8.4.11 Operation Mode
The operation mode and API/Body Brake feature is set by the MODE pin. They are selected by the resistor
connected from MODE pin to GND. Mode pin sets the device to be stand-alone mode or stackable mode. In
stand-alone mode, MODE pin sets the API on/off or trigger point sensitivity of API (1x stands for most sensitive
and 4x stands for least sensitive). In stackable mode, the MODE pin sets the device as master or slave, as well
as SYNC pin function (sync in or sync out) of the master device.
Table 5. MODE Pin-Strapping Selection
CONTROL MODE
SELECTION
API/BODY BRAKE
RESISTOR VALUE (kΩ) and API/BB
Threshold (1)
API OFF
BB OFF
Open
API ON
BB OFF
15.4, API = 35 mV
Standalone
API/body brake
•
•
Sync pin to receive clock
RT pin to set frequency
23.7
•
•
Sync pin to send out clock
RT pin to set frequency
34.8
•
•
Sync pin to receive clock
RT pin to set sync point
51.1
•
•
Sync pin to receive clock
RT pin to set sync point
121, API = 15 mV, BB = 30 mV
API ON
BB ON
(API Threshold Setting)
NOTE
187, API = 25 mV, BB = 30 mV
8.66, API = 35 mV, BB = 30 mV
78.7, API = 45 mV, BB = 30 mV
(Master sync out)
(Master sync in)
API OFF
BB OFF
(Slave Sync In)
(1)
The E48 series resistors with tolerance of 1% or less are recommended.
8.4.12 API/BODY Brake
TPS543C20 is a true fixed frequency converter. The major limitation for any fixed frequency converter is that
during transient load step up, the converter needs to wait for the next clock cycle to response to the load change,
depending on loop bandwidth design and the timing of load transient, this delay time could cause additional
output voltage drop. TPS543C20 implements a special circuitry to improve transient performance. During load
step up, the converter senses both the speed and the amplitude of the output voltage change, if the output
voltage change is fast and big enough, the converter will issue an additional PWM pulse before the next
available clock cycle to stop output voltage from further dropping, thus reducing the undershoot voltage.
20
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During load step down, TPS543C20 implements a body brake function, that turns off both high-side and lowside
FET, and allows power to dissipate through the low-side body diode, reducing overshoot. This approach is very
effective while having some impact on efficiency during transient. See Figure 20 and Figure 21.
Vout ± API enabled
Vout ± API disabled
Vout ± Body Brake disabled
Vout ± Body Brake enabled
LOAD
LOAD
Switch Node
Switch Node
Figure 20. Undershoot Comparison with API ON/OFF
Figure 21. Overshoot Comparison with Body Brake
ON/OFF
8.4.13 Sense and Overcurrent Protection
8.4.13.1 Low-Side MOSFET Overcurrent Protection
The TPS543C20 utilizes ILIM pin to set the OCP level. The ILIM pin should be connected to AGND through the
ILIM voltage setting resistor, RILIM. The ILIM terminal sources IILIM current, which is around 11.2 μA typically at
room temperature, and the ILIM level is set to the OCP ILIM voltage VILIM as shown in Equation 2. In order to
provide both good accuracy and cost effective solution, TPS543C20 supports temperature compensated
MOSFET RDS(on) sensing.
V ILIM mV
R ILIM (k:) u IILIM (PA)
Consider RDS(on) variation vs VDD in calculation
(2)
Also, TPS543C20 performs both positive and fixed negative inductor current limiting.
The inductor current is monitored by the voltage between GND pin and SW pin during the OFF time. ILIM has
1200 ppm/°C temperature slope to compensate the temperature dependency of the RDS(on). The GND pin is used
as the positive current sensing node.
The device has cycle-by-cycle over-current limiting control. The inductor current is monitored during the OFF
state and the controller maintains the OFF state during the period that the inductor current is larger than the
overcurrent ILIM level. VILIM sets the Peak level of the inductor current. Thus, the load current at the overcurrent
threshold, IOCP, can be calculated as shown in .
IOCP = VILIM (16 × RDS(on) ) - IIND(ripple) 2
=
(V IN - VOUT ) × VOUT
VILIM
1
×
16 × RDS(on) 2 × L × ƒSW
VIN
where
•
RDS(on) is the on-resistance of the low-side MOSFET.
(3)
Equation 3 is valid for VDD ≥ 5 V. Use 0.58 mΩ for RDS(on) in calculation, which is the pure on-resistance for
current sense.
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If an overcurrent event is detected in a given switching cycle, the device increments an overcurrent counter.
When the device detects three consecutive overcurrent (either high-side or low-side) events, the converter
responds, entering continuous restart hiccup. In continuous hiccup mode, the device implements a 7 soft-start
cycle timeout, followed by a normal soft-start attempt. When the overcurrent fault clears, normal operation
resumes; otherwise, the device detects overcurrent and the process repeats.
8.4.13.2 High-Side MOSFET Overcurrent Protection
The device also implements a fixed high-side MOSFET overcurrent protection to limit peak current, and prevent
inductor saturation in the event of a short circuit. The device detects an overcurrent event by sensing the voltage
drop across the high-side MOSFET during ON state. If the peak current reaches the IHOSC level on any given
cycle, the cycle terminates to prevent the current from increasing any further. High-side MOSFET overcurrent
events are counted. If the devices detect three consecutive overcurrent events (high-side or low-side), the
converter responds by entering continuous restart hiccup.
8.4.14 Output Overvoltage and Undervoltage Protection
The device includes both output overvoltage protection and output undervoltage protection capability. The
devices compare the RSP pin voltage to internal selectable pre-set voltages. If the RSP voltage with respect to
RSN voltage rises above the output overvoltage protection threshold, the device terminates normal switching and
turns on the low-side MOSFET to discharge the output capacitor and prevent further increases in the output
voltage. Then the device enters continuous restart hiccup.
If the RSP pin voltage falls below the undervoltage protection level, after soft-start has completed, the device
terminates normal switching and forces both the high-side and low-side MOSFETs off, then enters hiccup timeout delay prior to restart.
8.4.15 Overtemperature Protection
An internal temperature sensor protects the devices from thermal runaway. The internal thermal shutdown
threshold, TSD, is fixed at 165°C typical. When the devices sense a temperature above TSD, power conversion
stops until the sensed junction temperature falls by the thermal shutdown hysteresis amount; then, the device
starts up again.
8.4.16 RSP/RSN Remote Sense Function
RSP and RSN pins are used for remote sensing purpose. In the case where feedback resistors are required for
output voltage programming, the RSP pin should be connected to the mid-point of the resistor divider and the
RSN pin should always be connected to the load return.
In the case where feedback resistors are not required as when the VSEL programs the output voltage set point,
the RSP pin should be connected to the positive sensing point of the load and the RSN pin should always be
connected to the load return. RSP and RSN pins are extremely high-impedance input terminals of the true
differential remote sense amplifier. The feedback resistor divider should use resistor values much less than 100
kΩ. A simple rule of thumb is to use a 10-kΩ lower divider resistor and then size the upper resistor to achieve the
desired ratio.
22
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TPS543C20
TPS543C20
2
RSN
2
RSN
1
RSP
1
RSP
BOOT
BOOT
5
5
Load
Load
+
+
–
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Figure 22. Remote Sensing With Feedback Resistors
–
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Figure 23. Remote Sensing Without Feedback Resistors
8.4.17 Current Sharing
When devices operate in dual-phase stackable application, a current sharing loop maintains the current balance
between devices. Both devices share the same internal control voltage through VSHARE pin. The sensed
current in each phase is compared first in a current share block by connecting ISHARE pin of each device, then
the error current is added into the internal loop. The resulting voltage is compared with the PWM ramp to
generate the PWM pulse.
8.4.18 Loss of Synchronization
During sync clock condition, each individual converter will continuously compare current falling edge and
previous falling edge, if current falling edge exceeded a 1us delay versus previous pulse, converter will declare a
lost sync fault, and response by pulling down ISHARE to shut down all phases.
Declare fault and take action
Sync fault delay
Switching
pulses
Tp
Tp
Tp + Tdelay
Figure 24. Switching Response When Sync Clock Lost
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The TPS543C20 device is a highly-integrated synchronous step-down DC/DC converter. The device is used to
convert a higher DC input voltage to a lower DC output voltage, with a maximum output current of 40 A. Use the
following design procedure to select key component values for this device.
9.2 Typical Application: TPS543C20 Stand-alone Device
PVIN
20
19
18
PGND
17
SS
PGND
16
RT
PGND
15
MODE
PGND
14
RAMP
PGND
13
21 PVIN
22 PVIN
23 PVIN
VSEL
40
24 PVIN
PGND
39
25 PVIN
26 VDD
SYNC
38
27 GND
28 BP
PGND
37
29 AGND
30 ILIM
PGD
36
31 ISHARE
PGND
35
32 VSHARE
EN
34
PGOOD
33
EN
Thermal Tab
SW 12
SW 11
SW 10
9
6
SW
NC
5
8
NC
4
SW
NC
3
BOOT 7
NC
RSN 2
RSP 1
LOAD
-
+
Figure 25. 4.5-V to 16-V Input, 1-V Output, 40-A Converter
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9.2.1 Design Requirements
For this design example, use the input parameters shown in Table 6.
Table 6. Design Example Specifications
PARAMETER
VIN
Input voltage (1)
VIN(ripple)
Input ripple voltage
VOUT
Output voltage
TEST CONDITION
MIN
TYP
MAX
4
12
14
V
0.4
V
IOUT = 40 A
0.9
Line regulation
5 V ≤ VIN ≤ 14 V
UNIT
V
0.5%
Load regulation
0 V ≤ IOUT ≤ 40 A
VPP
Output ripple voltage
IOUT = 40 A
20
mV
VOVER
Transient response overshoot
ISTEP = 10 A
50
mV
VUNDER
Transient response undershoot
ISTEP = 10A
50
IOUT
Output current
5 V ≤ VIN ≤ 16 V
35
tSS
Soft-start time
VIN = 12 V
IOC
Overcurrent trip point (2)
η
Peak efficiency
fSW
Switching frequency
(1)
(2)
0.5%
IOUT = 20 A, VIN = 12 V, VDD = 5 V
mV
40
A
4
ms
45
A
90%
300
500
700
kHz
Recommended electrical ratings:
(a) Input voltage ≤ 7 V: current rating ≤ 40 A
(b) Input voltage ≤ 11 V: current rating ≤ 35 A
(c) Input voltage ≤ 14 V: current rating ≤ 30 A
DC overcurrent level
9.2.2 Detailed Design Procedure
9.2.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the TPS543C20 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
9.2.2.2 Switching Frequency Selection
Select a switching frequency for the TPS543C20. There is a trade off between higher and lower switching
frequencies. Higher switching frequencies may produce smaller solution size using lower valued inductors and
smaller output capacitors compared to a power supply that switches at a lower frequency. However, the higher
switching frequency causes extra switching losses, which decrease efficiency and impact thermal performance.
In this design, a moderate switching frequency of 500 kHz achieves both a small solution size and a high
efficiency operation is selected. The device supports continuous switching frequency programming; see
Equation 4. additional considerations (internal ramp compensation) other than switching frequency need to be
included.
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RRT =
20 ´ 109
500 ´ 103
- 2 ´
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500 ´ 103
= 39.5 kW
2000
(4)
In this case, a standard resistor value of 40.2 kΩ is selected.
9.2.2.3 Inductor Selection
To calculate the value of the output inductor (L), use Equation 5. The coefficient KIND represents the amount of
inductor-ripple current relative to the maximum output current. The output capacitor filters the inductor-ripple
current. Therefore, selecting a high inductor-ripple current impacts the selection of the output capacitor because
the output capacitor must have a ripple-current rating equal to or greater than the inductor-ripple current.
Generally, the KIND should be kept between 0.1 and 0.3 for balanced performance. Using this target ripple
current, the required inductor size can be calculated as shown in Equation 5.
VOUT
V - VOUT
1 V ´ (12 V - 1V)
L=
= 458 nH
- IN
=
VIN ´ ƒSW IOUT ´ KIND
12 V ´ 500 kHz ´ 40 A ´ 0.1
(5)
A standard inductor value of 470 nH is selected. For this application, Wurth 744309047 was used from the weborderable EVM.
9.2.2.4 Input Capacitor Selection
The TPS543C20 devices require a high-quality, ceramic, type X5R or X7R, input decoupling capacitor with a
value of at least 1 μF of effective capacitance on the VDD pin, relative to AGND. The power stage input
decoupling capacitance (effective capacitance at the PVIN and PGND pins) must be sufficient to supply the high
switching currents demanded when the high-side MOSFET switches on, while providing minimal input voltage
ripple as a result. This effective capacitance includes any DC bias effects. The voltage rating of the input
capacitor must be greater than the maximum input voltage. The capacitor must also have a ripple current rating
greater than the maximum input current ripple to the device during full load. The input ripple current can be
calculated using Equation 6.
ICIN(rms) = IOUT(max) ´
VOUT
´
VIN
(VIN -VOUT ) = 16 Arms
VIN
(6)
The minimum input capacitance and ESR values for a given input voltage ripple specification, VIN(ripple), are
shown in Equation 7 and Equation 8. The input ripple is composed of a capacitive portion, VRIPPLE(cap), and a
resistive portion, VRIPPLE(esr).
CIN (min ) =
IOUT (max ) × VOUT
= 38.5 JF
VRIPPLE :cap ; × VIN :max ; × fSW
ESR CIN (max ) =
VRIPPLE(ESR)
= 7 m3
I
IOUT :max ; + @ RIPPLE A
2
(7)
(8)
The value of a ceramic capacitor varies significantly over temperature and the amount of DC bias applied to the
capacitor. The capacitance variations due to temperature can be minimized by selecting a dielectric material that
is stable over temperature. X5R and X7R ceramic dielectrics are usually selected for power regulator capacitors
because they have a high capacitance to volume ratio and are fairly stable over temperature. The input capacitor
must also be selected with the DC bias taken into account. For this example design, a ceramic capacitor with at
least a 25-V voltage rating is required to support the maximum input voltage. For this design, allow 0.1-V input
ripple for VRIPPLE(cap), and 0.3-V input ripple for VRIPPLE(esr). Using Equation 7 and Equation 8, the minimum input
capacitance for this design is 38.5 µF, and the maximum ESR is 9.4 mΩ. For this example, four 22-μF, 25-V
ceramic capacitors and one additional 100-μF, 25-V low-ESR polymer capacitors in parallel were selected for the
power stage.
9.2.2.5 Bootstrap Capacitor Selection
A ceramic capacitor with a value of 0.1 μF must be connected between the BOOT and SW pins for proper
operation. It is recommended to use a ceramic capacitor with X5R or better grade dielectric. Use a capacitor with
a voltage rating of 25 V or higher.
26
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9.2.2.6 BP Pin
Bypass the BP pin to GND with 4.7-µF of capacitance. In order for the regulator to function properly, it is
important that these capacitors be localized to the TPS543C20 , with low-impedance return paths. See Power
Good and Enable section for more information.
9.2.2.7 R-C Snubber and VIN Pin High-Frequency Bypass
Though it is possible to operate the TPS543C20 within absolute maximum ratings without ringing reduction
techniques, some designs may require external components to further reduce ringing levels. This example uses
two approaches: a high frequency power stage bypass capacitor on the VIN pins, and an R-C snubber between
the SW area and GND.
The high-frequency VIN bypass capacitor is a lossless ringing reduction technique which helps minimizes the
outboard parasitic inductances in the power stage, which store energy during the low-side MOSFET on-time, and
discharge once the high-side MOSFET is turned on. For this example twin 2.2-nF, 25-V, 0603-sized highfrequency capacitors are used. The placement of these capacitors is critical to its effectiveness.
Additionally, an R-C snubber circuit is added to this example. To balance efficiency and spike levels, a 1-nF
capacitor and a 1-Ω resistor are chosen. In this example a 0805-sized resistor is chosen, which is rated for 0.125
W, nearly twice the estimated power dissipation. See SLUP100 for more information about snubber circuits.
9.2.2.8 Output Capacitor Selection
There are three primary considerations for selecting the value of the output capacitor. The output capacitor
affects three criteria:
• Stability
• Regulator response to a change in load current or load transient
• Output voltage ripple
These three considerations are important when designing regulators that must operate where the electrical
conditions are unpredictable. The output capacitance needs to be selected based on the most stringent of these
three criteria.
9.2.2.8.1 Response to a Load Transient
The output capacitance must supply the load with the required current when current is not immediately provided
by the regulator. When the output capacitor supplies load current, the impedance of the capacitor greatly affects
the magnitude of voltage deviation (such as undershoot and overshoot) during the transient.
Use Equation 9 and Equation 10 to estimate the amount of capacitance needed for a given dynamic load step
and release.
NOTE
There are other factors that can impact the amount of output capacitance for a specific
design, such as ripple and stability.
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COUT(min_under) =
COUT(min_over) =
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L ´ DILOAD(max)2
2 ´ DVLOAD(INSERT) ´ (VIN -VVOUT )
LOUT ´
+
DILOAD(max) ´ (1 - D ) ´ tSW
DVLOAD(INSERT)
(9)
2
(DILOAD(max) )
2 ´ DVLOAD(release) × VOUT
where
•
•
•
•
•
•
•
•
•
•
•
COUT(min_under) is the minimum output capacitance to meet the undershoot requirement
COUT(min_over)is the minimum output capacitance to meet the overshoot requirement
D is the duty cycle
L is the output inductance value (0.47 µH)
∆ILOAD(max) is the maximum transient step (10 A)
VOUT is the output voltage value (900 mV)
tSW is the switching period (2.0 µs)
VIN is the minimum input voltage for the design (12 V)
∆VLOAD(insert) is the undershoot requirement (50 mV)
∆VLOAD(release) is the overshoot requirement (50 mV)
(10)
This example uses a combination of POSCAP and MLCC capacitors to meet the overshoot requirement.
– POSCAP bank #1: 2 x 330 µF, 2.5 V, 3 mΩ per capacitor
– MLCC bank #2: 3 × 100 µF, 6.3 V, 1 mΩ per capacitor
9.2.2.8.2 Ramp Selection Design to Ensure Stability
Certain criteria is recommended for TPS543C20 to achieve optimized loop stability, bandwidth and switching
jitter performance. As a rule of thumb, the internal ramp voltage should be 2~4 times bigger than the output
capacitor ripple(capacitive ripple only). TPS543C20 is defined to be ease-of-use, for most applications, TI
recommends ramp resistor to be 187 kΩ to achieve the optimized jitter and loop response. For detailed design
procedure, see the WEBENCH® Power Designer.
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9.2.3
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Application Curves
Figure 26. Transient Response of 0.9-V Output at 12-VIN,
Transient is 15 A to 25 A to 15 A,
the Step is 10 A at 40 A/μs
Figure 27. Output Ripple and SW Node of 0.9-V Output at
12-VIN, 40-A Output
Figure 28. Output Ripple and SW Node of 0.9-V Output at
12-VIN, 0-A Output
Figure 29. Start up from Control, 0.9-V Output at 12-VIN,
10-mA Output
Figure 30. 0.5-V Prebias start up from Control, 0.9-V
Output at 12-VIN, 20-A Output
Figure 31. Output Voltage Start-up and Shutdown, 0.9-V
Output at 12-VIN, 0.5-A Output
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9.3 System Example
12
SW
PGND
SS
PGND
13
11
SW
RT
14
10
SW
PGND
15
9
SW
MODE
16
8
SW
BOOT 7
6
NC
5
NC
4
NC
3
39
NC
PGND
38
RSN 2
40
RAMP
37
RSP 1
9.3.1 Two-Phase Stackable
PVIN
PVIN
PVIN
23
22
21
17
18
19
PVIN
24
20
PVIN
25
PGND
26 VDD
EN
27 GND
PGND
28 BP
34
PGD
29 AGND
PGND
30 ILIM
35
SYNC
31 ISHARE
PGND
32 VSHARE
36
VSEL
33
Slave
LOAD
PVIN
±
PGND
16
PGND
15
MODE
PGND
14
RAMP
PGND
13
PVIN
PGND
17
21
PVIN
18
22
PVIN
19
23
PVIN
20
24
PVIN
VSEL
40
25
26 VDD
27 GND
28 BP
PGND
39
29 AGND
30 ILIM
SYNC
36
31 ISHARE
PGND
35
32 VSHARE
34
PGD
SS
38
PGND
37
33
EN
RT
Master
+
Thermal Tab
SW
SW
SW
9
10
11
12
8
SW
SW
6
BOOT 7
NC
4
5
NC
3
NC
NC
RSN 2
RSP 1
Figure 32. 2-Phase Stackable
See Synchronization and Stackable Configuration section.
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System Example (continued)
9.3.1.1 Application Curves
Figure 33. Transient Response of 0.9-V Output at 12 VIN,
Transient is 25 A to 50 A, Step is 25 A at 30 A/μs
Figure 34. Transient Response of 25-A to 50-A Load
at 30 A/μs Rise
Figure 35. Transient Response of 50-A to 25-A Load
at 30 A/μs Fall
Figure 37. Output Ripple and SW Node
of 0.9-V Output at 12 VIN, 0-A Output
Figure 36. Output Ripple and SW Node
of 0.9-V Output at 12 VIN, 80-A Output
Figure 38. Start up from Enable,
0.9-V Output at 12 VIN, 80-A Output
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System Example (continued)
Figure 39. 0.6-V Pre-Bias Start Up From Enable,
0.9-V Output at 12 VIN, 0-A Output
Figure 40. Output Voltage Start-up and Shutdown,
0.9-V Output at 12 VIN, 5-A Output
Figure 41. Master-Slave 180° Synchronization
10 Power Supply Recommendations
This device is designed to operate from an input voltage supply between 4 V and 16 V. Ensure the supply is well
regulated. Proper bypassing of input supplies and internal regulators is also critical for noise performance, as is
the quality of the PCB layout and grounding scheme. See the recommendations in Layout.
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11 Layout
11.1 Layout Guidelines
•
•
•
•
•
•
•
•
•
It is absolutely critical that all GND pins, including AGND (pin 29), GND (pin 27), and PGND (pins 13, 14, 15,
16, 17, 18, 19, and 20) are connected directly to the thermal pad underneath the device via traces or plane.
The number of thermal vias needed to support 40-A thermal operation should be as many as possible; in the
EVM design orderable on the Web, a total of 23 thermal vias are used. The TPS543C20EVM-799 is available
for purchase at ti.com.
Place the power components (including input/output capacitors, output inductor, and TPS543C20 device) on
one side of the PCB (solder side). At least one or two innner layers/planes should be inserted, connecting to
power ground, in order to shield and isolate the small signal traces from noisy power lines.
Place the VIN decoupling capacitors as close to the PVIN and PGND as possible to minimize the input AC
current loop. The high frequency decoupling capacitor (1 nF to 0.1 µF) should be placed next to the PVIN pin
and PGND pin as close as the spacing rule allows. This helps surpressing the switch node ringing.
Place a 10-nF to 100-nF capacitor close to IC from Pin 25 VIN to Pin 27 GND.
Place VDD and BP decoupling capacitors as close to the device pins as possible. Do not use PVIN plane
connection for VDD. VDD needs to be tapped off from PVIN with separate trace connection. Ensure to
provide GND vias for each decoupling capacitor and make the loop as small as possible.
The PCB trace defined as switch node, which connects the SW pins and up-stream of the output inductor
should be as short and wide as possible. In web orderable EVM design, the SW trace width is 400mil. Use
separate via or trace to connect SW node to snubber and bootstrap capacitor. Do not combine these
connections.
All sensitive analog traces and components such as RAMP, RSP, RSN, ILIM, MODE, VSEL and RT should
be placed away from any high voltage switch node (itself and others), such as SW and BOOT to avoid noise
coupling. In addition, MODE, VSEL, ILIM, RAMP and RT programming resistors should be placed near the
device/pins.
The RSP and RSN pins operate as inputs to a differential remote sense amplifier that operates with very high
impedance. It is essential to route the RSP and RSN pins as a pair of diff-traces in Kelvin-sense fashion.
Route them directly to either the load sense points (+ and –) or the output bulk capacitors. The internal circuit
uses the RSP pin for on-time adjustment. It is critical to tie the RSP pin directly tied to VOUT (load sense
point) for accurate output voltage result.
Use caution when routing of the SYNC, VSHARE and ISHARE traces for 2-phase configurations. The SYNC
trace carries a rail-to-rail signal and should be routed away from sensitive analog signals, including the
VSHARE, ISHARE, RT, and FB signals. The VSHARE and ISHARE traces should also be kept away from
fast switching voltages or currents formed by the PVIN, AVIN, SW, BOOT, and BP pins.
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11.2 Layout Example
Bypass for internal
regulators BP, VDD.
Use multiple vias to reduce
parasitic inductance
Place PVIN bypass capacitors as close
as possible to IC, with best high
frequency capacitor closest to PVIN/
PGND pins
EN
Signal
PVIN
PGD
Connect AGND to Connect GND to
Thermal Pad
Thermal Pad
SYNC
PGND
PVIN
PVIN
PVIN
PVIN
VDD
PVIN
BP
GND
ILIM
EN
AGND
Internal AGND Plane to
reduce the BP bypass
parasitics .
PGND
PGND
Thermal Pad
AGND
RSN
RSNS±
Place best high
frequency output
capacitor between
sense point
SW
SW
PGND
SW
PGND
SW
MODE
RAMP
SW
PGND
BOOT
PGND
RT
RSP
PGND
SS
RSN
VSEL
AGND and GND are
only connected
together on Thermal
Pad.
Kelvin Connect to
IC RSP and RSN pins
PGND
CBOOT
RSNS+
RBOOT
Optional RC
Snubber
Minimize SW area
for least noise.
Keep sensitive
traces away from
SW and BOOT on
all layers
L1
RSP
VOUT
Sense point should be
directly at the load
For best efficiency, use a heavy weight copper
and place these planes on multiple PCB layers
Figure 42. Example Layout
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11.3 Package Size, Efficiency and Thermal Performance
110
110
100
100
Ambient Temperature (qC)
Ambient Temperature (qC)
The TPS543C20 device is available in a 5 mm x 7 mm, QFN package with 40 power and I/O pins. It employs TI
proprietary MCM packaging technology with thermal pad. With a properly designed system layout, applications
achieve optimized safe operating area (SOA) performance. The curves shown in and are based on the orderable
evaluation module design.
90
80
70
60
50
Nat Conv
100 LFM
200 LFM
400 LFM
40
90
80
70
60
50
Nat Conv
100 LFM
200 LFM
400 LFM
40
30
30
0
5
10
VIN = 12 V
15
20
25
Output Current (A)
30
35
40
0
5
10
D001
VOUT = 5 V
500 kHz
VIN = 12 V
Figure 43. Safe Operating Area
15
20
25
Output Current (A)
30
VOUT = 1 V
35
40
D002
500 kHz
Figure 44. Safe Operating Area
Figure 45. Thermal Image at 0.9-V Output at 12 VIN, 40-A Output, at 25°C Ambient
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Package Size, Efficiency and Thermal Performance (continued)
tP
Temperature (°C)
TP
TL
TS(max)
tL
TS(min)
rRAMP(up)
tS
rRAMP(down)
t25P
25
Time (s)
Figure 46. Recommended Reflow Oven Thermal Profile
Table 7. Recommended Thermal Profile Parameters
PARAMETER
MIN
TYP
MAX
UNIT
Average ramp-up rate, TS(MAX) to TP
3
°C/s
Average ramp-down rate, TP to TS(MAX)
6
°C/s
RAMP UP AND RAMP DOWN
rRAMP(
up)
rRAMP(
down)
PRE-HEAT
TS
Pre-heat temperature
tS
Pre-heat time, TS(min) to TS(max)
150
200
°C
60
180
s
REFLOW
TL
Liquidus temperature
TP
Peak temperature
tL
Time maintained above liquidus temperature, TL
60
tP
Time maintained within 5°C of peak temperature, TP
20
t25P
Total time from 25°C of peak temperature, TP
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°C
260
°C
150
s
40
s
480
s
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12 Device and Documentation Support
12.1 Device Support
12.1.1 Development Support
12.1.1.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the TPS543C20 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
12.1.2 Documentation Support
12.1.2.1 Related Documentation
For related documentation see the following:
TPS543B20 40-A Single Phase Synchronous Step-Down Converter
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.4 Trademarks
NexFET, PowerStack, E2E are trademarks of Texas Instruments.
WEBENCH is a registered trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
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SLUSCD4B – MARCH 2017 – REVISED MAY 2018
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12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
38
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Product Folder Links: TPS543C20
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS543C20RVFR
ACTIVE
LQFN-CLIP
RVF
40
2500
RoHS-Exempt
& Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
TPS543C20
TPS543C20RVFT
ACTIVE
LQFN-CLIP
RVF
40
250
RoHS-Exempt
& Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
TPS543C20
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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