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TPS54561-Q1
SLVSC60A – SEPTEMBER 2014 – REVISED JANUARY 2017
TPS54561-Q1 4.5-V to 60-V Input, 5-A, Step-Down DC-DC Converter With Eco-mode™
1 Features
3 Description
•
•
The TPS54561-Q1 device is a 60-V, 5-A, step-down
regulator with an integrated high-side MOSFET. The
device survives load dump pulses up to 65 V per
ISO7637. Current-mode control provides simple
external compensation and flexible component
selection. A low-ripple pulse-skip mode and 152-µA
supply current enables high efficiency at light loads.
Pulling the enable pin low reduces shutdown supply
current to 2 µA .
1
•
•
•
•
•
•
•
•
•
•
•
•
•
Qualified for Automotive Applications
AEC-Q100 Qualified With the Following Results:
– Device Temperature Grade 1: –40°C to 125°C
Ambient Operating Temperature Range
– Device HBM ESD Classification H1C
– Device CDM ESD Classification C5
High Efficiency at Light Loads With PulseSkipping Eco-mode™ Control
87-mΩ High-Side MOSFET
152-µA Operating Quiescent Current and
2-µA Shutdown Current
100-kHz to 2.5-MHz Switching Frequency
Synchronizes to External Clock
Low-Dropout Operation at Light Loads With
Integrated BOOT Recharge FET
Adjustable UVLO Voltage and Hysteresis
Power-Good Output Monitor for Undervoltage and
Overvoltage
Adjustable Soft-Start and Sequencing
0.8-V 1% Internal Voltage Reference
10-Pin WSON With Thermal Pad Package
–40°C to 150°C TJ Operating Range
Create a Custom Design using the TPS54561-Q1
with the WEBENCH® Power Designer
2 Applications
•
•
•
Undervoltage lockout has an internal 4.3-V setting.
Use of an external resistor divider at the EN pin can
increase the setting. The soft-start pin controls the
output-voltage start-up ramp and also configures
sequencing or tracking. An open-drain power-good
signal indicates the output is within 93% to 106% of
its nominal voltage.
A wide adjustable switching-frequency range allows
optimization for either efficiency or external
component size. Cycle-by-cycle current limit,
frequency foldback, and thermal shutdown protect the
device during an overload condition.
The TPS54561-Q1 is available in a 10-pin, 4-mm × 4mm WSON package.
Device Information(1)
PART NUMBER
BODY SIZE (NOM)
WSON (10)
4.00 mm × 4.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Vehicle Accessories: GPS (see SLVA412),
Entertainment
USB Dedicated Charging Ports and Battery
Chargers (see SLVA464)
12-V and 24-V Automotive Power Systems
Space
Simplified Schematic
VI
PACKAGE
TPS54561-Q1
Efficiency vs Load Current
100
VDD
36 V to 12 V
PWRGD
95
TPS54561-Q1
RT/CLK
SS/TR
BOOT
SW
VO
COMP
FB
Efficiency (%)
90
EN
85
12 V to 3.3 V
80
12 V to 5 V
75
70
VO = 12 V, f (SW) = 620 kHz
VO = 5 V and 3.3 V, f (SW) = 400 kHz
65
GND
60
0
Copyright © 2016, Texas Instruments Incorporated
1
2
3
IO - Output Current (A)
4
5
C024
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS54561-Q1
SLVSC60A – SEPTEMBER 2014 – REVISED JANUARY 2017
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
4
4
4
5
5
6
6
7
Absolute Maximum Ratings .....................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics..........................................
Timing Requirements ................................................
Switching Characteristics ..........................................
Typical Characteristics ..............................................
Detailed Description ............................................ 11
7.1 Overview ................................................................. 11
7.2 Functional Block Diagram ....................................... 12
7.3 Feature Description................................................. 12
7.4 Device Functional Modes........................................ 27
8
Application and Implementation ........................ 28
8.1 Application Information............................................ 28
8.2 Typical Application .................................................. 28
9 Power Supply Recommendations...................... 42
10 Layout................................................................... 43
10.1 Layout Guidelines ................................................. 43
10.2 Layout Example .................................................... 43
11 Device and Documentation Support ................. 44
11.1
11.2
11.3
11.4
11.5
11.6
11.7
Device Support......................................................
Documentation Support .......................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
44
44
44
44
44
45
45
12 Mechanical, Packaging, and Orderable
Information ........................................................... 45
4 Revision History
Changes from Original (September 2014) to Revision A
Page
•
Changed package SON To: WSON in the Features and throughout the data sheet ........................................................... 1
•
Added the WEBENCH information in the Features, Detailed Design Procedure, and Device Support sections .................. 1
•
Added SW, 5-ns transient to the Absolute Maximum Ratings ............................................................................................... 4
•
Moved Storage temperature range to the Absolute Maximum Ratings ................................................................................. 4
•
Changed the Handling Ratings table to the ESD Ratings ..................................................................................................... 4
•
Changed Equation 10 and Equation 11 .............................................................................................................................. 19
•
Changed Equation 30 .......................................................................................................................................................... 30
•
Changed Equation 33 .......................................................................................................................................................... 30
•
Moved Power Dissipation Estimate to the Detailed Design Procedure section ................................................................... 35
•
Moved the location of the Safe Operating Area ................................................................................................................... 37
•
Moved Inverting Power Supply and Split-Rail Power Supply to the Application Information section................................... 41
2
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SLVSC60A – SEPTEMBER 2014 – REVISED JANUARY 2017
5 Pin Configuration and Functions
DPR Package
10-Pin WSON
(Top View)
BOOT
1
10
PWRGD
VDD
2
9
SW
EN
3
8
GND
SS/TR
4
7
COMP
RT/CLK
5
6
FB
Thermal
Pad
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
BOOT
1
O
The device requires a bootstrap capacitor between BOOT and SW. If the voltage on this capacitor is below
the minimum required voltage to operate the high-side MOSFET, the gate driver switches off until the
bootstrap capacitor recharges.
COMP
7
O
Error amplifier output, and input to the output switch-current comparator (PWM comparator). Connect
frequency compensation components to this pin.
EN
3
I
Enable pin, with internal pullup current source. Pull below 1.2 V to disable. Float to enable. Adjust the input
undervoltage lockout with two resistors. See the Enable and Adjust Undervoltage Lockout section.
FB
6
I
Inverting input of the transconductance (gm) error amplifier.
GND
8
—
Ground
PWRGD
10
O
Power-good is an open-drain output that asserts if the output voltage is low because of thermal shutdown,
dropout, overvoltage, or EN shutdown.
RT/CLK
5
I
Resistor timing and external clock. An internal amplifier holds this pin at a fixed voltage when using an
external resistor to ground to set the switching frequency. When pulled above the PLL upper threshold, a
mode change occurs, and the pin becomes a synchronization input. This change disables the internal
amplifier, and the pin is a high-impedance clock input to the internal PLL. Stopping the clocking edges reenables the internal amplifier, and the operating mode returns to resistor programmed mode.
SS/TR
4
I
Soft-start and tracking input pin. An external capacitor connected to this pin sets the output rise time. A
voltage on this pin overrides the internal reference, which allows use of the pin for tracking and sequencing.
SW
9
I
The source of the internal high-side power MOSFET, and switching node of the converter.
VDD
2
I
Input supply pin with 4.5-V to 60-V operating range.
Thermal pad
—
—
To ensure proper operation, electrically connect the GND pin to the copper pad under the IC on the printed
circuit board.
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6 Specifications
6.1 Absolute Maximum Ratings (1)
Over operating free-air temperature range (unless otherwise noted)
VALUE
MIN
Input voltage
Output voltage
VDD
–0.3
65
EN
–0.3
8.4
FB
–0.3
3
COMP
–0.3
3
PWRGD
–0.3
6
SS/TR
–0.3
3
RT/CLK
–0.3
3.6
BOOT-SW
–0.3
8
SW
–0.6
65
–7
65
SW, 5-ns transient
SW, 10-ns transient
UNIT
MAX
V
V
–2
65
Operating junction temperature
-40
150
°C
Storage temperature range, Tstg
–65
150
°C
(1)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and do not imply functional operation of the device at these or any other conditions beyond those indicated under
Rec–65ommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
Electrostatic discharge
Human-body model (HBM), per AEC Q100-002 (1)
±2000
Charged-device model (CDM), per AEC-Q100-011
±750
UNIT
V
AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
Over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
VDD
Supply input voltage
4.5
60
V
VO
Output voltage
0.8
58.8
V
IO
Output current
0
5
A
TJ
Junction temperature
–40
150
°C
4
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SLVSC60A – SEPTEMBER 2014 – REVISED JANUARY 2017
6.4 Thermal Information
TPS54561-Q1
THERMAL METRIC (1) (2)
DPR
UNIT
10 PINS
RθJA
Junction-to-ambient thermal resistance (standard board)
35.1
°C/W
RθJCtop
Junction-to-case (top) thermal resistance
34.1
°C/W
RθJB
Junction-to-board thermal resistance
12.3
°C/W
ψJT
Junction-to-top characterization parameter
0.3
°C/W
ψJB
Junction-to-board characterization parameter
12.5
°C/W
RθJCbot
Junction-to-case (bottom) thermal resistance
2.2
°C/W
(1)
(2)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
Determination of the power rating at a specific ambient temperature must be at the maximum junction temperature of 150°C. This is the
point where distortion starts to increase substantially. See the power dissipation estimate in the Power Dissipation Estimate section of
this data sheet for more information.
6.5
Electrical Characteristics
TJ = –40°C to 150°C, VDD = 4.5 to 60 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
60
V
4.3
4.48
V
SUPPLY VOLTAGE (VDD PIN)
Operating input voltage
Internal undervoltage lockout threshold
4.5
VDD rising
4.1
Internal undervoltage lockout threshold
hysteresis
325
mV
Shutdown supply current
V(EN) = 0 V, TA = 25°C, 4.5 V ≤ VDD ≤ 60 V
2.25
4.5
Operating: nonswitching supply current
V(FB) = 0.9 V, TA = 25°C
152
200
1.2
1.3
µA
ENABLE AND UVLO (EN PIN)
V(EN)th
Enable threshold voltage
Input current
I(HYS)
No voltage hysteresis, rising and falling
1.1
Enable threshold + 50 mV
Enable threshold – 50 mV
Hysteresis current
–4.6
V
µA
–0.58
–1.2
-1.8
–2.2
–3.4
-4.5
µA
0.792
0.8
0.808
V
87
185
VOLTAGE REFERENCE
Vref
Voltage reference
HIGH-SIDE MOSFET
On-resistance
VDD = 12 V, V(BOOT-SW) = 6 V
mΩ
ERROR AMPLIFIER
Input current
gm(ea)
A(OL)
Error-amplifier transconductance
–2 µA < I(COMP) < 2 µA, V(COMP) = 1 V
Error-amplifier transconductance (gm) during
soft-start
–2 µA < I(COMP) < 2 µA, V(COMP) = 1 V, V(FB) =
0.4 V
Error-amplifier open-loop dc gain
V(FB) = 0.8 V
Minnimum unity-gain bandwidth
Error-amplifier source and sink
gm(ps)
V(COMP) = 1 V, 100 mV overdrive
COMP to SW current transconductance
50
nA
350
µS
78
µS
10 000
V/V
2500
kHz
±30
µA
17
S
CURRENT LIMIT
Current limit threshold
All VDD and temperatures, open loop (1)
6.3
7.5
8.8
All temperatures, VDD = 12 V, open loop (1)
6.3
7.5
8.3
VDD = 12 V, TA = 25°C, open loop (1)
7.1
7.5
7.9
A
THERMAL SHUTDOWN
Thermal shutdown
Thermal shutdown hysteresis
(1)
176
°C
12
°C
Measure open-loop current limit directly at the SW pin. The current is independent of the inductor value and slope compensation.
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Electrical Characteristics (continued)
TJ = –40°C to 150°C, VDD = 4.5 to 60 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
1.55
2
UNIT
EXTERNAL CLOCK (RT/CLK PIN)
RT/CLK high threshold
RT/CLK low threshold
0.5
1.2
V
V
SOFT-START AND TRACKING (SS/TR PIN)
I(SS)
Charge current
V(SS/TR) = 0.4 V
1.7
µA
SS/TR-to-FB matching
V(SS/TR) = 0.4 V
42
mV
SS/TR-to-reference crossover
98% of nominal FB voltage
1.16
V
SS/TR discharge current (overload)
V(FB) = 0 V, V(SS/TR) = 0.4 V
354
µA
SS/TR discharge voltage
V(FB) = 0 V
54
mV
POWER GOOD (PWRGD PIN)
FB threshold for PWRGD low
FB falling
FB threshold for PWRGD high
FB rising
91%
93%
FB threshold for PWRGD low
FB rising
108%
FB threshold for PWRGD high
FB falling
106%
Hysteresis
FB falling
2%
Output-high leakage
V(PWRGD) = 5.5 V, TA = 25°C
10
nA
On-resistance
I(PWRGD) = 3 mA, V(FB) < 0.79 V
45
Ω
Minimum input voltage for defined output
voltage
V(PWRGD) < 0.5 V, I(PWRGD) = 100 µA
0.9
2
TYP
MAX
V
6.6 Timing Requirements
MIN
UNIT
RT/CLK
Minimum CLK input pulse duration
15
ns
6.7 Switching Characteristics
TJ = –40°C to 150°C, VDD = 4.5 V to 60 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ENABLE AND UVLO (EN PIN)
Enable to COMP active
VDD = 12 V, TA = 25°C
540
µs
60
ns
100
ns
CURRENT-LIMIT
td(CL)
Current limit threshold delay
SW
t(ON)
Minimum controllable on-time
VDD = 23.7 V, VO = 5 V, IO = 3.5 A, R(RT)
= 39.6 kΩ, TA = 25°C
RT/CLK
Switching frequency range using RT
mode
f(SW)
Switching frequency
100
R(RT) = 200 kΩ
450
Switching frequency range using CLK
mode
500
160
2500
kHz
550
kHz
2300
kHz
TIMING RESISTOR AND EXTERNAL CLOCK (RT/CLK PIN)
6
RT/CLK falling edge to SW rising edge
delay
Measured at 500 kHz with an RT resistor
(R(RT)) in series
55
ns
PLL lock-in time
Measured at 500 kHz
78
µs
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SLVSC60A – SEPTEMBER 2014 – REVISED JANUARY 2017
0.25
0.814
0.809
0.2
V o lta g e R e fe r e n c e ( V )
S ta tic D r a in - S o u r c e O n - S ta te R e s is ta n c e (: )
6.8 Typical Characteristics
0.15
0.1
0.05
0.804
0.799
0.794
0.789
BOOT-SW = 3 V
BOOT-SW = 6 V
0
0.784
-50
-25
0
25
50
75
100
125
Junction Temperature (qC)
150
-50
-25
0
25
50
75
100
125
150
Junction Temperature (qC)
D004
D028
VDD = 12 V
Figure 1. On-Resistance vs Junction Temperature
Figure 2. Voltage Reference vs Junction Temperature
6.5
9
-40q
8.5
H ig h - S id e S w itc h C u r r e n t ( A )
High-Side Switch Current (A)
6.3
8
7.5
7
6.5
25q
150q
6.1
5.9
5.7
5.5
5.3
5.1
4.9
4.7
6
-50
4.5
-25
0
25
50
75
100
Junction Temperature (qC)
125
0
150
10
20
30
40
50
60
Input Voltage (V)
D026
D027
VDD = 12 V
Figure 4. Switch-Current Limit vs Input Voltage
Figure 3. Switch-Current Limit vs Junction Temperature
500
550
450
530
S w itc h in g F r e q u e n c y ( k H z )
S w itc h in g F r e q u e n c y ( k H z )
540
520
510
500
490
480
470
350
300
250
200
150
460
450
-50
400
100
-25
0
25
50
75
100
Junction Temperature (qC)
R(RT) = 200 kΩ
125
150
200
300
400
500
600
700
800
900
Resistance at RT/CLK (k:)
D025
1000
D024
VDD = 12 V
Figure 5. Switching Frequency vs Junction Temperature
Figure 6. Switching Frequency vs RT/CLK Resistance,
Low-Frequency Range
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2500
500
2000
450
Transconductance (PS)
S w itc h in g F r e q u e n c y ( k H z )
Typical Characteristics (continued)
1500
1000
400
350
300
500
250
0
0
50
100
150
200
-50
200
Resistance at RT/CLK (k:)
-25
0
D023
25
50
75
100
Junction Temperature (ºC)
125
150
D022
VDD = 12 V
Figure 7. Switching Frequency vs RT/CLK Resistance,
High-Frequency Range
Figure 8. EA Transconductance vs Junction Temperature
1.33
120
110
1.3
90
E N T h r e s h o ld ( V )
Transconductance (PS)
100
80
70
60
50
40
1.27
1.24
1.21
1.18
30
20
-50
1.15
-25
0
25
50
75
100
Junction Temperature (qC)
125
-50
150
25
50
75
100
125
150
D020
VDD = 12 V
Figure 10. EN Pin Threshold Voltage vs Junction
Temperature
Figure 9. EA Transconductance During Soft-Start vs
Junction Temperature
-3.5
-0.5
-3.7
-0.7
-3.9
-0.9
In p u t C u r r e n t a t E N ( P A )
In p u t C u r r e n t a t E N ( P A )
0
Junction Temperature (qC)
VDD = 12 V
-4.1
-4.3
-4.5
-4.7
-4.9
-1.1
-1.3
-1.5
-1.7
-1.9
-5.1
-2.1
-5.3
-2.3
-5.5
-2.5
-50
-25
0
25
50
75
100
125
Junction Temperature (qC)
VDD = 12 V
150
-50
-25
V(EN) = Threshold + 50 mV
0
25
50
75
100
125
Junction Temperature (qC)
D019
Figure 11. EN Pin Current vs Junction Temperature
8
-25
D021
VDD = 12 V
150
D018
V(EN) = Threshold – 50 mV
Figure 12. EN Pin Current vs Junction Temperature
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Typical Characteristics (continued)
100
-2.5
V (FB) Falling
N o m in a l S w itc h in g F r e q u e n c y ( % )
-2.7
I ( E N ) H y s te r e s is ( P A )
-2.9
-3.1
-3.3
-3.5
-3.7
-3.9
-4.1
-4.3
V (FB) Rising
75
50
25
0
-4.5
-50
-25
0
25
50
75
100
125
0
150
Junction Temperature (qC)
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
Voltage at FB (V)
D017
D016
VDD = 12 V
Figure 13. EN Pin Current Hysteresis vs Junction
Temperature
Figure 14. Switching Frequency vs FB
3
Supply Current at V DD Pin (PA)
Supply Current at V DD Pin (PA)
3
2.5
2
1.5
1
0.5
0
-50
2.5
2
1.5
1
0.5
0
-25
0
25
50
75
100
Junction Temperature (qC)
125
150
0
VDD = 12 V
30
40
Input Voltage (V)
50
60
D014
Figure 16. Shutdown Supply Current vs Input Voltage
210
210
190
190
Supply Current at V DD Pin (PA)
Supply Current at V DD Pin (PA)
20
TJ = 25ºC
Figure 15. Shutdown Supply Current vs Junction
Temperature
170
150
130
110
90
70
-50
10
D015
170
150
130
110
90
70
-25
0
25
50
75
100
Junction Temperature (qC)
125
150
0
10
D013
VDD = 12 V
20
30
40
Input Voltage (V)
50
60
D012
TJ = 25ºC
Figure 17. I(VDD) Supply Current vs Junction Temperature
Figure 18. I(VDD) Supply Current vs Input Voltage
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Typical Characteristics (continued)
2.6
4.5
BOOT-SW UVLO Falling
BOOT-SW UVLO Rising
4.4
2.4
VDD Pin Voltage (V)
BOOT-SW UVLO Voltage (V)
2.5
2.3
2.2
2.1
4.2
4.1
4
2
3.9
1.9
3.8
1.8
-50
3.7
-50
-25
0
25
50
75
100
Junction Temperature (qC)
125
150
UVLO Start Switching
UVLO Stop Switching
-25
0
25
50
75
100
Junction Temperature (qC)
D011
Figure 19. BOOT-SW UVLO vs Junction Temperature
110
70
108
60
50
40
30
20
125
150
D010
Figure 20. Input Voltage UVLO vs Junction Temperature
80
Power-Good Threshold (%)
P o w e r - G o o d R e s is ta n c e (: )
4.3
106
104
102
FB Rising
FB Falling
FB Rising
FB Falling
100
98
96
94
92
10
90
0
-50
-25
0
25
50
75
100
125
Junction Temperature (qC)
88
-50
150
VDD = 12 V
25
50
75
100
Junction Temperature (qC)
125
150
D008
Figure 22. PWRGD Threshold vs Junction Temperature
900
60
800
55
700
SS/TR-to-FB Offset (mV)
SS/TR-to-FB Offset (mV)
0
VDD = 12 V
Figure 21. PWRGD On-Resistance vs Junction Temperature
600
500
400
300
200
50
45
40
35
30
25
100
0
0
100
VDD = 12 V
200
300
400
500
FB Pin Voltage (mV)
600
700
800
20
-50
-25
0
D007
TJ = 25ºC
VDD = 12 V
Figure 23. SS/TR to FB Offset vs FB
10
-25
D009
25
50
75
100
Junction Temperature (qC)
125
150
D006
V(FB) = 0.4 V
Figure 24. SS/TR to FB Offset vs Temperature
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Typical Characteristics (continued)
5.6
Start
5.5
Stop
I n p u t V o lta g e ( V )
5.4
5.3
5.2
5.1
Dropout
Voltage
5
4.9
Dropout
Voltage
4.8
4.7
4.6
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
Output Current (A)
0.45
0.5
D005
Figure 25. 5-V Start and Stop Voltage (see Low-Dropout Operation and Bootstrap Voltage (BOOT))
7 Detailed Description
7.1 Overview
The TPS54561-Q1 device is a 60-V, 5-A, step-down (buck) regulator with an integrated high-side n-channel
MOSFET. The device implements constant-frequency current-mode control, which reduces output capacitance
and simplifies external frequency compensation. The wide switching frequency range of 100 kHz to 2500 kHz
allows either efficiency or size optimization when selecting the output filter components. The use of a resistor
connected to ground from the RT/CLK pin adjusts the switching frequency. The device has an internal phaselocked loop (PLL) connected to the RT/CLK pin that synchronizes the power-switch turnon to the falling edge of
an external clock signal.
The TPS54561-Q1 device has a default input start-up voltage of approximately 4.3 V. The EN pin adjusts the
input-voltage undervoltage-lockout (UVLO) threshold with two external resistors. An internal pullup current source
enables operation when the EN pin is floating. The operating current is 152 µA under no-load conditions when
not switching. With the device disabled, the supply current is 2 µA.
The integrated 87-mΩ high-side MOSFET supports high-efficiency power supply designs capable of delivering
5 A of continuous current to a load. A bootstrap capacitor connected from the BOOT pin to the SW pin supplies
the gate-drive bias voltage for the integrated high-side MOSFET. The TPS54561-Q1 device reduces the external
component count by integrating the bootstrap recharge diode. A BOOT UVLO circuit monitors the BOOT pin
capacitor voltage, and turns off the high-side MOSFET when the BOOT to SW voltage falls below a preset
threshold. An automatic BOOT capacitor recharge circuit allows the TPS54561-Q1 to operate at high duty cycles
approaching 100%. Therefore, the maximum output voltage is near the minimum input supply voltage of the
application. The minimum output voltage is 0.8 V, which equals the internal feedback reference.
An overvoltage protection (OVP) comparator minimizes output overvoltage transients. On activation of the OVP
comparator, the high-side MOSFET turns off and remains off until the output voltage is less than 106% of the
desired output voltage.
Using the SS/TR (soft-start and tracking) pin minimizes inrush currents or provides power supply sequencing
during power-up. Couple a small-value capacitor from the SS/TR pin to the GND pin to adjust the soft-start time.
Couple a resistor divider from SS/TR pin to GND pin for critical power-supply sequencing requirements. The
device discharges the SS/TR pin before the output powers up. This discharging ensures a repeatable restart
after an overtemperature fault, UVLO fault, or a disabled condition. When the overload condition goes away, the
soft-start circuit controls the recovery from the fault output level to the nominal regulation voltage. A frequency
foldback circuit reduces the switching frequency during start-up or overcurrent fault conditions to help maintain
control of the inductor current.
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7.2 Functional Block Diagram
EN
PWRGD
VDD
Shutdown
UV
Enable
Comparator
Logic
Thermal
Shutdown
UVLO
Shutdown
Shutdown
Logic
OV
Enable
Threshold
Voltage
Reference
Boot
Charge
Minimum
Clamp
Pulse
Skip
Error
Amplifier
Boot
UVLO
PWM
Comparator
FB
SS/TR
Current
Sense
BOOT
Logic
Shutdown
S
Slope
Compensation
SW
COMP
Frequency
Shift
Overload
Recovery
Maximum
Clamp
GND
Oscillator
With PLL
Thermal Pad
RT/CLK
Copyright © 2016, Texas Instruments Incorporated
7.3 Feature Description
7.3.1 Fixed-Frequency PWM Control
The TPS54561-Q1 device uses fixed-frequency, peak-current-mode control with adjustable switching frequency.
An error amplifier compares the output voltage to an internal voltage reference through an external resistor
divider connected to the FB pin. An internal oscillator initiates the turnon of the high-side MOSFET. The error
amplifier output at the COMP pin controls the high-side MOSFET current. When the high-side MOSFET switch
current reaches the threshold level set by the COMP voltage, the power switch turns off. The COMP pin voltage
increases and decreases as the output current increases and decreases. The device implements current limiting
by clamping the COMP pin voltage to a maximum level. Implementation of the pulse-skipping Eco-mode control
scheme is through a minimum voltage clamp on the COMP pin.
7.3.2 Slope Compensation Output Current
The TPS54561-Q1 adds a compensating ramp to the MOSFET switch-current sense signal. This slope
compensation prevents sub-harmonic oscillations at duty cycles greater than 50%. The slope compensation does
not affect the peak current limit of the high-side switch, which remains constant over the full duty cycle range.
12
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Feature Description (continued)
7.3.3 Pulse-Skipping Eco-mode Control Scheme
The TPS54561-Q1 device operates in a pulse-skipping Eco-mode control scheme at light load currents to
improve efficiency by reducing switching and gate-drive losses. If the output voltage is within regulation and the
peak switch current of any switching cycle is below the pulse-skipping current threshold, the device enters pulseskipping mode. The pulse-skipping current threshold is the peak switch-current level corresponding to a nominal
COMP voltage of 600 mV.
When in pulse-skipping mode, the TPS54561-Q1 device clamps the COMP pin voltage to 600 mV and inhibits
the high-side MOSFET. Because the device is not switching, the output voltage begins to decay. The voltage
control loop responds to the falling output voltage by increasing the COMP pin voltage. The high-side MOSFET
enables and switching resumes when the error amplifier lifts COMP above the pulse-skipping threshold. The
output voltage recovers to the regulated value, and COMP eventually falls below the pulse-skipping threshold, at
which time the device again enters pulse-skipping mode. The internal PLL remains operational when in pulseskipping mode. When operating at light load currents in pulse-skipping mode, the switching transitions occur
synchronously with the external clock signal.
During pulse-skipping operation, the TPS54561-Q1 device senses and controls the peak switch current, not the
average load current. Therefore, the load current at which the device enters pulse-skipping mode depends on the
output inductor value. The circuit in Figure 46 enters pulse-skipping mode at about 25.3 mA output current. As
the load current approaches zero, the device enters the pulse-skipping mode. During the time period when there
is no switching the input current falls to the 152-µA quiescent current.
7.3.4 Low-Dropout Operation and Bootstrap Voltage (BOOT)
The TPS54561-Q1 device provides an integrated bootstrap voltage regulator. A small capacitor between the
BOOT and SW pins provides the gate-drive voltage for the high-side MOSFET. The BOOT capacitor recharges
when the high-side MOSFET is off and the external low-side diode conducts. The recommended value of the
BOOT capacitor is 0.1 µF. For stable performance over temperature and voltage, TI recommends a ceramic
capacitor with an X7R or X5R grade dielectric with a voltage rating of 10 V or higher.
When operating with a low voltage difference from input to output, the high-side MOSFET of the TPS54561-Q1
operates at 100% duty cycle as long as the BOOT-to-SW pin voltage is greater than 2.1 V. When the voltage
from BOOT to SW drops below 2.1 V, the high-side MOSFET turns off and an integrated low-side MOSFET pulls
SW low to recharge the BOOT capacitor. To reduce the losses of the small low-side MOSFET at high output
voltages, the device disables this small low-side MOSFET at 24-V output and re-enables it when the output
reaches 21.5 V.
Because the gate-drive current sourced from the BOOT capacitor is small, the high-side MOSFET can remain on
for many switching cycles before the MOSFET turns off to refresh the capacitor. Thus the effective duty cycle of
the switching regulator can be high, approaching 100%. The main influences on the effective duty cycle of the
converter during dropout are the voltage drops across the power MOSFET, the inductor resistance, the low-side
diode voltage, and the printed-circuit-board (PCB) resistance.
Figure 25 shows the start and stop voltages for a typical 5-V output application, and plots the input voltage
versus load current. The definition of start voltage is the input voltage required to regulate the output within 1% of
nominal voltage. The definition of stop voltage is the input voltage at which the output drops by 5% or where
switching stops.
During high-duty-cycle (low dropout) conditions, inductor current ripple increases while the BOOT capacitor
recharges, resulting in an increase in output-voltage ripple. Increased ripple occurs when the off-time required to
recharge the BOOT capacitor is longer than the high-side off-time associated with cycle-by-cycle PWM control.
At heavy loads, increase the minimum input voltage to ensure a monotonic start-up. For this condition, use
Equation 1 to calculate the maximum output voltage for a given minimum input voltage.
VO max = Dmax ´ (VI min - I Omax ´ rDS(on) + V(d) ) - V(d) + I Omax ´ R (DC)
where
•
•
•
Dmax = 0.9
V(d) = Forward drop of the catch diode
R(DC) = DC resistance of output inductor
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Feature Description (continued)
•
•
•
•
•
rDS(on) = 1 / (–0.3 × V(BOOT_SW)2 + 3.577 × V(BOOT_SW) – 4.246)
V(BOOT_SW) = V(BOOT) + V(d)
V(BOOT) = (1.41 × VImin – 0.554 – V(d) x f(SW) – 1.847 × 103 × I(BOOT_SW)) / (1.41 + f(SW))
I(BOOT_SW) = 100 × 10-6 A
f(SW) = Operating frequency in MHz
(1)
7.3.5 Error Amplifier
A transconductance error amplifier controls the TPS54561-Q1 voltage regulation loop. The error amplifier
compares the FB pin voltage to the lower of the internal soft-start voltage or the internal 0.8-V voltage reference.
The transconductance (gm(ea)) of the error amplifier is 350 µS during normal operation. During soft-start
operation, the device reduces the transconductance to 78 µS and references the error amplifier to the internal
soft-start voltage.
The frequency compensation components (capacitor, series resistor, and capacitor) connect the error-amplifier
output COMP pin to the GND pin.
7.3.6 Adjusting the Output Voltage
The internal voltage reference produces a precise 0.8-V ±1% voltage reference over the operating temperature
and voltage range by scaling the output of a bandgap reference circuit. A resistor divider from the output node to
the FB pin sets the output voltage. Divider resistors with a 1% tolerance or better are recommended. Select the
low-side resistor, R(LS), for the desired divider current, and use Equation 2 to calculate R(HS). To improve
efficiency at light loads, consider using larger-value resistors. However, if the values are too high, the regulator is
more susceptible to noise and voltage errors because of the FB input current may become noticeable.
æ V - 0.8 V ö
R (HS) = R (LS) ´ ç O
÷
è 0.8 V ø
(2)
7.3.7 Enable and Adjust Undervoltage Lockout
The VDD pin voltage rising above 4.3 V when the EN pin voltage exceeds the enable threshold of 1.2 V enables
the TPS54561-Q1 device. The VDD pin voltage falling below 4 V or the EN pin voltage dropping below 1.2 V
disables the TPS54561-Q1 device. The EN pin has an internal pullup current source, I(1), of 1.2 µA that enables
operation of the TPS54561-Q1 device when the EN pin floats.
If an application requires a higher undervoltage lockout (UVLO) threshold, use the circuit shown in Figure 26 to
adjust the input voltage UVLO with two external resistors. When the EN pin voltage exceeds 1.2 V, the EN pin
sources an additional 3.4 µA of hysteresis current, I(HYS). This additional current facilitates adjustable input
voltage UVLO hysteresis. Pulling the EN pin below 1.2 V removes the 3.4-µA I(HYS) current. Use Equation 3 to
calculate R(UVLO1) for the desired UVLO hysteresis voltage. Use Equation 4 to calculate R(UVLO2) for the desired
VDD start voltage.
In applications designed to start at relatively low input voltages (for example, from 4.5 V to 9 V) and withstand
high input voltages (for example, from 40 V to 60 V), the EN pin may experience a voltage greater than the
absolute maximum voltage of 8.4 V during the high-input-voltage condition. To avoid exceeding this voltage
when using the EN resistors, a 5.8-V Zener diode that is capable of sinking up to 150 µA internally clamps the
EN pin.
æ V(START) - V(STOP) ö
÷
R (UVLO1) = ç
ç
÷
I (HYS)
è
ø
(3)
V(EN)th
R (UVLO2) =
V(START) - V(EN)th
+ I(1)
R (UVLO1)
(4)
14
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Feature Description (continued)
VI
VDD
TPS54561-Q1
VI
I(1) I(HYS)
R(UVLO1)
R(UVLO1)
EN
EN
V(EN)th
R(UVLO2)
R(UVLO2)
Copyright © 2017, Texas Instruments Incorporated
Figure 26. Adjustable Undervoltage Lockout
(UVLO)
10 kW
Node
5.8 V
Copyright © 2017, Texas Instruments Incorporated
Figure 27. Internal Clamp On EN Pin
7.3.8 Soft-Start and Tracking Pin (SS/TR)
The TPS54561-Q1 device effectively uses the lower voltage of the internal voltage reference or the SS/TR pin
voltage as the power-supply reference voltage and regulates the output accordingly. A capacitor on the SS/TR
pin to ground implements a soft-start time. The TPS54561-Q1 device has an internal pullup current source of 1.7
µA that charges the external soft-start capacitor. Equation 5 shows the calculation for the soft-start time (10% to
90%). The voltage reference (Vref) is 0.8 V and the soft-start current (I(SS)) is 1.7 µA. The soft-start capacitor
should remain lower than 0.47 µF and greater than 0.47 nF.
t (SS) (ms) ´ I (SS) (μA)
C(SS) (nF) =
V ref ´ 0.8
(5)
At power up, the TPS54561-Q1 device does not start switching until the voltage in the soft-start pin is less than
54 mV to ensure a proper power up (see Figure 28).
Also, during normal operation, the TPS54561-Q1 stops switching and the SS/TR pin must discharge to 54 mV
when one of the following occurs: the VDD pin voltage exceeds the UVLO threshold, the EN pin drops below
1.2 V, or a thermal shutdown event occurs.
The FB voltage follows the SS/TR pin voltage with a 42-mV offset up to 85% of the internal voltage reference.
When the SS/TR voltage is greater than 85% of the internal reference voltage, the offset increases as the
effective system reference transitions from the SS/TR voltage to the internal voltage reference (see Figure 23).
The SS/TR voltage ramps linearly until clamped at 2.7 V typical, as shown in Figure 28.
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Feature Description (continued)
V(EN)
V(SS/TR)
V(FB)
VO
Figure 28. Operation of SS/TR Pin When Starting
7.3.9 Sequencing
A designer can implement many of the common power-supply sequencing methods using the SS/TR, EN, and
PWRGD pins. Implementation of the sequential method can be by using an open-drain output of the power-onreset pin of another device. Figure 29 illustrates the sequential method using two TPS54561-Q1 devices.
Connecting the power-good signal of the first TPS54561-Q1 device to the EN pin on the second TPS54561-Q1
device enables the second power supply once the primary supply reaches regulation. If needed, a 1-nF ceramic
capacitor on the EN pin of the second power supply provides a 1-ms start-up delay. Figure 30 shows the results
of Figure 29.
TPS54561-Q1
EN
TPS54561-Q1
PWRGD
EN
SS/TR
V(EN)(1)
V(PWRGD)(1)
SS/TR
PWRGD
Copyright © 2016, Texas Instruments Incorporated
VO(1)
VO(2)
Figure 29. Schematic for Sequential Start-Up
Sequence
Figure 30. Sequential Start-Up Using EN and
PWRGD
White space
16
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Feature Description (continued)
TPS54160
TPS54561-Q1
3
EN
V(EN)(1), V(EN)(2)
4
SS/TR
6
PWRGD
VO(1)
TPS54561-Q1
TPS54160
3
EN
4
SS/TR
6
PWRGD
VO(2)
Copyright © 2016, Texas Instruments Incorporated
Figure 31. Schematic for Ratiometric Start-Up
Sequence
Figure 32. Ratiometric Start-Up Using Coupled
SS/TR Pins
Figure 31 shows a method for a ratiometric start-up sequence by connecting the SS/TR pins together. The
regulator outputs ramp up and reach regulation at the same time. When calculating the soft-start capacitor by
using Equation 5, double the pullup current source (I(SS)). Figure 32 shows the results of Figure 31.
TPS54561-Q1
BOOT
EN
VO(1)
SW
SS/TR
PWRGD
R1
TPS54561-Q1
BOOT
EN
VO(2)
SW
SS/TR
R3
FB
R2
PWRGD
R4
Copyright © 2016, Texas Instruments Incorporated
Figure 33. Schematic for Ratiometric and Simultaneous Start-Up Sequence
One can implement ratiometric and simultaneous power-supply sequencing by connecting the resistor network of
R1 and R2 shown in Figure 33 to the output of a power supply that must be tracked, or to another voltage
reference source. Using Equation 7 and Equation 8, one can calculate values for the tracking resistors to initiate
VO(2) slightly before, after, or at the same time as VO(1). Equation 6 is the voltage difference between VO(1) and
VO(2) at 95% of nominal output regulation.
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Feature Description (continued)
The ΔV variable is zero volts for simultaneous sequencing. To minimize the effect of the inherent SS/TR-to-FB
offset (V(SSoffset)) in the soft-start circuit and the offset created by the pullup current source (I(SS)) and tracking
resistors, the equations include V(SSoffset) and I(SS) as variables.
To design a ratiometric start-up in which the VO(2) voltage is slightly greater than the VO(1) voltage when VO(2)
reaches regulation, use a negative number in Equation 6 through Equation 8 for ΔV. Equation 6 results in a
positive number for applications in which VO(2) is slightly lower than VO(1) when VO(2) reaches its regulation.
Because of the requirement for pulling the SS/TR pin below 54 mV before starting after an EN, UVLO, or thermal
shutdown fault, careful selection of the tracking resistors ensures that the device restarts after a fault. Make sure
the calculated R1 value from Equation 7 is greater than the value calculated in Equation 9 to ensure the device
can recover from a fault.
As the SS/TR voltage becomes more than 85% of the nominal reference voltage, V(SSoffset) becomes larger as the
soft-start circuits gradually hand off the regulation reference to the internal voltage reference. The SS/TR pin
voltage must be greater than 1.5 V for a complete handoff to the internal voltage reference as shown in
Figure 23.
DV = VO(1) - VO(2)
(6)
at 95% of nominal output regulation.
VO(2) + DV V(SSoffset)
´
R1 = VO(1) Vref
I (SS)
(7)
Vref ´ R1
R2 =
VO(2) + DV - Vref
(8)
R1 > 2800 ´ VO(1) - 180 ´ DV
(9)
V(EN)
V(EN)
VO(1)
VO(1)
VO(2)
VO(2)
Figure 34. Ratiometric Start-Up With Tracking Resistors –
VO(2) Before VO(1)
18
Figure 35. Ratiometric Start-Up With Tracking Resistors –
VO(2) After VO(1)
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Feature Description (continued)
V(EN)
VO(1)
VO(2)
Figure 36. Simultaneous Start-Up With Tracking Resistors
7.3.10 Constant Switching Frequency and Timing Resistor (RT/CLK Pin)
The switching frequency of the TPS54561-Q1 device is adjustable over a wide range, from 100 kHz to 2500 kHz,
by placing a resistor between the RT/CLK pin and GND pin. The RT/CLK pin voltage is typically 0.5 V and must
have a resistor to ground to set the switching frequency. To determine the timing resistance for a given switching
frequency, use Equation 10 or Equation 11 or the curves in Figure 6 and Figure 7. To reduce the solution size,
one would typically set the switching frequency as high as possible, but consider tradeoffs of the conversion
efficiency, maximum input voltage, and minimum controllable on-time. The minimum controllable on-time is
typically 100 ns, which limits the maximum operating frequency in applications with high input-to-output stepdown ratios. The frequency foldback circuit also limits the maximum switching frequency. The next section talks
about the maximum switching frequency in detail.
101756
RT (kW) =
f sw (kHz)1.008
(10)
f sw (kHz) =
92417
RT (kW)0.991
(11)
7.3.11 Accurate Current-Limit Operation and Maximum Switching Frequency
The TPS54561-Q1 device implements peak-current-mode control, in which the COMP pin voltage controls the
peak current of the high-side MOSFET. A signal proportional to the high-side switch current and the COMP pin
voltage are compared each cycle. When the peak switch current intersects the COMP control voltage, the highside switch turns off. During overcurrent conditions that pull the output voltage low, the error amplifier increases
switch current by driving the COMP pin high. The device clamps the error-amplifier output internally at a level
which sets the switch-current limit. The TPS54561-Q1 device provides an accurate current-limit threshold with a
typical current-limit delay of 60 ns. With smaller inductor values, the delay results in a higher peak inductor
current. Figure 37 shows the relationship between the inductor value and the peak inductor current.
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Feature Description (continued)
Peak Inductor Current
ΔCLpk
Inductor Current (A)
Open-Loop Current Limit
ΔCLpk = (VI / L(O)) ´ td(CL)
td(CL)
t(ON)
Figure 37. Current Limit Delay
To protect the converter in overload conditions at higher switching frequencies and input voltages, the
TPS54561-Q1 device implements frequency foldback. The divisor of the oscillator frequency changes from 1 to
2, 4, and 8 as the FB pin voltage falls from 0.8 V to 0 V. The TPS54561-Q1 device uses digital frequency
foldback to enable synchronization to an external clock during normal start-up and fault conditions. During shortcircuit events, the inductor current may exceed the peak current limit because of the high input voltage and the
minimum controllable on-time. When the shorted load forces the output voltage low, the inductor current
decreases slowly during the switch off-time. The frequency foldback effectively increases the off-time by
increasing the period of the switching cycle, providing more time for the inductor current to ramp down.
With a maximum frequency foldback ratio of 8, there is a maximum frequency at which frequency foldback
protection can still control the inductor current. Equation 12 calculates the maximum switching frequency at
which the inductor current remains under control with VO forced to VO(SC). The selected operating frequency
should not exceed the calculated value.
Equation 13 calculates the maximum switching frequency limitation set by the minimum controllable on-time and
the input-to-output step-down ratio. Setting the switching frequency above this value causes the regulator to skip
switching pulses to achieve the low duty cycle required to regulate the output at maximum input voltage.
f(DIV) æ I (CL) ´ R (dc) + VO(SC) + V(d) ö
´ç
÷
f(SW_ shift) =
t (ON) çè VI - I (CL) ´ rDS(on) + V(d) ÷ø
(12)
f (SW_skip) max =
1
t (ON)
æ I O ´ R (dc) + VO + V(d)
´ç
ç VI - I O ´ r DS(on) + V(d)
è
ö
÷
÷
ø
(13)
where
• f(DIV) is the frequency divisor, which equals (1, 2, 4, or 8)
• t(ON) is the minimum controllable on-time
• I(CL) is the switch current limit
• R(dc) is the inductor resistance
• VO(SC) is the output voltage during output short
• V(d) is the forward voltage drop of the catch diode
• VI is the maximum input voltage
• rDS(on) is the high-side MOSFET on-resistance
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Feature Description (continued)
•
•
IO is the output current
VO is the output voltage
7.3.12 Synchronization to RT/CLK Pin
The RT/CLK pin can receive a frequency synchronization signal from an external system clock. To implement
this synchronization feature, connect a square wave to the RT/CLK pin through either circuit network shown in
Figure 38. The square wave applied to the RT/CLK pin must switch lower than 0.5 V, and higher than 2 V, and
have a pulse duration greater than 15 ns. The synchronization frequency range is 160 kHz to 2300 kHz. The
rising edge of SW synchronizes to the falling edge of the RT/CLK pin signal. The design of the external
synchronization circuit should be such that the default frequency-set resistor connects from the RT/CLK pin to
GND pin when the synchronization signal is off. When using a low-impedance signal source, the connection of
the frequency-set resistor is in parallel with an ac-coupling capacitor to a termination resistor (for example, 300
Ω) as shown in Figure 38. The two resistors in series provide the default frequency-setting resistance when the
signal source turns off. The sum of the resistance should set the switching frequency close to the external CLK
frequency. TI recommends ac-coupling the synchronization signal through a 10-pF ceramic capacitor to the
RT/CLK pin.
The first time the input pulls the RT/CLK pin above the PLL high threshold, which has a 2-V maximum value, the
TPS54561-Q1 switches from the RT resistor free-running frequency mode to the PLL synchronized mode.
Removal of the internal 0.5-V voltage source results, and the RT/CLK pin becomes high-impedance as the PLL
starts to lock onto the external signal. The switching frequency can be higher or lower than the frequency set with
the RT/CLK resistor. The device transitions from the resistor-programmed mode to the PLL mode and locks onto
the external clock frequency within 78 µs. During the transition from the PLL mode to the resistor-programmed
mode, the switching frequency falls to 150 kHz and then increases or decreases to the resistor-programmed
frequency on re-application of the 0.5-V bias voltage to the RT/CLK resistor.
The switching frequency divisor goes from 8 to 4, 2, and 1 as the FB pin voltage ramps from 0 V to 0.8 V. The
device implements a digital-frequency foldback to enable synchronization to an external clock during normal
start-up and fault conditions. Figure 39, Figure 40, and Figure 41 show the device synchronized to an external
system clock in continuous-conduction mode (CCM), discontinuous-conduction (DCM) and pulse-skipping mode.
SPACER
TPS54561-Q1
TPS54561-Q1
RT/CLK
RT
Clock
Source
PLL
RT/CLK
PLL
Hi-Z
Clock
Source
RT
Copyright © 2017, Texas Instruments Incorporated
Figure 38. Synchronizing to a System Clock
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Feature Description (continued)
V(SW)
V(SW)
External
Clock
External
Clock
I(L)
I(L)
Figure 39. Plot of Synchronizing in CCM
Figure 40. Plot of Synchronizing in DCM
V(SW)
External
Clock
I(L)
Figure 41. Plot of Synchronizing in Pulse-Skipping Mode
7.3.13 Power Good (PWRGD Pin)
The PWRGD pin is an open-drain output. When the FB pin is between 93% and 106% of the internal voltage
reference, TPS54561-Q1 device de-asserts the PWRGD pin and this pin floats. TI recommends a pullup resistor
of 1 kΩ to a voltage source that is 5.5 V or less. A higher pullup resistance reduces the amount of current drawn
from the pullup voltage source when the PWRGD pin is low. A lower pullup resistance reduces the switching
noise seen on the PWRGD signal. PWRGD is in a defined state once the VDD pin voltage is greater than 2 V, but
with reduced current sinking capability. PWRGD achieves full current-sinking capability as the VDD pin voltage
approaches 3 V.
TPS54561-Q1 device pulls the PWRGD pin low when the FB pin voltage is lower than 90% or greater than 108%
of the nominal internal reference voltage. Also, the TPS54561-Q1 device pulls the PWRGD pin low after an EN,
UVLO, or thermal shutdown fault.
22
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Feature Description (continued)
7.3.14 Overvoltage Protection
The TPS54561-Q1 incorporates an output overvoltage-protection (OVP) circuit to minimize voltage overshoot
when recovering from output fault conditions or strong unload transients in designs with low output capacitance.
For example, on an overload event of the power-supply output, the error amplifier compares the actual output
voltage to the internal reference voltage. If the FB pin voltage is lower than the internal reference voltage for a
considerable time, the output of the error amplifier increases to a maximum voltage corresponding to the peak
current-limit threshold. On removal of the overload condition, the regulator output rises and the error amplifier
output transitions to the normal operating level. In some applications, the power-supply output voltage can
increase faster than the response of the error amplifier output, resulting in an output overshoot.
The OVP feature minimizes output overshoot when using a low-value output capacitor by comparing the FB pin
voltage to the rising OVP threshold, which is nominally 108% of the internal voltage reference. If the FB pin
voltage is greater than the rising OVP threshold, immediately disabling the high-side MOSFET minimizes output
overshoot. When the FB voltage drops below the falling OVP threshold, which is nominally 106% of the internal
voltage reference, the high-side MOSFET resumes normal operation.
7.3.15 Thermal Shutdown
The TPS54561-Q1 provides an internal thermal shutdown to protect the device when the junction temperature
exceeds 176°C. The high-side MOSFET stops switching when the junction temperature exceeds the thermal trip
threshold. Once the silicon temperature falls below 164°C, the device reinitiates the power-up sequence
controlled by the SS/TR pin.
7.3.16 Small-Signal Model for Loop Response
Figure 42 shows a simplified model for the TPS54561-Q1 control loop, with which the designer can simulate to
check the frequency response and dynamic load response. The error amplifier is a transconductance amplifier
with a gm(ea) of 350 µS. A user can model the error amplifier using an ideal voltage controlled current source. The
resistor, R(OEA), and capacitor, C(OEA), model the open-loop gain and frequency response of the amplifier. The
1-mV ac voltage source between nodes a and b effectively breaks the control loop for the frequency-response
measurements. Plotting c/b provides the small-signal response of the frequency compensation. Plotting a/b
provides the small-signal response of the overall loop. To evaluate the dynamic loop response, replace the load
resistor, R(L), with a current source that has the appropriate load-step amplitude and step rate in a time-domain
analysis. This equivalent model is only valid for continuous-conduction-mode (CCM) operation.
SW
VO
Power Stage
gm(ps) 17 S
a
b
R(ESR)
R(HS)
R(L)
COMP
c
gm(ea)
350 µS
R(COMP)
C(OEA)
C(POLE)
0.8 V
FB
R(OEA)
C(O)
R(LS)
C(ZERO)
Copyright © 2016, Texas Instruments Incorporated
Figure 42. Small-Signal Model for Loop Response
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Feature Description (continued)
7.3.17 Simplified Small-Signal Model for Peak-Current-Mode Control
Figure 43 describes a simple small-signal model for use in design of the frequency compensation. A voltagecontrolled current source (duty-cycle modulator) supplying current to the output capacitor and load resistor can
approximate the TPS54561-Q1 power stage. Equation 14 shows the control-to-output transfer function, which
consists of a dc gain, one dominant pole, and one ESR zero. The quotient of the change in switch current and
the change in COMP pin voltage (node c in Figure 42) is the power stage transconductance, gm(ps). The gm(ps) for
the TPS54561-Q1 device is 17 S. The low-frequency gain of the power stage is the product of the
transconductance and the load resistance as shown in Equation 15.
As the load current increases or decreases, the low-frequency gain decreases or increases, respectively. This
variation with the load may seem problematic at first glance, but fortunately the dominant pole moves with the
load current (see Equation 16). The dashed line in the right half of Figure 43 highlights the combined effect. As
the load current decreases, the gain increases and the pole frequency lowers, keeping the 0-dB crossover
frequency the same with varying load conditions. The type of output capacitor chosen determines whether the
ESR zero has a profound effect on the frequency compensation design. Using high-ESR aluminum electrolytic
capacitors may reduce the number of frequency compensation components needed to stabilize the overall loop,
because the phase margin increases by the ESR zero of the output capacitor (see Equation 17).
VO
A(dc)
V(c)
R(ESR)
f(P)
R(L)
gm(ea)
C(O)
f(Z)
Copyright © 2017, Texas Instruments Incorporated
Figure 43. Simplified Small-Signal Model and Frequency Response for Peak-Current-Mode Control
24
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Feature Description (continued)
æ
s
ç1 +
ç
p
´
2
f (Z)
VO
= A (dc) ´ è
V(C)
æ
s
ç1 +
ç
2p ´ f (P)
è
A (dc) = gm(ps) ´ R (L)
ö
÷
÷
ø
ö
÷
÷
ø
(14)
(15)
1
f (P) =
C(O) ´ R (L) ´ 2p
f (Z) =
(16)
1
C(O) ´ R(ESR) ´ 2p
(17)
7.3.18 Small-Signal Model for Frequency Compensation
The TPS54561-Q1 uses a transconductance amplifier for the error amplifier and supports three of the commonlyused frequency-compensation circuits. Figure 44 shows compensation circuits of Type 2A, Type 2B, and Type 1.
Implementation of Type 2 circuits is typically in high-bandwidth power-supply designs using low-ESR output
capacitors. The Type 1 circuit is good for the power-supply designs using high-ESR aluminum electrolytic or
tantalum capacitors. Equation 18 and Equation 19 relate the frequency response of the amplifier to the smallsignal model in Figure 44. Modeling of the open-loop gain and bandwidth uses R(OEA) and C(OEA), as shown in
Figure 44. See the application section for a design example using a Type 2A network with a low-ESR output
capacitor.
This data sheet includes Equation 18 through Equation 27 as a reference. An alternative is to use WEBENCH
software tools to create a design based on the power-supply requirements.
VO
a
b
R(HS)
FB
Type 2B
Type 2A
gm(ea)
Type 1
COMP
c
Vref
R(COMP)
R(COMP)
R(LS)
R(OEA)
C(POLE)
C(POLE)
C(OEA)
C(ZERO)
C(ZERO)
Copyright © 2016, Texas Instruments Incorporated
Figure 44. Types of Frequency Compensation
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Feature Description (continued)
A(OL)
P1
A0
Z1
A1
P2
BW
Figure 45. Frequency Response of the Type 2A and Type 2B Frequency Compensation
R (OEA) =
C(OEA) =
A (OL)
g m(ea)
(18)
g m(ea)
2p ´ BW (Hz)
(19)
æ
ö
s
ç1 +
÷
ç
2p ´ f (Z1) ÷ø
V(c)
è
= A0 ´
V(b)
æ
ö æ
s
s
ç1 +
÷ ´ ç1 +
ç
÷
ç
2
f
2
f (P2)
p
´
p
´
(P1) ø è
è
R (LS)
A0 = g m(ea) ´ R (OEA) ´
R (HS) + R (LS)
A1 = gm(ea) ´ R (OEA) P R (COMP) ´
P1 =
Z1 =
P2 =
26
(20)
(21)
R (LS)
R (HS) + R (LS)
(22)
1
2p´ R (OEA) ´ C(ZERO)
(23)
1
2p ´ R (COMP) ´ C(ZERO)
(24)
1
(
2p´ R (OEA) P R (COMP) ´ C(POLE) + C(OEA)
1
P2 =
2p´ R (OEA) P R (COMP) ´ C(OEA)
P2 =
ö
÷
÷
ø
(
Type 2A
(25)
Type 2B
(26)
1
2p ´ R (OEA) ´ C(POLE) + C(OEA)
)
)
Type 1
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7.4 Device Functional Modes
7.4.1 Operation With VI = < 4.5 V (Minimum VDD)
TI recommends operating the TPS54561-Q1 device with input voltages above 4.5 V. The typical VDD UVLO
threshold is 4.3 V, and the device may operate at input voltages down to the UVLO voltage. At input voltages
below the actual UVLO voltage, the device does not switch. If an external resistor divider pulls the EN pin up to
VDD or EN pin is floating, when VDD passes the UVLO threshold the device becomes active. Switching begins,
and the soft-start sequence initiates. The TPS54561-Q1 device starts at the soft-start time determined by the
external capacitance on the SS/TR pin.
7.4.2 Operation With EN Control
The enable threshold voltage is 1.2 V typical. With EN held below that voltage, the device shuts down and
switching stops even if VDD is above its UVLO threshold. The IC quiescent current decreases in this state. After
increasing the EN pin voltage above the threshold while VDD is above its UVLO threshold, the device becomes
active. Switching resumes and the soft-start sequence begins. The TPS54561-Q1 device starts at the soft-start
time determined by the external capacitance at the SS/TR pin.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TPS54561-Q1 device is a 60-V, 5-A, step-down regulator with an integrated high-side MOSFET. This device
typically converts a higher dc voltage to a lower dc voltage with a maximum available output current of 5 A.
Example applications are: 12-V, 24-V and 48-V industrial, automotive and communication power systems. Use
the following design procedure to select component values for the TPS54561-Q1 device. This procedure
illustrates the design of a high-frequency switching regulator using ceramic output capacitors. The Excel™
spreadsheet (SLVC452) located on the product page can help on all calculations. Alternatively, use the
WEBENCH software to generate a complete design. The WEBENCH software uses an iterative design
procedure and accesses a comprehensive database of components when generating a design. This section
presents a simplified discussion of the design process.
8.2 Typical Application
2
GND
1
1
7 V to 60 V
VI
TP1
+
DNP
C10
2.2µF
C3
2.2µF
C1
2.2µF
C2
2.2µF
PWRGD
PWRGD PULLUP
R8
2
J2
C11
U1
TP2
2
GND
3
R1
442k
5
2
1
GND
SS/TR
4
R3
243k
J4
C13
0.01µF
GND
R4
16.9k
EN
BOOT
RT/CLK
SW
SS/TR
FB
COMP
GND
PAD
10
TP10 1.00k
TP9
C4
1
9
6
0.1µF
FB
8
TPS54561-Q1
C8
47pF
GND
C5
4700pF
R2
90.9k
2
1
EN
GND
7
PWRGD
VDD
L1
TP5
1
D1
PDS760-13
1
C6
47µF
C7
47µF
+
C12
C9 DNP
47µF
2
GND
2 SS/TR
1
SS/TR
GND
R7
49.9
TP4
TP8
1
VO
2
GND
J1
GND
2
TP3
TP7
TP6
3
J3
5V@5A
7447798720
7.2µH
R5
53.6k
J5
GND
GND
FB
R6
10.2k
GND
Copyright © 2016, Texas Instruments Incorporated
Figure 46. 5-V Output TPS54561-Q1 Design Example
8.2.1 Design Requirements
This guide illustrates the design of a high-frequency switching regulator using ceramic output capacitors. The
designer must know a few parameters in order to start the design process. Determination of these requirements
is typically at the system level. This example design uses the following known parameters:
28
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Typical Application (continued)
DESIGN PARAMETER
EXAMPLE VALUE
Output voltage (VO)
5V
Transient response, 1.25-A to 3.75-A load step
ΔVO = ±4 %
Maximum output current (IO)
5A
Input voltage (VI)
12 V nominal, 7 V to 60 V
Output voltage ripple (VO(RIPPLE))
0.5% of VO
Start input voltage (rising VI)
6.5 V
Stop input voltage (falling VI)
5V
8.2.2 Detailed Design Procedure
8.2.2.1 Custom Design with WEBENCH® Tools
Click here to create a custom design using the TPS54561-Q1 device with the WEBENCH® Power Designer.
1. Start by entering your VIN, VOUT, and IOUT requirements.
2. Optimize your design for key parameters like efficiency, footprint and cost using the optimizer dial and
compare this design with other possible solutions from Texas Instruments.
3. The WEBENCH Power Designer provides you with a customized schematic along with a list of materials with
real time pricing and component availability.
4. In most cases, you will also be able to:
– Run electrical simulations to see important waveforms and circuit performance
– Run thermal simulations to understand the thermal performance of your board
– Export your customized schematic and layout into popular CAD formats
– Print PDF reports for the design, and share your design with colleagues
5. Get more information about WEBENCH tools at www.ti.com/WEBENCH.
8.2.2.2 Selecting the Switching Frequency
The first step is to choose a switching frequency for the regulator. Typically, the designer uses the highest
switching frequency possible because this produces the smallest solution size. High switching frequency allows
for lower-value inductors and smaller output capacitors compared to a power supply that switches at a lower
frequency. Several factors including the minimum controllable on-time of the internal power switch, the input
voltage, the output voltage, and the frequency-foldback protection limit the switching frequency that the designer
can select.
Use Equation 12 and Equation 13 to calculate the upper limit of the switching frequency for the regulator.
Choose the lower-value result from the two equations. Switching frequencies higher than these values result in
pulse-skipping or the lack of overcurrent protection during a short circuit.
The typical minimum controllable on-time, t(ON), is 100 ns for the TPS54561-Q1 device. For this example, the
output voltage is 5 V and the maximum input voltage is 60 V, which allows for a maximum switch frequency up to
955 kHz to avoid pulse skipping from Equation 28. To ensure overcurrent runaway is not a concern during short
circuits, use Equation 29 to determine the maximum switching frequency for frequency foldback protection. With
a maximum input voltage of 60 V, assuming a diode voltage of 0.7 V, inductor resistance of 11 mΩ, switch
resistance of 87 mΩ, a current limit value of 6 A, and short-circuit output voltage of 0.1 V, the maximum switching
frequency is 1151 kHz.
For this design, choose a lower switching frequency of 400 kHz to operate comfortably below the calculated
maximums. To determine the timing resistance for a given switching frequency, use Equation 10, or the curve in
Figure 6, or the curve in Figure 7. Resistor R3 sets the switching frequency shown in Figure 46. For 400-kHz
operation, the closest standard value resistor is 243 kΩ.
f (SW_skip)max =
æ 5 A ´ 11 mW + 5 V + 0.7 V ö
1
´ç
÷ = 955 kHz
100 ns è 60 V - 5 A ´ 87 mW + 0.7 V ø
(28)
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f (SW_shift) =
RT (kW) =
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æ 6 A ´ 11 mW + 0.1 V + 0.7 V ö
8
´ç
÷ = 1151 kHz
100 ns è 60 V - 6 A ´ 87 mW + 0.7 V ø
101756
400 (kHz)1.008
(29)
= 242 kW
(30)
8.2.2.3 Output Inductor Selection (L(O))
To calculate the minimum value of the output inductor, use Equation 31.
k(IND) is a ratio that represents the amount of inductor ripple current relative to the maximum output current. The
output capacitor filters the inductor ripple current. Therefore, choosing high inductor ripple currents impacts the
selection of the output capacitor, because the output capacitor must have a ripple current rating equal to or
greater than the inductor ripple current. In general, the inductor ripple value is at the discretion of the designer.
However, the designer may use the following guidelines.
For designs using low-ESR output capacitors such as ceramics, a value as high as k(IND) = 0.3 may be desirable.
When using higher-ESR output capacitors, k(IND) = 0.2 yields better results. Because the inductor ripple current is
part of the current-mode PWM control system, the inductor ripple current should always be greater than 150 mA
for stable PWM operation. In a wide-input voltage regulator, choosing a relatively large inductor ripple current is
best to provide sufficient ripple current with the input voltage at the minimum.
For this design example, k(IND) = 0.3 and the calculated inductor value is 7.6 µH. The nearest standard value is
7.2 µH. It is important not to exceed both the rms current and saturation-current ratings of the inductor.
Equation 33 and Equation 34 calculate the rms and peak inductor current. For this design, the rms inductor
current is 5.021 A and the peak inductor current is 5.817 A. The chosen inductor has an rms current rating of 6 A
and a saturation current rating of 7.9 A.
As the equation set demonstrates, lowering ripple currents reduces the output voltage ripple of the regulator but
requires a larger value of inductance. Selecting higher ripple currents increases the output-voltage ripple of the
regulator but allows for a lower inductance value.
The current flowing through the inductor is the inductor ripple current plus the output current. During power up,
faults, or transient load conditions, the inductor current can increase above the peak inductor current level
calculated previously. In transient conditions, the inductor current can increase up to the switch-current limit of
the device. For this reason, the most-conservative design approach is to choose an inductor with a saturation
current rating equal to or greater than the switch-current limit of the TPS54561-Q1 device, which is nominally 7.5
A.
æ VI max - VO
L (O)min = ç
ç
è I O ´ K (IND)
ö æ
VO
÷´ ç
÷ ç VI max ´ f (SW )
ø è
ö æ 60 V - 5 V ö æ
ö
5V
÷=
´
= 7.6 mH
÷ èç 5 A ´ 0.3 ø÷ èç 60 V ´ 400 kHz ø÷
ø
(31)
spacer
I(RIPPLE) =
(
VO ´ VI max - VO
)=
VI max ´ L (O) ´ f (SW )
5 V ´ (60 V - 5 V )
60 V ´ 7.2 mH ´ 400 kHz
= 1.591 A
(32)
spacer
I(L)RMS =
(IO )
2
(
) ÷ö
æ
1 ç VO ´ VI max - VO
+
´
12 ç VI max ´ L (O) ´ f (SW )
è
÷
ø
2
2
=
(5 A )
2
1 æ 5 V ´ (60 V - 5 V ) ö
+
´ç
÷ = 5.021 A
12 çè 60 V ´ 7.2 mH ´ 400 kHz ÷ø
(33)
spacer
I(L) peak = I O +
30
I(RIPPLE)
2
= 5.021 A +
1.591 A
= 5.817 A
2
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8.2.2.4 Output Capacitor
There are three primary considerations for selecting the value of the output capacitor. The output capacitor
determines the modulator pole, the output voltage ripple, and the regulator response to a large change in load
current. It is necessary to select the output capacitance based on the most-stringent of these three criteria.
The desired response to a large change in the load current is the first criterion. The output capacitor must supply
the increased load current until the regulator responds to the load step. The regulator does not respond
immediately to a large, fast increase in the load current such as transitioning from no load to a full load. The
regulator usually needs two or more clock cycles for the control loop to sense the change in output voltage and
adjust the peak switch current in response to the higher load. The output capacitance must be large enough to
supply the difference in current for two clock cycles to maintain the output voltage within the specified range.
Equation 35 shows the minimum output capacitance necessary, where ΔIO is the change in output current, f(sw) is
the regulator switching frequency, and ΔVO is the allowable change in the output voltage. For this example, the
transient load response specification is 4% change in VO for a load step from 1.25 A to 3.75 A. Therefore, ΔIO is
3.75 A – 1.25 A = 2.5 A, and ΔVO = 4% × 5 V = 0.2 V. Using these numbers gives a minimum capacitance of
62.5 µF. This value does not take the ESR of the output capacitor into account in the output voltage change. For
ceramic capacitors, the ESR is usually small enough to ignore. Aluminum electrolytic and tantalum capacitors
have higher ESR, and load-step calculations must include the ESR term.
Sizing of the output capacitor must be such as to absorb energy stored in the inductor when transitioning from a
high to low load current. The catch diode of the regulator cannot sink current, so energy stored in the inductor
can produce an output voltage overshoot when the load current rapidly decreases. Figure 51 shows a typical
load-step response. The excess energy absorbed in the output capacitor increases the voltage on the capacitor.
Sizing of the capacitor must be such as to maintain the desired output voltage during these transient periods.
Equation 36 calculates the minimum capacitance required to keep the output voltage overshoot to a desired
value, where L(O) is the value of the inductor, IOH is the output current under heavy load, IOL is the output under
light load, VP is the peak output voltage, and V(int) is the initial voltage. For this example, the worst-case load step
is from 3.75 A to 1.25 A. The output voltage increases during this load transition, and the stated maximum in our
specification is 4% of the output voltage. This makes V(P) = 1.04 × 5 V = 5.2 V. V(int) is the initial capacitor voltage
which is the nominal output voltage of 5 V. Using these numbers in Equation 36 yields a minimum capacitance of
44.1 µF.
Equation 37 calculates the minimum output capacitance needed to meet the output-voltage ripple specification,
where f(SW) is the switching frequency, VO(RIPPLE) is the maximum allowable output voltage ripple, and IO(RIPPLE) is
the inductor ripple current. Equation 37 yields 19.9 µF.
Equation 38 calculates the maximum ESR an output capacitor can have to meet the output voltage ripple
specification. Equation 38 indicates the ESR should be less than 15.7 mΩ.
The most stringent criterion for the output capacitor is 62.5 µF, required to maintain the output voltage within
regulation tolerance during a load transient.
Capacitance de-ratings for aging, temperature, and dc bias increase this minimum value. For this example, the
selection is three 47-µF, 10-V ceramic capacitors with 5 mΩ of ESR. The derated capacitance is 87.4 µF, well
above the minimum required capacitance of 62.5 µF.
Capacitors generally have a maximum ripple-current rating. Filtering a ripple current equal to or below that
maximum ripple current does not degrade capacitor reliability. Some capacitor data sheets specify the rootmean-square (rms) value of the maximum ripple current. Use Equation 39 to calculate the rms ripple current that
the output capacitor must support. For this example, Equation 39 yields 459 mA.
2 ´ DI O
2 ´ 2.5 A
C(O) >
=
= 62.5 μF
f (SW ) ´ DVO 400 kHz ´ 0.2 V
(35)
2
2ö
æ
ç I OH - I OL ÷
3.75 A 2 - 1.25 A 2
ø = 7.2 mH ´
= 44.1 mF
C(O) > L(O) ´ è
2
2ö
2
2
æ
5.2
V
5
V
ç V(P) - V(int) ÷
è
ø
( ) ( )
( ) (
)
(
(
)
)
(36)
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1
1
1
´
=
´
8 ´ f (SW ) æ VO(RIPPLE) ö 8 ´ 400 kHz
ç
÷
ç I O(RIPPLE) ÷
è
ø
VO(RIPPLE)
25 mV
R (ESR) <
=
= 15.7 mW
I O(RIPPLE)
1.591 A
C(O) >
I(CO)RMS =
(
VO ´ VI min - VO
)
12 ´ VI min ´ L(O) ´ f(SW )
1
æ 25 mV ö
ç
÷
è 1.591 A ø
= 19.9 mF
(37)
(38)
5 V ´ (60 V - 5 V )
=
12 ´ 60 V ´ 7.2 mH ´ 400 kHz
= 459 mA
(39)
8.2.2.5 Catch Diode
The TPS54561-Q1 device requires an external catch diode between the SW pin and GND. The selected diode
must have a reverse voltage rating equal to or greater than maximum input voltage. The peak current rating of
the diode must be greater than the maximum inductor current. Schottky diodes are typically a good choice for the
catch diode because of the low forward voltage of these diodes. The lower the forward voltage of the diode, the
higher the efficiency of the regulator.
Typically, diodes with higher voltage and current ratings have higher forward voltages. A diode with a minimum of
60-V reverse voltage is preferable, to allow input voltage transients up to the rated voltage of the TPS54561-Q1
device.
For the example design, select the Schottky diode for its lower forward voltage and good thermal characteristics
compared to smaller devices. The typical forward voltage of the diode is 0.52 V at 5 A.
One must select the diode with an appropriate power rating. The diode conducts the output current during the
off-time of the internal power switch. The off-time of the internal switch is a function of the maximum input
voltage, the output voltage, and the switching frequency. Multiplying the output current during the off-time with
the forward voltage of the diode can calculate the instantaneous conduction losses of the diode. At higher
switching frequencies, take the ac losses of the diode into account. The ac losses of the diode are because of
the charging and discharging of the junction capacitance, and also of reverse-recovery charge. Use Equation 40
to calculate the total power dissipation, including conduction losses and ac losses of the diode.
The selected diode has a junction capacitance of 180 pF. Using Equation 40 with the nominal input voltage of
12 V, the total loss in the diode is 1.65 W.
If the power supply spends a significant amount of time at light load currents or in sleep mode, consider using a
diode which has a low leakage current and slightly higher forward voltage drop.
2
P(D)
(VI - VO ) ´ IO ´ V(d) + C( j) ´ f(SW ) ´ (VI + V(d) )
=
VI
2
(12 V - 5 V ) ´ 5 A ´ 0.52 V
12 V
=
2
+
180 pF ´ 400 kHz ´ (12 V + 0.52 V )
2
= 1.65 W
(40)
8.2.2.6 Input Capacitor
The TPS54561-Q1 device requires a high-quality ceramic type X5R or X7R input decoupling capacitor with at
least 3 µF of effective capacitance. Some applications benefit from additional bulk capacitance. The effective
capacitance includes any loss of capacitance because of dc bias effects. The voltage rating of the input capacitor
must be greater than the maximum input voltage. The capacitor must also have a ripple-current rating greater
than the maximum input current ripple of the TPS54561-Q1 device. Use Equation 41 to calculate the input ripple
current.
The value of a ceramic capacitor varies significantly with temperature and the dc bias applied to the capacitor.
Selecting a dielectric material that is more stable over temperature can minimize the capacitance variations
because of temperature. The usual selection for capacitors in a switching regulator is X5R or X7R ceramic
dielectric, because they have a high capacitance-to-volume ratio and are fairly stable over temperature. The
input capacitor selection must also consider the dc bias. The effective value of a capacitor decreases as the dc
bias across a capacitor increases.
32
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This example design requires a ceramic capacitor with at least a 60-V voltage rating to support the maximum
input voltage. Common standard ceramic capacitor voltage ratings include 4 V, 6.3 V, 10 V, 16 V, 25 V, 50 V or
100 V. For this example, use four 2.2-µF, 100-V capacitors in parallel.
The input capacitance value determines the input ripple voltage of the regulator. Use Equation 42 to calculate the
input voltage ripple. Using the design example values, IO = 5 A, C(I) = 8.8 µF, f(sw) = 400 kHz, yields an input
voltage ripple of 355 mV and an rms input ripple current of 2.26 A.
I(CI) RMS = I O ´
DVI =
I O ´ 0.25
C(I) ´ f (SW )
æ VI min - VO
VO
´ç
VI min çè VI min
=
ö
÷ = 5 A´
÷
ø
5 V æ7 V- 5 V ö
´ç
÷ = 2.26 A
7V è 7V
ø
5 A ´ 0.25
= 355 mV
8.8 mF ´ 400 kHz
(41)
(42)
8.2.2.7 Soft-Start Capacitor
The soft-start capacitor determines the minimum amount of time for the output voltage to reach its nominal
programmed value during power up. This is useful if a load requires a controlled voltage slew rate. Adjustable
soft-start is also useful if the output capacitance is large and would require large amounts of current to charge
the capacitor quickly to the output-voltage level. The large currents necessary to charge the output capacitor may
make the TPS54561-Q1 device reach the current limit, or the excessive current draw from the input power supply
may cause the input voltage rail to sag. Limiting the output-voltage slew rate solves both of these problems.
The soft-start time must be long enough to allow the regulator to charge the output capacitor up to the output
voltage without drawing excessive current. Use Equation 43 to find the minimum soft-start time, t(SS), necessary
to charge the output capacitor, C(O), from 10% to 90% of the output voltage, VO, with an typical soft-start current
of I(SS). In the example, to charge the effective output capacitance of 87.4 µF up to 5 V with an average current of
1 A requires a 0.3-ms soft-start time.
After selecting the soft-start time, calculate the soft-start capacitor value by using Equation 5. For the example
circuit, the soft-start time is not too critical, because the output capacitor value is 3 × 47 µF, which does not
require much current to charge to 5 V. The example circuit has the soft-start time set to an arbitrary value of
3.5 ms, which requires a 9.3-nF soft-start capacitor, as calculated by Equation 44. For this design, use the nextlarger standard value of 10 nF.
C(O) ´ VO ´ 0.8
t (SS) >
I(SS)
(43)
C13 =
t (SS) (ms) ´ I(SS) (mA)
Vref (V) ´ 0.8
=
3.5 ms ´ 1.7 mA
= 9.3 nF
0.8 V ´ 0.8
(44)
8.2.2.8 Bootstrap Capacitor Selection
The TPS54561-Q1 device requires a 0.1-µF ceramic capacitor connected between the BOOT and SW pins for
proper operation. The recommendation is a ceramic capacitor with X5R or better grade dielectric. The capacitor
should have a 10-V or higher voltage rating.
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8.2.2.9 Undervoltage Lockout Set Point
Using an external voltage divider on the EN pin of the TPS54561-Q1 device can adjust the undervoltage lockout
(UVLO). The UVLO has two thresholds, one for power up when the input voltage is rising and the other for power
down when the input voltage is falling. For the example design, the TPS54561-Q1 device should turn on and
start switching once the input voltage increases above 6.5 V (UVLO start). After the regulator starts switching, it
should continue to do so until the input voltage falls below 5 V (UVLO stop).
A resistor divider consisting of R(UVLO1) and R(UVLO2) between VI and ground, and connected to the EN pin, can
set programmable UVLO threshold voltage. Equation 3 and Equation 4 calculate the resistance values
necessary. For the example application, a 442-kΩ resistor between VI and EN (R1) and a 90.9-kΩ resistor
between EN and ground (R2) are required to produce the 6.5-V start and 5-V stop voltages.
V(START) - V(STOP) 6.5 V - 5 V
R1 =
=
= 441.18 kW
I(HYS)
3.4 mA
(45)
R2 =
V(EN) th
V(START) - V(EN) th
R (UVLO1)
=
+ I(1)
1.2 V
= 90.97 kW
6.5 V - 1.2 V
+ 1.2 mA
442 kW
(46)
8.2.2.10 Output Voltage and Feedback Resistor Selection
The voltage divider of R5 and R6 sets the output voltage. For the example design, select 10.2 kΩ for R6. Use
Equation 2 to calculate R5 as 53.55 kΩ. The nearest standard 1% resistor is 53.6 kΩ. Because of the input
current of the FB pin, the current flowing through the feedback network should be greater than 1 µA to maintain
the output voltage accuracy. A value for R6 of less than 800 kΩ satisfies this requirement. Choosing higher
resistor values decreases quiescent current and improves efficiency at low output currents but may also
introduce noise immunity problems.
æ V - 0.8 V ö
æ 5 V - 0.8 V ö
R5 = R6 ´ ç O
÷ = 10.2 kW ´ ç
÷ = 53.55 kW
è 0.8 V ø
è 0.8 V ø
(47)
8.2.2.11 Compensation
There are several methods to design compensation for dc-dc regulators. The method presented here is easy to
calculate and ignores the effects of the slope compensation that is internal to the device. Ignoring the slope
compensation causes the actual crossover frequency to be lower than the crossover frequency used in the
calculations. This method assumes the crossover frequency is between the modulator pole and the ESR zero
and the ESR zero is at least 10 times greater the modulator pole.
To get started, calculate the modulator pole, f(P,mod), and the ESR zero, f(Z,mod) using Equation 48 and
Equation 49. For output capacitance C(O), use a derated value of 87.4 µF. Use equations Equation 50 and
Equation 51 to estimate a starting point for the crossover frequency, f(CO). For the example design, f(P,mod) is 1821
Hz and f(Z,mod) is 1090 kHz. Equation 50 is the geometric mean of the modulator pole and the ESR zero, and
Equation 51 is the geometric mean of modulator pole and half of the switching frequency. Equation 50 yields
44.6 kHz and Equation 51 gives 19.1 kHz. Use the geometric mean value of Equation 50 and Equation 51 for an
initial crossover frequency which is 29.2 kHz. For this example, the target crossover frequency is 30 kHz for an
improved transient response.
Next, calculate the compensation components. Use of a resistor in series with a capacitor creates a
compensating zero. A capacitor in parallel with these two components forms the compensating pole.
I O max
5A
f (P,mod) =
=
= 1821 Hz
2p ´ VO ´ C(O) 2p ´ 5 V ´ 87.4 mF
(48)
34
f (Z,mod) =
1
1
=
= 1090 kHz
2p ´ R (ESR) ´ C(O) 2p ´ 1.67 mW ´ 87.4 mF
(49)
f (CO1) =
f (P,mod) ´ f (Z,mod) = 1821 Hz ´ 1090 kHz = 44.6 kHz
(50)
f (CO2) =
f (P,mod) ´
f (SW )
2
= 1821 Hz ´
400 kHz
= 19.1 kHz
2
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To determine the compensation resistor, R4, use Equation 52. Assume the power stage transconductance,
gm(ps), is 17 S. The output voltage VO, reference voltage Vref, and amplifier transconductance gm(ea), are 5 V,
0.8 V and 350 µS, respectively. Calculated the value for R4 as 16.84 kΩ, and then select a standard value of
16.9 kΩ. Use Equation 53 to set the compensation zero to the modulator pole frequency. Equation 53 yields
5172 pF for compensating capacitor C5. The selection for this design is 4700 pF.
ö æ 2p ´ 29.2 kHz ´ 87.4 mF ö æ
æ 2p ´ f (CO) ´ C(O) ö æ
ö
VO
5V
÷=ç
´ç
R4 = ç
÷´ ç
÷
÷ = 16.84 kW
ç
÷ ç Vref ´ gm(ea) ÷ è
gm(ps)
17 S
ø è 0.8 V ´ 350 mS ø
è
ø è
ø
(52)
C5 =
1
1
=
= 5172 pF
2p ´ R4 ´ f (P,mod) 2p ´ 16.9 kW ´ 1821 Hz
(53)
If desired, implement a compensation pole by adding capacitor C8 in parallel with the series combination of R4
and C5. Use the larger value calculated from Equation 54 and Equation 55 for C8 to set the compensation pole.
The selected value of C8 is 47 pF for this example design.
C(O) ´ R (ESR) 87.4 mF ´ 1.67 mW
=
= 8.64 pF
C8 =
R4
16.9 kW
(54)
1
1
C8 =
=
= 47.1 pF
p´ R4 ´ f (SW ) p´ 16.9 kW ´ 400kHz
(55)
8.2.2.12 Discontinuous Conduction Mode and Eco-mode Boundary
With an input voltage of 12 V, the example design enters discontinuous-conduction mode when the output
current is less than 408 mA. The power supply enters Eco-mode when the output current is lower than 25.3 mA.
The input current draw is 257 µA with no load.
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8.2.2.13 Power Dissipation Estimate
The following formulas show how to estimate the TPS54561-Q1 device power dissipation under continuous
conduction mode (CCM) operation. These equations are not suitable if the device operates in discontinuous
conduction mode (DCM).
The power dissipation of the IC includes conduction loss (P(COND)), switching loss (P(SW)), gate drive loss (P(G))
and supply current loss (P(Q)). Example calculations are shown with the 12-V nominal input voltage of the
example design.
1. Conduction loss
æV ö
2
æ 5V ö
P(COND) = I O ´ rDS(on) ´ ç O ÷ = 5 A 2 ´ 87 mW ´ ç
÷ = 0.906 W
ç VI ÷
è 12 V ø
è
ø
( )
where
•
•
•
•
IO is the output current (A)
rDS(on) is the on-resistance of the high-side MOSFET (Ω)
VO is the output voltage (V)
VI is the input voltage (V)
(56)
2. Switching loss
P(SW ) = VI ´ f (SW ) ´ I O ´ tr = 12 V ´ 400 kHz ´ 5 A ´ 4.9 ns = 0.118 W
where
•
•
f(SW) is the switching frequency (Hz)
tr is the SW pin voltage rise time, estimated by tr = VDD (V) × 0.16 (ns/V) + 3 (ns)
(57)
3. Gate drive loss
P(G) = VI ´ Q g ´ f (SW ) = 12 V ´ 3 nC ´ 400 kHz = 0.014 W
where
•
Qg is the total gate charge of the internal MOSFET
(58)
4. Quiescent current loss
P(Q) = VI ´ I Q = 12 V ´ 152 mA = 0.0018 W
where
•
IQ is the operating nonswitching supply current
(59)
Therefore,
P(tot) = P(COND) + P(SW ) + P(G) + P(Q) = 0.906 W + 0.118 W + 0.014 W + 0.0018 W = 1.040 W
(60)
For given TA,
TJ = TA + RqJA ´ P(tot)
where
•
•
•
•
TJ is the junction temperature (°C)
TA is the ambient temperature (°C)
RθJA is the thermal resistance of the package (°C/W)
P(tot) is the total device power dissipation (W)
(61)
For given TJmax = 150°C
TA max = TJ max - RqJA ´ P(tot)
where
•
•
TAmax is maximum ambient temperature (°C)
TJmax is maximum junction temperature (°C)
(62)
Additional power losses occur in the regulator circuit because of the inductor ac and dc losses, the catch diode
and PCB trace resistance. All of these losses impact the overall efficiency of the regulator.
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8.2.3 Safe Operating Area
Figure 47 through Figure 50 show the safe operating area (SOA) of the device for 3.3-V, 5-V, and 12-V outputs
and varying amounts of forced air flow applications. The temperature derating curves represent the conditions at
which the TPS54561-Q1 device, PCB and the output Inductor are at or below the manufacturer’s maximum
operating temperatures. Figure 47, through Figure 50 doesn't consider the impact from the catch diode thermal
performance. For higher reliability, TI uses 125 °C as the temperature limit for TPS54561-Q1 device on
Figure 47, through Figure 50. Derating limits apply to devices soldered directly to a double-sided PCB with 2 oz.
copper, similar to the board on TPS54561EVM-555 evaluation module.
90
90
80
80
Ambient Temperature (q)
Ambient Temperature (qC)
Pay careful attention to the other components chosen for the design, especially the catch diode. In most
applications, the catch diode limits the thermal performance. When operating at high duty cycles or at a higher
switching frequency, the thermal performance of the TPS54561-Q1 device can become the limiting factor.
70
60
50
8V
12 V
24 V
36 V
48 V
60 V
40
30
70
60
50
8V
12 V
24 V
36 V
48 V
60 V
40
30
20
20
0
0.5
1
VO = 3.3 V
1.5
2
2.5
3
3.5
Output Current (A)
4
4.5
5
0
0.5
1
Natural Convection
f(SW) = 400 kHz
VO = 5 V
90
90
80
80
70
60
50
18 V
24 V
36 V
48 V
60 V
30
2
2.5
3
3.5
Output Current (A)
4
4.5
5
D048
Natural Convection
f(SW) = 400 kHz
Figure 48. 5-V Outputs
Ambient Temperature (qC)
Ambient Temperature (qC)
Figure 47. 3.3-V Outputs
40
1.5
D047
70
60
50
40
400 LFM
200 LFM
100 LFM
Nat. Conv.
30
20
20
0
0.5
1
VO = 12 V
1.5
2
2.5
3
3.5
Output Current (A)
Natural Convection
f(SW) = 600 kHz
4
4.5
5
0
0.5
D049
VI = 48 V
VO = 12 V
Figure 49. 12-V Outputs
1
1.5
2
2.5
3
3.5
Output Current (A)
4
4.5
5
D050
Air flow direction: L1 to output terminal
f(SW) = 600 kHz
Figure 50. Air Flow Conditions
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8.2.4 Application Curves
1 A/div
10 V/div
Acquisition of measurements uses a 12-V input, 5-V output, and 5-A load unless otherwise noted.
VI
10 mV/div
200 mV/div
IO
Vo, DC-Coupled With –5-V Offset
Vo, DC-Coupled With –5-V Offset
Time = 100 µs/div
Time = 4 ms/div
Figure 51. Load Transient Response (1.25-A to 3.75-A
Load Step)
Figure 52. Line Transient (8 V to 40 V)
VI
1 V/div
5 V/div
VI
V(EN)
4 V/div
V(EN)
VO
VO
Time = 2 ms/div
IO = 5 A
IO = 5 A
Figure 53. Start-Up With Input Voltage
Figure 54. Start-Up With EN
10 V/div
500 mA/div
I(L)
V(SW)
I(L)
10 mV/div
10 mV/div
1 A/div
10 V/div
V(SW)
VO, AC-Coupled
VO, AC-Coupled
Time = 4 µs/div
Time = 4 µs/div
IO = 100 mA
IO = 5 A
Figure 55. Output Ripple, CCM
38
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Figure 56. Output Ripple, DCM
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Acquisition of measurements uses a 12-V input, 5-V output, and 5-A load unless otherwise noted.
10 V/div
1 m\A/div
I(L)
I(L)
10 mV/div
200 mV/div
10 V/div
V(SW)
200 mA/div
V(SW)
VO, AC-Coupled
VI, AC-Coupled
Time = 4 µs/div
Time = 1 ms/div
No load
IO = 5 A
Figure 57. Output Ripple, Eco-mode
10 V/div
2 V/div
V(SW)
Figure 58. Input Ripple, CCM
V(SW)
I(L)
VO
20 mV/div
10 mV/div
200 mA/div
500 mA/div
I(L)
VI, AC-Coupled
Time = 40 µs/div
Time = 4 µs/div
VI = 5.5 V
VO = 5.0 V
IO = 100 mA
100 mA
Figure 60. Low-Dropout Operation, Steady State
2 V/div
2 V/div
Figure 59. Input Ripple, DCM
VI
VI
VO
VO
IO = 100 mA
Time = 40 ms/div
EN floating
No load
EN floating
IO = 1 A
Figure 61. Low-Dropout Operation
Time = 40 ms/div
EN floating
Figure 62. Low-Dropout Operation
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Acquisition of measurements uses a 12-V input, 5-V output, and 5-A load unless otherwise noted.
100
100
95
90
80
90
Efficiency (%)
Efficiency (%)
70
85
80
VDD
7V
12 V
24 V
36 V
48 V
60 V
75
70
65
1
f(SW) = 400 kHz
2
3
Output Current (A)
4
50
VDD
7V
12 V
24 V
36 V
48 V
60 V
40
30
20
10
60
0
60
0
0.001
5
0.01
0.1
Output Current (A)
D029
VO = 5 V
f(SW) = 400 kHz
Figure 63. Efficiency vs Load Current
1
D030
VO = 5 V
Figure 64. Light-Load Efficiency
100
100
95
90
80
90
Efficiency (%)
Efficiency (%)
70
85
80
75
60
50
VDD
6V
12 V
24 V
36 V
48 V
60 V
40
30
70
VDD
6V
12 V
24 V
65
20
36 V
48 V
60 V
10
0
0.001
60
0
1
f(SW) = 400 kHz
2
3
Output Current (A)
4
5
0.01
0.1
Output Current (A)
D031
VO = 3.3 V
f(SW) = 400 kHz
Figure 65. Efficiency vs Load Current
1
D032
VO = 3.3 V
Figure 66. Light-Load Efficiency
60
180
40
120
20
60
0
0
0.1
-60
-40
-120
Gain
Phase
-60
10
Output Voltage Deviation (%)
-20
Phase (Degrees)
Gain (dB)
0.08
0.06
0.04
0.02
0
-0.02
-0.04
-0.06
-0.08
100
f(SW) = 400 kHz
IO = 5 A
1000
Frequency (Hz)
10000
VI = 12 V
-180
100000
-0.1
0
1
D033
VO = 5 V
f(SW) = 400 kHz
2
3
Output Current (A)
4
VI = 12 V
5
D034
VO = 5 V
Figure 68. Regulation vs Load Current
Figure 67. Overall Loop Frequency Response
40
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Acquisition of measurements uses a 12-V input, 5-V output, and 5-A load unless otherwise noted.
0.1
Output Voltage Deviation (%)
0.08
0.06
0.04
0.02
0
-0.02
-0.04
-0.06
-0.08
-0.1
5
10
15
20
25 30 35 40
Input Voltage (V)
f(SW) = 400 kHz
45
50
55
60
D035
IO = 2.5 A
VO = 5 V
Figure 69. Regulation vs Input Voltage
8.2.5 Inverting Power Supply
One use of the TPS54561-Q1 is to convert a positive input voltage to a negative output voltage. Ideal
applications are amplifiers requiring a negative power supply. For a more-detailed example, see Create an
Inverting Power Supply From a Step-Down Regulator, application report SLVA317.
VI
+
C(I)
VDD
C(VDD)
C(BOOT)
BOOT
L(O)
SW
GND
R(HS)
GND
TPS54561-Q1
EN
COMP
R(COMP)
RT/CLK
R(RT)
C(O)
VO
FB
PWRGD
SS/TR
C(SS)
R(LS)
+
C(ZERO)
C(POLE)
Copyright © 2017, Texas Instruments Incorporated
Figure 70. TPS54561-Q1 Inverting Power Supply Based on Application Report SLVA317
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Acquisition of measurements uses a 12-V input, 5-V output, and 5-A load unless otherwise noted.
8.2.6 Split-Rail Power Supply
Another use of the TPS54561-Q1 device is to convert a positive input voltage to a split-rail positive- and
negative-output voltage by using a coupled inductor. Ideal applications are amplifiers requiring a split-rail
positive- and negative-voltage power supply. For a more-detailed example, see Creating a Split-Rail Power
Supply With a Wide Input Voltage Buck Regulator, application report SLVA369.
VO+
+
VI
+
C(I)
C(BOOT)
VDD
C(VDD)
BOOT
T(O)
SW
R(HS)
GND
R(LS)
TPS54561-Q1
GND
+
C(O)–
VO–
EN
PWRGD
SS/TR
C(SS)
C(O)+
FB
COMP
R(COMP)
RT/CLK
R(RT)
C(ZERO)
C(POLE)
Copyright © 2016, Texas Instruments Incorporated
Figure 71. TPS54561-Q1 Split-Rail Power Supply Based on Application Report SLVA369
9 Power Supply Recommendations
The design of the device is for operation from an input voltage supply range between 4.5 V and 60 V. Good
regulation of this input supply is essential. If the input supply is more distant than a few inches from the
TPS54561-Q1 converter, the circuit may require additional bulk capacitance besides the ceramic bypass
capacitors. An electrolytic capacitor with a value of 100 µF is a typical choice.
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10 Layout
10.1 Layout Guidelines
Layout is a critical portion of good power-supply design. There are several signal paths that conduct fastchanging currents or voltages that can interact with stray inductance or parasitic capacitance to generate noise
or degrade performance. See Figure 72 for a PCB layout example.
• To reduce parasitic effects, bypass the VDD pin to ground with a low-ESR ceramic bypass capacitor with X5R
or X7R dielectric.
• Take care to minimize the loop area formed by the bypass capacitor connections, the VDD pin, and the anode
of the catch diode. Route the SW pin to the cathode of the catch diode and to the output inductor. Because
the SW connection is the switching node, locate the catch diode and output inductor close to the SW pins,
and minimize the area of the PCB conductor to prevent excessive capacitive coupling.
• Tie the GND pin directly to the copper pad under the IC for the exposed thermal pad. Connect this copper
pad to internal PCB ground planes using multiple vias directly under the IC.
• For operation at full-rated load, the top-side ground area must provide adequate heat dissipating area.
• The RT/CLK pin is sensitive to noise, so locate the RT resistor as close as possible to the IC and route
conductors with minimal lengths of trace.
• Figure 72 shows the approximate placement for the additional external components.
• It may be possible to obtain acceptable performance with alternate PCB layouts. However, this layout, meant
as a guideline, demonstrably produces good results.
Boxing in the components in the design of Figure 46, the estimated printed-circuit board area is 1.025 in2
(661 mm2). This area does not include test points or connectors. To further reduce the area, use a two-sided
assembly and replace the 0603-sized passives with a smaller-sized equivalent.
10.2 Layout Example
VO
Output
Capacitor
Top-Side
Ground
Area
Output
Inductor
Route boot-capacitor
trace on another layer to
provide a wide path for
the top-side ground.
Input
Bypass
Capacitor
BOOT
VDD
VI
EN
UVLO
Adjust
Resistors
SS/TR
RT/CLK
Catch
Diode
PWRGD
SW
GND
COMP
FB
Compensation
Network
Resistor
Divider
Thermal Via
Soft-Start
Capacitor
Frequency
Set Resistor
Signal Via
Figure 72. PCB Layout Example
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Development Support
For the TPS54560, TPS54561, and TPS54561-Q1 family Excel design tool, see SLVC452.
11.2 Documentation Support
11.2.1 Related Documentation
For related documentation, see the following:
• Create an Inverting Power Supply From a Step-Down Regulator, SLVA317
• Creating a Split-Rail Power Supply With a Wide Input Voltage Buck Regulator, SLVA369
• Evaluation Module for the TPS54561 Step-Down Converter, SLVU993
• Creating a Universal Car Charger for USB Devices From the TPS54240 and TPS2511, SLVA464
11.2.2 Custom Design with WEBENCH® Tools
Click here to create a custom design using the TPS54561-Q1 device with the WEBENCH® Power Designer.
1. Start by entering your VIN, VOUT, and IOUT requirements.
2. Optimize your design for key parameters like efficiency, footprint and cost using the optimizer dial and
compare this design with other possible solutions from Texas Instruments.
3. The WEBENCH Power Designer provides you with a customized schematic along with a list of materials with
real time pricing and component availability.
4. In most cases, you will also be able to:
– Run electrical simulations to see important waveforms and circuit performance
– Run thermal simulations to understand the thermal performance of your board
– Export your customized schematic and layout into popular CAD formats
– Print PDF reports for the design, and share your design with colleagues
5. Get more information about WEBENCH tools at www.ti.com/WEBENCH.
11.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.5 Trademarks
Eco-mode, E2E are trademarks of Texas Instruments.
WEBENCH is a registered trademark of Texas Instruments.
Excel is a trademark of Microsoft Corporation.
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11.6 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the mostcurrent data available for the designated devices. This data is subject to change without notice and without
revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS54561QDPRRQ1
ACTIVE
WSON
DPR
10
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
TPS
54561Q
TPS54561QDPRTQ1
ACTIVE
WSON
DPR
10
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
TPS
54561Q
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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