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TPS54628
SLVSBW5A – APRIL 2013 – REVISED DECEMBER 2016
TPS54628 4.5-V to 18-V Input, 6-A Synchronous Step-Down Converter With Eco-Mode™
1 Features
3 Description
•
The TPS54628 device is an adaptive on-time DCAP2 mode synchronous-buck converter. The
TPS54628 enables system designers to complete the
suite of various end-equipment power-bus regulators
with a cost-effective, low-component count, lowstandby current solution.
1
•
•
•
•
•
•
•
•
•
•
•
D-CAP2™ Mode Enables Fast Transient
Response
Low-Output Ripple and Allows Ceramic Output
Capacitor
Wide VIN Input Voltage Range: 4.5 V to 18 V
Output Voltage Range: 0.76 V to 5.5 V
Highly Efficient Integrated FETs Optimized
for Lower Duty-Cycle Applications
– 36 mΩ (High-Side) and 28 mΩ (Low-Side)
High Efficiency, Less Than 10 µA at Shutdown
High Initial Band-Gap Reference Accuracy
Adjustable Soft Start
Prebiased Soft Start
650-kHz Switching Frequency (fSW)
Cycle-by-Cycle Overcurrent Limit
Auto-Skip Eco-Mode™ for High Efficiency at Light
Load
2 Applications
•
Wide Range of Applications for Low-Voltage
Systems:
– Digital-TV Power Supplies
– High-Definition Blu-Ray Disc™ Players
– Networking Home Terminals
– Digital Set-Top Boxes (STBs)
The main control loop for the TPS54628 uses the
D-CAP2 mode control that provides a fast transient
response
with
no
external
compensation
components. The adaptive on-time control supports
seamless transition between PWM mode at higher
load conditions and Eco-Mode operation at light
loads. Eco-Mode allows the TPS54628 to maintain
high efficiency during lighter load conditions. The
TPS54628 also has a proprietary circuit that enables
the device to adopt to both low equivalent-seriesresistance (ESR) output capacitors, such as
POSCAP or SP-CAP, and ultra-low ESR ceramic
capacitors.
The device operates from 4.5-V to 18-V VIN input.
The output voltage can be programmed between
0.76 V and 5.5 V. The device also features an
adjustable soft-start time. The TPS54628 is available
in the 8-pin SO PowerPAD package, and designed to
operate from –40°C to 85°C.
Device Information(1)
PART NUMBER
TPS54628
PACKAGE
SO PowerPAD (8)
BODY SIZE (NOM)
4.89 mm × 3.90 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematic
TPS54628
Load Transient Response
Vout( 50mV/div)
Iout( 2A/div)
Copyright © 2016, Texas Instruments Incorporated
100us/div
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS54628
SLVSBW5A – APRIL 2013 – REVISED DECEMBER 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
4
4
4
5
5
7
Absolute Maximum Ratings ......................................
ESD Ratings ............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics – DC .................................
Typical Characteristics ..............................................
Detailed Description .............................................. 9
7.1
7.2
7.3
7.4
Overview ................................................................... 9
Functional Block Diagram ......................................... 9
Feature Description................................................. 10
Device Functional Modes........................................ 11
8
Application and Implementation ........................ 12
8.1 Application Information............................................ 12
8.2 Typical Application ................................................. 12
9 Power Supply Recommendations...................... 15
10 Layout................................................................... 16
10.1 Layout Guidelines ................................................. 16
10.2 Layout Example .................................................... 16
10.3 Thermal Considerations ........................................ 17
11 Device and Documentation Support ................. 18
11.1
11.2
11.3
11.4
11.5
11.6
Documentation Support .......................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
18
18
18
18
18
18
12 Mechanical, Packaging, and Orderable
Information ........................................................... 18
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (April 2013) to Revision A
Page
•
Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section ............................... 1
•
Deleted Ordering Information table; see Package Option Addendum at the end of the data sheet ...................................... 1
2
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5 Pin Configuration and Functions
DDA Package
8-Pin SO PowerPAD
Top View
1
EN
VIN
8
EXPOSED
THERMAL PAD
2
VFB
VBST
7
SW
6
GND
5
TPS54628
DDA
3
VREG5
4
SS
HSOP8
Pin Functions
PIN
NO.
NAME
I/O
DESCRIPTION
1
EN
I
Enable input control. EN is active high and must be pulled up to enable the device.
2
VFB
I
Converter feedback input. Connect to output voltage with feedback resistor divider.
3
VREG5
O
5.5-V power supply output. A capacitor (typically 1 µF) must be connected to GND. VREG5 is not active
when EN is low.
4
SS
I
Soft-start control. An external capacitor must be connected to GND.
5
GND
—
Ground pin. Power ground return for switching circuit. Connect sensitive SS and VFB returns to GND at
a single point.
6
SW
O
Switch node connection between high-side NFET and low-side NFET.
7
VBST
O
Supply input for the high-side FET gate drive circuit. Connect 0.1-µF capacitor between VBST and SW
pins. An internal diode is connected between VREG5 and VBST.
8
VIN
I
Input voltage supply pin.
—
Exposed
Thermal
Pad
—
Thermal pad of the package. Must be soldered to achieve appropriate dissipation. Must be connected to
GND.
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SLVSBW5A – APRIL 2013 – REVISED DECEMBER 2016
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6 Specifications
6.1 Absolute Maximum Ratings
See (1)
Input voltage
Output voltage
MIN
MAX
VIN, EN
–0.3
20
VBST
–0.3
26
VBST (10-ns transient)
–0.3
28
VBST (vs SW)
–0.3
6.5
VFB, SS
–0.3
6.5
SW
–2
20
SW (10-ns transient)
–3
22
VREG5
–0.3
6.5
GND
–0.3
0.3
UNIT
V
V
Voltage from GND to thermal pad, Vdiff
–0.2
0.2
V
Operating junction temperature, TJ
–40
150
°C
Storage temperature, Tstg
–55
150
°C
(1)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
Electrostatic discharge
Human-body model (HBM)
(1)
±2000
Charged-device model (CDM)
±500
UNIT
V
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
VIN
Supply input voltage
Input voltage
MIN
MAX
4.5
18
VBST
–0.1
24
VBST (10-ns transient)
–0.1
27
VBST (vs SW)
–0.1
6
SS
–0.1
5.7
EN
–0.1
18
VFB
–0.1
5.5
SW
–1.8
18
SW (10-ns transient)
GND
UNIT
V
V
–3
21
–0.1
0.1
–0.1
5.7
0
5
mA
VO
Output voltage (VREG5)
IO
Output current (IVREG5)
TA
Operating free-air temperature
–40
85
°C
TJ
Operating junction temperature
–40
150
°C
4
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6.4 Thermal Information
TPS54628
THERMAL METRIC
DDA
(SO PowerPAD)
(1)
UNIT
8 PINS
RθJA
Junction-to-ambient thermal resistance
43.5
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
49.4
°C/W
RθJB
Junction-to-board thermal resistance
25.6
°C/W
ψJT
Junction-to-top characterization parameter
7.4
°C/W
ψJB
Junction-to-board characterization parameter
25.5
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
5.2
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics – DC
Over operating free-air temperature range and VIN = 12 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY CURRENT
IVIN
Operating non-switching supply current
VIN current, TA = 25°C, EN = 5 V,
VFB = 0.8 V
950
1400
µA
IVINSDN
Shutdown supply current
VIN current, TA = 25°C, EN = 0 V
3
10
µA
LOGIC THRESHOLD
VEN
REN
EN high-level input voltage
EN
EN low-level input voltage
EN
EN pin resistance to GND
VEN = 12 V
1.6
0.6
200
400
800
V
kΩ
VFB VOLTAGE AND DISCHARGE RESISTANCE
TA = 25°C, VO = 1.05 V, IO = 10 mA,
Eco-Mode operation
VFBTH
IVFB
VFB threshold voltage
772
mV
TA = 25°C, VO = 1.05 V,
continuous mode operation
757
765
773
mV
TA = –40 to 85°C, VO = 1.05 V,
continuous mode operation (1)
751
765
779
mV
0
±0.15
µA
5.5
5.7
V
VFB input current
VFB = 0.8 V, TA = 25°C
VVREG5
VREG5 output voltage
TA = 25°C, 6 V < VIN < 18 V,
0 < IVREG5 < 5 mA
5.2
IVREG5
Output current
VIN = 6 V, VREG5 = 4 V, TA = 25°C
20
VREG5 OUTPUT
mA
VOUT DISCHARGE
RDISCHG
VOUT discharge resistance
EN = 0 V, SW = 0.5 V, TA = 25°C
500
High-side switch resistance
25°C, VBST – SW = 5.5 V
36
Low-side switch resistance
25°C
28
Current limit
L out = 1.5 µH (1)
800
Ω
MOSFET
RDS(on)
mΩ
CURRENT LIMIT
IOCL
6.7
7.3
8.9
A
THERMAL SHUTDOWN
TSDN
Thermal shutdown threshold (1)
Shutdown temperature
Hysteresis
165
°C
35
ON-TIME TIMER CONTROL
tON
ON time
VIN = 12 V, VO = 1.05 V
150
tOFF(MIN)
Minimum OFF time
TA = 25°C, VFB = 0.7 V
260
(1)
ns
310
ns
Not production tested.
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Electrical Characteristics – DC (continued)
Over operating free-air temperature range and VIN = 12 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
7.8
UNIT
SOFT START
ISS
SS charge current
VSS = 1 V
4.2
6
SS discharge current
VSS = 0.5 V
1.5
3.3
µA
mA
HICCUP AND OVERVOLTAGE PROTECTION
VOVP
Output OVP threshold
OVP Detect (L > H)
VHICCUP
Output hiccup threshold
Hiccup detect (H > L)
125%
THICCUPDELAY
Output hiccup delay
To hiccup state
250
THICCUPENDELAY
Output hiccup enable delay
Relative to soft-start time
×1.7
65%
µs
UVLO
UVLO
6
UVLO threshold
Wake-up VREG5 voltage
3.45
3.75
4.05
Hysteresis VREG5 voltage
0.13
0.32
0.48
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6.6 Typical Characteristics
VIN = 12 V, TA = 25°C (unless otherwise noted).
10
Ivccsdn - Shutdown Current (µA)
1,400
ICC - Supply Current (µA)
1,200
1,000
800
600
400
200
0
9
8
7
6
5
4
3
2
1
0
±50
0
50
100
±50
150
TJ Junction Temperature (ƒC)
0
50
100
150
TJ Junction Temperature (ƒC)
C001
Figure 1. Supply Current vs Junction Temperature
C002
Figure 2. VIN Shutdown Current vs
Junction Temperature
50
0.780
VIN = 18 V
0.775
VFB Voltage (V)
EN Input Current (µA)
40
30
20
10
0.770
0.765
0.760
0.755
0
Io=1A
IO = 1 A
0.750
0
5
10
15
20
EN Input Voltage (V)
±50
0
50
100
150
TJ Junction Temperature (ƒC)
C003
Figure 3. EN Current vs EN Voltage
C012
Figure 4. VFB Voltage vs Junction Temperature
1.100
1.080
VOUT - Output Voltage (V)
VOUT - Output Voltage (V)
IO = 10 mA
Io=10mA
1.075
1.050
1.025
VVin=5V
IN = 5 V
VVin=18V
IN = 18 V
0.0
1.0
2.0
3.0
4.0
IOUT - Output Current (A)
5.0
1.060
1.050
1.040
1.030
VVin=12V
IN = 12 V
1.000
1.070
IOUT = 10 mA
Io=10mA
Io=1A
IOUT = 1 A
1.020
6.0
0
Figure 5. 1.05-V Output Voltage vs Output Current
5
10
15
VIN - Input Voltage (V)
C004
20
C005
Figure 6. 1.05-V Output Voltage vs Input Voltage
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Typical Characteristics (continued)
VIN = 12 V, TA = 25°C (unless otherwise noted).
100
100
VIN = 12 V
70
80
Efficiency (%)
Efficiency (%)
80
70
60
60
50
40
30
Vo=1.8V
50
1.0
2.0
3.0
4.0
5.0
Figure 7. Efficiency vs Output Current
fsw - Switching Frequency (kHz)
750
700
Vo=1.05V
V
O = 1.05 V
Vo=1.2V
V
O = 1.2 V
V
Vo=1.5V
O = 1.5 V
V
Vo=1.8V
O = 1.8 V
V
Vo=2.5V
O = 2.5 V
V
Vo=3.3V
O = 3.3 V
V
Vo=5V
O= 5 V
500
450
400
0
5
800
700
600
500
400
300
200
VVo=1.05V
O = 1.05 V
100
VVo=1.8V
O = 1.8 V
VVo=3.3V
O = 3.3 V
0
10
C009
Figure 8. Light Load Efficiency vs Output Current
800
550
0.1
900
IOUT = 1 A
600
0.01
IOUT - Output Current (A)
C008
900
650
Vo=5V
0
0.001
6.0
IOUT - Output Current (A)
850
Vo=3.3V
10
Vo=5V
0.0
Vo=1.8V
20
Vo=3.3V
40
fsw - Switching Frequency (kHz)
VIN = 12 V
90
90
15
20
VIN - Input Voltage (V)
0.0
C010
Figure 9. Switching Frequency vs Input Voltage
0.1
1.0
IO - Output Current (A)
10.0
C011
Figure 10. Switching Frequency vs Output Current
7.00
Output Current (A)
6.00
5.00
4.00
3.00
VO=1.05V
2.00
VO=1.8V
1.00
VO=3.3V
VO=5V
0.00
-50
0
50
Ta Ambient Temperature (ºC)
100
C013
Figure 11. Output Current vs Ambient Temperature
8
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7 Detailed Description
7.1 Overview
The TPS54628 is a 6-A Eco-Mode™ synchronous step-down (buck) converter with two integrated N-channel
MOSFETs. It operates using D-CAP2™ mode control. The fast transient response of D-CAP2™ control reduces
the output capacitance required to meet a specific level of performance. Proprietary internal circuitry allows the
use of low-ESR output capacitors including ceramic and special polymer types.
7.2 Functional Block Diagram
EN
EN
1
Logic
VIN
-35%
VIN
+
8
HICCUP
-
VREG5
Control Logic
+
7
VBST
OV
+25%
1 shot
SW
VO
6
Ref
+
SS
+ PWM
XCON
ON
VFB
VREG5
Ceramic
Capacitor
-
2
5
+
ZC
-
SGND
SW
GND
PGND
VREG5
3
+
OCP
PGND
SS
SS
4
Softstart
SW
PGND
VIN
HICCUP
VREG5
SGND
OV
UVLO
UVLO
Protection
Logic
TSD
REF
Ref
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7.3 Feature Description
7.3.1 Auto-Skip Eco-Mode™ Control
The TPS54628 is designed with Auto-Skip Eco-Mode™ to increase light load efficiency. As the output current
decreases from heavy load condition, the inductor current is also reduced and eventually comes to point that its
rippled valley touches zero level, which is the boundary between continuous conduction and discontinuous
conduction modes. The rectifying MOSFET is turned off when its zero inductor current is detected. As the load
current further decreases the converter run into discontinuous conduction mode. The on time is kept almost the
same as is was in the continuous conduction mode so that it takes longer time to discharge the output capacitor
with smaller load current to the level of the reference voltage. The transition point to the light load operation
IOUT(LL) current can be calculated in Equation 1.
(VIN - VOUT )×VOUT
1
×
I OUT ( LL ) =
2 × L × fsw
VIN
(1)
7.3.2 Soft Start and Prebiased Soft Start
The soft-start function is adjustable. When the EN pin becomes high, 6-µA current begins charging the capacitor
which is connected from the SS pin to GND. Smooth control of the output voltage is maintained during start-up.
The equation for the slow-start time is shown in Equation 2. VFB voltage is 0.765 V and SS pin source current is
6 µA.
C6(nF) ´ VFB ´ 1.1 C6(nF) ´ 0.765 ´ 1.1
t SS (ms) =
=
ISS (μA)
6
(2)
The TPS54628 contains a unique circuit to prevent current from being pulled from the output during start-up if the
output is prebiased. When the soft-start commands a voltage higher than the prebias level (internal soft start
becomes greater than feedback voltage VFB), the controller slowly activates synchronous rectification by starting
the first low-side FET gate driver pulses with a narrow on time. It then increments that on time on a cycle-bycycle basis until it coincides with the time dictated by (1–D), where D is the duty cycle of the converter. This
scheme prevents the initial sinking of the pre-bias output, and ensure that the out voltage (VO) starts and ramps
up smoothly into regulation and the control loop is given time to transition from prebiased start-up to normal
mode operation.
7.3.3 Output Discharge Control
TPS54628 discharges the output when EN is low, or the controller is turned off by the UVLO protection. The
internal low-side MOSFET is not turned on for the output discharge operation to avoid the possibility of causing
negative voltage at the output.
7.3.4 Current Protection
The output overcurrent protection (OCP) is implemented using a cycle-by-cycle valley detect control circuit. The
switch current is monitored by measuring the low-side FET switch voltage between the SW pin and GND. This
voltage is proportional to the switch current. To improve accuracy, the voltage sensing is temperature
compensated.
During the on time of the high-side FET switch, the switch current increases at a linear rate determined by VIN,
VOUT, the on time and the output inductor value. During the on time of the low-side FET switch, this current
decreases linearly. The average value of the switch current is the load current IOUT. The TPS54628 constantly
monitors the low-side FET switch voltage, which is proportional to the switch current, during the low-side on time.
If the measured voltage is above the voltage proportional to the current limit, an internal counter is incremented
per each SW cycle and the converter maintains the low-side switch on until the measured voltage is below the
voltage corresponding to the current limit at which time the switching cycle is terminated and a new switching
cycle begins. In subsequent switching cycles, the on time is set to a fixed value and the current is monitored in
the same manner. If the overcurrent condition exists for 7 consecutive switching cycles, the internal OCL
threshold is set to a lower level, reducing the available output current. When a switching cycle occurs where the
switch current is not above the lower OCL threshold, the counter is reset and the OCL limit is returned to the
higher value.
10
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Feature Description (continued)
There are some important considerations for this type of overcurrent protection. The peak current is the average
load current plus one half of the peak-to-peak inductor current. The valley current is the average load current
minus one half of the peak-to-peak inductor current. Because the valley current is used to detect the overcurrent
threshold, the load current is higher than the overcurrent threshold. Also, when the current is being limited, the
output voltage tends to fall. When the VFB voltage becomes lower than 65% of the target voltage, the UVP
comparator detects it. If the undervoltage condition persists for 250 µs, the device shuts down and restarts in
hiccup mode after 7 times the SS period. When the overcurrent condition is removed, the output voltage returns
to the regulated value. This protection is non-latching.
7.3.5 Overvoltage Protection
TPS54628 detects overvoltage and undervoltage conditions by monitoring the feedback voltage (VFB). This
function is enabled after approximately 1.7 times the soft-start time. When the feedback voltage becomes higher
than 125% of the target voltage, the OVP comparator output goes high and both the high-side MOSFET driver
and the low-side MOSFET driver turn off. This function is non-latch operation.
7.3.6 UVLO Protection
Undervoltage lockout protection (UVLO) monitors the voltage of the VREG5 pin. When the VREG5 voltage is lower
than UVLO threshold voltage, the TPS54628 is shut off. This protection is non-latching.
7.3.7 Thermal Shutdown
TPS54628 monitors the temperature of itself. If the temperature exceeds the threshold value (typically 165°C),
the device is shut off. This is non-latch protection.
7.4 Device Functional Modes
7.4.1 PWM Operation
The main control loop of the TPS54628 is an adaptive on-time pulse width modulation (PWM) controller that
supports a proprietary D-CAP2™ mode control. D-CAP2™ mode control combines constant on-time control with
an internal compensation circuit for pseudo-fixed frequency and low external component count configuration with
both low-ESR and ceramic output capacitors. It is stable even with virtually no ripple at the output.
At the beginning of each cycle, the high-side MOSFET is turned on. This MOSFET is turned off after internal
one-shot timer expires. This one shot is set by the converter input voltage, VIN, and the output voltage, VO, to
maintain a pseudo-fixed frequency over the input voltage range, hence it is called adaptive on-time control. The
one-shot timer is reset and the high-side MOSFET is turned on again when the feedback voltage falls below the
reference voltage. An internal ramp is added to reference voltage to simulate output ripple, eliminating the ESRinduced output ripple from D-CAP2™ mode control.
7.4.2 PWM Frequency and Adaptive On-Time Control
TPS54628 uses an adaptive on-time control scheme and does not have a dedicated on board oscillator. The
TPS54628 runs with a pseudo-constant frequency of 650 kHz by using the input voltage and output voltage to
set the on-time one-shot timer. The on time is inversely proportional to the input voltage and proportional to the
output voltage; therefore, when the duty ratio is VOUT/VIN, the frequency is constant.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TPS54628 is designed to provide up to a 6-A output current from an input voltage source ranging from 4.5 V
to 18 V. The output voltage is configurable from 0.76 V to 5.5 V. A simplified design procedure for a 1.05-V
output is shown in Figure 12.
8.2 Typical Application
U1
TPS54628DDA
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Figure 12. Simplified Application Schematic Example
8.2.1 Design Requirements
To
•
•
•
•
•
begin the design process, the user must know the following application parameters:
Input voltage range
Output voltage
Output current
Output voltage ripple
Input voltage ripple
8.2.2 Detailed Design Procedure
8.2.2.1 Output Voltage Resistors Selection
The output voltage is set with a resistor divider from the output node to the VFB pin. TI recommends using 1%
tolerance or better divider resistors. Start by using Equation 3 to calculate VOUT.
V
= 0.765 x
OUT
12
æ
ö
çç1 + R1÷÷
÷
çè
R2 ø
(3)
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Typical Application (continued)
To improve efficiency at light loads consider using larger value resistors, high resistance is more susceptible to
noise, and the voltage errors from the VFB input current are more noticeable.
8.2.2.2 Output Filter Selection
The output filter used with the TPS54628 is an LC circuit. This LC filter has double pole at Equation 4.
F =
P
2p L
1
x COUT
OUT
(4)
At low frequencies, the overall loop gain is set by the output setpoint resistor divider network and the internal
gain of the TPS54628. The low frequency phase is 180 degrees. At the output filter pole frequency, the gain rolls
off at a –40 dB per decade rate and the phase drops rapidly. D-CAP2 introduces a high frequency zero that
reduces the gain roll off to –20 dB per decade and increases the phase to 90 degrees one decade above the
zero frequency. The inductor and capacitor selected for the output filter must be selected so that the double pole
of Equation 4 is located below the high frequency zero, but close enough that the phase boost provided be the
high frequency zero provides adequate phase margin for a stable circuit. To meet this requirement, use the
values recommended in Table 1.
Table 1. Recommended Component Values
(1)
C4 (pF) (1)
OUTPUT
VOLTAGE
(V)
R1 (kΩ)
R2 (kΩ)
L1 (µH)
C8 + C9 (µF)
MIN
TYP
MAX
MIN
TYP
MAX
MIN
MAX
1
6.81
22.1
5
150
220
1
1.5
4.7
22
68
1.05
8.25
22.1
5
150
220
1
1.5
4.7
22
68
1.2
12.7
22.1
5
100
1
1.5
4.7
22
68
1.5
21.5
22.1
5
68
1
1.5
4.7
22
68
1.8
30.1
22.1
5
22
1.2
1.5
4.7
22
68
2.5
49.9
22.1
5
22
1.5
2.2
4.7
22
68
3.3
73.2
22.1
2
22
1.8
2.2
4.7
22
68
5
124
22.1
2
22
2.2
3.3
4.7
22
68
Optional
Because the DC gain is dependent on the output voltage, the required inductor value increases as the output
voltage increases. Additional phase boost can be achieved by adding a feedforward capacitor (C4) in parallel
with R1. The feedforward capacitor is most effective for output voltages at or above 1.8 V.
The inductor peak-to-peak ripple current, peak current and RMS current are calculated using Equation 5,
Equation 6, and Equation 7. The inductor saturation current rating must be greater than the calculated peak
current and the RMS or heating current rating must be greater than the calculated RMS current. Use 700 kHz for
fSW.
Use 650 kHz for fSW. Make sure the chosen inductor is rated for the peak current of Equation 6 and the RMS
current of Equation 7.
- VOUT
V
V
OUT x IN(max)
I
=
IPP
V
L x f
IN(max)
O
SW
I
=I +
Ipeak
O
=
I
Lo(RMS)
(5)
I
lpp
2
I
2
O
(6)
+
1
2
I
12 IPP
(7)
For this design example, the calculated peak current is 6.51 A and the calculated RMS current is 6.01 A. The
inductor used is a TDK SPM6530-1R5M100 with a peak current rating of 11.6 A and an RMS current rating of
11 A.
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The capacitor value and ESR determines the amount of output voltage ripple. The TPS54628 is intended for use
with ceramic or other low-ESR capacitors. TI recommends the value range from 22 µF to 68 µF. Use Equation 8
to determine the required RMS current rating for the output capacitor.
I
Co(RMS)
=
VOUT x (VIN - VOUT )
12 x VIN x LO x fSW
(8)
For this design two TDK C3216X5R0J226M 22-µF output capacitors are used. The typical ESR is 2 mΩ each.
The calculated RMS current is 0.284 A and each output capacitor is rated for 4 A.
8.2.2.3 Input Capacitor Selection
The TPS54628 requires an input decoupling capacitor and a bulk capacitor is required depending on the
application. TI recommends using a ceramic capacitor over 10 µF for the decoupling capacitor. An additional
0.1-µF capacitor (C3) from pin 8 to ground is optional to provide additional high-frequency filtering. The capacitor
voltage rating must be greater than the maximum input voltage.
8.2.2.4 Bootstrap Capacitor Selection
A 0.1-µF ceramic capacitor must be connected between the VBST to SW pin for proper operation. TI
recommends using a ceramic capacitor.
8.2.2.5 VREG5 Capacitor Selection
A 1-µF ceramic capacitor must be connected between the VREG5 to GND pin for proper operation. TI
recommends using a ceramic capacitor.
14
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8.2.3 Application Curves
Vout( 50mV/div)
EN(10V/div)
Iout( 2A/div)
VREG5(5V/div)
Vout(0.5V/div)
1ms/div
100us/div
Figure 13. 1.05-V Load Transient Response
Vo=1.05V
Figure 14. Start-Up Waveform
Vo(10mV/div)
VO = 50 mV / div (-950 mV dc offset)
SW = 10 V / div
SW( 5V/div)
400ns/div
Time = 1 µsec / div
(IO = 6 A)
Figure 15. Voltage Ripple at Output
Vo=1.05V
(IO = 30 mA)
Figure 16. DCM Voltage Ripple at
Output
VIN(50mV/div)
SW( 5V/div)
400ns/div
(IO = 6 A)
Figure 17. Voltage Ripple at Input
9 Power Supply Recommendations
The input voltage range is from 4.5 V to 18 V. The input power supply and the input capacitors must be placed
as close to the device as possible to minimize the impedance of the power-supply line.
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10 Layout
10.1 Layout Guidelines
The following lists the grounding and PCB circuit layout considerations:
1. The TPS54628 can supply large load currents up to 6 A, so heat dissipation may be a concern. The top-side
area adjacent to the TPS54628 must be filled with ground as much as possible to dissipate heat.
2. The bottom-side area directly below the IC must a dedicated ground area. It must be directly connected to
the thermal pad of the device using vias as shown. The ground area must be as large as practical. Additional
internal layers can be dedicated as ground planes and connected to the vias as well.
3. Keep the input switching current loop as small as possible.
4. Keep the SW node as physically small and short as possible to minimize parasitic capacitance and
inductance and to minimize radiated emissions. Kelvin connections must be brought from the output to the
feedback pin of the device.
5. Keep analog and non-switching components away from switching components.
6. Make a single point connection from the signal ground to power ground.
7. Do not allow switching current to flow under the device.
8. Keep the pattern lines for VIN and PGND broad.
9. Exposed pad of device must be connected to PGND with solder.
10. VREG5 capacitor must be placed near the device, and connected PGND.
11. Output capacitor must be connected to a broad pattern of the PGND.
12. Voltage feedback loop must be as short as possible, and preferably with ground shield.
13. Lower resistor of the voltage divider which is connected to the VFB pin must be tied to SGND.
14. Providing sufficient via is preferable for VIN, SW and PGND connection.
15. PCB pattern for VIN, SW, and PGND must be as broad as possible.
16. VIN Capacitor must be placed as near as possible to the device.
10.2 Layout Example
VIN
VIN
INPUT
BYPASS
CAPACITOR
VIN
HIGH FREQENCY
BYPASS
CAPACITOR
TO ENABLE
CONTROL
FEEDBACK
RESISTORS
BIAS
CAP
EN
VIN
VFB
VBST
VREG5
SW
SS
GND
SLOW
START
CAP
Connection to
POWER GROUND
on internal or
bottom layer
ANALOG
GROUND
TRACE
BOOST
CAPACITOR
OUTPUT
INDUCTOR
EXPOSED
THERMAL PAD
AREA
VOUT
OUTPUT
FILTER
CAPACITOR
POWER GROUND
VIA to Ground Plane
Figure 18. PCB Layout
16
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10.3 Thermal Considerations
This 8-pin SO PowerPAD package incorporates an exposed thermal pad that is designed to be directly to an
external heat sink. The thermal pad must be soldered directly to the printed-board (PCB). After soldering, the
PCB can be used as a heat sink. In addition, through the use of thermal vias, the thermal pad can be attached
directly to the appropriate copper plane shown in the electrical schematic for the device, or alternatively, can be
attached to a special heat sink structure designed into the PCB. This design optimizes the heat transfer from the
integrated circuit (IC).
For additional information on the exposed thermal pad and how to use the advantage of its heat dissipating
abilities, see PowerPAD™ Thermally Enhanced Package (SLMA002) and PowerPAD™ Made Easy (SLMA004).
The exposed thermal pad dimensions for this package are shown in Figure 19.
Figure 19. Thermal Pad Dimensions
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11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation see the following:
• PowerPAD™ Thermally Enhanced Package (SLMA002)
• PowerPAD™ Made Easy (SLMA004)
• TPS54628EVM-052, 6-A, Regulator Evaluation Module (SLVU888)
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 Trademarks
D-CAP2, Eco-Mode, E2E are trademarks of Texas Instruments.
Blu-Ray Disc is a trademark of Blu-ray Disc Association.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
18
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS54628DDA
ACTIVE SO PowerPAD
DDA
8
75
RoHS & Green
NIPDAU | SN
Level-2-260C-1 YEAR
-40 to 150
54628
TPS54628DDAR
ACTIVE SO PowerPAD
DDA
8
2500
RoHS & Green
NIPDAU | SN
Level-2-260C-1 YEAR
-40 to 150
54628
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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