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TPS54A20
SLVSCQ8A – DECEMBER 2015 – REVISED APRIL 2016
TPS54A20 8-V to 14-V Input, 10-A, up to 10-MHz SWIFT™ Step Down Converter
1 Features
2 Applications
•
•
1
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•
•
•
•
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Two-phase, Synchronous Series Capacitor Buck
Converter
Automatic Current Balancing Between Phases
2-MHz to 5-MHz Per Phase Switching Frequency
14-ns Minimum On-Time
0.51-V to 2-V Output Voltage Range with ±0.5%
Feedback Reference Voltage
Input Overvoltage Lockout for 17-V Surge
Protection
Adjustable Current Limit with Auto Restart
(Hiccup)
Synchronizes to an External Clock
Fixed Frequency in Steady State
Adaptive On-Time Control
Internal Feedback Loop Compensation
Internal Gate Drive LDO with External Supply
Option
EN Pin Allowing for Adjustable Input UVLO
Selectable Soft-Start Time
Monotonic Startup with Pre-biased Output
Output Power Good Indicator (Open Drain)
Output Overvoltage/Undervoltage Protection
Telecom, base station, and communications
equipment
Storage, SSD, DDR memory, switches, hubs,
routers, and other networking equipment
Low profile/Backside board mounting (< 2 mm
height)
•
•
3 Description
The TPS54A20 is a two-phase, synchronous series
capacitor buck converter designed for small size, low
voltage applications from a 12-V input rail. This
topology uniquely merges a switched capacitor circuit
with a two phase buck converter. Advantages include
automatic current balancing between the inductors,
lower switching losses which enable high frequency
(HF) operation, and voltage step-down through the
series capacitor. Small, low profile inductors used
with the TPS54A20 significantly reduce total solution
area and height. An adaptive on-time control
architecture provides fast transient response and
accurate voltage regulation at up to 10-MHz operating
frequency. Fixed frequency operation during steady
state is maintained through the use of a phase lock
loop (PLL) to lock switching signals to a reference
oscillator.
Device Information(1)
PART NUMBER
TPS54A20
PACKAGE
VQFN (20 pins)
BODY SIZE (NOM)
3.5 mm x 4 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Simplified Schematic
VIN
Efficiency vs Load Current
95
VIN
BOOTA
90
PGOOD
85
SCAP
SS/FSEL
EN
LA
VOUT
SWA
ILIM
VGA
Efficiency (%)
SYNC
80
75
70
BOOTB
65
TON
VG+
VGAGND
LB
SWB
60
FB
55
9 VIN
12 VIN
14 VIN
0
PGND
2
4
6
Output Current (A)
8
10
D019
1.8 VOUT, 2 MHz per phase, External VG+,
3.2 x 2.5 x 1.2 mm inductors
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS54A20
SLVSCQ8A – DECEMBER 2015 – REVISED APRIL 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
4
5
5
5
6
7
8
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Timing Requirements ................................................
Typical Characteristics ..............................................
Detailed Description ............................................ 15
7.1 Overview ................................................................. 15
7.2 Functional Block Diagram ....................................... 16
7.3 Feature Description................................................. 16
8
Application and Implementation ........................ 22
8.1 Application Information............................................ 22
8.2 Typical Application ................................................. 23
9 Power Supply Recommendations...................... 31
10 Layout................................................................... 32
10.1 Layout Guidelines ................................................. 32
10.2 Layout Example .................................................... 33
11 Device and Documentation Support ................. 35
11.1
11.2
11.3
11.4
11.5
Documentation Support ........................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
35
35
35
35
35
12 Mechanical, Packaging, and Orderable
Information ........................................................... 35
4 Revision History
Changes from Original (December 2015) to Revision A
•
2
Page
Changed the device status to Production data. .................................................................................................................... 1
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SLVSCQ8A – DECEMBER 2015 – REVISED APRIL 2016
5 Pin Configuration and Functions
RNJ Package
VQFN (20 Pin)
Top View
Pin Functions
PIN
I/O (1)
DESCRIPTION
NAME
NO.
AGND
1
G
Analog signal ground of the IC. AGND should be connected to PGND and VG- at a single point on PCB
(e.g. underneath the IC).
BOOTA
8
S
Bootstrap capacitor node for phase A high-side MOSFET gate driver. Connect the bootstrap capacitor
from this pin to the SCAP pin (pin 9).
BOOTB
10
S
Bootstrap capacitor node for phase B high-side MOSFET gate driver. Connect the bootstrap capacitor
from this pin to the SWB pin.
EN
4
I
Enable pin. Floating this pin will enable the IC. Pull below 1.23V to enter shutdown mode. Can also be
used to adjust the input undervoltage lockout above 8 V with two resistors.
FB
18
I
Feedback pin for voltage regulation. Connect this pin to the center tap of a resistor divider to set the
output voltage.
ILIM
5
I
Current limit programming pin. A resistor between this pin and ground sets the current limit. If no resistor
is included, the default load current limit is 15 A.
NC
11
PGND
2
G
Power ground of the IC. PGND should be connected to AGND and VG- at a single point on PCB (e.g.
underneath the IC). Thermal vias to internal ground planes should be added beneath this pin.
PGOOD
15
O
Power good indicator. This pin is an open-drain output and will assert low if the output voltage is greater
than ±5% away from the desired value or due to thermal shutdown, over-voltage/under-voltage, EN
shutdown, or during soft start. A pull-up resistor can be connected between PGOOD and VG+ or an
external logic supply pin.
9,20
O
Series capacitor pin. Connect a ceramic capacitor from pin 20 to the SWA pin.
SS/FSEL
6
I
Soft start/frequency select pin. Connect a resistor from this pin to ground to set the soft-start time and the
switching frequency. If no resistor is provided, the default setting of 4MHz oscillator frequency and 512µs
soft start time is used.
SWA
13
O
Switching node for phase A. Connect an inductor from this pin to the output capacitors.
SWB
12
O
Switching node for phase B. Connect an inductor from this pin to the output capacitors.
SYNC
14
I
External clock synchronization pin. An external clock signal can be connected to this pin to synchronize
the oscillator frequency (within ±10% of the nominal frequency set via SS/FSEL).
SCAP
(1)
No connect. This pin is not electrically connected to the IC and is included for board level reliability (BLR)
purposes. Connect this pin to the SCAP trace.
I = Input, O = Output, S = Supply, G = Ground Return
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SLVSCQ8A – DECEMBER 2015 – REVISED APRIL 2016
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Pin Functions (continued)
PIN
NAME
I/O (1)
NO.
DESCRIPTION
TON
19
I
On-time selection. An external resistor from this pin to the AGND pin programs the nominal on-time of the
high side switches.
VG+
16
S
Gate driver positive supply pin. Connect a bypass capacitor from this pin to VG-. To improve converter
efficiency, the internal regulator can be overridden by connecting an external 5V supply to this pin. This
supply rail also provides power to the control circuitry.
VG-
17
G
Gate driver supply return pin. VG- should be connected to PGND and AGND at a single point on PCB
(e.g. underneath the IC).
VGA
7
S
High side phase A gate driver supply pin. Connect a bypass capacitor from this pin to ground.
VIN
3
I
The power input pin to the IC. Connect VIN to a supply voltage between 8 V and 14 V.
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
Power Conversion, VIN
Bootstrap, V(BOOTA)
(1)
MIN
MAX
DC w.r.t. PGND, switching
–0.3
15
DC w.r.t. PGND, non-switching
–0.3
17
DC with respect to PGND
–0.3
22
V
6
V
14
V
DC with respect to SCAP
DC with respect to PGND
Bootstrap, V(BOOTB)
DC with respect to SWB
6
V
–0.3
6
V
Series Capacitor Node Voltage,
DC with respect to PGND
V(SCAP)
–0.3
16
–1
9
Bias Supply, VG
Switch Node Voltage, V(SWA,
DC with respect to PGND
SWB)
Pulse < 10 ns
Feedback, V(FB)
Voltage
Input Current
Output Current
V
DC with respect to PGND
Input Voltage
Output Voltage
–0.3
UNIT
Bias Supply, V(VGA)
DC with respect to PGND
V
–4
14
–0.3
3
V
V
–0.3
15
Enable Voltage, V(EN)
–0.3
7
Soft Start/Freq. Select, V(SS/FSEl)
–0.3
3
Power Good Voltage, V(PGOOD)
–0.3
6
External Sync Clock Voltage, V(SYNC)
–0.3
6
Current Limit/Mode Select, V(ILIM)
–0.3
3
On Time Pin Voltage, V(TON)
–0.3
3
Power Conversion, I(VIN)
V
6
A
100
mA
Switch Node A, I(SWA)
Current
Limit
A
Switch Node B, I(SWB)
Current
Limit
A
Bias Supply, I(VG)
Operating Junction Temperature, TJ
–40
125
°C
Storage temperature, Tstg
–65
150
°C
(1)
4
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
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SLVSCQ8A – DECEMBER 2015 – REVISED APRIL 2016
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1)
±2000
Charged device model (CDM), per JEDEC specification JESD22-C101,
all pins (2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
VIN
Input Voltage
8
14
V
VOUT
Output Voltage
0.5
VIN/5
V
IOUT
Output Current
0
10
A
TJ
Junction Temperature
-40
125
°C
6.4 Thermal Information
THERMAL METRIC (1)
RNJ
20 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
25 (2)
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
13.4
°C/W
RθJB
Junction-to-board thermal resistance
4.9
°C/W
ψJT
Junction-to-top characterization parameter
0.2
°C/W
ψJB
Junction-to-board characterization parameter
4.7
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
2.0
°C/W
(1)
(2)
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
Tested on four layer evaluation board.
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6.5 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY VOLTAGE (VIN PIN)
VIN
VIN Operating
VIN Input UVLO Voltage
VIN rising
8
12
14
7.4
7.65
7.95
VIN UVLO hysteresis
VIN Input OVLO Voltage
250
VIN rising
VIN falling
15.4
14.1
VIN OVLO hysteresis
IQ
V
V
mV
15.8
V
14.8
V
600
mV
Shutdown
EN < 0.4 V, VIN = 12 V, TA = 25°C
47
µA
Operating into VIN
FB = 0.53 V, VIN = 12 V, TA = 25°C
6
mA
ENABLE (EN PIN)
Enable threshold
Input current
1.17
1.23
1.27
V
Enable threshold + 50 mV
–4
µA
Enable threshold – 50 mV
–1
µA
VOLTAGE REFERENCE
Voltage Reference
TA = 25°C
0.5054
0.508
0.5106
V
–40°C < TJ < 125°C
0.5029
0.508
0.5131
V
R(SS/FSEL) = Open, 71.5 kΩ,
or 48.7 kΩ
3.6
4
4.4
MHz
R(SS/FSEL) = Short or 35.7 kΩ
6.3
7
7.7
MHz
9
10
11
MHz
20
ns
2
V
FREQUENCY
fOSC
Oscillator Frequency
R(SS/FSEL) = 21.5 kΩ, 15.4 kΩ,
or 8.66 kΩ
SYNC
Minimum Input Clock Pulsewidth
SYNC high threshold
SYNC low threshold
0.8
Frequency sync range
Last SYNC falling/rising edge to
return to resistor timing mode if
SYNC is not present
V
±10
10 MHz: 400 ns
7 MHz: 571 ns
4 MHz : 1 µs
% nominal
4
Cycles
LOW-SIDE A MOSFET
On resistance
VG = 5 V, Measured at pins
6.8
10.5
mΩ
VG = 5 V, Measured at pins
9.3
14.8
mΩ
On resistance
Vgs = 5 V, Measured at pins
27
50
mΩ
SW rise time 10% to 90%
VIN = 12 V
2
ns
SW fall time 90% to 10%
VIN = 12 V
2
ns
LOW-SIDE B MOSFET
On resistance
HIGH-SIDE MOSFETS
CURRENT LIMIT
Peak Switch LSA Current Limit
Peak Switch LSB Current Limit
~15A Load Trip, R(ILIM) = Open
12.7
16.3
19.9
~11.25A Load Trip, R(ILIM) = 47 kΩ
9.9
12.7
15.5
~15A Load Trip, R(ILIM) = Open
6.8
8.7
10.6
~11.25A Load Trip, R(ILIM) = 47 kΩ
5.3
6.8
8.3
Overcurrent protection scheme
6
A
Hiccup
OCP cycle count to trip fault
Fault hiccup wait time
A
10 MHz: 13.1 ms
7 MHz: 18.7 ms
4 MHz: 32.8 ms
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3
Cycles
131,072
Cycles
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Electrical Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
4.4
4.8
5
100
140
mA
60
mA
INTERNAL REGULATOR (VG LDO)
0 mA ≤ IVG ≤ 100 mA
Output Voltage
Current Limit
Nominal Operating Current
Fosc = 10 MHz, ILOAD = 10A
V
DYNAMIC REGULATOR (VGA LDO)
15
Output Voltage
VIN = 12 V
V
10.5
V
SERIES CAP MONITOR
Low Voltage Fault Trip
35
Nominal Voltage
50
High Voltage Fault Trip
62
65
Capacitor Precharge Current
5.5
10
38
%VIN
14.5
mA
POWER GOOD
VFB falling (Fault), UVP
90
VFB rising (Good)
VFB threshold
95
VFB rising (Fault), OVP
110
VFB falling (Good)
105
PGOOD sink current
V(PGOOD) = 0.4 V
2.7
PGOOD pin leakage current
VFB = VREF, V(PGOOD)= 5 V
Minimum VIN for valid PGOOD
V(PGOOD) ≤ 0.5 V at 100 µA
1.2
%VREF
mA
1
μA
2.75
V
THERMAL SHUTDOWN
Thermal shutdown set threshold
Thermal shutdown hysteresis
Thermal shutdown hiccup time
10 MHz: 13.1 ms
7 MHz: 18.7 ms
4 MHz: 32.8 ms
135
°C
20
°C
131,072
Cycles
6.6 Timing Requirements
MIN
NOM
MAX
UNIT
ENABLE (EN PIN)
Enable to Start Switching time
1 µF series cap, VIN = 12V
625
µs
30
µs
SW minimum ON pulse width
14
ns
SW minimum OFF pulse width
10
ns
SYNC
Lock in time
HIGH-SIDE MOSFETS
Non-Overlap Time between HS FET
Off and LS FET On (deadtime)
Non-Overlap Time between LS FET
Off and HS FET On (deadtime)
3
Fsw = 5 MHz, VIN = 12 V
3
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ns
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6.7 Typical Characteristics
VIN = 12 V, VOUT = 1.2 V, TA = 25 ºC, unless otherwise noted.
50
10
High Side Phase A
Low Side Phase A
Rds(on) - On Resistance (m:)
Rds(on) - On Resistance (m:)
45
40
35
30
25
20
15
10
-50
-25
0
25
50
75
100
Junction Temperature (qC)
125
9
8
7
6
5
4
-50
150
Figure 1. On Resistance vs Junction Temperature
0
25
50
75
100
Junction Temperature (qC)
125
150
D002
Figure 2. On Resistance vs Junction Temperature
15
510
Low Side Phase B
VREF - Voltage Reference (V)
14
Rds(on) - On Resistance (m:)
-25
D001
13
12
11
10
9
8
7
509.5
509
508.5
508
507.5
6
5
-50
-25
0
25
50
75
100
Junction Temperature (qC)
125
507
-50
150
-25
0
D003
Figure 3. On Resistance vs Junction Temperature
25
50
75
100
Junction Temperature (qC)
125
150
D004
Figure 4. Voltage Reference vs Junction Temperature
7.1
4.1
7 MHz
4 MHz
4.05
7
Frequency (MHz)
Frequency (MHz)
4
3.95
3.9
3.85
6.9
6.8
6.7
3.8
6.6
3.75
3.7
-50
-25
0
25
50
75
100
Junction Temperature (qC)
125
150
-25
D005
Figure 5. Oscillator Frequency vs Junction Temperature
8
6.5
-50
0
25
50
75
100
Junction Temperature (qC)
125
150
D006
Figure 6. Oscillator Frequency vs Junction Temperature
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Typical Characteristics (continued)
VIN = 12 V, VOUT = 1.2 V, TA = 25 ºC, unless otherwise noted.
10.4
90
10 MHz
10.3
Shutdown Current (PA)
10.2
Frequency (MHz)
8V
12 V
14 V
80
10.1
10
9.9
9.8
70
60
50
40
30
9.7
9.6
-50
-25
0
25
50
75
100
Junction Temperature (qC)
125
20
-50
150
-25
0
D007
25
50
75
100
Junction Temperature (qC)
125
150
D008
EN = 0 V
Figure 7. Oscillator Frequency vs Junction Temperature
Figure 8. Shutdown Current vs Junction Temperature
4.2
1.2
4.1
1.15
1.1
1.05
Current (PA)
Current (PA)
4
3.9
3.8
1
0.95
3.7
0.9
3.6
0.85
3.5
-50
-25
0
25
50
75
100
Junction Temperature (qC)
125
0.8
-50
150
EN = Threshold + 50 mV
Figure 9. EN Pin Current vs Junction Temperature
25
50
75
100
Junction Temperature (qC)
125
150
D010
Figure 10. EN Pin Current vs Junction Temperature
6.8
1.235
6.6
1.233
6.4
Current (mA)
Voltage (V)
0
EN = Threshold - 50 mV
1.237
1.231
1.229
1.227
1.225
-50
-25
D009
8V
12 V
14 V
6.2
6
5.8
-25
0
25
50
75
100
Junction Temperature (qC)
125
150
5.6
-50
-25
D011
0
25
50
75
100
Junction Temperature (qC)
125
150
D008
FB = 0.53 V (non-switching)
Figure 11. EN Pin Threshold vs Junction Temperature
Figure 12. Non-Switching Operating Current vs Junction
Temperature
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Typical Characteristics (continued)
VIN = 12 V, VOUT = 1.2 V, TA = 25 ºC, unless otherwise noted.
115
16
15.5
110
100
UVP Falling
OVP Rising
Current (A)
Voltage (%VREF)
15
105
PGOOD Rising
PGOOD Falling
95
14.5
14
15 A Limit
11.25 A Limit
13.5
13
90
12.5
85
-50
-25
0
25
50
75
100
Junction Temperature (qC)
125
12
-50
150
-25
0
D013
Figure 13. PGOOD and Under/Overvoltage Protection
Threshold vs Junction Temperature
25
50
75
100
Junction Temperature (qC)
125
150
D014
Figure 14. Phase A Low-Side MOSFET Current Limit vs
Junction Temperature
9
4.82
4.815
8.5
4.81
7.5
Voltage (V)
Current (A)
8
15 A Limit
11.25 A Limit
7
4.805
4.8
4.795
4.79
6.5
6
-50
4.785
-25
0
25
50
75
100
Junction Temperature (qC)
125
4.78
-50
150
Figure 15. Phase B Low-Side MOSFET Current Limit vs
Junction Temperature
15.5
7.7
15.4
Voltage (V)
Voltage (V)
UVLO Rising
UVLO Falling
7.5
150
D016
15.2
15.1
OVLO Rising
OVLO Falling
15
14.8
-25
0
25
50
75
100
Junction Temperature (qC)
125
150
14.7
-50
D100
Figure 17. Undervoltage Lockout Threshold vs Junction
Temperature
10
125
14.9
7.45
7.4
-50
25
50
75
100
Junction Temperature (qC)
15.3
7.65
7.55
0
Figure 16. Internal Gate Drive Voltage (VG) vs Junction
Temperature
7.75
7.6
-25
D015
-25
0
25
50
75
100
Junction Temperature (qC)
125
150
D018
Figure 18. Overvoltage Lockout Threshold vs Junction
Temperature
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Typical Characteristics (continued)
95
95
90
90
85
85
Efficiency (%)
Efficiency (%)
VIN = 12 V, VOUT = 1.2 V, TA = 25 ºC, unless otherwise noted.
80
75
70
65
75
70
65
60
1.8 VOUT
1.2 VOUT
0.8 VOUT
60
External VG+
Internal VG+
55
55
0
2
4
6
Output Current (A)
8
10
0
2
D022
fsw = 2 MHz per phase
3.2 x 2.5 x 1.2 mm
inductors
35
0.3
30
0.2
Load Regulation (%V O)
0.4
20
15
10
8
10
D034
External
VG+
3.2 x 2.5 x 1.2 mm
inductors
Figure 20. Efficiency vs Output Current for Output Voltage
40
25
4
6
Output Current (A)
fsw = 2 MHz per phase
Figure 19. Efficiency vs Output Current for Gate Drive
Supply
Temperature Rise (qC)
80
5
8 VIN
12 VIN
14 VIN
0.1
0
-0.1
-0.2
-0.3
0
-0.4
0
2
4
6
Output Current (A)
fsw = 2 MHz per phase
8
10
0
2
4
6
Output Current (A)
D023
3.2 x 2.5 x 1.2 mm
inductors
8
10
D024
No air flow
Figure 22. Load Regulation
Figure 21. Case Temperature Rise vs Output Current
0.4
4
0A
5A
10 A
Recommended
Theoretical
3.5
0.2
Max Output Voltage (V)
Line Regulation (%V O)
0.3
0.1
0
-0.1
-0.2
3
2.5
2
1.5
1
-0.3
-0.4
0.5
8
10
12
Input Voltage (V)
Figure 23. Line Regulation
14
8
10
12
Input Voltage (V)
D025
14
D026
Figure 24. Max Output Voltage vs Input Voltage
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Typical Characteristics (continued)
VIN = 12 V, VOUT = 1.2 V, TA = 25 ºC, unless otherwise noted.
12
2.04
Recommended
2.03
Frequency (MHz)
Min Input Voltage (V)
11
10
9
8
7
2.02
2.01
2.00
8 VIN
12 VIN
14 VIN
1.99
6
1.98
1
1.1
1.2
1.3
1.4 1.5 1.6 1.7
Output Voltage (V)
1.8
1.9
2
0
2
D033
Figure 25. Min Input Voltage vs Output Voltage
1 Ω Load
40 ms/div
Series capacitance = 1 µF
200 µs/div
fsw = 2 MHz per phase
fsw = 2 MHz per phase
12
10
D027
fsw = 2 MHz per phase
Figure 28. Startup Through EN
40 µs/div
Figure 29. Shutdown Through EN
8
Figure 26. Frequency vs Output Current
Figure 27. Input UVLO and OVLO
5 Ω Load
4
6
Output Current (A)
Series capacitance = 1 µF
200 µs/div
fsw = 2 MHz per phase
Figure 30. Pre-biased Startup Through EN
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Typical Characteristics (continued)
VIN = 12 V, VOUT = 1.2 V, TA = 25 ºC, unless otherwise noted.
Series capacitance = 1 µF
2 ms/div
fsw = 2 MHz per phase
0 A Load
fsw = 2 MHz per phase
400 µs/div
Figure 32. Pre-biased Startup Through VIN
Figure 31. Startup Through VIN
75 Ω Load
0.5 Ω Load
4 ms/div
Figure 34. Shutdown Through VIN
Figure 33. Shutdown Through VIN
fsw = 2 MHz per phase
20 µs/div
2 µs/div
Figure 35. Short Circuit Protection
4 ms/div
Figure 36. Short Circuit Hiccup Restart
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Typical Characteristics (continued)
VIN = 12 V, VOUT = 1.2 V, TA = 25 ºC, unless otherwise noted.
3.2 MHz SYNC clock
fsw = 2 MHz per phase
0 A load
200 ns/div
Figure 38. External SYNC Add/Remove
Figure 37. Steady-State Waveforms
Figure 39. Thermal Shutdown
Figure 40. Thermal Shutdown Recovery
Room temperature
fsw = 2 MHz per phase
10 A load
3.2 x 2.5 x 1.2 mm inductors
No air flow
Four layer board
Figure 41. Thermal Image
14
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7 Detailed Description
7.1 Overview
The TPS54A20 is a 14-V, 10-A, synchronous series capacitor step-down (buck) converter with four integrated Nchannel MOSFETs. To improve performance during line and load transients the TPS54A20 implements an
adaptive on-time control scheme which does not require external compensation components. The selectable
switching frequencies are 2 MHz, 3.5 MHz, or 5 MHz per phase which allows for efficiency and size optimization
when selecting the output filter components. A resistor to ground on the TON pin sets the nominal high side
switch on-time based on the desired output voltage.
The TPS54A20 contains an internal oscillator for steady-state, fixed frequency operation that is set through the
SS/FSEL pin. The controller operates at twice the per phase switching frequency (that is, 4 MHz, 7 MHz, or 10
MHz) and the oscillator is set accordingly. An external synchronization clock can also be provided via the SYNC
pin.
The TPS54A20 starts up safely into loads with pre-biased outputs (non-zero volts at startup). The device
implements an internal under voltage lockout (UVLO) feature on the VIN pin with a nominal starting voltage of
7.65 V. The total operating current for the TPS54A20 is approximately 6 mA when not switching and under no
load. When the TPS54A20 is disabled by pulling the EN pin low, the supply current is typically less than 50 µA.
The integrated MOSFETs allow for high-efficiency, high-density power supply designs with continuous output
currents up to 10 A. The MOSFETs are sized to optimize efficiency for low duty cycle applications operating
around 2 MHz per phase switching frequency.
The TPS54A20 reduces the external component count by integrating the bootstrap recharge circuit. Capacitors
connected between the BOOTA/BOOTB and SCAP/SWB pins (respectively) supply the gate drive voltage for the
integrated high-side MOSFETs. The output voltage can be stepped down to as low as the 0.5-V voltage
reference (VREF).
The TPS54A20 has a power good comparator (PGOOD) which monitors the output voltage through the FB pin.
The PGOOD pin is an open-drain MOSFET which is pulled low when the FB pin voltage is less than 95% or
greater than 105% of the reference voltage (VREF). The PGOOD pin floats (de-asserted) when the FB pin voltage
is between 95% to 105% of VREF. The PGOOD pin is held low during startup or when a fault occurs.
The EN pin is used to provide power supply sequencing during power up. Soft start times for each frequency can
be selected through the SS/FSEL pin. Soft start helps to minimize inrush currents.
The device current limit can be set via the ILIM pin. Two selectable current limits are provided.
The control scheme implemented is an adaptive on-time control. The on-time is adjusted based on input voltage
and oscillator frequency. An internal phase lock loop (PLL) ensures fixed-frequency operation of the converter
over the entire load range and adapts the on-time accordingly.
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7.2 Functional Block Diagram
SS/FSEL
VG-
VIN
VG+
Regulator
BOOTB BOOTA
VGA
4.8V
Regulator
SYNC
Oscillator
VIN
Pulse Freq.
Detector
VIN
TON
Input Voltage
Feedforward
SCAP
On-time
Generator
Error
Amplifier
Switching
Signal Logic
and
Deadtime
Control
Protection
and
Supervisory
Circuits
SWB
PGND
SWA
AGND
FB
PGOOD
EN
ILIM
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7.3 Feature Description
7.3.1 Frequency Selection
The oscillator frequency of this converter can be selected to be one of three options: 4, 7, or 10 MHz. The per
phase switching frequency of the converter is half the oscillator frequency (that is, 2, 3.5, or 5 MHz per phase).
The internal oscillator frequency is selected by programming the SS/FSEL pin. The resistor programming
information is shown in Table 1. The frequency setting is latched in at power up and cannot be changed during
operation. Cycling the input power or the EN pin will reset the frequency setting.
7.3.2 External Clock Syncronization
An external clock can be connected to the SYNC pin. The external clock signal overrides the internal oscillator
and is used as the system clock. This feature enables the user to synchronize the switching events to a master
clock on their board and reduce/manage the ripple on the input capacitors. The internal phase locked loop (PLL)
has been implemented to allow synchronization at frequencies between ±10% of the nominal oscillator frequency
programmed on the SS/FSEL pin. This allows the user to easily switch from the internal oscillator mode to the
external clock mode. Before the external clock is present or after it is removed, the device with default to the
internal oscillator setting as programmed on the SS/FSEL pin.
To implement the synchronization feature, connect a square wave clock signal to the SYNC pin with a duty cycle
between 20% and 80%. The clock signal amplitude must transition lower than 0.8 V and higher than 2 V. The
start of the switching cycle is synchronized to the rising edge of the SYNC pin. The device can be configured for
operation in applications where both an internal oscillator mode and an external synchronization clock mode are
needed. Before the external clock is present, the device functions with the internal oscillator and the switching
16
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Feature Description (continued)
frequency is set by the RSS/FSEL resistor. When the external clock is present, the SYNC mode overrides the
internal oscillator. The first time the SYNC pin is pulled above the SYNC high threshold (2 V), the device
switches from the internal oscillator mode to the SYNC mode and the PLL starts to lock onto the frequency of the
external clock. When the external SYNC clock is removed, the converter will transition back to the internal
oscillator after 4 internal clock cycles.
7.3.3 Adjusting the Output Voltage
The output voltage is set by connecting a resistor divider network from the output voltage to the FB pin of the
device and to AGND. It is recommended that the lower divider resistor maintain a range between 1 kΩ and 10
kΩ. To change the output voltage of a design, it is necessary to select the value of the upper resistor. Equation 2
can be used to select the upper resistor. Selecting the value of the upper resistor can change the output voltage
between 0.508 V and 2 V. The minimum output setpoint voltage cannot be less than the reference voltage of
0.508 V. The maximum output voltage can be limited by minimum input voltage as shown in Figure 24. The
recommended minimum input voltage should be at least five times the output voltage as shown in Figure 25.
This is due to the nature of the series capacitor buck converter.
7.3.4 Soft Start
Soft start is an important feature that limits current inrush into the converter and reduces the load on the bus
converter that supplies this device. During soft start, the internal reference voltage is slowly ramped up to the
nominal internal reference voltage (~0.5 V). This slowly increases the commanded output voltage of the
converter and reduces the initial surge in current. PGOOD remains low during soft start, the PLL is not active,
and output UVP/OVP faults are disabled. After the soft start interval is complete, the converter operates with
normal operating conditions and PGOOD will no longer be held low when the output is within bounds.
Soft-start time is programmed with an external resistor on SS/FSEL pin (or by shorting to ground or by leaving
the pin open). There are multiple soft-start time options per operating frequency available to the user through the
SS/FSEL pin. The soft-start setting is latched in at power up or when the EN pin voltage is set high. Resistors
used for programing the SS/FSEL pin must have ±1% or lower tolerance. The following frequencies and soft start
times can be programmed on the SS/FSEL pin.
Table 1. Frequency and Soft Start Resistor Selection
RSS/FSEL (kΩ)
FOSC (MHz)
FSW (MHz)
Soft Start Time
(µs)
Hiccup Time (ms)
71.5
4
2
64
32.8
Open
4
2
512
32.8
48.7
4
2
4096
32.8
35.7
7
3.5
36.6
18.7
Short
7
3.5
293
18.7
21.5
10
5
25.6
13.1
15.4
10
5
205
13.1
8.66
10
5
1638
13.1
7.3.5 Startup into Pre-biased Outputs
The device prevents the low-side MOSFETs from discharging a pre-biased output. During pre-biased startup, the
low-side MOSFETs do not turn on until after the phase A high-side MOSFET has started switching. The highside MOSFETs do not start switching until the internal soft-start reference voltage exceeds the voltage at the FB
pin. It is required to first apply the gate driver supply voltage (VG+) before starting up into pre-biased loads.
Alternatively, 6.8 µF bypass capacitance or more can be used.
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7.3.6 Power Good (PGOOD)
The Power Good (PGOOD) pin is an open drain output. After startup when the FB pin is typically between 95%
and 105% of the internal voltage reference, the PGOOD pin pull-down is de-asserted and the pin floats. It is
recommended to use a pullup resistor between the values of 10 kΩ and 100 kΩ to a voltage source that is 5.5 V
or less. The PGOOD is in a defined state once the VIN input voltage is greater than approximately 1.2 V but with
reduced current sinking capability. The PGOOD achieves full current sinking capability once the VIN input
voltage is above the input UVLO. The PGOOD pin is pulled low when the FB pin voltage is typically lower than
95% or greater than 105% of the nominal internal reference voltage. A resistor-capacitor (RC) filter can be
connected to the PGOOD pin to filter out PGOOD being pulled low during large load transients if low output
capacitance is used. The PGOOD pin is also pulled low if a fault is detected, the EN pin is pulled low, or the
converter is performing its soft-start power up sequence.
7.3.7 Overcurrent Protection
The device protects itself from an overcurrent condition by a current limit detector. The device senses inductor
currents using the low side MOSFETs. After three sequential overcurrent measurements are made (in phase A
or B), the over current flag is triggered, the converter switches are turned off, and PGOOD is pulled low. The
converter attempts to restart after a hiccup interval counter has expired (that is, 32.8 ms, 18.7 ms, or 13.1 ms
when in 4 MHz, 7 MHz, or 10 MHz mode, respectively). This provides a hiccup response to an overcurrent
condition.
The two overcurrent trip points are based on two full load applications of 7.5 A or 10 A. The overcurrent trip
points correspond to the load demanding 1.5 times the full load current (11.25 A and 15 A, respectively). This
provides enough margin for brief overshoots in inductor currents during a load transient while at the same time
protecting against short circuits or other potentially catastrophic faults on the output. The table below lists the
resistor values for programming the ILIM pin to select the desired overcurrent limit. Programming resistors with
up to ±5% variation can be used. The current limit selection is latched in at power up and cannot be changed
without cycling power input or the EN pin voltage.
Table 2. Current Limit Selection
RILIM (kΩ)
Load Current Limit (A)
Open
15
47
11.25
7.3.8 Light Load Operation
The converter operates in forced continuous conduction mode (FCCM) under light load conditions. When
operating in FCCM, the high side and low side MOSFETs are turned on and off in a complementary fashion and
negative inductor current is allowed for part of the switching cycle. The switching frequency remains constant in
FCCM.
7.3.9 Output Undervoltage/Overvoltage Protection
The device incorporates an output undervoltage/overvoltage protection (UVP/OVP) circuit to prevent damage to
the load. This fault can be triggered during large, fast load transients if insufficient output capacitance is used.
The UVP/OVP feature compares the FB pin voltage to internal thresholds. If the FB pin voltage is lower than
90% or greater than 110% of the nominal internal reference voltage, the converter is turned off (i.e. power
MOSFETs are turned OFF), a fault is triggered, and the PGOOD pin is pulled low. When the fault hiccup interval
is complete, the converter will attempt to restart.
7.3.10 Input Undervoltage/Overvoltage Lockout
The device incorporates an input undervoltage/overvoltage lockout (UVLO/OVLO) circuit. The converter will not
operate if the input voltage is below the UVLO threshold. The OVLO circuit protects the converter if the input bus
voltage flies higher than the input voltage rating of the device while it is switching. When the input voltage
crosses the input rising OVLO trip threshold, the converter turns off all the switches (makes them high
impedance) and PGOOD is pulled low. When the input voltage drops lower than the falling OVLO threshold, the
converter restarts using the normal soft-start sequence. This feature increases the maximum input voltage the
device can sustain without being damaged due to a fault in the system.
18
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7.3.11 Enable and Adjusting Undervoltage Lockout
The EN pin provides electrical on and off control of the device. Once the EN pin voltage exceeds the threshold
voltage, the device starts operation. If the EN pin voltage is pulled below the threshold voltage, the regulator
stops switching and enters a low power state. There is no voltage hysteresis in the EN threshold. The rising and
falling voltage thresholds occur at the same level.
The EN pin has an internal hysteretic current source. This allows the user to float the EN pin for self-enabling the
device or to design the ON and OFF threshold input voltages with a resistor divider at the EN pin. If an
application requires controlling the EN pin, use open drain or open collector output logic to interface with the pin.
The EN pin can be configured as shown in Figure 42. The EN pin has a 1 µA pull-up current iP which sets the
current source value before the start-up sequence. The device includes the second 3 µA current source iH which
is activated when the EN threshold voltage has been exceeded. To achieve clean transitions between the OFF
and ON states, it is recommended that the turn OFF threshold is no less than 7.75 V, and the turn ON threshold
is no less than 8 V on the VIN pin. It is also recommended to set the UVLO hysteresis to be greater than 500mV
in order to avoid repeated chatter during start up or shut down. The value of REN(TOP) and REN(BOT) can be
calculated using Equation 18 and Equation 19 as described in the applications section.
Figure 42. Adjustable VIN Undervoltage Lockout
7.3.12 Series Capacitor Monitoring
The series capacitor voltage is preconditioned and monitored during operation. The series capacitor is located
between the source of the high-side MOSFET and the drain of the low-side MOSFET in Phase A . After the input
voltage is above UVLO and the EN pin is high, the series capacitor is precharged. A 10 mA current source
charges the series capacitor up to half the input voltage. When the series capacitor precharge is complete, the
soft start sequence begins. The delay due series capacitor precharge can be calculated using Equation 1.
C x VIN
t pc = t
2 x I pc
(1)
Here Ct is the series capacitance, Ipc is the precharge current, and VIN is the input voltage.
The voltage monitor is continuously tracking the status of the series capacitor. Its function is to ensure the series
capacitor voltage, measured differentially between the SCAP pin and the SWA pin, stays within predefined
thresholds. These thresholds are relative to the VIN voltage with respect to PGND and set at 35% and 65% of
VIN. If the voltage monitor indicates a voltage outside of these thresholds has occurred, a fault is triggered and
following actions are taken based on which threshold has been crossed.
7.3.12.1 Dropping Below 35% Threshold
The 35% of VIN threshold detects a series capacitor undervoltage fault. Once the 35% threshold is breached, a
fault is triggered, the converter shuts down, and PGOOD is pulled low. After the fault hiccup time is complete, the
converter will start up in the normal manner. The start up sequence begins with pre-charging the series capacitor
to half the input voltage and is followed by the soft start.
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7.3.12.2 Rising Above 65% Threshold
The 65% of VIN threshold indicates a series capacitor overvoltage fault has occurred. Once the 65% threshold is
breached, a fault is triggered, the converter shuts down, PGOOD is pulled low, and an internal bleed resistor is
connected to the SCAP to reduce the series capacitor voltage. After the fault hiccup time is complete, the
converter will start up in the normal manner.
7.3.13 Thermal Shutdown
The die temperature is continuously monitored to ensure it is within limits. The thermal shutdown (TSD) fault is
triggered when the die temperature exceeds the rising temperature threshold. This interrupts switching by making
the switches high impedance. The fault state persists until the die temperature cools down to below the falling
temperature threshold. The converter then automatically goes through the normal soft start sequence.
7.3.14 Phase A Power Stage
Phase A implements a bootstrap driver for the high-side MOSFET, an LDO, a low-side driver and a low-side
current monitor. Additional logic is included to implement deadtime control and overcurrent protection.
An LDO is implemented to manage the high-side bootstrap driver. This LDO is unique to this topology given the
high-side driver is referenced to the SCAP pin and not to the conventional switch node of a buck converter. A
conventional bootstrap circuit will not work because the SCAP pin is never connected to PGND during operation.
The LDO is designed to produce an output voltage at the VGA pin. This allows a nominal enhancement of
around 5V about the VIN rail. The bootstrap capacitor charges when the phase A low side switch is on. An
external decoupling capacitor is required on the VGA pin.
The low-side MOSFET current is monitored using a sense FET configuration. This circuit enables the driver to
monitor the current delivered in Phase A for overcurrent protection. In the case of overcurrent, a fault flag is set if
the current detected exceeds the current limit threshold. Adjustment of this threshold is accomplished via
programming the ILIM pin.
7.3.15 Phase B Power Stage
Phase B implements a bootstrap driver for the high-side MOSFET, a low-side driver and a low-side current
monitor. Additional logic is included to implement deadtime control and overcurrent protection.
No additional LDO function is required for Phase B as the bootstrap capacitor is charged directly from the VG
input rail. A conventional bootstrap circuit is used in phase B.
The overcurrent protection operates in the same manner as Phase A.
7.3.16 Internal Gate Drive Regulator
There is an internal linear regulator that generates a 4.8 V supply rail on the VG+ pin. The input comes from the
VIN pin. The VG+ supply rail is used to power the gate drivers of phase A low side switch and phase B switches.
It also is the input to another regulator that generates the internal supply rails used by the controller. To improve
converter efficiency, an external 5V supply is recommended to be connected to the VG+ pin, thereby overriding
the internal 4.8 V regulator. The VG+ supply requires external decoupling capacitance connected between the
VG+ and VG- pins. The VG- pin must be connected to AGND and PGND. It is recommended to make this
connection directly beneath the device.
7.3.17 Voltage Feed Forward
The input voltage feed forward (VFF) circuit adapts the nominal on-time of the converter in response to changes
in the input voltage. The VFF provides a control signal to the on-time generator based on the value of the resistor
placed on the TON pin and the input voltage.
7.3.18 Internal Oscillator
The internal oscillator provides a default system clock for the converter. The oscillator can be programmed to run
at 4 MHz, 7 MHz, or 10 MHz depending on the resistor connected to the SS/FSEL pin. Synchronization to an
external clock is allowed. If provided, an external synchronization clock signal is passed through to the oscillator
block and bypasses internal oscillator.
20
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7.3.19 Pulse Frequency Detector
The pulse frequency detector is an important block used to create a phase lock loop (PLL). This portion of the
PLL accepts two clock signals and delivers a control signal. The PLL control is held inactive during startup and is
activated once soft start is complete. The control signal is delivered to the on-time generator to make small
adjustments in the on-time such that the frequency and phase of the switching signals match the reference clock
(internal or external SYNC).
7.3.20 On-Time Generator
The on-time generator provides the on-time pulse for high side switches of the converter. The nominal on-time is
programmed from the TON pin. The control signal generated by the VFF circuit is proportional to the on-time
required by the converter and is adjusted for input voltage variation. Fine adjustment of the on-time comes from
pulse frequency detector which enables fixed frequency operation in steady state.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TPS54A20 is a two-phase, synchronous series capacitor buck converter optimized for small size, low
voltage applications from a 12 V input rail. See (SLVA750) for a more detailed introduction to the series capacitor
buck converter topology.
8.1.1 Two-Phase Series Capacitor Buck Converter Topology
The series capacitor buck converter topology uniquely merges a switched capacitor converter and a buck
converter. Only one extra capacitor (the series capacitor) is needed as compared to a conventional two-phase
buck converter. Advantages include automatic current balancing between the inductors (inductor current sensing
and a current sharing loop are not required), lower switching losses which enable high frequency (HF) operation,
and voltage step-down through the series capacitor. The on-time of both high side switches is double that of a
regular buck converter. This is particularly helpful in high frequency, high conversion ratio applications. The
schematic of the converter topology and the converter switch states are shown below.
+
+
La
Ct Vswa
-
Q1a
+
Co
Q2a
Vo
-
-
Q1b
Lb
Vswb
Q2b
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Figure 43. Two-Phase Series Capacitor Buck Converter Topology
8.1.2 Converter Switch Configurations
Q1a
+
-
Vswa
+
+
+
Co
Q2a
+
Vswb
+
Co
Q2a
-
Vo
-
Lb
Q1b
Q2b
Vswb
Lb
Q2b
Copyright © 2016, Texas Instruments Incorporated
Figure 44. Phase A High Side MOSFET On
22
Vswa
Q1a
Vo
Q1b
-
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Figure 45. Phase B High Side MOSFET On
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Application Information (continued)
Vswa
Ct
+
Q1a
+
+
Co
Q2a
Vo
-
Q1b
Lb
Vswb
Q2b
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Figure 46. Phase A/B Low Side MOSFET On
8.2 Typical Application
Vin = 9.2 V - 14 V
VIN
C24
22µF
C1
10µF
C2
10µF
U1 TPS54A20RNJR
PGND
R2
80.6k
VG+
R6
VIN 3
PGOOD 15
SYNC
14
SSFSEL 6
R3
12.4k
R5
22.1k
SYNC
8 BTA
C5
0.047µF
SCAP
SCAP
9
20
SWA
13
EN
C6
2.2µF
SWA
L1
220nH
ILIM
5
ILIM
VGA
7
VGA
TON
19
Vout = 1.2 V, 10 A
BOOTB
10 BTB
VG+
17
VG-
C4
1µF
VOUT
C7
0.047µF
TON
VG+ 16
C9
47µF
L2
SWB
PGND
SCAP
SS/FSEL
4
1
AGND
PGOOD
EN
SCAP 11
PGND
BOOTA
PG
47.5k
C3
1µF
16V
VIN
FB
12
18
C10
47µF
SWB
FB
220nH R9
R10
1.40k
PGND
0
NC
AGND
PGND
2
R8
100
PGND
AGND
C8
330pF
R7
1.00k
AGND
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Figure 47. Typical Application
8.2.1 Design Requirements
Table 3. Design Parameters
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
VOUT
Output voltage
1.2
IOUT
Output current
10
A
ΔVOUT
Transient response
60
mV
VIN
Input voltage
VOUT(ripple)
Output voltage ripple
9-A load step
9.2
12
V
14
V
20
mV(P-P)
V
Start input voltage
Input voltage rising
9.4
Stop input voltage
Input voltage falling
9.2
V
fSW
Switching frequency
2
MHz
TA
Ambient temperature
25
°C
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8.2.2 Detailed Design Procedure
8.2.2.1 Output Voltage
Before beginning design, ensure that the series capacitor buck converter can be used in the application. It is
recommended to use this converter when the minimum input voltage is at least five times greater than the target
output voltage. If this recommendation is not followed, output voltage dropout can occur at heavy load conditions
and poor transient response to load increases can result.
The output voltage is set by connecting a resistor divider network from the output voltage to the FB pin of the
device and to AGND. It is recommended that the lower divider resistor maintain a range between 1 kΩ and 10
kΩ. To change the output voltage of a design, it is necessary to select the value of the upper resistor. The value
of RTOP for a specific output voltage can be calculated using Equation 2.
R (BOT) x (VOUT - VREF )
R (TOP) =
VREF
(2)
For the example design, 1 kΩ was selected for RBOT (R7). Using Equation 2, RTOP (R9) is calculated as 1.4 kΩ. It
is recommended to use resistors with ±1% or less variation.
A capacitor can be connected in parallel with the upper resistor to provide additional phase boost near the
converter's crossover frequency. See (SLVA289) for more details and design guidelines. For this design, 330 pF
in series with 100 Ω is used. The values were optimized based on measured loop performance.
8.2.2.2 Switching Frequency
A key design step is to decide on a switching frequency for the regulator. There is a tradeoff between higher and
lower switching frequencies. Higher switching frequencies may produce a smaller solution size using lower
valued inductors and smaller output capacitors compared to a power supply that switches at a lower frequency.
However, the higher switching frequency creates extra switching loss, which reduces the converter’s efficiency
and thermal performance. In this design, a moderate switching frequency of 2 MHz per phase is selected to
achieve both a small solution size and a high efficiency operation. Refer to Table 1 for the SS/FSEL
programming resistor selection.
8.2.2.3 On-Time
The TON pin requires a resistor to set the nominal on-time and to support the input voltage feedforward circuit.
The resistance value used also influences the internal ramp in the controller. As a starting point, Equation 3 is
recommended for selecting the TON resistor.
R (TON) = 3 k + 15 k x VOUT
(3)
The RTON resistor (R5) is calculated to be 21 kΩ. The selected value for this design example is 22.1 kΩ. During
startup, the converter uses the nominal on-time programmed through TON. The phase lock loop (PLL) is only
activated after startup is complete. When the PLL is engaged, the on-time is adjusted. If the nominal on-time
programmed through the TON pin is not close to the on-time when the PLL is engaged, the SYNC range of the
device may be reduced. The TON resistor can also be adjusted to tune the controller. Lowering the RTON value
will increase the internal ramp height. This will reduce the converter’s sensitivity to noise and jitter but it will also
reduce the transient response capabilities of the converter.
8.2.2.4 Inductor Selection
To calculate the value of the output inductors, use Equation 4. KIND is a coefficient that represents the amount of
inductor ripple current relative to the maximum output current. The inductor ripple current is filtered by the output
capacitor. In general, the inductor ripple value is at the discretion of the designer; however, KIND is normally from
0.1 to 0.4 for the majority of applications.
L =
(
2 x VOUT x VIN(MAX) - 2 x VOUT
)
K (IND) x IOUT x VIN(MAX) x FSW
(4)
For this design example, use KIND = 0.4 and the inductor value is calculated to be 249 nH. For this design, the
nearby standard value of 220 nH was chosen. For the output filter inductor, it is generally recommended that the
RMS current and saturation current ratings not be exceeded. The current ripple, RMS, and peak inductor current
are calculated in Equation 5, Equation 6, and Equation 7.
24
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DI L =
SLVSCQ8A – DECEMBER 2015 – REVISED APRIL 2016
(
2 x VOUT x VIN(MAX) - 2 x VOUT
)
L x VIN(MAX) x FSW
(5)
2
1
æ IOUT ö
2
ç 2 ÷ + 12 x (DI L )
è
ø
IOUT
DI L
=
+
2
2
I L(RMS) =
I L(PEAK)
(6)
(7)
For this design, the RMS inductor current is calculated to be 5.04 A and the peak inductor current is 6.13 A. The
chosen inductor is 220 nH with a saturation current rating of 8.2 A and a dc current rating of 7.6 A.
The current flowing through each inductor is the inductor ripple current plus half the output current. During power
up, faults, or transient load conditions, the inductor current can increase above the peak inductor current level
calculated above. In transient conditions, the inductor current can increase up to the switch current limit of the
device. For this reason, the most conservative approach is to specify an inductor with a saturation current rating
equal to or greater than half the load current limit rather than the peak inductor current in steady state. Many
inductors today have soft saturation characteristics that may be able to ride through a transient that pushes
current beyond the saturation rating specified in the datasheet. An example list of inductors that have been
tested to work with the TPS54A20 are shown in Table 4. Inductors not listed below can also be used with this
device.
Table 4. Example Inductor List
Inductance (nH)
Saturation Current
Rating (A)
Dimensions
[L x W x H] (mm)
220 ±20%
9.3
330 ±20%
7.5
220 ±30%
DCR Typ/Max (mΩ)
Type
Vendor
3.2 x 2.5 x 1.2
9 / 12
HMLW32251B-R22MS
CYNTEC
3.2 x 2.5 x 1.2
13 / 16
HMLW32251B-R33MS
CYNTEC
8.2
3.2 x 2.5 x 1.2
7.5 / 10.5
MLA-FY12NR22N-M3
MAGLAYERS
330 ±30%
7.5
3.2 x 2.5 x 1.2
13.5 / 16
MLA-FY12NR33N-M3
MAGLAYERS
220 ±20%
8.7
3.2 x 2.5 x 1.2
9.4 / 11.6
MCMK3225TR22MG
TAIYO YUDEN
330 ±20%
10.4
3.2 x 2.5 x 1.2
11.2 / 13.8
MCMK3225TR33MG
TAIYO YUDEN
250 ±30%
12
3.2 x 2.5 x 1.5
10 / 12.5
74479290125
WURTH ELECTRONIK
330 ±30%
12.4
4.1 x 4.1 x 2.1
6 / 7.2
744383560033
WURTH ELECTRONIK
220 ±20%
10.1
3.5 x 3.2 x 1.5
7.8 / 8.9
XEL3515-221
COILCRAFT
350 ±20%
8.2
3.5 x 3.2 x 1.5
11.6 / 13.4
XEL3515-351
COILCRAFT
330 ±20%
8.5
2.5 x 2.0 x 1.2
14 / 19
DFE252012F-R33M
TOKO
8.2.2.5 Output Capacitor Selection
For most applications, the primary consideration for selecting the value of the output capacitor is how the
regulator responds to a large change in load current. The output capacitance may also be selected based on
output voltage ripple or closed-loop bandwidth design objectives.
The output capacitance required to maintain an output voltage ripple ΔVOUT during steady-state operation can be
estimated using Equation 8.
DI L
CO >
16 x fSW x DVOUT
(8)
The desired response to a large change in the load current is typically the most stringent criteria. The output
capacitor needs to supply the load with current when the regulator cannot. This situation would occur if there are
desired hold-up times for the regulator where the output capacitor must hold the output voltage above a certain
level for a specified amount of time after the input power is removed. The regulator is also temporarily not able to
supply sufficient output current if there is a large, fast change in the load current such as a transition from no
load to full load. The output capacitor must be sized to supply the extra current to the load until the control loop
responds to the load change. The minimum output capacitance required for a load increase can be estimated
using Equation 9.
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2
CO >
2 x L x (DIOUT )
(VIN
- 4 x VOUT ) x DVOUT
(9)
In low voltage applications, the inductor slew rate during a load step decrease is sometimes slower than its slew
rate during a load step increase. The minimum output capacitance required for a load decrease can be estimated
using Equation 10 for a given tolerable amount of overshoot in the output voltage.
2
CO >
L x (DIOUT )
4 x VOUT x DVOUT
(10)
Here ΔIOUT is the change in output current and ΔVOUT is the allowable change in the output voltage. For this
design example, the transient load response is specified as a 3% change in VOUT for a load step of 5A. For this
example, ΔIOUT = 5 A and ΔVOUT = 0.03 x 1.2 = 0.036 V. Based on these design parameters, a minimum
capacitance of 93 µF is calculated using Equation 9. This value does not take the ESR of the output capacitor
into account in the output voltage change. For ceramic capacitors, the ESR is usually small enough to ignore in
this calculation. Additional capacitance de-ratings for aging, temperature and DC bias should be factored in
which also increases this minimum value. For this design example, two 47 µF, 6.3 V rated, ceramic capacitors
with 3 mΩ of ESR are selected.
8.2.2.6 Input Capacitor Selection
The TPS54A20 requires a high quality ceramic, type X5R or X7R, input decoupling capacitor of at least 4.7 µF of
effective capacitance on the VIN input voltage pin. Additional bulk capacitance may also be required for the VIN
input. The value of a ceramic capacitor varies significantly over temperature and the amount of DC bias applied
to the capacitor. The capacitance variations due to temperature can be minimized by selecting a dielectric
material that is stable over temperature. X5R and X7R ceramic dielectrics are usually selected for power
regulator capacitors because they have a high capacitance to volume ratio and are fairly stable over
temperature. The capacitor must also be selected with the DC bias taken into account. The capacitance value of
a capacitor decreases as the DC bias across a capacitor increases. For this example design, a ceramic capacitor
with at least a 25-V voltage rating is selected to support the maximum input voltage. The input capacitance value
impacts the input ripple voltage of the regulator. The minimum input capacitance can be estimated using
Equation 11.
CIN(MIN) =
(
2 x IOUT x VOUT VIN(MIN) - 2 x VOUT
fSW x V
2
IN(MIN)
)
x DVIN
(11)
Here ΔVIN is the input voltage ripple in steady state. Using the design example values, IOUT = 10 A, VOUT = 1.2 V,
VIN(MIN) = 9 V, FSW = 2 MHz and ΔVIN = 25 mV, Equation 11 yields an input capacitance of 39 µF. For this
example, two 10µF, 25-V and a single 22-µF, 25-V ceramic capacitors in parallel have been selected for the VIN
voltage rail. Because ESR is typically fairly low in ceramic capacitors, it is not included in this calculation.
The capacitor must also have a ripple current rating greater than the maximum input current ripple to the device
during full load. The input ripple current can be calculated using Equation 12.
ICIN( RMS) =
IOUT
x
2
æ
2 x VOUT
2 x VOUT
x ç1 ç
VIN(MIN)
VIN(MIN)
è
ö
÷
÷
ø
(12)
For this example design, the RMS input ripple current is 2.21 A (RMS). The ripple current can be assumed to be
shared equally between the input capacitors.
8.2.2.7 Series Capacitor Selection
A major function of the series capacitor is energy transfer. This is a different role from input and output capacitors
where decoupling is the primary function. In many ways, the series capacitor is similar to the capacitor used for
energy transfer in SEPIC converters and can be designed accordingly. A design objective may be to ensure the
series capacitor voltage ripple does not exceed 5% to 10% of the nominal voltage under the worst case
conditions. The series capacitor voltage ripple is given by Equation 13.
VOUT x IOUT
DV(Ct) =
C t x fsw x VIN(MIN)
(13)
26
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Here Ct is the series capacitance. Equation 13 can be rearranged to provide the design equation for series
capacitor selection which is
2 x VOUT x IOUT
Ct ³
k Ct x fsw x V 2 IN(MIN)
(14)
where kCt represents the voltage ripple percentage. For example, if the voltage ripple target is 5%, the value for
kCt is 0.05. The largest voltage ripple occurs at full load current (highest IOUT), highest duty ratio (lowest input
voltage/highest output voltage), and lowest frequency. For this design example, the value for kCt was selected to
be 0.08. The resulting series capacitance calculated is 1.85 µF. A 10 V, X7R ceramic capacitor with 2.2 µF of
capacitance is selected.
Another aspect to consider is capacitor RMS current rating. This impacts the temperature rise of the capacitor.
Check the capacitor datasheet for temperature rise information. If the temperature rise is too large for a single
capacitor, multiple capacitors may be placed in parallel to share the RMS current. The series capacitor has the
same current profile as the high side MOSFETs. The RMS current squared can be expressed as
I 2Ct(RMS) = 2 x D x I 2 L(RMS)
(15)
where IL(RMS) is the RMS inductor current of either inductor. The series capacitor RMS current can be expressed
as
ICt(RMS) =
æ VOUT
4x ç
ç VIN(MIN)
è
ö éæ IOUT ö2 æ DI L ö2 ù
+ ç
÷ êç
÷ ú
÷ êè 2 ÷ø
è 12 ø úû
øë
(16)
where ΔIL is the inductor current ripple. The largest RMS current occurs at the highest load current and highest
duty ratio.
Multilayer ceramic capacitors (MLCC) are well suited for operating as the series capacitor. The equivalent series
resistance (ESR) is relatively low (for example, 5 mΩ to 10 mΩ) which helps to reduce power loss and self
heating. The equivalent series inductance (ESL) is fairly low which results in a high self resonant frequency
(SRF). There are a few key items that should be considered when designing. First, the effective capacitance
decreases with DC bias. This means that the capacitor should be selected based on its capacitance with the
nominal voltage of VIN/2 applied. Temperature variation also reduces effective capacitance. For this reason, X7R
capacitors with up to 125°C operating temperature range are recommended. If capacitors are not properly
selected, cracking or other failure modes may result.
8.2.2.8 Soft-Start Time Selection
The soft-start time is the amount of time it takes for the output voltage to reach its nominal programmed value
during power up. This is useful if a load requires a controlled voltage slew rate. This is also used if the output
capacitance is very large and would require large amounts of current to quickly charge the capacitor to the
desired output voltage level. The large currents necessary to charge the capacitor may make the TPS54A20
reach the current limit and trigger a fault. Excessive current draw from the input power supply may cause the
input voltage rail to sag. Limiting the output voltage slew rate solves both of these problems. The soft-start time
can be selected using the resistor values listed in Table 1. For the example circuit, the soft-start time is not
critical since the output capacitor value is 94 µF which does not require a large amount of current to charge to
1.2 V. For this example design, the average output current is approximately 220 mA during soft start. The
example circuit has the soft start time set to 512 µs which requires no resistor (open connection) on the SS/FSEL
pin. The average converter output current required to charge the output capacitors to the target output voltage
during soft start can be estimated using Equation 17.
C x VOUT
IOUT,SS = O
t SS
(17)
8.2.2.9 Bootstrap Capacitor Selection
A 0.047 μF ceramic capacitor should be connected between the BOOTA to SCAP pins and between the BOOTB
and SWB pins for proper operation. It is recommended to use a ceramic capacitor with X5R or better grade
dielectric. The capacitor should have 10 V or higher voltage rating.
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8.2.2.10 Gate Drive Capacitor Selection
A 1 μF ceramic capacitor should be connected between VGA and PGND and between the VG+ and VG- pins for
proper operation. It is recommended to use a ceramic capacitor with X5R or better grade dielectric. The VGA
capacitor should have 16 V or higher voltage rating and the VG+ capacitor should have 10 V or higher voltage
rating.
8.2.2.11 Under Voltage Lockout Set Point
The Under Voltage Lock Out (UVLO) set point can be adjusted using an external voltage divider network. The
top resistor is connected between VIN and the EN pin and bottom resistor is connected between EN and GND as
shown in Figure 42. For the example design, the supply should turn on and start switching once the input voltage
increases above 9.4 V (UVLO start or enable). After the regulator starts switching, it should continue to do so
until the input voltage falls below 9.2 V (UVLO stop or disable). The resistor values for obtaining the desired
UVLO thresholds can be calculated using Equation 18 and Equation 19. REN,TOP, the top UVLO divider resistor,
is calculated using Equation 18. REN,BOT, the bottom UVLO divider resistor, is calculated in Equation 19.
VIN(RISE) - VIN(FALL)
REN(TOP) =
IEN(FALL) - IEN(RISE)
(18)
REN(BOT) =
REN(TOP) x VEN
VIN(FALL) - VEN + REN(TOP) x IEN(FALL)
(19)
For the start and stop voltages specified the resistor value selected for REN,TOP (R2) is 80.6 kΩ and for REN,BOT
(R3) is 12.4 kΩ.
8.2.2.12 Current Limit Selection
The current limit can be selected using the ILIM pin. Refer to Table 2 for resistor selection information. It is
recommended to choose a current limit that is 1.5 times or more than the full load current expected in the
application. This allows for margin in the inductor currents when responding to load transients and limits
nuisance trips.
28
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8.2.3 Application Curves
90
90
80
80
70
70
Efficiency (%)
100
Efficiency (%)
100
60
50
40
30
60
50
40
30
20
20
VIN = 9V
VIN = 12V
VIN = 14V
10
0
0
1
2
3
4
5
6
Output Current (A)
7
8
9
VIN = 9V
VIN = 12V
VIN = 14V
10
0
0.001
10
Figure 48. Efficiency
1
0.5
0.8
0.4
0.6
0.3
0.4
0.2
0
-0.2
-0.4
2 3 4 5 7 10
D029
0.2
0.1
0
-0.1
-0.2
-0.6
-0.3
-0.8
-0.4
-1
-0.5
0
1
2
3
4
5
6
Output Current (A)
7
8
9
10
9
10
D030
Figure 50. Load Regulation
60
180
50
150
40
120
30
90
20
60
10
30
0
0
-10
-30
-20
-60
-30
-90
-40
-50
-60
100 200
500 1000
10000
Frequency (Hz)
11
12
Input Voltage (V)
13
14
D031
Figure 51. Line Regulation
-120
Gain (dB)
Phase (Deg) -150
-180
100000
500000
VO = 50 mV / div (ac coupled)
Phase (Degree)
Gain (dB)
1
Figure 49. Light Load Efficiency
Line Regulation (%)
Load Regulation (%)
0.01 0.02 0.05 0.1 0.2 0.5
Output Current (A)
D028
IO = 5 A / div
Load step = 0 A - 9 A, slew rate = 9 A / µsec
D032
Figure 52. Loop Response
Time = 50 µsec / div
Figure 53. Transient Response
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VI = 50 mV / div (ac coupled)
VI = 50 mV / div (ac coupled)
SWA = 5 V / div
SWA = 5 V / div
SWB = 5 V / div
SWB = 5 V / div
Time = 200 nsec / div
Figure 54. No Load Input Voltage Ripple
Time = 200 nsec / div
Figure 55. Full Load Input Voltage Ripple
VO = 20 mV / div (ac coupled)
VO = 20 mV / div (ac coupled)
SWA = 5 V / div
SWA = 5 V / div
SWB = 5 V / div
SWB = 5 V / div
Time = 200 nsec / div
Figure 56. No Load Output Voltage Ripple
Time = 200 nsec / div
Figure 57. Full Load Output Voltage Ripple
VIN = 10=0 V / div
VIN = 10=0 V / div
EN = 1 V / div
EN = 1 V / div
VO = 500 mV / div
VO = 500 mV / div
Time = 2 msec / div
Figure 58. Start Up with VIN
30
Time = 2 msec / div
Figure 59. Start Up with EN
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VIN = 10=0 V / div
VIN = 10=0 V / div
EN = 1 V / div
EN = 1 V / div
VO = 500 mV / div
VO = 500 mV / div
Time = 2 msec / div
Figure 60. Shut Down with VIN
Time = 2 msec / div
Figure 61. Shut Down with EN
9 Power Supply Recommendations
The TPS54A20 is designed to operate from an input voltage supply range between 8V and 14V. This supply
voltage must be well regulated. Power supplies must be well bypassed for proper electrical performance. This
includes a minimum of one 4.7μF (after de-rating) ceramic capacitor, type X5R or better, from VIN to PGND.
Additional local ceramic bypass capacitance may be required in systems with small input ripple specifications, in
addition to bulk capacitance, if the TPS54A20 device is located more than a few inches away from its input
power supply. In systems with an auxiliary power rail available, the power stage input, VIN, and the gate driver
power input, VG+, may operate from separate input supplies. See the recommendations in the Layout section for
further explanation.
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10 Layout
10.1 Layout Guidelines
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
32
Layout is a critical portion of good power supply design. See Figure 62 and Figure 63 for a PCB layout
example. It may be possible to obtain acceptable performance with alternate PCB layouts, however this
layout has been shown to produce good results and is meant as a guideline.
The IC package design provides several quiet pads for heat removal and enables a tight layout of the board
components.
Place the power components (including input and output capacitors, inductors, the series capacitor, and the
TPS54A20 device) on the solder side of the PCB. To shield and isolate the small signal traces from noisy
power lines, insert and connect at least one inner plane to ground.
All sensitive analog traces and components such as FB, EN, TON, PGOOD, ILIM, and SS/FSEL must be
placed away from high-voltage switching nodes such as SWA, SWB, SCAP, BOOTA, and BOOTB to avoid
coupling. Use internal layers as ground planes and shield the feedback trace from power traces and
components.
Care should be taken to minimize the loop area formed by the input bypass capacitor connections, the VIN
pin, and the ground connections. Place the input capacitors right next to the IC. Use low ESR ceramic
capacitors with X5R or X7R dielectric.
Care should also be taken to minimize the loop area formed by the series capacitor. Place the series
capacitor directly beside the IC. If this guideline is not followed, extra voltage ringing due to parasitic
inductances could occur on the switch nodes and the device could be damaged. Use low ESR ceramic
capacitors with X7R or better dielectric. Ensure the capacitor operating temperature is sufficient. It is
recommended to have at least 125 °C rating.
Place the bootstrap capacitors close to the device to reduce parasitic inductance caused by switching loop
area. Place the BOOTA to SCAP capacitor right next to the device.
Thermal vias should be inserted in the PGND strip and connected to internal ground planes. This aids with
heat removal and ground return current.
The top layer ground area should be connected to the internal ground layer(s) using vias at the input bypass
capacitor, the output filter capacitor and directly under the TPS54A20 device to provide a thermal path from
the exposed thermal pad land to ground.
For operation at full rated load, the top side ground area together with the internal ground planes, must
provide adequate heat dissipating area.
Place the output inductors close to the SWA and SWB pins and keep the switch node area small. This helps
to prevent excessive capacitive coupling, reduce electromagnetic interference, and reduce conduction loss.
The output filter capacitor ground should be returned directly to the PGND strip using an inner layer.
The FB pin is sensitive to noise. The feedback resistors should be located as close as possible to the IC and
routed with minimal lengths of trace. Place the feedback resistor network near the device to minimize the FB
trace distance. When operating at 7 MHz or 10 MHz, a resistor (e.g. 10 kΩ) is required in series with the FB
pin to reduce noise coupling and filter out high frequency noise as shown in Figure 62.
Adding a phase boost capacitor in parallel with the top resistor of the output voltage feedback divider is
recommended.
Place the TON resistor directly next to the device. Connect the ground return to the AGND pin.
Place the gate drive capacitor as close as possible to the VG+ and VG- pins. Make the return connection
directly to the VG- pin instead of an inner ground layer. This reduces gate drive loop area.
Place the VGA capacitor next to the VGA pin. Provide a ground via for the capacitor and ensure the loop is
as small as possible.
The no connect (NC) pin should be connected to the trace connecting the SCAP pin to the series capacitor.
This will improve board level reliability.
A snubber can be placed between the switch nodes and ground for effective ringing reduction.
Land pattern and stencil information is provided in the data sheet addendum.
Try to minimize conductor lengths while maintaining adequate width.
It is recommended to experimentally validate all designs before production.
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10.2 Layout Example
Figure 62. Layout Recommendation
Figure 63. Example Converter Layout
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TPS54A20
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Layout Example (continued)
Figure 64. Top Layer of Example Converter Layout
Figure 65. Bottom Layer of Example Converter Layout
34
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TPS54A20
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11 Device and Documentation Support
11.1 Documentation Support
Optimizing Transient Response of Internally Compensated DC-DC Converters, SLVA289.
Introduction to the Series Capacitor Buck Converter, SLVA750.
11.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.3 Trademarks
SWIFT, E2E are trademarks of Texas Instruments.
11.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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14-Nov-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
TPS54A20RNJR
ACTIVE
VQFN-HR
RNJ
20
3000
RoHS & Green
Call TI | NIPDAU
Level-2-260C-1 YEAR
-40 to 125
54A20
Samples
TPS54A20RNJT
ACTIVE
VQFN-HR
RNJ
20
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
54A20
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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