TPS56100PWP

        
   

 SLVS201A − JUNE 1999 − REVISED JULY 1999 D Single-Channel, 5-V Controller D Synchronous-Rectifier Drivers for Greater PWP PACKAGE (TOP VIEW) Than 90% Efficiency IOUT NC OCP VHYST VREFB VSENSE ANAGND SLOWST BIAS LODRV LOHIB DRVGND LOWDR DRV D Useable for All Common DSP Supply D D D D D D Voltages – Popular Output Voltage Options Set With Program Pins EVM Available Ideal for Applications With Current Ranges From 3 A to 30 A. Hysteretic Control Technique Enables Fast Transient Response — Ideal for ’C6000 or Multiple ’C5000 Applications Low Supply Current − 3 mA in Operation − 90 µA in Standby Power Good Output 28-Pin TSSOP PowerPAD Package 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 PWRGD VP0 VP1 VP2 VP3 VP4 INHIBIT IOUTLO LOSENSE HISENSE BOOTLO HIGHDR BOOT VCC NC − Not Connected description The TPS56100 is a high-efficiency synchronous-buck regulator controller which provides an accurate programmable supply voltage to low-voltage digital signal processors, such as the ‘C6x and ‘C54x DSPs. An internal 5-bit DAC is used to program the reference voltage from 1.3 V to 2.6 V. Higher output voltages can be implemented using an external input resistive divider. The TPS56100 uses a fast hysteretic control method that provides a quick transient response. The propagation delay from the comparator input to the output driver is application example 5V GND 1 2 3 4 5 6 7 VCC HIGHDR BOOTLO BOOT DRV LOWDR DRVGND 1.5 V LOHIB HISENSE IOUTLO LOSENSE 8 LODRV VSENSE ANAGND VREFB VHYST OCP NC IOUT TPS56100 SLOWST BIAS VP4 INHIBIT VP3 VP2 VP1 VP0 PWRGD 28 27 26 25 24 23 22 21 20 19 18 17 16 15 + CVDD DSP 9 10 11 12 13 14 GND Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a trademark of Texas Instruments Incorporated. Copyright  1999, Texas Instruments Incorporated 
 
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 SLVS201A − JUNE 1999 − REVISED JULY 1999 description (continued) less than 300 ns, even at maximum output current. Overcurrent shutdown and crossover protection combine to eliminate destructive faults in the output MOSFETs, thereby protecting the processor during operation. The slowstart current source is proportional to the reference voltage, thereby eliminating variation of the slowstart timing when changes are made to the output voltage. When the output drops to less than 93% of the nominal output voltage, PWRGD will pull the open-drain output low. The overvoltage circuit will disable the output drivers if the output voltage rises more than 15% above the nominal output voltage. The TPS56100 also includes an inhibit input to control power sequencing and undervoltage lockout thereby insuring the 5-V supply is within limits before the controller starts. The 2-A MOSFET drivers can power multiple MOSFETs in parallel to drive single or multiple DSPs and load currents up to 30 A. The high-side driver can be configured as a ground-referenced driver or as a floating bootstrap driver with the included internal bootstrap Schottky diode. The TPS56100 is available in a 28-pin TSSOP PowerPAD package, which increases thermal efficiency and eliminates bulky heat sinks. AVAILABLE OPTIONS PACKAGES TJ TSSOP† (PWP) EVM 0°C to 125°C TPS561000PWP TPS56100EVM−128 † The PWP package is also available taped and reel. To order, add an R to the end of the part number (e.g., TPS561000PWPR). 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 22 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Bandgap SLOWST OCP INHIBIT 27 − + 26 Deglitch Deglitch 25 23 IVREFB 5 5 + − VREF Q 15 6 Fault 7 + − + − Hysteresis Comp Shutdown HIGHIN 28 PWRGD Slowstart Comp VPGD 0.93 Vref Shutdown CM Filters ANAGND VHYST VSENSE 4 Hysteresis Setting Analog Bias R S UVLO VSENSE NOCPU VP3 VP4 VREFB 24 VP MUX and Decoder Shutdown VOVP 1.15 Vref VP0 VP1 VP2 8 + 100 mV VCC 3.6 V 2V 11111 Decode VCC LOHIB 11 20 LOSENSE Analog Bias LODRV 10 Rising Edge Delay 21 + − 19 1 HIGHDR BOOT DRV BIAS IOUT 12 13 DRVGND LOWDR 200 kΩ 18 BOOTLO 17 16 14 9 HIGHDR 2x 200 kΩ IOUTLO HISENSE functional block diagram I VREFB VP0 VP1 VP2 VP3 VP4
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 SLVS201A − JUNE 1999 − REVISED JULY 1999 Terminal Functions TERMINAL NAME NO. I/O DESCRIPTION ANAGND 7 I Analog ground BIAS 9 I Analog BIAS pin. This terminal must be connected to 5-V supply voltage. A 1-µF ceramic capacitor should be connected from BIAS to ANAGND. BOOT 16 I Bootstrap. Connect a 1-µF low-ESR capacitor from BOOT to BOOTLO. BOOTLO 18 I Bootstrap low. Connect BOOTLO to the junction of the high-side and low-side FETs for floating drive configuration. Connect BOOTLO to PGND for ground reference drive configuration. DRV 14 I Drive bias for the FET drivers. This terminal must be connected to 5-V supply voltage. A 1-µF ceramic capacitor should be connected from DRV to DRVGND. DRVGND 12 I Drive ground. Ground for FET drivers. Connect to FET PWRGND. HIGHDR 17 O High drive. Output drive to high-side power switching FETs HISENSE 19 I High current sense. For current sensing across high-side FETs, connect to the drain of the high-side FETs; for optional resistor sensing scheme, connect to power supply side of current-sense resistor placed in series with high-side FET drain. INHIBIT 22 I Disables the drive signals to the MOSFET drivers. IOUT 1 O Current out. Output voltage on this pin is proportional to the load current as measured across the Rds(on) of the high-side FETs. The voltage on this pin equals 2×Rds(on)×IOUT. In applications where very accurate current sensing is required, a sense resistor should be connected between the input supply and the drain of the high-side FETs. IOUTLO 21 O Current sense low output. This is the voltage on the LOSENSE pin when the high-side FETs are on. A ceramic capacitor should be connected from IOUTLO to HISENSE to hold the sensed voltage while the high-side FETs are off. Capacitance range should be between 0.033 µF and 0.1 µF. LODRV 10 I Low drive enable. Normally tied to 5 V. To activate the low-side FETs as a crowbar, pull LODRV low. LOHIB 11 I Low side inhibit. Connect to the junction of the high and low side FETs to control the anti-cross-conduction and eliminate shoot-through current. Disabled when configured in crowbar mode. LOSENSE 20 I Low current sense. For current sensing across high-side FETs, connect to the source of the high-side FETs; for optional resistor sensing scheme, connect to high-side FET drain side of current-sense resistor placed in series with high-side FET drain. LOWDR 13 O Low drive. Output drive to synchronous rectifier FETs NC 2 OCP 3 I Over current protection. Current limit trip point is set with a resistor divider between IOUT and ANAGND. PWRGD 28 O Power good. Power Good signal goes high when output voltage is within 7% of voltage set by VID pins. Open-drain output. SLOWST 8 O Slow Start (soft start). A capacitor from SLOWST to ANAGND sets the slowstart time. Slowstart current = IVREFB/5 VCC 15 I 5-V supply. A 1-µF ceramic capacitor should be connected from VCC to DRVGND. VHYST 4 I HYSTERESIS set pin. The hysteresis is set with a resistor divider from VREFB to ANAGND. The hysteresis window = 2 × (VREFB – VHYST) VP0 27 I Voltage programming input 0 VP1 26 I Voltage programming input 1 VP2 25 I Voltage programming input 2 VP3 24 I Voltage programming input 3 VP4 23 I Voltage programming input 4. Digital inputs that set the output voltage of the converter. The code pattern for setting the output voltage is located in Table 1. Internally pulled up to 5 V. VREFB 5 O Buffered reference voltage from VP network VSENSE 6 I Voltage sense Input. To be connected to converter output voltage bus to sense and control output voltage. It is recommended that an RC low pass filter be connected at this pin to filter noise. 4 Not connected POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 
        
   

 SLVS201A − JUNE 1999 − REVISED JULY 1999 detailed description VREF The reference/voltage programming (VP) section consists of a temperature-compensated bandgap reference and a 5-bit voltage selection network. The 5 VP terminals are inputs to the VP selection network and are TTL-compatible inputs internally pulled up to 5 V. The VP codes conform to the Intel VRM 8.3 DC-DC Converter Specification for voltage settings between 1.8 V and 2.6 V, and they are decremented by 50 mV, down to 1.3 V, for the lower VP settings. Voltages higher than VREF can be implemented using an external resistive divider. Refer to Table 1 for the VP code settings. The output voltage of the VP network, VREF, is within ±1.5% of the nominal setting over the VP range of 1.3 V to 2.6 V, including a junction temperature range of 0°C to +125°C. The output of the reference/VP network is indirectly brought out through a buffer to the VREFB pin. The voltage on this pin will be within 2% of VREF. It is not recommended to drive loads with VREFB, other than setting the hysteresis of the hysteretic comparator, because the current drawn from VREFB sets the charging current for the slowstart capacitor. Refer to the slowstart section for additional information. hysteretic comparator The hysteretic comparator regulates the output voltage of the synchronous-buck converter. The hysteresis is set by 2 external resistors and is centered about VREF. The 2 external resistors form a resistor divider from VREFB to ANAGND, with the output voltage connecting to the VHYST pin. The hysteresis of the comparator will be equal to twice the voltage difference between the VREFB and VHYST pins. The propagation delay from the comparator inputs to the driver outputs is 300 ns (maximum). The maximum hysteresis setting is 60 mV. low-side driver The low-side driver is designed to drive low-Rds(on) n-channel MOSFETs. The current rating of the driver is 2 A, source and sink. The bias to the low-side driver is derived from DRV. high-side driver The high-side driver is designed to drive low-Rds(on) n-channel MOSFETs. The current rating of the driver is 2 A, source and sink. The high-side driver can be configured either as a ground-referenced driver or as a floating bootstrap driver. When configured as a floating driver, the bias voltage to the driver is developed from DRV. The internal bootstrap diode connected between the DRV and BOOT pins is a Schottky for improved drive efficiency. The maximum voltage that can be applied between BOOT and DRVGND is 30 V. The driver can be referenced to ground by connecting BOOTLO to DRVGND, and connecting BOOT to a voltage supply. deadtime control Deadtime control prevents shoot-through current from flowing through the main power FETs during switching transitions by actively controlling the turnon times of the MOSFET drivers. The high-side driver is not allowed to turn on until the gate-drive voltage to the low-side FETs is below 2 V; the low-side driver is not allowed to turn on until the voltage at the junction of the high-side and low-side FETs (Vphase) is below 2 V. current sensing Current sensing is achieved by sampling and holding the voltage across the high-side power FETs while the high-side FETs are on. The sampling network consists of an internal 85-Ω switch and an external ceramic hold capacitor. Recommended value of the hold capacitor is between 0.033 µF and 0.1 µF. Internal logic controls the turnon and turnoff of the sample/hold switch such that the switch does not turn on until the Vphase voltage transitions high, and the switch turns off when the input to the high-side driver goes low. The sampling will occur only when the high-side FETs are conducting current. The voltage on the IOUT pin equals 2 times the sensed high-side voltage. In applications where a higher accuracy in current sensing is required, a sense resistor can be placed in series with the high-side FETs, and the voltage across the sense resistor can be sampled by the current sensing circuit. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 
        
   

 SLVS201A − JUNE 1999 − REVISED JULY 1999 detailed description (continued) inhibit INHIBIT is a TTL-compatible digital input used to enable the controller. When INHIBIT is low, the output drivers are low and the slowstart capacitor is discharged. When INHIBIT goes high, the short across the slowstart capacitor is released and normal converter operation begins. The 5-V supply must be above UVLO thresholds before the controller is allowed to start up. The inhibit start threshold is 2.1 V and the hysteresis is 100 mV for the INHIBIT comparator. VCC undervoltage lockout (UVLO) The undervoltage lockout circuit disables the controller while the VCC supply is below the 4-V start threshold during power up. When the controller is disabled, the output drivers will be low and the slowstart capacitor is discharged. When VCC exceeds the start threshold, the short across the slowstart capacitor is released and normal converter operation begins. There is a 0.5-V hysteresis in the undervoltage lockout circuit for noise immunity. slowstart The slowstart circuit controls the rate at which VO powers up. A capacitor is connected between SLOWST and ANAGND and is charged by an internal current source. The current source is proportional to the reference voltage, so that the charging rate of CSLOWST is proportional to the reference voltage. By making the charging current proportional to VREF, the power-up time for VO will be independent of VREF. Thus, CSLOWST can remain the same value for all VP settings. The slowstart charging current is determined by the following equation: Islowstart = I(VREFB) / 5 (amps) Where I(VREFB) is the current flowing out of VREFB. It is recommended that no additional loads be connected to VREFB, other than the resistor divider for setting the hysteresis voltage. The maximum current that can be sourced by the VREFB circuit is 500 µA. The equation for setting the slowstart time is: tSLOWST = 5 × CSLOWST × RVREFB (seconds) Where RVREFB is the total external resistance from VREFB to ANAGND. power good The power-good circuit monitors for an undervoltage condition on VO. If VO is 7% below VREF, then the PWRGD pin is pulled low. PWRGD is an open-drain output. overvoltage protection The overvoltage protection (OVP) circuit monitors VO for an overvoltage condition. If VO is 15% above VREF, then a fault latch is set and both output drivers are turned off. The latch will remain set until VCC goes below the undervoltage lockout value or INHIBIT is low. A 3-µs deglitch timer is included for noise immunity. Refer to the LODRV section for information on how to protect the microprocessor against overvoltages due to a shorted high-side power FET. 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 
        
   

 SLVS201A − JUNE 1999 − REVISED JULY 1999 detailed description (continued) overcurrent protection The overcurrent protection (OCP) circuit monitors the current through the high-side FET. The overcurrent threshold is adjustable with an external resistor divider between IOUT and ANAGND, with the divider voltage connected to the OCP pin. If the voltage on OCP exceeds 100 mV, then a fault latch is set and the output drivers are turned off. The latch will remain set until VCC goes below the undervoltage lockout value and back up above 3.6 V or INHIBIT is similarly brought below its stop threshold and back above its start threshold. A 3-µs deglitch timer is included for noise immunity. The OCP circuit is also designed to protect the high-side power FET against a short-to-ground fault on the terminal common to both power FETs. LODRV The LODRV circuit is designed to protect the microprocessor against overvoltages that can occur if the high-side power FETs become shorted. External components sensing an overvoltage condition are required to use this feature. When an overvoltage fault occurs, the low-side FETs are used as a crowbar. LODRV is pulled low and the low-side FET will be turned on, overriding all control signals inside the TPS5210 controller. The crowbar action will short the input supply to ground through the faulted high-side FETs and the low-side FETs. A fuse in series with Vin should be added to disconnect the short circuit. Table 1. Voltage Programming Codes VP TERMINALS (0 = GND, 1 = floating or pull-up to 5 V) VREF VP4 VP3 VP2 VP1 VP0 (Vdc) 0 1 1 1 1 1.30 0 1 1 1 0 1.35 0 1 1 0 1 1.40 0 1 1 0 0 1.45 0 1 0 1 1 1.50 0 1 0 1 0 1.55 0 1 0 0 1 1.60 0 1 0 0 0 1.65 0 0 1 1 1 1.70 0 0 1 1 0 1.75 0 0 1 0 1 1.80 0 0 1 0 0 1.85 0 0 0 1 1 1.90 0 0 0 1 0 1.95 0 0 0 0 1 2.00 0 0 0 0 0 2.05 1 1 1 1 1 No CPU 1 1 1 1 0 2.10 1 1 1 0 1 2.20 1 1 1 0 0 2.30 1 1 0 1 1 2.40 1 1 0 1 0 2.50 1 1 0 0 1 2.60 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 
        
   

 SLVS201A − JUNE 1999 − REVISED JULY 1999 Table 1. Voltage Programming Codes (Continued) VP TERMINALS (0 = GND, 1 = floating or pull-up to 5 V) VREF VP4 VP3 VP2 VP1 VP0 (Vdc) 1 1 0 0 0 2.60 1 0 1 1 1 2.60 1 0 1 1 0 2.60 1 0 1 0 1 2.60 1 0 1 0 0 2.60 1 0 0 1 1 2.60 1 0 0 1 0 2.60 1 0 0 0 1 2.60 1 0 0 0 0 2.60 absolute maximum ratings over operating virtual junction temperature (unless otherwise noted)† Supply voltage range, VCC (see Note1), BIAS, DRV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 7 V Input voltage range: BOOT to DRVGND (High-side Driver ON) . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 30 V BOOT to HIGHDRV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 15 V BOOT to BOOTLO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 15 V INHIBIT, VPx, LODRV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 7.3 V PWRGD, OCP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 7 V LOHIB, LOSENSE, IOUTLO, HISENSE . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 7 V VSENSE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 5 V Voltage difference between ANAGND and DRVGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±0.5 V Output current, VREFB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 mA Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table Operating virtual junction temperature range, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 125°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C Lead temperature soldering 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . 260°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: Unless otherwise specified, all voltages are with respect to ANAGND. DISSIPATION RATING TABLE 8 PACKAGE TA ≤ 25°C POWER RATING DERATING FACTOR ABOVE TA = 25°C TA = 70°C POWER RATING TA = 85°C POWER RATING PWP 1150 mW 11.5 mW/°C 630 mW 460 mW POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 
        
   

 SLVS201A − JUNE 1999 − REVISED JULY 1999 recommended operating conditions MIN MAX UNIT Supply voltage, VCC Input voltage, BOOT to DRVGND 4.5 6 V 0 28 V Input voltage, BOOT to BOOTLO 0 13 V Input voltage, INHIBIT, VPx, LODRV, PWRGD, OCP 0 6 V Input voltage, LOHIB, LOSENSE, IOUTLO, HISENSE, BIAS, DRV 0 6 V Input voltage, VSENSE 0 4.5 V Voltage difference between ANAGND and DRVGND Output current, VREFB† 0 ±0.2 V 0 0.4 mA † Not recommended to load VREFB other than to set hystersis since IVREFB sets slowstart time. electrical characteristics over recommended operating virtual junction temperature range, VCC = 5 V (unless otherwise noted) reference/voltage programming PARAMETER VREF Cumulative voltage reference accuracy VPx High-level input voltage VPx Low-level input voltage TEST CONDITIONS MIN VCC = 4.5 to 5.5 V, 1.3 V ≤ VREF ≤ 2.6 V, See Note 2 TYP −1.5% MAX 1.5% 2.25 V 1 Output voltage VREFB IVREFB = 50 µA Output regulation 10 µA ≤ IO ≤ 500 µA VPx Input pullup resistance VREF−10 mV UNIT VREF VREF+10 mV V V 2 mV 190 kΩ NOTES: 2. Cumulative reference accuracy is the combined accuracy of the reference voltage and the input offset voltage of the hysteretic comparator. Cumulative accuracy equals the average of the high-level and low-level thresholds of the hysteretic comparator. 3. This parameter is ensured by design and is not production tested. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 
        
   

 SLVS201A − JUNE 1999 − REVISED JULY 1999 electrical characteristics over recommended operating virtual junction temperature range, VCC = 5 V (unless otherwise noted) (continued) power good PARAMETER TEST CONDITIONS Undervoltage trip threshold VOL IOH Low-level output voltage Vhys Hysteresis voltage MIN 90 IO = 2.5 mA VPWRGD = 5 V High-level input current TYP 93 0.4 MAX UNIT 95 %VREF V 0.75 1 µA 3 %VREF slowstart PARAMETER TEST CONDITIONS Charge current VSLOWST = 0.5 V, IVREFB = 65 µA Discharge current VSLOWST = 1 V VVREFB = 1.3 V, Comparator input offset voltage Comparator input bias current MIN TYP MAX UNIT 10.4 13 15.6 µA 3 mA −18 See Note 3 18 10 Comparator hysteresis −8.5 mV 100 nA 8.5 mV NOTE 3: This parameter is ensured by design and is not production tested. hysteretic comparator PARAMETER TEST CONDITIONS Input offset voltage See Note 3 Input bias current See Note 3 Hysteresis accuracy VREFB – VHYST = 15 mV (Hysteresis window = 30 mV) MIN TYP −4 4 −5 Maximum hysteresis setting VREFB – VHYST = 30 mV NOTE 3: This parameter is ensured by design and is not production tested. MAX UNIT mV 500 nA 5 mV 60 mV thermal shutdown PARAMETER TEST CONDITIONS TYP MAX UNIT See Note 3 160 °C Hysteresis See Note 3 10 °C NOTE 3: This parameter is ensured by design and is not production tested. 10 MIN Over temperature trip point POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 
        
   

 SLVS201A − JUNE 1999 − REVISED JULY 1999 electrical characteristics over recommended operating virtual junction temperature range, VCC = 5 V (unless otherwise noted) (continued) high-side VDS sensing PARAMETER TEST CONDITIONS MIN Gain Sink current VHISENSE = 5 V, VIOUTLO = 5 V VLOSENSE = 4.5 V VHISENSE = 5 V, IOUT Source current VIOUT = 0.5 V, VIOUTLO = 4.5 V IOUT Sink current VIOUT = 0.05 V, VHISENSE = 5 V, VIOUTLO = 5 V Output voltage swing VHISENSE = 4.5 V, RIOUT = 10 kΩ VHISENSE = 3 V, RIOUT = 10 kΩ High-level input voltage LOSENSE MAX 2 Initial accuracy IOUTLO TYP Low-level input voltage Sample/hold resistance 194 V/V 206 mV 250 nA 500 µA 50 µA 0 1 V 0 0.75 V 2.85 V VHISENSE = 4.5 V (see Note 3) 4.5 V ≤ VHISENSE ≤ 5.5 V, LOSENSE connected to HISENSE, VHISENSE − VIOUTLO = 0.15 V 3 V ≤ VHISENSE ≤ 3.6 V, LOSENSE connected to HISENSE, VHISENSE − VIOUTLO = 0.15 V VHISENSE = 5.5 V to 3 V, VHISENSE − VOUTLO = 100 mV NOTE 3. This parameter is ensured by design and is not production tested. CMRR UNIT 2.4 62 85 V 123 Ω 67 95 62 65 144 dB inhibit MIN TYP MAX UNIT Start threshold PARAMETER TEST CONDITIONS 1.85 2.1 2.35 V Hysteresis 0.08 0.1 0.14 V Stop threshold 1.76 V overvoltage protection PARAMETER TEST CONDITIONS Overvoltage trip threshold Hysteresis MIN TYP 112 115 See Note 3 10 MAX UNIT 120 %VREF mV NOTE 3: This parameter is ensured by design and is not production tested. overcurrent protection PARAMETER TEST CONDITIONS OCP trip threshold Input bias current POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MIN TYP MAX UNIT 80 100 125 mV 100 nA 11 
        
   

 SLVS201A − JUNE 1999 − REVISED JULY 1999 electrical characteristics over recommended operating virtual junction temperature range, VCC = 5 V (unless otherwise noted) (continued) deadtime PARAMETER TEST CONDITIONS High-level input voltage LOHIB LOWDR MIN TYP MAX UNIT 2.4 Low-level input voltage 1.33 High-level input voltage See Note 3 Low-level input voltage See Note 3 V 2.38 1.23 V NOTE 3: This parameter is ensured by design and is not production tested. LODRV PARAMETER TEST CONDITIONS High-level input voltage LODRV MIN TYP MAX UNIT 1.70 Low-level input voltage 0.95 V input undervoltage lockout PARAMETER 12 TEST CONDITIONS MIN TYP MAX UNIT Start threshold 3.8 4.08 4.46 V Hysteresis 0.4 0.5 0.6 V Stop threshold 3.3 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 V 
        
   

 SLVS201A − JUNE 1999 − REVISED JULY 1999 electrical characteristics over recommended operating virtual junction temperature range, VCC = 5 V (unless otherwise noted) (continued) output drivers PARAMETER Peak output current (see Note 4) TEST CONDITIONS Duty cycle < 2%, TJ = 125°C, High-side source VHIGHDR = 0.5 V (source) or 4 V (sink), See Note 3 Low-side sink Duty Cycle < 2%, TJ = 125°C, Low-side source VLOWDR = 0.5 V (source) or 4 V (sink), See Note 3 High-side sink Output resistance (see Note 4) tpw < 100 µs, VBOOT – VBOOTLO = 4.5 V, High-side sink tpw < 100 µs, VDRV = 4.5 V, MIN TYP Low-side sink 1.2 A 1.3 1.4 5 75 9 TJ = 125 125°C, C, VDRV = 4.5 V, VLOWDR = 4 V (source) or 0.5 V (sink) Low-side source UNIT 0.7 125°C, VBOOT – VBOOTLO = 4.5 V, TJ = 125 C, VHIGHDR = 4 V (source) or 0.5 V (sink) High-side source MAX Ω 75 NOTES: 3. This parameter is ensured by design and is not production tested. 4. The pullup/pulldown circuits of the drivers are bipolar and MOSFET transistors in parallel. The peak output current rating is the combined current from the bipolar and MOSFET transistors. The output resistance is the Rds(on) of the MOSFET transistor when the voltage on the driver output is less than the saturation voltage of the bipolar transistor. supply current PARAMETER VCC VCC TEST CONDITIONS Supply voltage range Quiescent current High-side driver quiescent current MIN TYP MAX 4.5 5 5.5 10 VINHIBIT = 5 V, VCC > 4.46 V at startup, VP code ≠ 11111, VBOOTLO = 0 V 3 VINHIBIT = 5 V, VCC > 4.46 V at startup, CHIGHDR = 50 pF, fSWX = 200 kHz, VP code ≠ 11111, VBOOTLO = 0 V, CLOWDR = 50 pF, See Note 3 5 VINHIBIT = 0 V or VP code = 11111 or VCC < 3.8 V at startup, VBOOT = 13 V, VBOOTLO = 0 V VINHIBIT = 5 V, VP code ≠ 11111, VCC > 4.46 V at startup, VBOOT = 13 V, VBOOTLO = 0 V, CHIGHDR = 50 pF, fSWX = 200 kHz (see Note 3) UNIT V mA 90 2 µA mA NOTE 3: This parameter is ensured by design and is not production tested. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13 
        
   

 SLVS201A − JUNE 1999 − REVISED JULY 1999 switching characteristics over recommended operating virtual-junction temperature range, VCC = 5 V (unless otherwise noted) PARAMETER TEST CONDITIONS VSENSE to HIGHDR or LOWDR (excluding deadtime) Propagation delay MIN 1.3 V ≤ VVREF ≤ 2.6 V, 10 mV overdrive (see Note 3) OCP comparator OVP comparator Deglitch time (Includes comparator propagation delay) Response time MAX UNIT 230 300 ns 1 µs 1 See Note 3 PWRGD comparator 1 SLOWST comparator Overdrive = 10 mV (see Note 3) HIGHDR output CL = 6 nF, VBOOTLO = 0 V, VBOOT = 4.5 V, TJ = 125°C LOWDR output CL = 6 nF, TJ = 125°C VDRV = 4.5 V, Rise and fall time TYP OCP 700 1000 120 ns 80 2 5 1.8 5 See Note 3 OVP High-side VDS sensing VHISENSE = 4.5 V, VIOUTLO pulsed from 4.5 V to 4.4 V, 100 ns rise/fall times (see Note 3) 3 VHISENSE = 3 V, VIOUTLO pulsed from 3 V to 2.9 V, 100 ns rise/fall times (see Note 3) 3 Short-circuit protection rising-edge delay SCP LOSENSE = 0 V (see Note 3) Turnon/turnoff delay VDS sensing sample/hold switch Crossover delay time ns µss µss 300 500 ns 3 V ≤ VHISENSE ≤ 5.5 V, VLOSENSE = VHISENSE (see Note 3) 30 100 ns LOWDR to HIGHDRV, and LOHIB to LOWDR See Note 3 50 200 ns Prefilter pole frequency Hysteretic comparator See Note 3 Propagation delay LODRV See Note 3 NOTE 3: This parameter is ensured by design and is not production tested. 14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 MHz 400 ns 
        
   

 SLVS201A − JUNE 1999 − REVISED JULY 1999 TYPICAL CHARACTERISTICS SLOWSTART TIME vs SLOWSTART CAPACITANCE SLOWSTART TIME vs SUPPLY CURRENT (VREFB) 100 1000 V(VREFB) = 2 V I(VREFB) = 100 µA TJ = 27°C V(VREFB) = 2 V CS = 0.1 µF TJ = 27°C Slowstart Time − ms Slowstart Time − ms 10 1 100 10 0.1 0.01 0.0001 0.0010 0.0100 0.1000 1 1 1 10 Slowstart Capacitance − µF Figure 1 DRIVER DRIVER RISE TIME vs LOAD CAPACITANCE FALL TIME vs LOAD CAPACITANCE 1000 TJ = 27°C TJ = 27°C 100 t f − Fall Time − ns t r − Rise Time − ns 1000 Figure 2 1000 High Side Low Side 10 1 0.1 100 ICC − Supply Current (VREFB) − µA 1 10 100 100 High Side Low Side 10 1 0.1 CL − Load Capacitance − nF 1 10 100 CL − Load Capacitance − nF Figure 3 Figure 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 15 
        
   

 SLVS201A − JUNE 1999 − REVISED JULY 1999 TYPICAL CHARACTERISTICS OCP THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE OVP THRESHOLD vs JUNCTION TEMPERATURE 105 118.0 117.5 OCP Threshold Voltage − mV OVP Threshold − % 117.0 116.5 116.0 115.5 115.0 114.5 114.0 103 101 99 97 113.5 95 113.0 0 25 50 75 100 TJ − Junction Temperature − °C 0 125 25 50 75 100 125 TJ − Junction Temperature − °C Figure 5 Figure 6 INHIBIT START THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE INHIBIT HYSTERESIS VOLTAGE vs JUNCTION TEMPERATURE 2.10 110 Inhibit Hysteresis Voltage − mV Inhibit Start Threshold Voltage − V 109 2.05 2.00 1.95 108 107 106 105 104 103 102 101 1.90 100 0 25 50 75 100 TJ − Junction Temperature − °C 125 0 Figure 7 16 25 50 75 100 TJ − Junction Temperature − °C Figure 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 125 
        
   

 SLVS201A − JUNE 1999 − REVISED JULY 1999 TYPICAL CHARACTERISTICS UVLO START THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE UVLO HYSTERESIS vs JUNCTION TEMPERATURE 4.020 470 VI = 5 V VI = 5 V 469 4.016 468 UVLO Hysteresis − mV UVLO Start Threshold Voltage − V 4.018 4.014 4.012 4.010 4.008 4.006 467 466 465 464 463 4.004 462 4.002 461 4.000 460 0 25 50 75 100 TJ − Junction Temperature − °C 125 0 25 50 75 100 TJ − Junction Temperature − °C Figure 9 Figure 10 QUIESCENT CURRENT vs JUNCTION TEMPERATURE POWERGOOD THRESHOLD vs JUNCTION TEMPERATURE 2.0 93.0 VI = 5 V 1.9 92.9 1.8 92.8 Powergood Threshold − % Quiescent Current − mA 125 1.7 1.6 1.5 1.4 1.3 92.7 92.6 92.5 92.4 92.3 1.2 92.2 1.1 92.1 1.0 92.0 0 25 50 75 100 TJ − Junction Temperature − °C 125 0 Figure 11 25 50 75 100 TJ − Junction Temperature − °C 125 Figure 12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 17 
        
   

 SLVS201A − JUNE 1999 − REVISED JULY 1999 TYPICAL CHARACTERISTICS DRIVER SLOW START CHARGE CURRENT vs JUNCTION TEMPERATURE HIGH-SIDE OUTPUT RESISTANCE vs JUNCTION TEMPERATURE 15 4.0 R O − High-Side Output Resistance − Ω Slow Start Charge Current − µ A V(VREFB) = 1.3 V R(VREFB) = 20 kΩ 14 13 12 11 10 0 25 50 75 100 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 125 0 TJ − Junction Temperature − °C 25 50 75 100 TJ − Junction Temperature − °C Figure 13 125 Figure 14 DRIVER LOW-SIDE OUTPUT RESISTANCE vs JUNCTION TEMPERATURE SENSING SAMPLE/HOLD RESISTANCE vs JUNCTION TEMPERATURE 125 R O − Sensing Sample/Hold Resistance − Ω R O − Low-Side Output Resistance − Ω 8 7 6 5 4 3 2 1 0 V(HISENSE) = 5 V 100 75 50 25 0 0 25 50 75 100 TJ − Junction Temperature − °C 125 0 Figure 15 18 25 50 75 100 TJ − Junction Temperature − °C Figure 16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 125 
        
   

 SLVS201A − JUNE 1999 − REVISED JULY 1999 APPLICATION INFORMATION The hysteretic-type controller method used in the TPS56100 controller gives very fast transient response for today’s high-speed DSP applications. Traditional PWM-type controllers use an oscillator to control the timing of the control signals used to adjust the output voltage. During a transient load event, the PWM-type controller must wait until the next oscillator cycle to begin the output voltage adjustment process. This delay causes output droop (or overshoot) and longer recovery times. Hysteretic-type controllers, such as the TPS56100, are self-oscillating and require no cycle-time to begin the recovery process. Hysteretic controllers have extremely high gain and are sensitive to noise. The TPS56100 has internal low-pass noise filters to eliminate much of this problem, however an external RC low-pass filter between the output and VSENSE input is recommended. The TPS56100 controller includes all of the functions necessary for a dependable high-efficiency power converter. High-current synchronous MOSFET drivers are used for fast, low-loss switching allowing for efficiencies greater than 90%. An internal bootstrap circuit provides the high-side drive voltage necessary for the upper n-channel MOSFET. Overcurrent protection protects the power supply in case of load faults. Overvoltage protection protects the load in case of high-side switch failure. Programmable hysteresis allows users to tailor the output ripple and operating frequency to suit their needs. Slowstart provides a controlled rampup time for the output voltage eliminating output overshoot. Inhibit is provided for sequencing of the converter in multiple-voltage circuits. Power good provides an indication that the output voltage is within operating limits. The design of each of these functions is discussed in detail in the following. Refer to Figure 19 for location of components discussed in the following. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 19 
        
   

 SLVS201A − JUNE 1999 − REVISED JULY 1999 APPLICATION INFORMATION frequency calculation A detailed derivation of frequency calculation is shown in the application report, Designing Fast Response Synchronous Buck Regulators Using the TPS5210, TI Literature number SLVA044. When less accurate results are acceptable, the simplified equation shown below can be used: fs ≅ ǒV O ǒVI ƪVI * VOƫ L Ǔ ESR Ǔ Hysteresis Window control section Below are the equations needed to select the various components within the control section. Component reference numbers refer to the example application given at the end of this section. Details and the derivations of the equations used in this section are available in the application report Designing Fast Response Synchronous Buck Regulators Using the TPS5210, TI Literature number SLVA044. output voltage selection Of course the most important function of the power supply is to regulate the output voltage to a specific value. Values between 1.3 V and 2.6 V can be easily set by shorting the correct VP inputs to ground. Values above the maximum reference voltage (2.6 V) can be set by changing the reference voltage to any convenient voltage within its range and selecting values for R2 and R3 to give the correct output. Select R3: R3