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TPS56428
SLVSBV4B – APRIL 2013 – REVISED OCTOBER 2015
TPS56428 4.5-V to 18-V Input, 4-A Sync. Step-Down Converter with Advanced Eco-mode™
1 Features
3 Description
•
The TPS56428 is a D-CAP2 mode synchronous buck
converter which is optimized for various power bus
regulation needs with a cost effective, low component
count, low standby current solution.
1
•
•
•
•
•
•
•
•
•
•
D-CAP2™ Mode at 650kHz Switching for Fast
Transient Response, Ceramic Capacitor Support
VIN Input Voltage Range: 4.5 V to 18 V
Output Voltage Range: 0.6 V to 7.0 V
Advanced Eco-mode for High Light Load
Efficiency
Integrated FETs Optimized for Lower Duty Cycle
– 68 mΩ (High Side) and 37 mΩ (Low Side)
Shutdown Current Less Than 10 μA
1% Initial Reference Voltage Accuracy
Soft Start with Pre-Bias Output Support
Cycle By Cycle Over Current Limit
Power Good Output
Fixed Soft Start : 1.0ms
2 Applications
•
•
•
•
Digital TV, High Definition Video Equipment
Networking Home Terminal
Digital Set Top Box (STB)
Network Controllers
The D-CAP2 mode control provides a fast transient
response
with
no
external
compensation
components. This adaptive on-time control supports
seamless transition between PWM mode at higher
load conditions and advanced Eco-mode operation at
light loads. Advanced Eco-mode™ maintains higher
efficiency during lighter load conditions than
traditional skip mode.
The TPS56428 also has a proprietary circuit to adopt
to both low equivalent series resistance (ESR) output
capacitors, such as POSCAP or SP-CAP, and ultralow ESR ceramic capacitors. The device operates
from 4.5-V to 18 V VIN input and its output voltage
can be programmed between 0.6V and 7.0V. The
device also features a fixed 1-ms soft start and a
power-good output.
The TPS56428 is available in 8-pin SOIC-8 and 14pin QFN packages designed to operate over the
ambient temperature range of –40°C to 85°C.
Device Information(1)
PART NUMBER
TPS56428
PACKAGE
BODY SIZE (NOM)
HSOP (8)
4.89 mm × 3.9 mm
VQFN (14)
3.5 mm × 3.5 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematic
spacer
Light Load Efficiency with Advanced Eco-mode
100
TPS56428
Efficiency (%)
80
60
40
20
Vo = 1.8V
Vo = 5.0V
Vo = 3.3V
0
1
10
IOUT - Output Current (mA)
100
C009
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS56428
SLVSBV4B – APRIL 2013 – REVISED OCTOBER 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
3
4
7.1
7.2
7.3
7.4
7.5
7.6
4
4
5
5
5
7
Absolute Maximum Ratings ......................................
ESD Ratings ............................................................
Recommended Operating Conditions.......................
Thermal Information .................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Detailed Description .............................................. 8
8.1 Overview ................................................................... 8
8.2 Functional Block Diagram ......................................... 8
8.3 Feature Description................................................... 8
8.4 Device Functional Modes.......................................... 9
9
Application and Implementation ........................ 11
9.1 Application Information............................................ 11
9.2 Typical Application ................................................. 11
10 Power Supply Recommendations ..................... 14
11 Layout................................................................... 15
11.1 Layout Guidelines ................................................. 15
11.2 Layout Example .................................................... 16
11.3 Thermal Information .............................................. 18
12 Device and Documentation Support ................. 19
12.1
12.2
12.3
12.4
12.5
Documentation Support .......................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
19
19
19
19
19
13 Mechanical, Packaging, and Orderable
Information ........................................................... 19
4 Revision History
Changes from Revision A (April 2013) to Revision B
Page
•
Added Device Information and ESD Rating tables, Feature Description section, Device Functional Modes,
Application and Implementation section, Power Supply Recommendations section, Layout section, Device and
Documentation Support section, and Mechanical, Packaging, and Orderable Information section ..................................... 1
•
Added RHL package outline and pinout descriptions ........................................................................................................... 3
•
Added RHL package Thermal Information ............................................................................................................................ 5
•
Changed Figure 14 Y-axis label from "VOUT - Output Voltage (V)" to "fSW - Switching Frequency (kHz)" ........................... 13
•
Added PCB layout example for RHL package. ................................................................................................................... 17
Changes from Original (April 2013) to Revision A
•
2
Page
Changed the device From: Preview To: Production............................................................................................................... 1
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5 Device Comparison Table
TA
PART NUMBER
–40°C to 85°C
PINS
HSOP (DDA)
VQFN (RHL)
8
14
TPS56428
6 Pin Configuration and Functions
2
VFB
VIN
8
VBST
7
POWER PAD
4
HSOP8
VREG5
6
SW
13
PG
12
VREG5
GND
3
SW
4
Exposed
Thermal Pad 11
SW
5
10
VBST
6
5
GND
PG
14
2
7
8
VIN
3
1
GND
TPS56428
DDA
GND
EN
9
VREG5
VFB
EN
VIN
1
14-Pin VQFN with Thermal Pad
RHL Package
(Top View)
GND
8-Pin HSOP with Thermal Pad
DDA PACKAGE
(Top View)
Pin Functions
PIN
DESCRIPTION
NUMBER
NAME
DDA
RHL
EN
1
9
Enable input control. Active high. Active high and must be pulled up to enable the device.
VFB
2
10
Converter feedback input. Connect to output voltage with feedback resistor divider.
VREG5
3
11, 12
PG
4
13
GND
5
1, 2, 3, 14
SW
6
4, 5
VBST
7
6
VIN
8
7, 8
Back side
Back side
Exposed
Thermal Pad
5.5 V power supply output. A capacitor (typical 0.47 µF) should be connected to GND.
VREG5 is not active when EN is low.
Open drain power good output.
Ground pin. Power ground return for switching circuit. Connect sensitive SS and VFB
returns to GND at a single point.
Connect all four GND pins together on a PCB trace as short as possible.
Switch node connection between high-side NFET and low-side NFET.
Connect two SW pins together on a PCB trace.
Supply input for the high-side FET gate drive circuit. Connect 0.1µF capacitor between
VBST and SW pins. An internal diode is connected between VREG5 and VBST.
Input voltage supply pin.
Connect two VIN pins together on a PCB trace as short as possible.
Thermal pad of the package. Must be soldered to achieve appropriate dissipation. Must be
connected to GND.
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
VALUE
Input voltage range
UNIT
MIN
MAX
VIN, EN
–0.3
20
V
VBST
–0.3
26
V
VBST (10 ns transient)
–0.3
28
V
VBST (vs SW)
–0.3
6.5
V
VFB, PG
–0.3
6.5
V
–2
20
V
SW
SW (10 ns transient)
–3
22
V
VREG5
–0.3
6.5
V
GND
–0.3
0.3
V
Voltage from GND to thermal pad, Vdiff
–0.2
0.2
V
Operating junction temperature, TJ
–40
150
°C
Storage temperature, Tstg
–55
150
°C
Output voltage range
(1)
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
4
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
VIN
Supply input voltage range
VBST
VI
Input voltage range
MIN
MAX
4.5
18
–0.1
24
VBST (10 ns transient)
-0.1
27
VBST(vs SW)
–0.1
6.0
PG
–0.1
5.7
EN
–0.1
18
VFB
–0.1
5.5
SW
–1.8
18
SW (10 ns transient)
UNIT
V
V
–3
21
GND
–0.1
0.1
–0.1
5.7
0
5
mA
VO
Output voltage range
VREG5
IO
Output Current range
IVREG5
V
TA
Operating free-air temperature
–40
85
°C
TJ
Operating junction temperature
–40
150
°C
7.4 Thermal Information
TPS56428
THERMAL METRIC
(1)
DDA
RHL
8 PINS
14 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
44.4
45.2
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
51.6
50.7
°C/W
RθJB
Junction-to-board thermal resistance
27.8
21.4
°C/W
ψJT
Junction-to-top characterization parameter
8.7
0.9
°C/W
ψJB
Junction-to-board characterization parameter
27.7
21.6
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
5.3
3.5
°C/W
(1)
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
7.5 Electrical Characteristics
over operating free-air temperature range, VIN = 12 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY CURRENT
IVIN
Operating - non-switching supply current
VIN current, TA = 25°C, EN = 5 V,
VFB = 0.7 V
170
350
μA
IVINSDN
Shutdown supply current
VIN current, TA = 25°C, EN = 0 V
3.8
10
μA
LOGIC THRESHOLD
VENH
EN high-level input voltage
EN
VENL
EN low-level input voltage
EN
REN
EN pin resistance to GND
VEN = 12 V
1.6
180
V
350
0.6
V
700
kΩ
mV
VFB VOLTAGE AND DISCHARGE RESISTANCE
TA = 25°C, VO = 1.05 V, IO = 10 mA,
advanced Eco-mode™ operation
VFBTH
IVFB
(1)
VFB threshold voltage
VFB input current
606
TA = 25°C, VO = 1.05 V, continuous mode
operation
593
600
607
TA = –40°C to 85°C , VO = 1.05V, continuous
mode operation (1)
588
600
612
0
±0.15
VFB = 0.7 V, TA = 25°C
µA
Not production tested.
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Electrical Characteristics (continued)
over operating free-air temperature range, VIN = 12 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
EN=0V SW=1V, TA = 25°C
1.0
1.5
5.5
MAX
UNIT
SW DISCHARGE
IDischg
SW discharge current
mA
VREG5 OUTPUT
VVREG5
VREG5 output voltage
TA = 25°C, 6.0 V < VIN < 18 V,
0 < IVREG5 < 5 mA
5.2
IVREG5
Output current
VIN = 6 V, VREG5 = 4.0 V, TA = 25°C
20
RDS(on)h
High side switch resistance
25°C, VBST - SW = 5.5 V
68
mΩ
RDS(on)l
Low side switch resistance
25°C
37
mΩ
5.7
V
mA
MOSFET
CURRENT LIMIT
Iocl
Current limit
L out = 1.5 µH
(1)
4.8
5.6
7.0
A
THERMAL SHUTDOWN
TSDN
Thermal shutdown threshold
Shutdown temperature (1)
165
Hysteresis (1)
°C
35
ON-TIME TIMER CONTROL
tON
On time
VIN = 12 V, VO = 1.05 V
150
tOFF(MIN)
Minimum off time
TA = 25°C, VFB = 0.5 V
260
310
ns
ns
0.7
1.0
1.3
ms
85%
90%
95%
SOFT START
tss
Soft-start time
Internal soft-start time
POWER GOOD
VTHPG
PG threshold
IPG
IPG PG sink current
VFB rising(good)
VFB falling(Fault)
PG=0.5V
85%
2
4
mA
OUTPUT UNDERVOLTAGE AND OVERVOLTAGE PROTECTION
VOVP
Output OVP threshold
OVP Detect (L>H)
125%
VUVP
Output UVP threshold
UVP detect (H>L)
65%
tUVPDEL
Output UVP delay
To Hiccup state
tUVPEN
Output UVP Enable delay
Relative to soft start time
7
µs
x1.7
UVLO
UVLO
6
UVLO threshold
Wake up VREG5 voltage
3.45
3.75
4.05
Hysteresis VREG5 voltage
0.13
0.32
0.48
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7.6 Typical Characteristics
VIN = 12 V, TA = 25°C (unless otherwise noted)
IVCCSDN - Shutdown Supply Current (uA)
400
ICC - Supply Current (uA)
350
300
250
200
150
100
VIN = 12 V
VO = 1.2 V
50
0
±50
0
50
100
20
15
10
5
EN = 0 V
0
±50
150
Tj Junction Temperature (C)
0
50
100
150
TJ - Junction Temperature -C
C004
Figure 1. Supply Current vs Junction Temperature
C001
Figure 2. VIN Shutdown Current vs Junction Temperature
60
1.100
VIN = 18 V
VOUT - Output Voltage (V)
EN Input Current (uA)
50
40
30
20
1.075
1.050
1.025
V
VIN=5V
IN = 5 V
V
VIN=12V
IN = 12 V
V
VIN=18V
IN = 18 V
10
0
1.000
0
5
10
15
20
EN Input Voltage (V)
1.0
2.0
3.0
4.0
IOUT - Output Current (A)
Figure 3. EN Current vs EN Voltage
Figure 4. Output Voltage vs Output Current
1.100
0.615
0.610
1.075
VFB Voltage - V
VOUT - Output Voltage (V)
0.0
C014
1.050
0.605
0.600
0.595
1.025
IIOUT
10mA
10mA
OUT = =
0.590
IIOUT
1A1A
OUT = =
1.000
Iout = 1 A
0.585
0
5
10
15
20
VIN - Input Voltage (V)
-50
50
100
TJ - Junction Temperature - C
C007
Figure 5. Output Voltage vs Input Voltage
0
150
C015
Figure 6. VFB Voltage vs Junction Temperature
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8 Detailed Description
8.1 Overview
The TPS56428 is a 4-A synchronous step-down (buck) converter with two integrated N-channel MOSFETs. It
operates using D-CAP2™ mode control. The fast transient response of D-CAP2™ control reduces the output
capacitance required to meet a specific level of performance. Proprietary internal circuitry allows the use of low
ESR output capacitors including ceramic and special polymer types. PG output can be used for sequence
operation.
8.2 Functional Block Diagram
EN
EN
EN
1
Logic
VIN
VIN
+
8
OV
-
+25%
OCP
VREG5
Control Logic
7
+
REF
VBST
+ PWM
SS
1 shot
VFB
SW
VO
6
-
2
XCON
ON
VREG5
Ceramic
Capacitor
VREG5
3
AGND
5
Softstart
SS
PGND
PG
4
+
REF
-
-10%
+
ZC
-
PGND
+
OCP
-
PGND
GND
SW
PGND
SW
VIN
OV
VREG5
EN
UVLO
UVLO
Protection
Logic
TSD
REF
REF
Figure 7. Functional Block Diagram
8.3 Feature Description
8.3.1 PWM Operation
The main control loop of the TPS56428 is an adaptive on-time pulse width modulation (PWM) controller that
supports a proprietary D-CAP2™ mode control. D-CAP2™ mode control combines constant on-time control with
an internal compensation circuit for pseudo-fixed frequency and low external component count configuration with
both low ESR and ceramic output capacitors. It is stable even with virtually no ripple at the output.
8
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Feature Description (continued)
At the beginning of each cycle, the high-side MOSFET is turned on. This MOSFET is turned off after internal one
shot timer expires. This one shot is set by the converter input voltage, VIN, and the output voltage, VO, to
maintain a pseudo-fixed frequency over the input voltage range, hence it is called adaptive on-time control. The
one-shot timer is reset and the high-side MOSFET is turned on again when the feedback voltage falls below the
reference voltage. An internal ramp is added to reference voltage to simulate output ripple, eliminating the need
for ESR induced output ripple from D-CAP2™ mode control.
8.3.2 PWM Frequency and Adaptive On-Time Control
TPS56428 uses an adaptive on-time control scheme and does not have a dedicated on board oscillator. The
TPS56428 runs with a pseudo-constant frequency of 650 kHz by using the input voltage and output voltage to
set the on-time one-shot timer. The on-time is inversely proportional to the input voltage and proportional to the
output voltage, therefore, when the duty ratio is VOUT/VIN, the frequency is constant.
8.3.3 Advanced Auto-Skip Eco-mode™ Control
The TPS56428 is designed with advanced auto-skip Eco-mode™ to increase higher light load efficiency. As the
output current decreases from heavy load condition, the inductor current is also reduced. If the output current is
reduced enough, the inductor current ripple valley reaches the zero level, which is the boundary between
continuous conduction and discontinuous conduction modes. The rectifying low-side MOSFET is turned off when
its zero inductor current is detected. As the load current further decreases the converter run into discontinuous
conduction mode. The on-time is kept approximately the same as is in continuous conduction mode. The off-time
increases as it takes more time to discharge the output capacitor to the level of the reference voltage with
smaller load current. The transition point to the light load operation IOUT(LL) current can be calculated in
Equation 1.
1
(VIN - VOUT ) ´ VOUT
IOUT(LL) =
´
2 ´ L ´ fSW
VIN
(1)
8.3.4 Soft Start and Pre-Biased Soft Start
The TPS56428 has an internal 1.0ms soft-start. When the EN pin becomes high, internal soft-start function
begins ramping up the reference voltage to the PWM comparator.
The TPS56428 contains a unique circuit to prevent current from being pulled from the output during startup if the
output is pre-biased. When the soft-start commands a voltage higher than the pre-bias level (internal soft start
becomes greater than feedback voltage VFB), the controller slowly activates synchronous rectification by starting
the first low side FET gate driver pulses with a narrow on-time. It then increments that on-time on a cycle-bycycle basis until it coincides with the time dictated by (1-D), where D is the duty cycle of the converter. This
scheme prevents the initial sinking of the pre-bias output, and ensure that the out voltage (VO) starts and ramps
up smoothly into regulation and the control loop is given time to transition from pre-biased start-up to normal
mode operation.
8.4 Device Functional Modes
8.4.1 Power Good
The power-good function is activated after soft start has finished. The power good function becomes active after
1.7 times soft-start time. When the output voltage becomes within –10% of the target value, internal comparators
detect power good state and the power good signal becomes high. The power good output, PG is an open drain
output. If the feedback voltage goes under 15% of the target value, the power good signal becomes low.
8.4.2 Output Discharge Control
TPS56428 discharges the output via SW pin when EN is low, or the controller is turned off by the protection
functions(UVP, UVLO and thermal shutdown). The internal regular low-side MOSFET is not turned on during the
output discharge operation to avoid the possibility of causing negative voltage at the output
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Device Functional Modes (continued)
8.4.3 Current Protection
The output over-current protection (OCP) is implemented using a cycle-by-cycle valley detect control circuit. The
switch current is monitored by measuring the low-side FET switch voltage between the SW pin and GND. This
voltage is proportional to the switch current. To improve accuracy, the voltage sensing is temperature
compensated.
During the on time of the high-side FET switch, the switch current increases at a linear rate determined by Vin,
Vout, the on-time and the output inductor value. During the on time of the low-side FET switch, this current
decreases linearly. The average value of the switch current is the load current Iout. The TPS56428 constantly
monitors the low-side FET switch voltage, which is proportional to the switch current, during the low-side on-time.
If the measured voltage is above the voltage proportional to the current limit, an internal counter is incremented
per each SW cycle and the converter maintains the low-side switch on until the measured voltage is below the
voltage corresponding to the current limit at which time the switching cycle is terminated and a new switching
cycle begins. In subsequent switching cycles, the on-time is set to a fixed value and the current is monitored in
the same manner. If the over current condition exists for 7 consecutive switching cycles, the internal OCL
threshold is set to a lower level, reducing the available output current. When a switching cycle occurs where the
switch current is not above the lower OCL threshold, the counter is reset and the OCL limit is returned to the
higher value.
There are some important considerations for this type of over-current protection. The load current one half of the
peak-to-peak inductor current is higher than the over-current threshold also when the current is being limited, the
output voltage tends to fall as the demanded load current may be higher than the current available from the
converter. This may cause the output voltage to fall. . When the VFB voltage becomes lower than 65% of the
target voltage, the UVP comparator detects it. After 5µs detecting the UVP voltage, device will shut down and restart after hiccup time.
When the over current condition is removed, the output voltage returns to the regulated value.
8.4.4 UVLO Protection
Undervoltage lock out protection (UVLO) monitors the voltage of the VREG5 pin. When the VREG5 voltage is
lower than UVLO threshold voltage, the TPS56428 is shut off. This protection is non-latching.
8.4.5 Thermal Shutdown
TPS56428 monitors the temperature of itself. If the temperature exceeds the threshold value (typically 165°C),
the device is shut off. This is non-latch protection.
10
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The TPS56428 is typically used as a step down converter, which convert a voltage from 4.5V–18V to a lower
voltage. WEBENCH software is available to aid in the design and analysis of circuits.
9.2 Typical Application
U1
TPS56428DDA
Figure 8. Schematic Diagram for This Design Example.
9.2.1 Design Requirements
To
•
•
•
•
•
begin the design process, you must know a few application parameters:
Input voltage range
Output voltage
Output current
Output voltage ripple
Input voltage ripple
9.2.2 Detailed Design Procedure
9.2.2.1 Output Voltage Resistors Selection
The output voltage is set with a resistor divider from the output node to the VFB pin. It is recommended to use
1% tolerance or better divider resistors. Start by using Equation 2 to calculate VOUT.
To improve efficiency at very light loads consider using larger value resistors, too high of resistance will be more
susceptible to noise and voltage errors from the VFB input current will be more noticeable.
R1 ö
æ
VOUT = 0.60 ´ ç 1 +
÷
è R2 ø
(2)
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Typical Application (continued)
9.2.2.2 Output Filter Selection
The output filter used with the TPS56428 is an LC circuit. This LC filter has double pole at:
1
FP =
2p LOUT ´ COUT
(3)
At low frequencies, the overall loop gain is set by the output set-point resistor divider network and the internal
gain of the TPS56428. The low frequency phase is 180 degrees. At the output filter pole frequency, the gain rolls
off at a –40 dB per decade rate and the phase drops rapidly. D-CAP2™ introduces a high frequency zero that
reduces the gain roll off to –20 dB per decade and increases the phase to 90 degrees one decade above the
zero frequency. The inductor and capacitor selected for the output filter must be selected so that the double pole
of is located below the high frequency zero but close enough that the phase boost provided be the high
frequency zero provides adequate phase margin for a stable circuit. To meet this requirement use the values
recommended in Table 1.
Table 1. Recommended Component Values
(1)
C4 (pF) (1)
Output
Voltage
(V)
R1 (kΩ)
R2 (kΩ)
L1 (µH)
MIN
TYP
MAX
MIN
TYP
MAX
C7 + C8
(µF)
1
33.2
49.9
5
33
100
1.0
1.5
4.7
20 - 68
1.05
37.4
49.9
5
33
100
1.0
1.5
4.7
20 - 68
1.2
49.9
49.9
5
22
47
1.0
1.5
4.7
20 - 68
1.5
75.0
49.9
5
15
33
1.0
1.5
4.7
20 - 68
1.8
100
49.9
5
10
22
1.0
1.5
4.7
20 - 68
2.5
158
49.9
5
10
22
1.5
2.2
4.7
20 - 68
3.3
226
49.9
2
5
15
1.5
2.2
4.7
20 - 68
5
365
49.9
2
5
10
2.2
3.3
4.7
20 - 68
6.5
487
49.9
2
2
10
2.2
3.3
4.7
20 - 68
Optional
For higher output voltages at or above 1.8 V, additional phase boost can be achieved by adding a feed forward
capacitor (C4) in parallel with R1
The inductor peak-to-peak ripple current, peak current and RMS current are calculated using Equation 4,
Equation 5 and Equation 6. The inductor saturation current rating must be greater than the calculated peak
current and the RMS or heating current rating must be greater than the calculated RMS current. Use 650 kHz for
fSW.
Use 650 kHz for fSW. Make sure the chosen inductor is rated for the peak current of Equation 5 and the RMS
current of Equation 6.
VIN(MAX) - VO UT
VO UT
I lP-P =
´
VIN(MA X)
LO ´ f SW
(4)
I lPEAK = IO +
I lP -P
2
ILO(RMS) = IO2 +
(5)
1
I lP -P2
12
(6)
For this design example, the calculated peak current is 4.51 A and the calculated RMS current is 4.01 A. The
inductor used is a TDK SPM6530-1R5M100 with a peak current rating of 11.5 A and an RMS current rating of 11
A.
The capacitor value and ESR determines the amount of output voltage ripple. The TPS56428 is intended for use
with ceramic or other low ESR capacitors. Recommended values range from 20µF to 68µF. Use Equation 7 to
determine the required RMS current rating for the output capacitor.
12
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ICO(RMS) =
VOx ´
(VIN
- VO UT )
12 ´ VIN ´ L O ´ f SW
(7)
For this design two TDK C3216X5R0J226M 22µF output capacitors are used. The typical ESR is 2 mΩ each.
The calculated RMS current is 0.284A and each output capacitor is rated for 4A.
9.2.2.3 Input Capacitor Selection
The TPS56428 requires an input decoupling capacitor and a bulk capacitor is needed depending on the
application. A ceramic capacitor over 10µF is recommended for the decoupling capacitor. An additional 0.1 µF
capacitor from pin 8 to ground is optional to provide additional frequency filtering. The capacitor voltage rating
needs to be greater than the maximum input voltage.
9.2.2.4 Bootstrap Capacitor Selection
A 0.1µF ceramic capacitor must be connected between the VBST to SW pin for proper operation. It is
recommended to use a ceramic capacitor.
9.2.2.5 VREG5 Capacitor Selection
A 0.47-µF ceramic capacitor must be connected between the VREG5 to GND pin for proper operation. It is
recommended to use a ceramic capacitor
9.2.3 Application Curves
VIN = 12 V, TA = 25°C (unless otherwise noted)
EN( 10V/div)
Vout( 50mV/div)
VREG5( 5V/div)
Vout( 0.5V/div)
Iout( 2A/div)
PG( 5V/div)
100us/div
400us/div
Figure 10. Slow Start
100
100
90
90
80
80
Efficiency (%)
Efficiency (%)
Figure 9. 1.05 V Load Transient Response
70
60
Vo=1.8V
Vo=5.0V
Vo=3.3V
50
40
0.0
1.0
2.0
3.0
IOUT - Output Current (A)
70
60
Vo=1.8V
Vo=5.0V
Vo=3.3V
50
40
0.001
4.0
C008
Figure 11. Efficiency vs Output Current
0.01
IOUT - Output Current (A)
0.1
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C009
Figure 12. Efficiency vs Output Current
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VIN = 12 V, TA = 25°C (unless otherwise noted)
800
VVo=1.05V
O = 1.05 V
VVo=1.2V
O = 1.2 V
VVo=1.5V
O = 1.5 V
VVo=1.8V
O = 1.8 V
VVo=2.5V
O = 2.5 V
VVo=3.3V
O = 3.3 V
VVo=5V
O= 5 V
850
800
750
700
650
fSW - Switching Frequency (kHz)
fSW - Switching Frequency (kHz)
900
600
550
500
VIN = 12 V
700
600
500
400
300
200
VVIN=5V
O = 1.05 V
VVIN=12V
O = 1.8 V
VVIN=18V
O = 3.3 V
100
450
IO = 1A
400
0
0.0
5.0
10.0
15.0
20.0
VIN - Input Voltage (V)
Figure 13. Switching Frequency vs Input Voltage
Vo=1.05V
0
1
2
4
5
C012
Figure 14. Output Voltage vs Output Current
Vo=1.05V
VIN( 50mV/div)
3
IOUT - Output Current (A)
C011
Vo( 10mV/div)
SW( 5V/div)
SW( 5V/div)
400ns/div
400ns/div
Figure 15. VIN Ripple
Figure 16. VOUT Ripple
10 Power Supply Recommendations
The TPS56428 designed to operate from input supply voltage in the range of 4.5 V to 18 V. Buck converters
require the input voltage to be higher than the output voltage for proper operation. The maximum recommended
operating duty cycle is 65%. Using that criteria, the minimum recommended input voltage is VOUT ÷ 0.65.
14
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11 Layout
11.1 Layout Guidelines
1. The TPS56428 can supply relatively large current up to 4 A; so heat dissipation may be a concern. The top
side area adjacent to the TPS56428 must be filled with ground as much as possible to dissipate heat.
2. The bottom side area directly below the IC must be a dedicated ground area; and, be directly connected to
the thermal pad using vias as shown. The ground area must be as large as practical. Additional internal
layers can be dedicated as ground planes and connected to vias as well.
3. Keep the input switching current loop as small as possible.
4. Keep the SW node as physically small and short as possible to minimize parasitic capacitance and
inductance and to minimize radiated emissions. Kelvin connections must be brought from the output to the
feedback pin of the device.
5. Keep analog and non-switching components away from switching components.
6. Make a single point connection from the signal ground to power ground.
7. Do not allow switching current to flow under the device.
8. Keep the pattern lines for VIN and PGND broad.
9. Exposed pad of device must be connected to PGND with solder.
10. VREG5 capacitor must be placed near the device, and connected PGND.
11. Output capacitor must be connected to a broad pattern of the PGND.
12. Voltage feedback loop must be as short as possible, and preferably with ground shield.
13. Lower resistor of the voltage divider which is connected to the VFB pin must be tied to SGND.
14. Providing sufficient via is preferable for VIN, SW and PGND connection.
15. PCB pattern for VIN, SW, and PGND must be as broad as possible.
16. VIN Capacitor must be placed as near as possible to the device.
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11.2 Layout Example
VIN
VIN
INPUT
BYPASS
CAPACITOR
VIN
HIGH FREQENCY
BYPASS
CAPACITOR
TO ENABLE
CONTROL
EN
VIN
VFB
VBST
VREG5
SW
PG
GND
FEEDBACK
RESISTORS
POWER
GOOD
PULL UP
TO POWER
GOOD
MONITOR
BIAS
CAP
BOOST
CAPACITOR
EXPOSED
THERMAL PAD
AREA
ANALOG
GROUND
TRACE
OUTPUT
INDUCTOR
VOUT
OUTPUT
FILTER
CAPACITOR
POWER GROUND
VIA to Ground Plane
Figure 17. TPS56428 Layout – HSOP (DDA) Package
16
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Layout Example (continued)
Power and Anlaog Gound Short
Power Ground
Analog Ground Trace
Bias Voltage
Capacitor
GND
GND
To Power-Good
Monitor
Output
Filter
Capacitor
GND
PG
GND
VREG5
SW
VOUT
VOUT
Output
Inductor
Boost
Capacitor
Thermal Pad
Power-Good
Pull-Up
VREG5
SW
VFB
VBST
EN
To Enable
Control
VIN
VIN
Feed-Back
Resistors
VIN Input
Bypass Capacitor
VIN
Two of VIN
High Frequency
Bypass Capacitors
Figure 18. TPS56428 Layout – VQFN (RHL) Package
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11.3 Thermal Information
This 8-pin DDA package incorporates an exposed thermal pad that is designed to be soldered directly to an
external heatsink. The thermal pad must be soldered directly to the printed board (PCB). After soldering, the PCB
can be used as a heatsink. In addition, through the use of thermal vias, the thermal pad can be attached directly
to the appropriate copper plane shown in the electrical schematic for the device, or alternatively, can be attached
to a special heatsink structure designed into the PCB. This design optimizes the heat transfer from the integrated
circuit (IC).
For additional information on the exposed thermal pad and how to use the advantage of its heat dissipating
abilities, refer to Technical Brief, PowerPAD™ Thermally Enhanced Package, Texas Instruments Literature No.
SLMA002 and Application Brief, PowerPAD™ Made Easy, Texas Instruments Literature No. SLMA004.
The exposed thermal pad dimensions for this package are shown in Figure 19.
8
5
Exposed Thermal Pad
2,40
1,65
1
3,10
2,65
4
Figure 19. Thermal Pad Dimensions – HSOP (DDA) Package
18
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
Technical Brief, PowerPAD™ Thermally Enhanced Package, SLMA002
Application Brief, PowerPAD™ Made Easy, SLMA004
12.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.3 Trademarks
D-CAP2, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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11-Aug-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
TPS56428DDA
ACTIVE SO PowerPAD
DDA
8
75
RoHS & Green
SN
Level-2-260C-1 YEAR
-40 to 85
56428
Samples
TPS56428DDAR
ACTIVE SO PowerPAD
DDA
8
2500
RoHS & Green
SN
Level-2-260C-1 YEAR
-40 to 85
56428
Samples
TPS56428RHLR
ACTIVE
VQFN
RHL
14
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
56428
Samples
TPS56428RHLT
ACTIVE
VQFN
RHL
14
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
56428
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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