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Table of Contents
User’s Guide
TPS56921 Buck Converter Evaluation Module User's
Guide
ABSTRACT
This user’s guide contains information for the TPS56921EVM-188 evaluation module (PWR188) as well as for
the TPS56921 dc/dc converter. Also included are the performance specifications, the schematic, and the bill of
materials for the TPS56921EVM-188.
Table of Contents
1 Introduction.............................................................................................................................................................................2
2 Test Setup and Results.......................................................................................................................................................... 4
3 Board Layout.........................................................................................................................................................................12
4 Schematic and Bill of Materials...........................................................................................................................................14
5 Revision History................................................................................................................................................................... 15
List of Figures
Figure 2-1. TPS56921EVM-188 Efficiency.................................................................................................................................. 5
Figure 2-2. TPS56921EVM-188 Low Current Efficiency..............................................................................................................6
Figure 2-3. TPS56921EVM-188 Load Regulation....................................................................................................................... 6
Figure 2-4. TPS56921EVM-188 Line Regulation........................................................................................................................ 7
Figure 2-5. TPS56921EVM-188 Transient Response................................................................................................................. 7
Figure 2-6. TPS56921EVM-188 Loop Response, VOUT Set by Resistor Divider.........................................................................8
Figure 2-7. TPS56921EVM-188 Loop Response, VOUT Set by I2C Interface..............................................................................8
Figure 2-8. TPS56921EVM-188 Output Ripple........................................................................................................................... 9
Figure 2-9. TPS56921EVM-188 Input Ripple.............................................................................................................................. 9
Figure 2-10. TPS56921EVM-188 Start-Up Relative to VIN ....................................................................................................... 10
Figure 2-11. TPS56921EVM-188 Start-Up Relative to Enable.................................................................................................. 10
Figure 2-12. TPS56921EVM-188 Start-Up Relative to VIN Detail.............................................................................................. 11
Figure 3-1. TPS56921EVM-188 Top-Side Assembly.................................................................................................................12
Figure 3-2. TPS56921EVM-188 Top-Side Layout..................................................................................................................... 12
Figure 3-3. TPS56921EVM-188 Internal Layer-1 Layout.......................................................................................................... 13
Figure 3-4. TPS56921EVM-188 Internal Layer-2 Layout.......................................................................................................... 13
Figure 3-5. TPS56921EVM-188 Bottom-Side Layout................................................................................................................13
Figure 4-1. TPS56921EVM-188 Schematic...............................................................................................................................14
List of Tables
Table 1-1. Input Voltage and Output Current Summary...............................................................................................................2
Table 1-2. TPS56921EVM-188 Performance Specification Summary.........................................................................................2
Table 1-3. Ideal VOUT versus Code............................................................................................................................................ 3
Table 2-1. EVM Connectors and Test Points............................................................................................................................... 4
Table 4-1. TPS56921EVM-188 Bill of Materials.........................................................................................................................15
Trademarks
I2C™ is a trademark of NXP.
All trademarks are the property of their respective owners.
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Introduction
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1 Introduction
1.1 Background
The TPS56921 dc/dc converter is designed to provide up to a 9-A output. The TPS56921 implements split-input
power rails with separate input voltage inputs for the power stage and control circuitry. The power stage
input (PVIN) is rated for 1.6 V to 17 V whereas the control input (VIN) is rated for 4.5 V to 17 V. The
TPS56921EVM-188 provides both inputs but is designed and tested using the PVIN connected to VIN. Rated
input voltage and output current range for the evaluation module are given in Table 1-1. This evaluation module
is designed to demonstrate the small printed-circuit-board areas that may be achieved when designing with
the TPS56921 regulator. The switching frequency is externally set at a nominal 500 kHz. The high-side and
low-side MOSFETs are incorporated inside the TPS56921 package along with the gate drive circuitry. The
low drain-to-source on-resistance of the MOSFET allows the TPS56921 to achieve high efficiencies and helps
keep the junction temperature low at high output currents. The compensation components are external to the
integrated circuit (IC), and an external divider allows for an adjustable output voltage. Additionally, the TPS56921
provides adjustable slow start, tracking, and undervoltage lockout inputs. The absolute maximum input voltage is
20 V for the TPS56921EVM-188.
Table 1-1. Input Voltage and Output Current Summary
EVM
INPUT VOLTAGE RANGE
OUTPUT CURRENT
RANGE
TPS56921EVM-188
VIN = 4.5 V to 17 V
0 A to 9 A
1.2 Performance Specification Summary
A summary of the TPS56921EVM-188 performance specifications is provided in Table 1-2. Specifications are
given for an input voltage of VIN = 12 V and an output voltage of 1.1 V, unless otherwise specified. The
TPS56921EVM-188 is designed and tested for VIN = 4.5 V to 17 V with the VIN and PVIN pins connect together
with the JP1 jumper. The ambient temperature is 25°C for all measurements, unless otherwise noted.
Table 1-2. TPS56921EVM-188 Performance Specification Summary
SPECIFICATION
TEST CONDITIONS
VIN voltage range (PVIN = VIN)
MIN
TYP
MAX
4.5
12
17
UNIT
V
VIN start voltage (internal UVLO)
4.0
V
VIN stop voltage (internal UVLO)
3.85
V
1.1
V
Output voltage setpoint
Output current range
VIN = 8 V to 17 V
Line regulation
IO = 4.5 A, VIN = 4.5 V to 17 V
±0.01
Load regulation
VIN = 12 V, IO = 0 A to 9 A
±0.18
IO = 2.25 A to 6.75 A
Load transient response
IO = 6.75 A to 2.25 A
0
A
%
%
Voltage change
–90
Recovery time
100
µs
Voltage change
90
mV
Recovery time
Loop bandwidth
VIN = 12 V, IO = 4 A
Phase margin
VIN = 12 V , IO = 4 A
Input ripple voltage
IO = 9 A, measured with 330 µF added
capacitance at J2
Output ripple voltage
IO = 8 A
Output rise time
Operating frequency
Maximum efficiency
9
TPS56921EVM-188, VIN = 5 V, IO = 1.6 A
mV
100
µs
50.1
kHz
63
°
300
mVPP
10
mVPP
4
ms
500
kHz
88.1
%
1.3 Modifications
These evaluation modules are designed to provide access to the features of the TPS56921. Some modifications
can be made to this module.
2
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Introduction
1.3.1 Output Voltage Setpoint
The output voltage of the EVM is set either externally using a voltage divider or internally using the integrated
I2C™ interface. The external adjustment of the output voltage is set by the resistor divider network of R10 and
R11. R10 is fixed at 10 kΩ. To change the output voltage of the EVM, it is necessary to change the value of
resistor R11. Changing the value of R11 can change the output voltage in the range of 0.72 V to 1.48 V. The
value of R11 for a specific output voltage can be calculated using Equation 1.
R11=
10 kW ´ 0.8 V
VOUT - 0.8V
(1)
The output voltage can also be set using the optional VID control using the I2C interface. The EVM is designed
so that the J3 connector is compatible with the HPA665-001 USB2ANY interface. Using that control and
USB2ANY_GUI software allows the output voltage to be programmed to any of 77 preset voltages from 0.72
V to 1.48 V. See the TPS56921 datasheet for a complete description of the available codes. With the software
running and the cable attached, confirm the connection by clicking the "Read" button under "Firmware Revision".
The firmware revision number will be returned if the connection is good. Set up the interface by selecting "Speed
= _400kHz", "Address = _7Bits" and "Pull Ups = OFF" in the "I2C" section. Click on "Set I2C". In the "3.3V/5.0V"
section set "3.3V = ON" and "5.0V = OFF". Click on "Set", then click on "Get Status". "GOOD" should be
returned for both 3.3 V and 5.0 V. To communicate with the TPS56921EVM-188, in the "Single-Register" section
set "I2C Address = 34". In the "Register Address" field, enter the data byte for the voltage you wish to set. Ignore
the "Byte to Write" field. Click on "Write" to send the data.
Table 1-3. Ideal VOUT versus Code
Code
Binary
VOUT
Code
Binary
VOUT
Code
Binary
VOUT
0
0000000
0.720
26
0011010
0.980
52
0110100
1.240
1
0000001
0.730
27
0011011
0.990
53
0110101
1.250
2
0000010
0.740
28
0011100
1.000
54
0110110
1.260
3
0000011
0.750
29
0011101
1.010
55
0110111
1.270
4
0000100
0.760
30
0011110
1.020
56
0111000
1.280
5
0000101
0.770
31
0011111
1.030
57
0111001
1.290
6
0000110
0.780
32
0100000
1.040
58
0111010
1.300
7
0000111
0.790
33
0100001
1.050
59
0111011
1.310
8
0001000
0.800
34
0100010
1.060
60
0111100
1.320
9
0001001
0.810
35
0100011
1.070
61
0111101
1.330
10
0001010
0.820
36
0100100
1.080
62
0111110
1.340
11
0001011
0.830
37
0100101
1.090
63
0111111
1.350
12
0001100
0.840
38
0100110
1.100
64
1000000
1.360
13
0001101
0.850
39
0100111
1.110
65
1000001
1.370
14
0001110
0.860
40
0101000
1.120
66
1000010
1.380
15
0001111
0.870
41
0101001
1.130
67
1000011
1.390
16
0010000
0.880
42
0101010
1.140
68
1000100
1.400
17
0010001
0.890
43
0101011
1.150
69
1000101
1.410
18
0010010
0.900
44
0101100
1.160
70
1000110
1.420
19
0010011
0.910
45
0101101
1.170
71
1000111
1.430
20
0010100
0.920
46
0101110
1.180
72
1001000
1.440
21
0010101
0.930
47
0101111
1.190
73
1001001
1.450
22
0010110
0.940
48
0110000
1.200
74
1001010
1.460
23
0010111
0.950
49
0110001
1.210
75
1001011
1.470
24
0011000
0.960
50
0110010
1.220
76
1001100
1.480
25
0011001
0.970
51
0110011
1.230
>76
>1001100
Illegal / Special
1.3.2 Slow-Start Time
The slow-start time can be adjusted by changing the value of C5. Use Equation 2 to calculate the required value
of C5 for a desired slow-start time
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C5(nF)=
Tss(ms) ´ Iss(μA)
Vref(V)
(2)
The EVM is set for a slow-start time of 5.7 ms using C5 = 0.01 µF.
1.3.3 Adjustable UVLO
The undervoltage lockout (UVLO) can be adjusted externally using R1 and R2. The EVM is set to use the
internal UVLO and R1 and R2 are not populated. Use Equation 3 and Equation 4 to calculate required resistor
values for different start and stop voltages.
æV
ö
VSTART ç ENFALLING ÷ - VSTOP
V
è ENRISING ø
R1=
æ VENFALLING ö
Ip ç 1÷ +Ih
è VENRISING ø
R2=
(3)
R1× VENFALLING
VSTOP - VENFALLING +R1(Ip +Ih)
(4)
1.3.4 Input Voltage Rails
The EVM is designed to accommodate different input voltage levels for the power stage and control logic. During
normal operation, the PVIN and VIN inputs are connected using a jumper across JP1. The single input voltage
is supplied at J2. If desired, these two input voltage rails may be separated by removing the jumper across JP1.
Two input voltages must then be provided at both J1 and J2.
2 Test Setup and Results
This section describes how to properly connect, set up, and use the TPS56921EVM-188 evaluation module.
The section also includes test results typical for the evaluation module and covers efficiency, output voltage
regulation, load transients, loop response, output ripple, input ripple, and start-up.
2.1 Input/Output Connections
The TPS56921EVM-188 is provided with input/output connectors and test points as shown in Table 2-1. A power
supply capable of supplying 4 A must be connected to J2 through a pair of 20-AWG wires. The jumper across
JP1 must be in place. See Section 1.3.4 for split-input voltage rail operation. The load must be connected to
J4 through a pair of 20-AWG wires. The maximum load current capability must be 9 A. Wire lengths must
be minimized to reduce losses in the wires. Test-point TP3 provides a place to monitor the VIN input voltages
with TP4 providing a convenient ground reference. TP9 is used to monitor the output voltage with TP10 as the
ground reference.
Table 2-1. EVM Connectors and Test Points
Reference Designator
4
Function
J1
VIN input voltage connector. Not normally used.
J2
PVIN input voltage connector. (See Table 1-1 for VIN range.)
J3
I2C interface connector.
J4
VOUT, 1.1 V at 9 A maximum
JP1
PVIN to VIN jumper. Normally closed to tie VIN to PVIN for common rail voltage operation.
JP2
2-pin header for enable. Connect EN to ground to disable, open to enable.
JP3
I2C interface pull up jumper for SDA.
JP4
I2C interface pull up jumper for SCL.
JP5
I2C interface grounding jumper for A0.
JP6
I2C interface grounding jumper for A1.
JP7
PWRGD pull up to Vin. (1)
TP1
VIN test point at VIN connector.
TP2
GND test point at VIN connector.
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Test Setup and Results
Table 2-1. EVM Connectors and Test Points (continued)
Reference Designator
(1)
Function
TP3
PVIN test point at PVIN connector.
TP4
GND test point at PVIN connector.
TP5
PWRGD test point.
TP6
PH test point.
TP7
COMP pin test point.
TP8
Analog GND test point.
TP9
Test point in voltage divider network at VO. Used for loop response measurements when output voltage is set
using I2C control.
TP10
Test point in voltage divider network. Used for loop response measurements when output voltage is set using
external resistor divider network.
TP11
Output voltage test point at VOUT connector.
TP12
GND test point at VOUT connector.
Absolute maximum voltage for PWRGD is 6 V. Do not use JP7 to connect to VIN for input voltages above 6 V.
2.2 Efficiency
Figure 2-1 shows the efficiency for the TPS56921EVM-188 at an ambient temperature of 25°C.
100
90
80
Efficiency - %
70
60
VIN = 12 V
VIN = 5 V
50
40
30
20
10
0
0
1
2
3
4
5
6
7
8
9
Output Current - A
C001
Figure 2-1. TPS56921EVM-188 Efficiency
Figure 2-2 shows the efficiency for the TPS56921EVM-188 using a semi-log scale to more easily show efficiency
at lower output currents. The ambient temperature is 25°C.
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100
90
80
Efficiency - %
70
VIN = 5 V
60
50
40
30
VIN = 12 V
20
10
0
0.001
0.01
0.1
1
10
Output Current - A
Figure 2-2. TPS56921EVM-188 Low Current Efficiency
The efficiency may be lower at higher ambient temperatures, due to temperature variation in the drain-to-source
resistance of the internal MOSFET.
2.3 Output Voltage Load Regulation
Figure 2-3 shows the load regulation for the TPS56921EVM-188.
0.2
0.15
VIN = 5 V
VIN = 12 V
Load Regulation - %
0.1
0.05
0
-0.05
-0.1
-0.15
-0.2
0
1
2
3
4
5
6
7
8
9
Output Current - A
C003
Figure 2-3. TPS56921EVM-188 Load Regulation
Measurements are given for an ambient temperature of 25°C.
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Test Setup and Results
2.4 Output Voltage Line Regulation
Figure 2-4 shows the line regulation for the TPS56921EVM-188.
0.05
0.04
0.03
IOUT = 4.5 A
Line Rgulation - %
0.02
0.01
0
-0.01
-0.02
-0.03
-0.04
-0.05
4
6
8
10
12
14
16
18
Input Voltage - V
C004
Figure 2-4. TPS56921EVM-188 Line Regulation
2.5 Load Transients
Figure 2-5 shows the TPS56921EVM-188 response to load transients. The current step is from 25% to 75% of
maximum rated load at 12-V input. The current step slew rate is 100 mA/µs. Total peak-to-peak voltage variation
is as shown, including ripple and noise on the output.
VOUT = 100 mV / div (ac coupled)
IOUT = 2 A / div
Load step = 2.25 - 6.75 A, slew rate = 100 mA / µsec
Time = 200 µsec / div
Figure 2-5. TPS56921EVM-188 Transient Response
2.6 Loop Characteristics
Figure 2-6 shows the TPS56921EVM-188 loop-response characteristics when the output voltage is set by the
external resistor divider network. Gain and phase plots are shown for VIN voltage of 12 V. Load current for the
measurement is 4 A.
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60
180
40
120
60
0
0
Gain
-20
-60
-40
-120
-60
10
100
1000
10000
Phase - Degrees
Gain - dB
Phase
20
-180
1000000
100000
Frequency - Hz
C005
Figure 2-6. TPS56921EVM-188 Loop Response, VOUT Set by Resistor Divider
Figure 2-7 shows the TPS56921EVM-188 loop-response characteristics when the output voltage is set by the
external resistor divider network. Gain and phase plots are shown for VIN voltage of 12 V. Load current for the
measurement is 4 A.
60
180
40
120
60
0
0
Gain
-20
-60
-40
-120
-60
10
100
1000
10000
100000
Phase - Degrees
Gain - dB
Phase
20
-180
1000000
Frequency - Hz
C005
Figure 2-7. TPS56921EVM-188 Loop Response, VOUT Set by I2C Interface
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Test Setup and Results
2.7 Output Voltage Ripple
Figure 2-8 shows the TPS56921EVM-188 output voltage ripple. The output current is the rated full load of 9 A
and VIN = 12 V. The ripple voltage is measured directly across the output capacitors.
VOUT = 20 mV / div (ac coupled)
PH = 5 V / div
Time = 1 µsec / div
Figure 2-8. TPS56921EVM-188 Output Ripple
2.8 Input Voltage Ripple
Figure 2-9 shows the TPS56921EVM-188 input voltage. The output current is the rated full load of 9 A and VIN =
12 V. The ripple voltage is measured directly across the input capacitors.
VIN = 200 mV / div (ac coupled)
PH = 5 V / div
Time = 1 µsec / div
Figure 2-9. TPS56921EVM-188 Input Ripple
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Test Setup and Results
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2.9 Powering Up
Figure 2-10 and Figure 2-11 show the start-up waveforms for the TPS56921EVM-188. In Figure 2-10, the output
voltage ramps up as soon as the input voltage reaches the UVLO threshold as set by the R1 and R2 resistor
divider network. In Figure 2-11, the input voltage is initially applied and the output is inhibited by using a jumper
at JP2 to tie EN to GND. When the jumper is removed, EN is released. When the EN voltage reaches the
enable-threshold voltage, the start-up sequence begins and the output voltage ramps up to the externally set
value of 1.1 V. The input voltage for these plots is 12 V and the load is 1 Ω. Figure 2-12 shows a detailed view of
the output voltage ramp up.
VIN = 10 V / div
EN = 2 V / div
SS = 2 V / div
VOUT = 1 V / div
Time = 2 msec / div
Figure 2-10. TPS56921EVM-188 Start-Up Relative to VIN
VIN = 10 V / div
EN = 2 V / div
SS = 2 V / div
VOUT = 1 V / div
Time = 2 msec / div
Figure 2-11. TPS56921EVM-188 Start-Up Relative to Enable
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VIN = 5 V / div
VOUT = 500 mV / div
Time = 2 msec / div
Figure 2-12. TPS56921EVM-188 Start-Up Relative to VIN Detail
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Board Layout
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3 Board Layout
This section provides a description of the TPS56921EVM-188 board layout and layer illustrations.
3.1 Layout
The board layout for the TPS56921EVM-188 is shown in Figure 3-1 through Figure 3-5. The top-side layer of the
EVM is laid out in a manner typical of a user application. The top, bottom, and internal layers are 2-oz. copper.
The top layer contains the main power traces for PVIN, VIN, VOUT, and VPHASE. Also on the top layer are
connections for the remaining pins of the TPS56921 and a large area filled with ground. The internal layer-1 is
dedicated to a power ground plane. the internal layer-2 contains an analog ground fill area. This analog ground
is used as a return for the I2C interface as well as for sensitive analog circuits for RT, SS, EN, COMP and
VSENSE. The analog ground is connected to the main power ground at one place to inhibit circulating currents.
This connection is made at the via near TP7. Internal layer-2 also contains additional fill areas for PVIN and
VOUT, as well as connections to the I2C interface connector at J3. The bottom layer contains a power ground
plane only. The top-side ground traces are connected to the bottom and internal ground planes with multiple vias
placed around the board including nine vias directly under the TPS56921 and 12 vias directly adjacent to the
TPS56921device to provide a thermal path from the top-side ground area to the internal layer-1 and bottom-side
ground planes.
The input decoupling capacitors (C1,C2, C3 and C4) and bootstrap capacitor (C8) are all located as close to
the IC as possible. Additionally, the voltage setpoint resistor divider components are kept close to the IC. The
voltage divider network ties to the output voltage at the point of regulation, the copper VOUT trace at the J4
output connector. For the TPS56921, an additional input bulk capacitor may be required, depending on the EVM
connection to the input supply.
Figure 3-1. TPS56921EVM-188 Top-Side Assembly
12
Figure 3-2. TPS56921EVM-188 Top-Side Layout
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Board Layout
Figure 3-3. TPS56921EVM-188 Internal Layer-1
Layout
Figure 3-4. TPS56921EVM-188 Internal Layer-2
Layout
Figure 3-5. TPS56921EVM-188 Bottom-Side Layout
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Schematic and Bill of Materials
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4 Schematic and Bill of Materials
This section presents the TPS56921EVM-188 schematic and bill of materials.
4.1 Schematic
Figure 4-1 is the schematic for the TPS56921EVM-188.
TP1
J1
VIN
1
VIN
2
GND
TP2
C1
4.7uF
TP5
JP1
VIN
R6
100k
1
2
PVIN
U1
J2
18 VIN
17 PVIN
PVIN = 4.5 - 17 V
2
1
GND
C3
10uF
10uF
0.1uF
open
C5
R2
JP2
EN
1
GND
2
open
PWRGD 8
BOOT 7
16 PVIN
3 EN
R1
C4
C2
TP4
PG-PU
VIN
0.01uF
11 SDA
12 SCL
R3
9 A0
10 A1
100k
C8
0.1uF
PH 6
VOUT 20
VSENSE 19
COMP 1
JP3
I2C_SCL_PU
1
I2C_SCL
2
10.0k
JP4
1
I2C_SDA_PU
2
I2C_SDA
C10
C11
100uF
100uF
open
0
JP6
I2C_A1
1
I2C_A0_PD
I2C_A1_PD
2
VOUT
GND
TP9
R10
C12
10.0k
open
R11
S1
SHORT
2
J4
C7
I2C_SCL
1
2
R7
1.58k
I2C_SDA
JP5
TP12
51.1 TP10
0.022uF
I2C_A0
TP11
R9
GND 14
GND 15
220pF
10.0k
C9
R8
TP7
C6
R5
R4
VOUT= 1.1V , IOUT = 9 A max
1
PWPD
21
J3
L1
1.0uH
TP6
PH 4
PH 5
2 SS
13 RT/CLK
I2C_VIN
1
2
3
4
5
6
7
8
9
10
JP7
2
TPS56921PWP
TP3
PVIN
1
VIN
TP8
26.7k
Figure 4-1. TPS56921EVM-188 Schematic
14
TPS56921 Buck Converter Evaluation Module User's Guide
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SLVU793A – OCTOBER 2012 – REVISED JUNE 2021
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Schematic and Bill of Materials
4.2 Bill of Materials
Table 4-1 presents the bill of materials for the TPS56921EVM-188.
Table 4-1. TPS56921EVM-188 Bill of Materials
Count RefDes
Value
Description
Size
Part Number
MFR
1
C1
4.7uF
Capacitor, Ceramic, 25V, X5R, 10%
805
Std
Std
2
C2, C3
10uF
Capacitor, Ceramic, 25V, X5R, 10%
1206
Std
Std
2
C4, C8
0.1uF
Capacitor, Ceramic, 25V, X5R, 10%
603
Std
Std
1
C5
0.01uF
Capacitor, Ceramic, 25V, X7R, 10%
603
Std
Std
1
C6
220pF
Capacitor, Ceramic, 50V, NPO, 5%
603
Std
Std
1
C7
0.022uF
Capacitor, Ceramic, 50V, X7R, 10%
603
Std
Std
2
C9, C10
100uF
Capacitor, Ceramic, 6.3V, X5R, 20%
1210
Std
Std
0
C11
open
Capacitor, Ceramic
1210
Std
Std
0
C12
open
Capacitor, Ceramic
603
Std
Std
7
JP1, JP2, JP3,
JP4, JP5, JP6,
JP7
PEC02S
AAN
Header, Male 2-pin, 100mil spacing,
0.100 inch x 2
PEC02SAAN
Sullins
2
J1, J2
ED555/2
DS
Terminal Block, 2-pin, 6-A, 3.5mm
0.27 x 0.25 inch
ED555/2DS
OST
1
J3
PEC05D
AAN
Header, Male 2x5-pin, 100mil spacing
0.100 inch x 5 X
2
PEC05DAAN
Sullins
1
J4
ED120/2
DS
Terminal Block, 2-pin, 15-A, 5.1mm
0.40 x 0.35 inch
ED120/2DS
OST
1
L1
1.0uH
Inductor, Power Choke
7.0 x 6.9 mm
744311100
Wurth Elektronik
0
R1
open
Resistor, Chip, 1/16W, 1%
603
Std
Std
0
R2
open
Resistor, Chip, 1/16W, 1%
603
Std
Std
2
R3, R6
100k
Resistor, Chip, 1/16W, 1%
603
Std
Std
3
R4, R5, R10
10.0k
Resistor, Chip, 1/16W, 1%
603
Std
Std
1
R7
1.58k
Resistor, Chip, 1/16W, 1%
603
Std
Std
1
R8
0
Resistor, Chip, 1/16W, 1%
603
Std
Std
1
R9
51.1
Resistor, Chip, 1/16W, 1%
603
Std
Std
1
R11
26.7k
Resistor, Chip, 1/16W, 1%
603
Std
Std
3
TP1, TP3,TP11
5000
Test Point, Red, Thru Hole Color Keyed
0.100 x 0.100
inch
5000
Keystone
4
TP2, TP4 ,TP8,
TP12
5001
Test Point, Black, Thru Hole Color Keyed
0.100 x 0.100
inch
5001
Keystone
5
TP5, TP6, TP7,
TP9, TP10
5002
Test Point, White, Thru Hole Color Keyed
0.100 x 0.100
inch
5002
Keystone
1
U1
TPS5692 IC, 4.5V to 17V Input, 9A Synchronous
1PWP
Step Down SWIFTConverter With VID
Control
HTSSOP
TPS56921PWP
TI
7
--
Shunt, 100-mil, Black
0.100
929950-00
3M
1
--
Label (See Note 5)
1.25 x 0.25 inch
THT-13-457-10
Brady
1
--
PCB, 3" x 3" x 0.062"
PWR188
Any
5 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision * (October 2012) to Revision A (June 2021)
Page
• Updated user's guide title................................................................................................................................... 2
• Updated the numbering format for tables, figures, and cross-references throughout the document. ................2
SLVU793A – OCTOBER 2012 – REVISED JUNE 2021
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TPS56921 Buck Converter Evaluation Module User's Guide
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15
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