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TPS57060-Q1
SLVSAP2C – DECEMBER 2010 – REVISED FEBRUARY 2016
TPS57060-Q1 0.5-A 60-V Step-Down DC-DC Converter With Eco-mode™
1 Features
3 Description
•
•
The TPS57060-Q1 device is a 60-V 0.5-A step-down
regulator with an integrated high-side MOSFET.
Current-mode control provides simple external
compensation and flexible component selection. A
low-ripple pulse-skip mode reduces the no load,
regulated output supply current to 116 μA. When the
enable pin is in the low state, the shutdown current is
reduced to 1.3 μA.
1
•
•
•
•
•
•
•
•
•
•
•
•
Qualified for Automotive Applications
AEC-Q100 Qualified with the Following Results:
– Device Temperature Grade 1: –40°C to
+125°C
– Device HBM ESD Classification Level 2
– Device CDM ESD Classification Level C4B
3.5-V to 60-V Input Voltage Range
200-mΩ High-Side MOSFET
High Efficiency at Light Loads with a Pulse
Skipping Eco-mode™ Control Scheme
116-μA Operating Quiescent Current
1.3-μA Shutdown Current
100-kHz to 2.5-MHz Switching Frequency
Synchronizes to External Clock
Adjustable Slow Start/Sequencing
Undervoltage and Overvoltage Power Good
Output
Adjustable UVLO Voltage and Hysteresis
0.8-V Internal Voltage Reference
Supported by SwitcherPro™ Software Tool
(www.ti.com/tool/SwitcherPro)
2 Applications
•
•
•
•
•
12-V, 24-V, and 48-V Industrial and Commercial
Low Power Systems
Automotive Infotainment, Head Unit, Display
Navigation, Audio and Clusters
Automotive Body Applications, HVAC, Wireless
Charging
Advanced Driver-Assistance System (ADAS),
Rear-View Camera Module, Blind Spot Radar
Industrial DC Power Systems
Undervoltage lockout is internally set at 2.5 V, but
can be increased using the enable pin. The output
voltage startup ramp is controlled by the slow start
pin that can also be configured for sequencing and
tracking. An open-drain power good signal indicates
the output is within 92% to 109% of the nominal
voltage.
A wide switching frequency range allows efficiency
and external component size to be optimized.
Frequency fold back and thermal shutdown protects
the part during an overload condition.
The TPS57060-Q1 device is available in a 10-pin
thermally enhanced MSOP-PowerPAD™ package
(DGQ) and a VSON (DRC) package.
Device Information(1)
PART
NUMBER
PACKAGE
TPS57060-Q1
BODY SIZE (NOM)
MSOP-PowerPAD (10)
3.00 mm × 3.00 mm
VSON (10)
3.00 mm × 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Efficiency vs Load Current
Simplified Schematic
100
VIN
90
PWRGD
80
EN
BOOT
PH
SS /TR
RT /CLK
COMP
Efficiency - %
TPS57060-Q1
70
60
50
40
30
VI = 12 V,
VO = 3.3 V,
fsw = 500 kHz
20
VSENSE
10
0
GND
0
0.05
0.1 0.15
0.2 0.25 0.3 0.35
Load Current - A
0.4 0.45
0.5
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS57060-Q1
SLVSAP2C – DECEMBER 2010 – REVISED FEBRUARY 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
4
4
4
5
5
7
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Detailed Description ............................................ 11
7.1
7.2
7.3
7.4
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
11
12
12
24
8
Application and Implementation ........................ 29
8.1 Application Information............................................ 29
8.2 Typical Application ................................................. 29
9 Power Supply Recommendations...................... 37
10 Layout................................................................... 37
10.1 Layout Guidelines ................................................. 37
10.2 Layout Example .................................................... 38
10.3 Power Dissipation Estimate .................................. 39
11 Device and Documentation Support ................. 40
11.1
11.2
11.3
11.4
11.5
11.6
Device Support......................................................
Documentation Support ........................................
Community Resource............................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
40
40
40
40
40
40
12 Mechanical, Packaging, and Orderable
Information ........................................................... 40
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (December 2015) to Revision C
•
Page
Changed the test condition and removed the redundant values for the voltage reference parameter in the Electrical
Characteristics table ............................................................................................................................................................... 5
Changes from Revision A (December 2010) to Revision B
Page
•
Added the AEC-Q100 list items to the Features section........................................................................................................ 1
•
Added ESD Ratings table, Recommended Operating Conditions table,Feature Description section, Device
Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout
section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section ...... 1
•
Added the DRC package drawing ......................................................................................................................................... 3
•
Reworded the PH output voltage specifications and specified the maximum value for TJ = –40°C in the Absolute
Maximum Ratings table for clarity .......................................................................................................................................... 4
•
Deleted the RθJA values for the custom board and changed the other values in the Thermal Information table................... 5
•
Reworded the PWRGD switching threshold specifications in the Electrical Characteristics table for clarity ........................ 6
•
Deleted the Estimated Circuit Area section ......................................................................................................................... 39
2
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SLVSAP2C – DECEMBER 2010 – REVISED FEBRUARY 2016
5 Pin Configuration and Functions
DGQ Package
10-Pin MSSOP PowerPAD
Top View
BOOT
VIN
EN
SS/TR
RT/CLK
1
10
2
9
Thermal
Pad
(11)
3
4
8
7
6
5
DRC Package
10-Pin VSON With Thermal Pad
Top View
PH
GND
COMP
VSENSE
PWRGD
BOOT
1
10
PH
VIN
EN
SS/TR
RT/CLK
2
9
GND
COMP
VSENSE
PWRGD
3
4
5
Thermal
Pad
(11)
8
7
6
Pin Functions
PIN
I/O
DESCRIPTION
NAME
NO.
BOOT
1
O
A bootstrap capacitor is required between BOOT and PH. If the voltage on this capacitor is below the
minimum required by the output device, the output is forced to switch off until the capacitor is refreshed.
COMP
8
O
Error amplifier output, and input to the output switch current comparator. Connect frequency compensation
components to this pin.
EN
3
I
Enable pin, internal pullup current source. Pull below 1.2 V to disable. Float to enable. Adjust the input
undervoltage lockout with two resistors.
GND
9
—
PH
10
I
The source of the internal high-side power MOSFET.
PWRGD
6
O
An open drain output, asserts low if output voltage is low due to thermal shutdown, dropout, overvoltage or
EN shut down.
Ground
RT/CLK
5
I
Resistor Timing and External Clock. An internal amplifier holds this pin at a fixed voltage when using an
external resistor to ground to set the switching frequency. If the pin is pulled above the PLL upper threshold,
a mode change occurs and the pin becomes a synchronization input. The internal amplifier is disabled and
the pin is a high impedance clock input to the internal PLL. If clocking edges stop, the internal amplifier is reenabled and the mode returns to a resistor set function.
SS/TR
4
I
Slow-start and Tracking. An external capacitor connected to this pin sets the output rise time. Because the
voltage on this pin overrides the internal reference, it can be used for tracking and sequencing.
VIN
2
I
Input supply voltage, 3.5 V to 60 V.
VSENSE
7
I
Inverting node of the transconductance (gm) error amplifier.
PowerPAD
11
—
GND pin must be electrically connected to the exposed pad on the printed circuit board for proper operation.
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
VIN
–0.3
65
EN (2)
–0.3
BOOT
Input voltage
VSENSE
–0.3
3
COMP
–0.3
3
PWRGD
–0.3
6
SS/TR
–0.3
3
RT/CLK
–0.3
3.6
–0.6
65
–1
65
–2
65
PH
200 ns
30 ns
DC voltage, TJ = –40°C
PAD to GND
Source current
V
–0.85
65
–200
200
mV
EN
100
μA
BOOT
100
mA
VSENSE
10
μA
PH
Current Limit
RT/CLK
100
VIN
μA
Current Limit
100
μA
PWRGD
10
mA
SS/TR
200
μA
COMP
Sink current
V
8
DC voltage
Voltage difference
5
73
BOOT-PH
Output voltage
UNIT
Operating junction temperature
–40
150
°C
Storage temperature, Tstg
–65
150
°C
(1)
(2)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
See the Enable and Adjusting Undervoltage Lockout (UVLO) section for details.
6.2 ESD Ratings
VALUE
Human-body model (HBM), per AEC Q100-002 (1)
V(ESD)
(1)
Electrostatic
discharge
Charged-device model (CDM), per AEC
Q100-011
UNIT
±2000
All pins
±500
Corner pins (1, 5, 6, and 10)
±750
V
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
VIN supply voltage
3.5
60
V
Output voltage for adjustable voltage
0.8
VIN
V
0.5
A
Output current capability
Effective input capacitance
3
Operating Ambient temperature, TA
4
–40
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µF
125
°C
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SLVSAP2C – DECEMBER 2010 – REVISED FEBRUARY 2016
6.4 Thermal Information
TPS57060-Q1
THERMAL METRIC (1) (2)
DGQ (MSOP-PowerPAD)
DRC (VSON)
10 PINS
10 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
67.4
45.2
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
46.7
52.1
°C/W
RθJB
Junction-to-board thermal resistance
38.4
20.6
°C/W
ψJT
Junction-to-top characterization parameter
1.9
0.9
°C/W
ψJB
Junction-to-board characterization parameter
38.1
20.8
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
15.9
5.2
°C/W
(1)
(2)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
Power rating at a specific ambient temperature TA should be determined with a junction temperature of 150°C. This is the point where
distortion starts to substantially increase. See the Power Dissipation Estimate section for more information.
6.5 Electrical Characteristics
TJ = –40°C to 150°C, VIN = 3.5 to 60 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY VOLTAGE (VIN PIN)
Operating input voltage
Internal undervoltage lockout
threshold
Shutdown supply current
Operating: nonswitching supply
current
3.5
60
V
No voltage hysteresis, rising and falling
2.5
V
EN = 0 V, 25°C, 3.5 V ≤ VIN ≤ 60 V
1.3
4
EN = 0 V, 125°C, 3.5 V ≤ VIN ≤ 60 V
1.9
6.5
VSENSE = 0.83 V, VIN = 12 V, 25°C
116
136
μA
1.25
1.36
V
μA
ENABLE AND UVLO (EN PIN)
Enable threshold voltage
Input current
No voltage hysteresis, rising and falling, 25°C
1.15
Enable threshold +50 mV
–3.8
Enable threshold –50 mV
–0.9
Hysteresis current
μA
μA
–2.9
VOLTAGE REFERENCE
Voltage reference
0.792
0.8
0.808
V
HIGH-SIDE MOSFET
On-resistance
VIN = 3.5 V, BOOT-PH = 3 V
300
VIN = 12 V, BOOT-PH = 6 V
200
410
mΩ
ERROR AMPLIFIER
Input current
50
nA
Error amplifier transconductance (gM) –2 μA < ICOMP < 2 μA, VCOMP = 1 V
97
μMhos
Error amplifier transconductance (gM) –2 μA < ICOMP < 2 μA, VCOMP = 1 V,
during slow start
VVSENSE = 0.4 V
26
μMhos
Error amplifier dc gain
VVSENSE = 0.8 V
Error amplifier bandwidth
Error amplifier source/sink
V(COMP) = 1 V, 100 mV overdrive
COMP to switch current
transconductance
10,000
V/V
2700
kHz
±7
μA
1.9
A/V
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Electrical Characteristics (continued)
TJ = –40°C to 150°C, VIN = 3.5 to 60 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
0.6
0.94
A
182
°C
CURRENT LIMIT
Current limit threshold
VIN = 12 V, TJ = 25°C
THERMAL SHUTDOWN
Thermal shutdown
TIMING RESISTOR AND EXTERNAL CLOCK (RT/CLK PIN)
fSW
Switching frequency using RT mode
VIN = 12 V
100
Switching frequency
VIN = 12 V, RT = 200 kΩ
450
Switching frequency using CLK mode VIN = 12 V
581
300
Minimum CLK input pulse width
2500
kHz
720
kHz
2200
kHz
40
RT/CLK high threshold
VIN = 12 V
1.9
RT/CLK low threshold
VIN = 12 V
RT/CLK falling edge to PH rising
edge delay
Measured at 500 kHz with RT resistor in series
PLL lock in time
Measured at 500 kHz
0.45
ns
2.2
V
0.7
V
60
ns
100
μs
SLOW START AND TRACKING (SS/TR)
Charge current
VSS/TR = 0.4 V
2
μA
SS/TR-to-VSENSE matching
VSS/TR = 0.4 V
45
mV
SS/TR-to-reference crossover
98% nominal
1.0
V
SS/TR discharge current (overload)
VSENSE = 0 V, V(SS/TR) = 0.4 V
112
μA
SS/TR discharge voltage
VSENSE = 0 V
54
mV
VSENSE falling (fault)
92
POWER GOOD (PWRGD PIN)
PWRGDTH
6
PWRGD switching threshold as % of
the nominal VSENSE
VSENSE rising (good)
94
VSENSE rising (fault)
109
VSENSE falling (good)
107
% of
VSENSE
2
% of
VSENSE
VSENSE = VREF, V(PWRGD) = 5.5 V, 25°C
10
nA
I(PWRGD) = 3 mA, VSENSE < 0.79 V
50
Hysteresis
VSENSE falling and rising
Output high leakage
On resistance
Minimum VIN for defined output
V(PWRGD) < 0.5 V, II(PWRGD) = 100 μA
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0.95
Ω
1.5
V
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SLVSAP2C – DECEMBER 2010 – REVISED FEBRUARY 2016
0.816
500
VI = 12 V
VI = 12 V
375
Vref - Voltage Reference - V
RDSON - Static Drain-Source On-State Resistance - mW
6.6 Typical Characteristics
BOOT-PH = 3 V
250
BOOT-PH = 6 V
125
0
-50
-25
0
25
50
75
100
TJ - Junction Temperature - °C
125
150
0.808
0.800
0.792
0.784
-50
Figure 1. On Resistance vs Junction Temperature
-25
0
25
50
75
100
TJ - Junction Temperature - °C
125
150
Figure 2. Voltage Reference vs Junction Temperature
1.1
610
VI = 12 V,
RT = 200 kW
VI = 12 V
fs - Switching Frequency - kHz
600
Switch Current - A
1
0.9
0.8
590
580
570
560
0.7
-50
-25
0
25
50
75
100
125
550
-50
150
-25
0
TJ - Junction Temperature - °C
25
50
75
100
TJ - Junction Temperature - °C
150
Figure 4. Switching Frequency vs Junction Temperature
Figure 3. Switch Current Limit vs Junction Temperature
2500
500
VI = 12 V,
TJ = 25°C
2000
fs - Switching Frequency - kHz
fs - Switching Frequency - kHz
125
1500
1000
500
0
0
25
50
75
100
125
RT/CLK - Resistance - kW
150
175
200
Figure 5. Switching Frequency vs RT/CLK Resistance HighFrequency Range
VI = 12 V,
TJ = 25°C
400
300
200
100
0
200
300
400
500
600 700
800
900
RT/CLK - Resistance - kW
1000 1100
1200
Figure 6. Switching Frequency vs RT/CLK Resistance LowFrequency Range
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Typical Characteristics (continued)
150
40
VI = 12 V
VI = 12 V
130
110
gm - mA/V
gm - mA/V
30
90
20
70
10
-50
-25
0
25
50
75
100
TJ - Junction Temperature - °C
125
50
-50
150
-25
0
25
50
75
100
125
150
TJ - Junction Temperature - °C
Figure 7. EA Transconductance During Slow Start vs
Junction Temperature
Figure 8. EA Transconductance vs Junction Temperature
1.40
-3.25
VI = 12 V,
VI(EN) = Threshold +50 mV
VI = 12 V
-3.5
I(EN) - mA
EN - Threshold - V
1.30
-3.75
1.20
-4
1.10
-50
-25
0
25
50
75
100
125
150
-4.25
-50
-25
0
Figure 9. EN Pin Voltage vs Junction Temperature
75
100
125
150
Figure 10. EN Pin Current vs Junction Temperature
VI = 12 V,
VI(EN) = Threshold -50 mV
VI = 12 V
-0.85
-1.5
I(SS/TR) - mA
I(EN) - mA
50
-1
-0.8
-0.9
-0.95
-2
-2.5
-1
-50
-25
0
25
50
75
100
TJ - Junction Temperature - °C
125
150
Figure 11. EN Pin Current vs Junction Temperature
8
25
TJ - Junction Temperature - °C
TJ - Junction Temperature - °C
-3
-50
-25
0
25
50
75
100
TJ - Junction Temperature - °C
125
150
Figure 12. SS/TR Charge Current vs Junction Temperature
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Typical Characteristics (continued)
120
100
VI = 12 V
VI = 12 V,
TJ = 25°C
80
% of Nominal fsw
II(SS/TR) - mA
115
110
60
40
105
20
100
-50
0
-25
0
25
50
75
100
TJ - Junction Temperature - °C
125
150
0
Figure 13. SS/TR Discharge Current vs Junction
Temperature
0.6
0.8
2
VI = 12 V
TJ = 25°C
1.5
1.5
I(VIN) - mA
I(VIN) - mA
0.4
VSENSE - V
Figure 14. Switching Frequency vs VSENSE
2
1
0.5
1
0.5
0
-50
0
-25
0
25
50
75
100
TJ - Junction Temperature - °C
125
150
Figure 15. Shutdown Supply Current vs Junction
Temperature
0
20
30
40
VI - Input Voltage - V
50
60
140
VI = 12 V,
VI(VSENSE) = 0.83 V
o
TJ = 25 C,
VI(VSENSE) = 0.83 V
130
120
120
I(VIN) - mA
130
110
100
90
-50
10
Figure 16. Shutdown Supply Current vs Input Voltage (VIN)
140
I(VIN) - mA
0.2
110
100
90
-25
0
25
50
75
100
TJ - Junction Temperature - °C
125
150
Figure 17. VIN Supply Current vs Junction Temperature
0
20
40
VI - Input Voltage - V
60
Figure 18. VIN Supply Current vs Input Voltage
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Typical Characteristics (continued)
115
100
VI = 12 V
VI = 12 V
PWRGD Threshold - % of Vref
RDSON - W
80
60
40
VSENSE Rising
110
VSENSE Falling
105
100
VSENSE Rising
95
20
VSENSE Falling
90
0
-50
-25
0
25
50
75
125
100
85
-50
150
-25
0
TJ - Junction Temperature - °C
Figure 19. PWRGD On Resistance vs Junction Temperature
25
50
75
100
TJ - Junction Temperature - °C
125
150
Figure 20. PWRGD Threshold vs Junction Temperature
3
2.3
2.1
VI(VIN) - V
VI(BOOT-PH) - V
2.75
2.50
1.9
2.25
1.7
-50
-25
0
25
50
75
100
TJ - Junction Temperature - °C
125
2
-50
150
Figure 21. BOOT-PH UVLO vs Junction Temperature
25
50
75
100
TJ - Junction Temperature - °C
125
150
60
V(SS/TR) = 0.2 V
VI = 12 V
VIN = 12 V
TJ = 25°C
500
55
400
50
Offset - mV
Offset Voltage Threshold (mV)
0
Figure 22. Input Voltage (UVLO) vs Junction Temperature
600
300
45
200
40
100
35
0
0
200
400
600
Voltage Sense (mV)
Figure 23. SS/TR to VSENSE Offset vs VSENSE
10
-25
800
30
-50
-25
0
25
50
75
100
125
150
TJ - Junction Temperature - °C
Figure 24. SS/TR to VSENSE Offset vs Temperature
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7 Detailed Description
7.1 Overview
The TPS57060-Q1 device is a 60-V, 0.5-A, step-down (buck) regulator with an integrated high side n-channel
MOSFET. To improve performance during line and load transients the device implements a constant frequency,
current mode control which reduces output capacitance and simplifies external frequency compensation design.
The wide switching frequency of 100 kHz to 2500 kHz allows for efficiency and size optimization when selecting
the output filter components. A resistor to ground on the RT/CLK pin sets the switching frequency. The device
has an internal phase lock loop (PLL) on the RT/CLK pin that is used to synchronize the power switch turn on to
a falling edge of an external system clock.
The TPS57060-Q1 device has a default start up voltage of approximately 2.5 V. The EN pin has an internal
pullup current source that can be used to adjust the input voltage under voltage lockout (UVLO) threshold with
two external resistors. In addition, the pullup current provides a default condition. When the EN pin is floating the
device will operate. The operating current is 116 μA when not switching and under no load. When the device is
disabled, the supply current is 1.3 μA.
The integrated 200-mΩ high-side MOSFET allows for high efficiency power supply designs capable of delivering
0.5 amperes of continuous current to a load. The TPS57060-Q1 device reduces the external component count by
integrating the boot recharge diode. A capacitor between the BOOT and PH pins supplies the bias voltage for the
integrated high-side MOSFET. The boot capacitor voltage is monitored by an UVLO circuit and will turn the highside MOSFET off when the boot voltage falls below a preset threshold. The TPS57060-Q1 device can operate at
high duty cycles because of the boot UVLO. The output voltage can be stepped down to as low as the 0.8-V
reference.
The TPS57060-Q1 device has a power good comparator (PWRGD) which asserts when the regulated output
voltage is less than 92% or greater than 109% of the nominal output voltage. The PWRGD pin is an open drain
output which deasserts when the VSENSE pin voltage is between 94% and 107% of the nominal output voltage
allowing the pin to transition high when a pullup resistor is used.
The TPS57060-Q1 device minimizes excessive output overvoltage (OV) transients by taking advantage of the
OV power good comparator. When the OV comparator is activated, the high-side MOSFET is turned off and
masked from turning on until the output voltage is lower than 107%.
The SS/TR (slow start/tracking) pin minimizes inrush currents and provides power-supply sequencing during
power up. A small value capacitor should be coupled to the pin to adjust the slow start time. A resistor divider
can be coupled to the pin for critical power supply sequencing requirements. The SS/TR pin is discharged before
the output powers up. This discharging ensures a repeatable restart after an over-temperature fault, UVLO fault
or a disabled condition.
The TPS57060-Q1 device also discharges the slow start capacitor during overload conditions with an overload
recovery circuit. The overload recovery circuit will slow start the output from the fault voltage to the nominal
regulation voltage when a fault condition is removed. A frequency foldback circuit reduces the switching
frequency during startup and overcurrent fault conditions to help control the inductor current.
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7.2 Functional Block Diagram
PWRGD
6
EN
3
VIN
2
Shutdown
UV
Thermal
Shutdown
Enable
Comparator
Logic
UVLO
Shutdown
Shutdown
Logic
OV
Enable
Threshold
Boot
Charge
Voltage
Reference
Boot
UVLO
Minimum
Clamp
Pulse
Skip
ERROR
AMPLIFIER
PWM
Comparator
VSENSE 7
Current
Sense
1 BOOT
Logic
And
PWM Latch
SS/TR 4
Shutdown
Slope
Compensation
10 PH
COMP 8
Frequency
Shift
Overload
Recovery
Maximum
Clamp
Oscillator
with PLL
11 POWERPAD
9 GND
5
RT/CLK
7.3 Feature Description
7.3.1 Fixed Frequency PWM Control
The TPS57060-Q1 device uses an adjustable fixed frequency, peak current mode control. The output voltage is
scaled downed to the internal voltage reference level using the external voltage divider resistors on the VSENSE
pin and this voltage is compared to an internal voltage reference by an error amplifier which drives the COMP
pin. An internal oscillator initiates the turn on of the high-side power switch. The error amplifier output is
compared to the high-side power-switch current. When the power switch current reaches the level set by the
COMP voltage, the power switch is turned off. The COMP pin voltage will increase and decrease as the output
current increases and decreases. The device implements a current limit by clamping the COMP pin voltage to a
maximum level. The Eco-Mode™ is implemented with a minimum clamp on the COMP pin.
7.3.2 Slope Compensation Output Current
The TPS57060-Q1 device adds a compensating ramp to the switch current signal. This slope compensation
prevents sub-harmonic oscillations. The available peak inductor current remains constant over the full duty-cycle
range.
12
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Feature Description (continued)
7.3.3 Low Dropout Operation and Bootstrap Voltage (BOOT)
The TPS57060-Q1 device has an integrated boot regulator, and requires a small ceramic capacitor between the
BOOT and PH pins to provide the gate drive voltage for the high-side MOSFET. The BOOT capacitor is
refreshed when the high-side MOSFET is off and the low-side diode conducts. The value of this ceramic
capacitor should be 0.1 μF. A ceramic capacitor with an X7R or X5R grade dielectric with a voltage rating of 10 V
or higher is recommended because of the stable characteristics overtemperature and voltage.
To improve drop out, the TPS57060-Q1 device is designed to operate at 100% duty cycle as long as the BOOT
to PH pin voltage is greater than 2.1 V. When the voltage from BOOT to PH drops below 2.1 V, the high-side
MOSFET is turned off using an UVLO circuit which allows the low-side diode to conduct and refresh the charge
on the BOOT capacitor. Because the supply current sourced from the BOOT capacitor is low, the high-side
MOSFET can remain on for more switching cycles than are required to refresh the capacitor, thus the effective
duty cycle of the switching regulator is high.
The effective duty cycle during dropout of the regulator is mainly influenced by the voltage drops across the
power MOSFET, inductor resistance, low-side diode and printed circuit board resistance. During operating
conditions in which the input voltage drops and the regulator is operating in continuous conduction mode, the
high-side MOSFET can remain on for 100% of the duty cycle to maintain output regulation, until the BOOT to PH
voltage falls below 2.1 V.
Attention must be taken in maximum duty cycle applications which experience extended time periods with light
loads or no load. When the voltage across the BOOT capacitor falls below the 2.1-V UVLO threshold, the highside MOSFET is turned off, but there may not be enough inductor current to pull the PH pin down to recharge the
BOOT capacitor. The high-side MOSFET of the regulator stops switching because the voltage across the BOOT
capacitor is less than 2.1 V. The output capacitor then decays until the difference in the input voltage and output
voltage is greater than 2.1 V, at which point the BOOT UVLO threshold is exceeded, and the device starts
switching again until the desired output voltage is reached. This operating condition persists until the input
voltage, the load current increases, or both. TI recommends to adjust the VIN stop voltage greater than the
BOOT UVLO trigger condition at the minimum load of the application using the adjustable VIN UVLO feature with
resistors on the EN pin.
The start and stop voltages for typical 3.3-V and 5-V output applications are shown in Figure 25 and Figure 26.
The voltages are plotted versus load current. The start voltage is defined as the input voltage needed to regulate
the output within 1%. The stop voltage is defined as the input voltage at which the output drops by 5% or stops
switching.
During high duty cycle conditions, the inductor current ripple increases while the BOOT capacitor is being
recharged resulting in an increase in ripple voltage on the output. This is due to the recharge time of the boot
capacitor being longer than the typical high side off time when switching occurs every cycle.
4
5.6
VO = 3.3 V
VO = 5 V
5.4
VI - Input Voltage - V
VI - Input Voltage - V
3.8
3.6
Start
3.4
Stop
3.2
5.2
Start
5
Stop
4.8
3
4.6
0
0.05
0.10
IO - Output Current - A
0.15
0.20
0
Figure 25. 3.3-V Start and Stop Voltage
0.05
0.10
IO - Output Current - A
0.15
Figure 26. 5-V Start and Stop Voltage
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Feature Description (continued)
7.3.4 Error Amplifier
The TPS57060-Q1 device has a transconductance amplifier for the error amplifier. The error amplifier compares
the VSENSE voltage to the lower of the SS/TR pin voltage or the internal 0.8-V voltage reference. The
transconductance (gm) of the error amplifier is 97 μA/V during normal operation. During the slow start operation,
the transconductance is a fraction of the normal operating gm. When the voltage of the VSENSE pin is below 0.8
V and the device is regulating using the SS/TR voltage, the gm is 25 μA/V.
The frequency compensation components (capacitor, series resistor and capacitor) are added to the COMP pin
to ground.
7.3.5 Voltage Reference
The voltage reference system produces a precise ±2% voltage reference over temperature by scaling the output
of a temperature stable bandgap circuit.
7.3.6 Adjusting the Output Voltage
The output voltage is set with a resistor divider from the output node to the VSENSE pin. TI recommends to use
1% tolerance or better divider resistors. Refer to the schematic in Figure 40, start with 10 kΩ for the R2 resistor
and use Equation 1 to calculate R1. To improve efficiency at light loads consider using larger value resistors. If
the values are too high the regulator will be more susceptible to noise and voltage errors from the VSENSE input
current will be noticeable
æ Vout - 0.8V ö
R1 = R2 ´ ç
÷
0.8 V
è
ø
(1)
7.3.7 Enable and Adjusting Undervoltage Lockout (UVLO)
The TPS57060-Q1 device is disabled when the VIN pin voltage falls below 2.5 V. If an application requires a
higher undervoltage lockout (UVLO), use the EN pin as shown in Figure 27 to adjust the input voltage UVLO by
using the two external resistors. Although using the UVLO adjust registers is not is not required, consistent
power-up behavior is highly recommended for operation. The EN pin has an internal pullup current source, I1, of
0.9 μA that provides the default condition of the TPS57060-Q1 device operating when the EN pin floats. When
the EN pin voltage exceeds 1.25 V, an additional 2.9 μA of hysteresis, Ihys, is added. This additional current
facilitates input voltage hysteresis. Use Equation 2 to set the external hysteresis for the input voltage. Use
Equation 3 to set the input start voltage.
TPS57060-Q1
VIN
Ihys
I1
0.9 mA
R1
2.9 mA
+
R2
EN
1.25 V
-
Figure 27. Adjustable Undervoltage Lockout (UVLO)
V
- VSTOP
R1 = START
IHYS
R2 =
14
(2)
VENA
VSTART - VENA
+ I1
R1
(3)
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Feature Description (continued)
Another technique to add input voltage hysteresis is shown in Figure 28. This method may be used, if the
resistance values are high from the previous method and a wider voltage hysteresis is needed. The resistor R3
sources additional hysteresis current into the EN pin.
TPS57060-Q1
VIN
Ihys
R1
I1
0.9 mA
2.9 mA
+
EN
R2
1.25 V
-
VOUT
R3
Figure 28. Adding Additional Hysteresis
R1 =
R2 =
VSTART - VSTOP
V
IHYS + OUT
R3
(4)
VENA
VSTART - VENA
V
+ I1 - ENA
R1
R3
(5)
Do not place a low-impedance voltage source with greater than 5 V directly on the EN pin. Do not place a
capacitor directly on the EN pin if VEN > 5 V when using a voltage divider to adjust the start and stop voltage.
The node voltage, (see Figure 29) must remain equal to or less than 5.8 V. The zener diode can sink up to 100
μA. The EN pin voltage can be greater than 5 V if the VIN voltage source has a high impedance and does not
source more than 100 μA into the EN pin.
VIN
IA
RUVLO1
EN
10 kW
Node
3
IB
RUVLO2
IC
5.8 V
UDG-10065
Figure 29. Node Voltage
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Feature Description (continued)
7.3.8 Slow Start and Tracking Pin (SS/TR)
The TPS57060-Q1 device effectively uses the lower voltage of the internal voltage reference or the SS/TR pin
voltage as the reference voltage of the power supply and regulates the output accordingly. A capacitor on the
SS/TR pin to ground implements a slow start time. The TPS57060-Q1 device has an internal pullup current
source of 2 μA that charges the external slow-start capacitor. The calculations for the slow start time (10% to
90%) are shown in Equation 6. The voltage reference (VREF) is 0.8 V and the slow start current (ISS) is 2μA. The
slow start capacitor should remain lower than 0.47 μF and greater than 0.47 nF.
Tss(ms) ´ Iss(m A)
Css(nF) =
Vref (V) ´ 0.8
(6)
At power up, the TPS57060-Q1 device does not start switching until the slow start pin is discharged to less than
40 mV to ensure a proper power up, see Figure 30.
Also, during normal operation, the TPS57060-Q1 device stops switching and the SS/TR must be discharged to
40 mV, when the VIN UVLO is exceeded, EN pin pulled below 1.25 V, or a thermal shutdown event occurs.
The VSENSE voltage will follow the SS/TR pin voltage with a 45-mV offset up to 85% of the internal voltage
reference. When the SS/TR voltage is greater than 85% on the internal reference voltage the offset increases as
the effective system reference transitions from the SS/TR voltage to the internal voltage reference (see
Figure 23). The SS/TR voltage will ramp linearly until clamped at 1.7 V.
EN
SS/TR
VSENSE
VOUT
Figure 30. Operation of SS/TR Pin When Starting
7.3.9 Overload Recovery Circuit
The TPS57060-Q1 has an overload recovery (OLR) circuit. The OLR circuit will slow start the output from the
overload voltage to the nominal regulation voltage when the fault condition is removed. The OLR circuit will
discharge the SS/TR pin to a voltage slightly greater than the VSENSE pin voltage using an internal pulldown of
100μA when the error amplifier is changed to a high voltage from a fault condition. When the fault condition is
removed, the output will slow start from the fault voltage to nominal output voltage.
16
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Feature Description (continued)
7.3.10 Constant Switching Frequency and Timing Resistor (RT/CLK Pin)
The switching frequency of the TPS57060-Q1 device is adjustable over a wide range from approximately 100
kHz to 2500 kHz by placing a resistor on the RT/CLK pin. The RT/CLK pin voltage is typically 0.5 V and must
have a resistor to ground to set the switching frequency. To determine the timing resistance for a given switching
frequency, use Equation 7 or the curves in Figure 31 or Figure 32. To reduce the solution size, set the switching
frequency as high as possible, but tradeoffs of the supply efficiency, maximum input voltage and minimum
controllable on time should be considered.
The minimum controllable on time is typically 130 ns and limits the maximum operating input voltage.
The maximum switching frequency is also limited by the frequency shift circuit. Use Equation 7 or the curves in
Figure 31 or Figure 32 to calculate the timing resistor values for the required switching frequency.
206033
RT (kOhm ) =
¦ sw (kHz )1.0888
(7)
2500
500
2000
fs - Switching Frequency - kHz
fs - Switching Frequency - kHz
VI = 12 V,
TJ = 25°C
1500
1000
500
0
0
25
50
75
100
125
150
RT/CLK - Clock Resistance - kW
175
200
VI = 12 V,
TJ = 25°C
400
300
200
100
0
200
300
400
500
600 700
800
900
RT/CLK - Resistance - kW
1000 1100
1200
Figure 32. Low Range RT
Figure 31. High Range RT
7.3.11 Overcurrent Protection and Frequency Shift
The TPS57060-Q1 device implements current mode control which uses the COMP pin voltage to turn off the
high-side MOSFET on a cycle-by-cycle basis. Each cycle the switch current and COMP pin voltage are
compared, when the peak switch current intersects the COMP voltage, the high side switch is turned off. During
overcurrent conditions that pull the output voltage low, the error amplifier responds by driving the COMP pin high,
increasing the switch current. The error amplifier output is clamped internally, which functions as a switch current
limit.
To increase the maximum operating switching frequency at high input voltages the TPS57060-Q1 device
implements a frequency shift. The switching frequency is divided by 8, 4, 2, and 1 as the voltage ramps from 0 to
0.8 vV on VSENSE pin.
The device implements a digital frequency shift to enable synchronizing to an external clock during normal
startup and fault conditions. Because the device can only divide the switching frequency by 8, the device
operates within a maximum input voltage limit that still allows for frequency shift protection.
During short-circuit events (particularly with high input voltage applications), the control loop has a finite minimum
controllable on time and the output has a low voltage. During the switch on time, the inductor current ramps to
the peak current limit because of the high input voltage and minimum on time. During the switch off time, the
inductor would normally not have enough off time and output voltage for the inductor to ramp down by the ramp
up amount. The frequency shift effectively increases the off time allowing the current to ramp down.
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Feature Description (continued)
7.3.12 Selecting the Switching Frequency
The switching frequency that is selected should be the lower value of the two equations, Equation 8 and
Equation 9. Equation 8 is the maximum switching frequency limitation set by the minimum controllable on time.
Setting the switching frequency above this value will cause the regulator to skip switching pulses.
Equation 9 is the maximum switching frequency limit set by the frequency shift protection. To have adequate
output short circuit protection at high input voltages, the switching frequency should be set to be less than the
fsw(maxshift) frequency. In Equation 9, to calculate the maximum switching frequency one must take into
account that the output voltage decreases from the nominal voltage to 0 V, the fdiv integer increases from 1 to 8
corresponding to the frequency shift.
In Figure 33, the solid line illustrates a typical safe operating area regarding frequency shift and assumes the
output voltage is zero volts, and the resistance of the inductor is 0.130 Ω, FET on resistance of 0.2 Ω and the
diode voltage drop is 0.5 V. The dashed line is the maximum switching frequency to avoid pulse skipping. Enter
these equations in a spreadsheet or other software or use the SwitcherPro design software to determine the
switching frequency.
fSW (max skip ) =
fSWshift =
1
tON
æ I ´R + V
dc
OUT + Vd
´ç L
ç VIN - IL ´ RDS(on ) + Vd
è
fDIV æç IL ´ Rdc + VOUT(sc ) + Vd
´
tON ç VIN - IL ´ RDS(on ) + Vd
è
ö
÷
÷
ø
(8)
ö
÷
÷
ø
where
•
•
•
•
•
•
•
•
•
IL = Inductor current
Rdc = Inductor resistance
VIN = Maximum input voltage
VOUT = Output voltage
VOUTSC = Output voltage during short
Vd = Diode voltage drop
rDS(on) = Switch on-resistance
tON = Controllable on-time
ƒDIV = Frequency divide (equals 1, 2, 4, or 8)
(9)
2500
fs - Switching Frequency - kHz
VO = 3.3 V
2000
Shift
1500
Skip
1000
500
0
10
20
30
40
VI - Input Voltage - V
50
60
Figure 33. Maximum Switching Frequency vs. Input Voltage
18
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Feature Description (continued)
7.3.13 How to Interface to RT/CLK Pin
The RT/CLK pin can be used to synchronize the regulator to an external system clock. To implement the
synchronization feature connect a square wave to the RT/CLK pin through the circuit network shown in
Figure 34. The square wave amplitude must transition lower than 0.5 V and higher than 2.2 V on the RT/CLK pin
and have an on time greater than 40 ns and an off time greater than 40 ns. The synchronization frequency range
is 300 kHz to 2200 kHz. The rising edge of the PH will be synchronized to the falling edge of RT/CLK pin signal.
The external synchronization circuit should be designed in such a way that the device will have the default
frequency set resistor connected from the RT/CLK pin to ground should the synchronization signal turn off. TI
recommends to use a frequency set resistor connected as shown in Figure 34 through a 50-Ω resistor to ground.
The resistor should set the switching frequency close to the external CLK frequency. TI recommends to AC
couple the synchronization signal through a 10-pF ceramic capacitor to RT/CLK pin and a 4-kΩ series resistor.
The series resistor reduces PH jitter in heavy load applications when synchronizing to an external clock and in
applications which transition from synchronizing to RT mode. The first time the CLK is pulled above the CLK
threshold the device switches from the RT resistor frequency to PLL mode. The internal 0.5-V voltage source is
removed and the CLK pin becomes high impedance as the PLL starts to lock onto the external signal. Because
there is a PLL on the regulator the switching frequency can be higher or lower than the frequency set with the
external resistor. The device transitions from the resistor mode to the PLL mode and then will increase or
decrease the switching frequency until the PLL locks onto the CLK frequency within 100 ms.
When the device transitions from the PLL to resistor mode the switching frequency will slow down from the CLK
frequency to 150 kHz, then reapply the 0.5-V voltage and the resistor then sets the switching frequency. The
switching frequency is divided by 8, 4, 2, and 1 as the voltage ramps from 0 to 0.8 V on VSENSE pin. The device
implements a digital frequency shift to enable synchronizing to an external clock during normal startup and fault
conditions. Figure 35, Figure 36 and Figure 37 show the device synchronized to an external system clock in
continuous conduction mode (CCM) discontinuous conduction (DCM) and pulse skip mode (PSM).
TPS57060-Q1
10 pF
4 kW
PLL
Rfset
EXT
Clock
Source
50 W
RT/CLK
Figure 34. Synchronizing to a System Clock
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Feature Description (continued)
PH
PH
EXT
EXT
IL
IL
Figure 35. Plot of Synchronizing in CCM
Figure 36. Plot of Synchronizing in DCM
PH
EXT
IL
Figure 37. Plot of Synchronizing in PSM
7.3.14 Power Good (PWRGD Pin)
The PWRGD pin is an open drain output. When the VSENSE pin is between 94% and 107% of the internal
voltage reference the PWRGD pin is de-asserted and the pin floats. TI recommends to use a pullup resistor
between the values of 1 kΩ and 100 kΩ to a voltage source that is 5.5 V or less. The PWRGD is in a defined
state when the VIN input voltage is greater than 1.5 V but with reduced current sinking capability. The PWRGD
achieves full current sinking capability as VIN input voltage approaches 3 V.
The PWRGD pin is pulled low when the VSENSE is lower than 92% or greater than 109% of the nominal internal
reference voltage. Also, the PWRGD is pulled low, if the UVLO or thermal shutdown are asserted or the EN pin
pulled low.
20
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Feature Description (continued)
7.3.15 Overvoltage Transient Protection
The TPS57060-Q1 device incorporates an overvoltage transient protection (OVTP) circuit to minimize voltage
overshoot when recovering from output fault conditions or strong unload transients on power supply designs with
low value output capacitance. For example, when the power supply output is overloaded the error amplifier
compares the actual output voltage to the internal reference voltage. If the VSENSE pin voltage is lower than the
internal reference voltage for a considerable time, the output of the error amplifier will respond by clamping the
error amplifier output to a high voltage. Thus, requesting the maximum output current. When the condition is
removed, the regulator output rises and the error amplifier output transitions to the steady state duty cycle. In
some applications, the power supply output voltage can respond faster than the error amplifier output can
respond, this actuality leads to the possibility of an output overshoot. The OVTP feature minimizes the output
overshoot, when using a low value output capacitor, by implementing a circuit to compare the VSENSE pin
voltage to OVTP threshold which is 109% of the internal voltage reference. If the VSENSE pin voltage is greater
than the OVTP threshold, the high-side MOSFET is disabled preventing current from flowing to the output and
minimizing output overshoot. When the VSENSE voltage drops lower than the OVTP threshold, the high-side
MOSFET is allowed to turn on at the next clock cycle.
7.3.16 Thermal Shutdown
The device implements an internal thermal shutdown to protect itself if the junction temperature exceeds 182°C.
The thermal shutdown forces the device to stop switching when the junction temperature exceeds the thermal
trip threshold. When the die temperature decreases below 182°C, the device reinitiates the power up sequence
by discharging the SS/TR pin.
7.3.17 Small Signal Model for Loop Response
Figure 38 shows an equivalent model for the TPS57060-Q1 control loop which can be modeled in a circuit
simulation program to check frequency response and dynamic load response. The error amplifier is a
transconductance amplifier with a gmEA of 97 μA/V. The error amplifier can be modeled using an ideal voltage
controlled current source. The resistor Ro and capacitor Co model the open loop gain and frequency response of
the amplifier. The 1-mV AC voltage source between the nodes a and b effectively breaks the control loop for the
frequency response measurements. Plotting c/a shows the small signal response of the frequency compensation.
Plotting a/b shows the small signal response of the overall loop. The dynamic loop response can be checked by
replacing RL with a current source with the appropriate load step amplitude and step rate in a time domain
analysis. This equivalent model is only valid for continuous conduction mode designs.
PH
VO
Power Stage
gmps 1.9 A/V
a
b
RESR
R1
RL
COMP
c
0.8 V
R3
CO
C2
RO
VSENSE
COUT
gmea
97 mA/V
R2
C1
Figure 38. Small Signal Model for Loop Response
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Feature Description (continued)
7.3.18 Simple Small-Signal Model for Peak Current-Mode Control
Figure 39 shows a simple small signal model that can be used to understand how to design the frequency
compensation. The TPS57060-Q1 power stage can be approximated to a voltage-controlled current source (duty
cycle modulator) supplying current to the output capacitor and load resistor. The control to output transfer
function is shown in Equation 10 and consists of a DC gain, one dominant pole, and one ESR zero. The quotient
of the change in switch current and the change in COMP pin voltage (node c in Figure 38) is the power stage
transconductance. The gmPS for the TPS57060-Q1 device is 1.9 A/V. The low-frequency gain of the power stage
frequency response is the product of the transconductance and the load resistance as shown in Equation 11.
As the load current increases and decreases, the low-frequency gain decreases and increases, respectively. This
variation with the load may seem problematic at first glance, but fortunately the dominant pole moves with the
load current (see Equation 12). The combined effect is highlighted by the dashed line in the right half of
Figure 39. As the load current decreases, the gain increases and the pole frequency lowers, keeping the 0-dB
crossover frequency the same for the varying load conditions which makes it easier to design the frequency
compensation. The type of output capacitor chosen determines whether the ESR zero has a profound effect on
the frequency compensation design. Using high ESR aluminum electrolytic capacitors may reduce the number
frequency compensation components needed to stabilize the overall loop because the phase margin increases
from the ESR zero at the lower frequencies (see Table 1).
VO
Adc
VC
RESR
fp
RL
gmps
COUT
fz
Figure 39. Simple Small-Signal Model and Frequency Response for Peak Current-Mode Control
VOUT
VC
æ
s
ç1 +
2
p
´ fZ
= Adc ´ è
æ
s
ç1 +
2p ´ fP
è
ö
÷
ø
ö
÷
ø
(10)
Adc = gmps ´ RL
fP =
fZ =
22
(11)
1
COUT ´ RL ´ 2p
(12)
1
COUT ´ RESR ´ 2p
(13)
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Feature Description (continued)
7.3.19 Small Signal Model for Frequency Compensation
The TPS57060-Q1 device uses a transconductance amplifier for the error amplifier and readily supports three of
the commonly-used frequency compensation circuits. Compensation circuits Type 2A, Type 2B, and Type 1 are
shown in Figure 40. Type 2 circuits most likely implemented in high bandwidth power-supply designs using low
ESR output capacitors. The Type 1 circuit is used with power-supply designs with high-ESR aluminum
electrolytic or tantalum capacitors.. Equation 14 and Equation 15 show how to relate the frequency response of
the amplifier to the small signal model in Figure 40. The open-loop gain and bandwidth are modeled using the RO
and CO shown in Figure 40. See the application section for a design example using a Type 2A network with a
low ESR output capacitor.
Equation 14 through Equation 23 are provided as a reference for those who prefer to compensate using the
preferred methods. Those who prefer to use prescribed method use the method outlined in the application
section or use switched information.
VO
R1
VSENSE
gmea
Type 2A
COMP
Type 2B
Type 1
Vref
R2
RO
R3
CO
C2
C1
R3
C2
C1
Figure 40. Types of Frequency Compensation
Aol
A0
P1
Z1
P2
A1
BW
Figure 41. Frequency Response of the Type 2A and Type 2B Frequency Compensation
Ro =
CO =
Aol(V/V)
gmea
(14)
gmea
2p ´ BW (Hz)
(15)
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Feature Description (continued)
æ
ö
s
ç1 +
÷
2p ´ fZ1 ø
è
EA = A0 ´
æ
ö æ
ö
s
s
ç1 +
÷ ´ ç1 +
÷
2
2
p
´
p
´
f
f
P1 ø è
P2 ø
è
A0 = gmea ´ Ro ´
R2
R1 + R2
A1 = gmea ´ Ro| | R3 ´
P1 =
Z1 =
P2 =
P2 =
P2 =
(16)
(17)
R2
R1 + R2
(18)
1
2p ´ Ro ´ C1
(19)
1
2p ´ R3 ´ C1
(20)
1
type 2a
2p ´ R3 | | RO ´ (C2 + CO )
(21)
1
type 2b
2p ´ R3 | | RO ´ CO
(22)
1
type 1
2 p ´ R O ´ (C2 + C O )
(23)
7.4 Device Functional Modes
7.4.1 Sequencing
Many of the common power supply sequencing methods can be implemented using the SS/TR, EN and PWRGD
pins. The sequential method can be implemented using an open drain output of a power on reset pin of another
device. The sequential method is illustrated in Figure 42 using two TPS57060-Q1 devices. The power good is
coupled to the EN pin on the TPS57060-Q1 device which enables the second power supply when the primary
supply reaches regulation. If needed, a 1nF ceramic capacitor on the EN pin of the second power supply
provides a 1-ms start-up delay. Figure 43 shows the results of Figure 42.
Figure 44 shows a method for ratiometric start-up sequence by connecting the SS/TR pins together. The
regulator outputs will ramp up and reach regulation at the same time. When calculating the slow start time the
pullup current source must be doubled in Equation 6. Figure 45 shows the results of Figure 44.
24
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Device Functional Modes (continued)
TPS57060-Q1
EN
PWRGD
EN
EN1
SS /TR
SS /TR
PWRGD1
PWRGD
VOUT1
VOUT2
Figure 42. Schematic for Sequential Start-Up
Sequence
Figure 43. Sequential Startup Using EN and
PWRGD
TPS57060-Q1
3
EN
4
SS/TR
6
PWRGD
EN1, EN2
VOUT1
TPS57060-Q1
3
EN
4
SS/TR
6
PWRGD
VOUT2
Figure 44. Schematic for Ratiometric Start-Up
Using Coupled SS/TR Pins
Figure 45. Ratiometric Startup Using Coupled
SS/TR pins
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Device Functional Modes (continued)
TPS57060-Q1
EN
VOUT 1
SS/TR
PWRGD
TPS57060-Q1
VOUT 2
EN
R1
SS/ TR
R2
PWRGD
R3
R4
Figure 46. Schematic for Ratiometric and Simultaneous Start-Up Sequence
Ratiometric and simultaneous power supply sequencing can be implemented by connecting the resistor network
of R1 and R2 shown in Figure 46 to the output of the power supply that needs to be tracked or another voltage
reference source. Using Equation 24 and Equation 25, the tracking resistors can be calculated to initiate the
Vout2 slightly before, after or at the same time as Vout1. Equation 26 is the voltage difference between Vout1
and Vout2 at the 95% of nominal output regulation.
The deltaV variable is 0 V for simultaneous sequencing. To minimize the effect of the inherent SS/TR to
VSENSE offset (Vssoffset) in the slow start circuit and the offset created by the pullup current source (Iss) and
tracking resistors, the Vssoffset and Iss are included as variables in the equations.
To design a ratiometric start up in which the Vout2 voltage is slightly greater than the Vout1 voltage when Vout2
reaches regulation, use a negative number in Equation 24 through Equation 26 for deltaV. Equation 26 results in
a positive number for applications which the Vout2 is slightly lower than Vout1 when Vout2 regulation is
achieved.
Because the SS/TR pin must be pulled below 40 mV before starting after an EN, UVLO or thermal shutdown
fault, careful selection of the tracking resistors is needed to ensure the device will restart after a fault. Make sure
the calculated R1 value from Equation 24 is greater than the value calculated in Equation 27 to ensure the
device can recover from a fault.
As the SS/TR voltage becomes more than 85% of the nominal reference voltage the Vssoffset becomes larger
as the slow start circuits gradually handoff the regulation reference to the internal voltage reference. The SS/TR
pin voltage needs to be greater than 1.3 V for a complete handoff to the internal voltage reference as shown in
Figure 23.
Vout2 + deltaV
Vssoffset
R1 =
´
VREF
Iss
(24)
R2 =
VREF ´ R1
Vout2 + deltaV - VREF
(25)
deltaV = Vout1 - Vout2
26
(26)
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Device Functional Modes (continued)
R1 > 2800 ´ Vout1 - 180 ´ deltaV
(27)
EN
EN
VOUT1
VOUT1
VOUT2
Figure 47. Ratiometric Startup With VOUT2 Leading
VOUT1
VOUT2
Figure 48. Ratiometric Startup With VOUT1 Leading
VOUT2
EN
VOUT1
VOUT2
Figure 49. Simultaneous Startup With Tracking Resistor
7.4.2 Pulse Skip Eco-Mode
The TPS57060-Q1 device operates in a pulse-skip Eco mode at light load currents to improve efficiency by
reducing switching and gate drive losses. The TPS57060-Q1 device is designed so that if the output voltage is
within regulation and the peak switch current at the end of any switching cycle is below the pulse skipping current
threshold, the device enters Eco mode. This current threshold is the current level corresponding to a nominal
COMP voltage of 500 mV.
When in Eco-mode, the COMP pin voltage is clamped at 500 mV and the high-side MOSFET is inhibited. Further
decreases in load current or in output voltage cannot drive the COMP pin below this clamp voltage level.
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Device Functional Modes (continued)
Because the device is not switching, the output voltage begins to decay. As the voltage control loop
compensates for the falling output voltage, the COMP pin voltage begins to rise. At this time, the high-side
MOSFET is enabled and a switching pulse initiates on the next switching cycle. The peak current is set by the
COMP pin voltage. The output voltage re-charges the regulated value (see Figure 50), then the peak switch
current starts to decrease, and eventually falls below the Eco mode threshold at which time the device again
enters Eco mode.
For Eco mode operation, the TPS57060-Q1 device senses peak current, not average or load current, so the load
current where the device enters Eco mode is dependent on the minimum on-time, input voltage, output voltage,
and output inductance value. For example, the circuit in Figure 51 enters Eco mode at about 20 mA of output
current. When the load current is low and the output voltage is within regulation, the device enters a sleep mode
and draws only 116-μA input quiescent current. The internal PLL remains operating when in sleep mode. When
operating at light load currents in the pulse skip mode, the switching transitions occur synchronously with the
external clock signal.
VOUT(ac)
IL
PH
Figure 50. Pulse-Skip Mode Operation
28
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TPS57060-Q1 DC-DC converter is designed to provide up to a 0.5-A output from an input voltage source of
3.5 V to 60 V. The high-side MOSFET is incorporated inside the TPS57060-Q1 package along with the gate
drive circuitry. The low drain-to-source on-resistance of the MOSFET allows the TPS57060-Q1 device to achieve
high efficiencies and helps keep the junction temperature low at high output currents. The compensation
components are external to the integrated circuit (IC), and an external divider allows for an adjustable output
voltage. Additionally, the TPS57060-Q1 device provides adjustable slow start and undervoltage-lockout inputs.
8.2 Typical Application
This application example details the design of a high frequency switching regulator design using ceramic output
capacitors. A few parameters must be known in order to start the design process. These parameters are typically
determined at the system level.
TPS57060-Q1
Figure 51. High Frequency, 3.3-V Output Power-Supply Design With Adjusted UVLO
8.2.1 Design Requirements
For this example, use the values listed in Table 1.
Table 1. Design Parameters
PARAMETER
VALUE
Output voltage
3.3 V
Transient response 0-A to 1.5-A load step
ΔVout = 4%
Maximum output current
0.5 A
Input voltage
34 V nominal, 12 V to 48 V
Output voltage ripple
1% of Vout
Start input voltage (rising VIN)
8.9 V
Stop input voltage (falling VIN)
7.9 V
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8.2.2 Detailed Design Procedure
8.2.2.1 Selecting the Switching Frequency
The first step is to decide on a switching frequency for the regulator. Typically, the user will want to choose the
highest switching frequency possible because this will produce the smallest solution size. The high switching
frequency allows for lower valued inductors and smaller output capacitors compared to a power supply that
switches at a lower frequency. The switching frequency that can be selected is limited by the minimum on-time of
the internal power switch, the input voltage and the output voltage and the frequency shift limitation.
Equation 8 and Equation 9 must be used to find the maximum switching frequency for the regulator, choose the
lower value of the two equations. Switching frequencies higher than these values will result in pulse skipping or
the lack of overcurrent protection during a short circuit.
The typical minimum on time, tonmin, is 130 ns for the TPS57060-Q1. For this example, the output voltage is 3.3 V
and the maximum input voltage is 48 V, which allows for a maximum switch frequency up to 616 kHz when
including the inductor resistance, on resistance and diode voltage in Equation 8. To ensure overcurrent runaway
is not a cwhenrn during short circuits in your design use Equation 9 or the solid curve in Figure 33 to determine
the maximum switching frequency. With a maximum input voltage of 48 V, assuming a diode voltage of 0.5 V,
inductor resistance of 130 mΩ, switch resistance of 400 mΩ, a current limit value of 0.94 A and a short circuit
output voltage of 0.1 V. The maximum switching frequency is approximately 923 kHz.
Choosing the lower of the two values and adding some margin a switching frequency of 500 kHz is used. To
determine the timing resistance for a given switching frequency, use Equation 7 or the curve in Figure 31.
The switching frequency is set by resistor R3 shown in Figure 51.
8.2.2.2 Output Inductor Selection (LO)
To calculate the minimum value of the output inductor, use Equation 28.
KIND is a coefficient that represents the amount of inductor ripple current relative to the maximum output current.
The inductor ripple current will be filtered by the output capacitor. Therefore, choosing high inductor ripple
currents will impact the selection of the output capacitor because the output capacitor must have a ripple current
rating equal to or greater than the inductor ripple current. In general, the inductor ripple value is at the discretion
of the designer; however, the following guidelines may be used.
For designs using low ESR output capacitors such as ceramics, a value as high as KIND = 0.3 may be used.
When using higher ESR output capacitors, KIND = 0.2 yields better results. Because the inductor ripple current is
part of the PWM control system, the inductor ripple current should always be greater than 30 mA for dependable
operation. In a wide input voltage regulator, it is best to choose an inductor ripple current on the larger side. This
allows the inductor to still have a measurable ripple current with the input voltage at its minimum.
For this design example, use KIND = 0.3 and the minimum inductor value is calculated to be 39.7 μH. For this
design, a nearest standard value was chosen: 47 μH. For the output filter inductor, it is important that the RMS
current and saturation current ratings not be exceeded. The RMS and peak inductor current can be found from
Equation 30 and Equation 31.
For this design, the RMS inductor current is 0.501 A and the peak inductor current is 0.563 A. The chosen
inductor is a MSS1048-473ML. It has a saturation current rating of 1.44 A and an RMS current rating of 1.83A.
As the equation set demonstrates, lower ripple currents will reduce the output voltage ripple of the regulator but
will require a larger value of inductance. Selecting higher ripple currents will increase the output voltage ripple of
the regulator but allow for a lower inductance value.
The current flowing through the inductor is the inductor ripple current plus the output current. During power up,
faults or transient load conditions, the inductor current can increase above the calculated peak inductor current
level calculated above. In transient conditions, the inductor current can increase up to the switch current limit of
the device. For this reason, the most conservative approach is to specify an inductor with a saturation current
rating equal to or greater than the switch current limit rather than the peak inductor current.
Vinmax - Vout
Vout
Lo min =
´
Io ´ KIND
Vinmax ´ ƒsw
(28)
30
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IRIPPLE =
IL(rms) =
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VOUT ´
(Vin max
- VOUT )
Vin max ´ L O ´ fSW
(IO )
2
(29)
1 æ VOUT ´ (Vinmax - VOUT ) ö
+
´ç
÷
÷
12 çè
Vinmax ´ LO ´ fSW
ø
ILpeak = Iout +
2
(30)
Iripple
2
(31)
8.2.2.3 Output Capacitor
There are three primary considerations for selecting the value of the output capacitor. The output capacitor will
determine the modulator pole, the output voltage ripple, and how the regulators responds to a large change in
load current. The output capacitance needs to be selected based on the more stringent of these three criteria.
The desired response to a large change in the load current is the first criteria. The output capacitor needs to
supply the load with current when the regulator can not. This situation would occur if there are desired hold-up
times for the regulator where the output capacitor must hold the output voltage above a certain level for a
specified amount of time after the input power is removed. The regulator also will temporarily not be able to
supply sufficient output current if there is a large, fast increase in the current needs of the load such as
transitioning from no load to a full load. The regulator usually needs two or more clock cycles for the control loop
to see the change in load current and output voltage and adjust the duty cycle to react to the change. The output
capacitor must be sized to supply the extra current to the load until the control loop responds to the load change.
The output capacitance must be large enough to supply the difference in current for 2 clock cycles while only
allowing a tolerable amount of droop in the output voltage. Equation 32 shows the minimum output capacitance
necessary to accomplish this.
Where ΔIout is the change in output current, ƒsw is the regulators switching frequency and ΔVout is the
allowable change in the output voltage. For this example, the transient load response is specified as a 4%
change in Vout for a load step from 0 A (no load) to 0.5 A (full load). For this example, ΔIout = 0.5 – 0 = 0.5 A
and ΔVout = 0.04 × 3.3 = 0.132 V. Using these numbers gives a minimum capacitance of 15.2 μF. This value
does not take the ESR of the output capacitor into account in the output voltage change. For ceramic capacitors,
the ESR is usually small enough to ignore in this calculation. Aluminum electrolytic and tantalum capacitors have
higher ESR that should be taken into account.
The catch diode of the regulator can not sink current so any stored energy in the inductor will produce an output
voltage overshoot when the load current rapidly decreases, see Figure 52. The output capacitor must also be
sized to absorb energy stored in the inductor when transitioning from a high load current to a lower load current.
The excess energy that gets stored in the output capacitor will increase the voltage on the capacitor. The
capacitor must be sized to maintain the desired output voltage during these transient periods. Equation 33 is
used to calculate the minimum capacitance to keep the output voltage overshoot to a desired value. Where L is
the value of the inductor, IOH is the output current under heavy load, IOL is the output under light load, VF is the
final peak output voltage, and Vi is the initial capacitor voltage. For this example, the worst case load step will be
from 0.5 A to 0 A. The output voltage will increase during this load transition, and the stated maximum output
voltage in the specification is 4% of the nominal output voltage. This will make Vf = 1.04 × 3.3 = 3.432. Vi is the
initial capacitor voltage which is the nominal output voltage of 3.3 V. Using these numbers in Equation 33 yields
a minimum capacitance of 13.2 μF.
Equation 34 calculates the minimum output capacitance needed to meet the output voltage ripple specification.
Where fsw is the switching frequency, Voripple is the maximum allowable output voltage ripple, and Iripple is the
inductor ripple current. Equation 34 yields 1 μF.
Equation 35 calculates the maximum ESR an output capacitor can have to meet the output voltage ripple
specification. Equation 35 indicates the ESR should be less than 248 mΩ.
The most stringent criteria for the output capacitor is 15.2 μF of capacitance to keep the output voltage in
regulation during an load transient.
Additional capacitance de-ratings for aging, temperature and dc bias should be factored in which will increase
this minimum value. For this example, a 47 μF 10 V X5R ceramic capacitor with 5 mΩ of ESR will be used.
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Capacitors generally have limits to the amount of ripple current they can handle without failing or producing
excess heat. An output capacitor that can support the inductor ripple current must be specified. Some capacitor
data sheets specify the Root Mean Square (RMS) value of the maximum ripple current. Equation 36 can be used
to calculate the RMS ripple current the output capacitor needs to support. For this application, Equation 36 yields
37.7 mA.
2 ´ DIout
Cout >
¦ sw ´ DVout
(32)
COUT > LO ´
((I )
((V )
OH
f
1
Cout >
8 ´ ¦ sw
´
2
2
)
- (V ) )
- (IOL )2
i
2
(33)
1
VORIPPLE
IRIPPLE
(34)
V
RESR < ORIPPLE
IRIPPLE
Icorms =
(35)
Vout ´ (Vin max - Vout)
12 ´ Vin max ´ Lo ´ ¦ sw
(36)
8.2.2.4 Catch Diode
The TPS57060-Q1 requires an external catch diode between the PH pin and GND. The selected diode must
have a reverse voltage rating equal to or greater than Vinmax. The peak current rating of the diode must be
greater than the maximum inductor current. The diode should also have a low forward voltage. Schottky diodes
are typically a good choice for the catch diode due to their low forward voltage. The lower the forward voltage of
the diode, the higher the efficiency of the regulator.
Typically, the higher the voltage and current ratings the diode has, the higher the forward voltage will be.
Because the design example has an input voltage up to 48 V, a diode with a minimum of 60-V reverse voltage
will be selected.
For the example design, the B160A Schottky diode is selected for its lower forward voltage and it comes in a
larger package size which has good thermal characteristics over small devices. The typical forward voltage of the
B160A is 0.50 V.
The diode must also be selected with an appropriate power rating. The diode conducts the output current during
the off-time of the internal power switch. The off-time of the internal switch is a function of the maximum input
voltage, the output voltage, and the switching frequency. The output current during the off-time is multiplied by
the forward voltage of the diode which equals the conduction losses of the diode. At higher switch frequencies,
the ac losses of the diode need to be taken into account. The ac losses of the diode are due to the charging and
discharging of the junction capacitance and reverse recovery. Equation 37 is used to calculate the total power
dissipation, conduction losses plus ac losses, of the diode.
The B160A has a junction capacitance of 110 pF. Using Equation 37, the selected diode will dissipate 0.297 W.
This power dissipation, depending on mounting techniques, should produce a 5.9°C temperature rise in the diode
when the input voltage is 48V and the load current is 0.5 A.
If the power supply spends a significant amount of time at light load currents or in sleep mode consider using a
diode which has a low leakage current and slightly higher forward voltage drop.
2
(Vin max - Vout) ´ Iout ´ Vƒd Cj ´ ƒsw ´ (Vin + Vƒd)
Pd =
+
2
Vin max
32
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8.2.2.5 Input Capacitor
The TPS57060-Q1 requires a high quality ceramic, type X5R or X7R, input decoupling capacitor of at least 3 μF
of effective capacitance and in some applications a bulk capacitance. The effective capacitance includes any dc
bias effects. The voltage rating of the input capacitor must be greater than the maximum input voltage. The
capacitor must also have a ripple current rating greater than the maximum input current ripple of the TPS57060Q1. The input ripple current can be calculated using Equation 38.
The value of a ceramic capacitor varies significantly over temperature and the amount of dc bias applied to the
capacitor. The capacitance variations due to temperature can be minimized by selecting a dielectric material that
is stable over temperature. X5R and X7R ceramic dielectrics are usually selected for power regulator capacitors
because they have a high capacitance to volume ratio and are fairly stable over temperature. The output
capacitor must also be selected with the dc bias taken into account. The capacitance value of a capacitor
decreases as the dc bias across a capacitor increases.
For this example design, a ceramic capacitor with at least a 60 V voltage rating is required to support the
maximum input voltage. Common standard ceramic capacitor voltage ratings include 4 V, 6.3 V, 10 V, 16 V, 25
V, 50 V or 100 V so a 100-V capacitor should be selected. For this example, two 2.2-μF, 100-V capacitors in
parallel have been selected. Table 2 shows a selection of high voltage capacitors. The input capacitance value
determines the input ripple voltage of the regulator. The input voltage ripple can be calculated using Equation 39.
Using the design example values, Ioutmax = 0.5 A, Cin = 4.4 μF, ƒsw = 500 kHz, yields an input voltage ripple of
57 mV and a RMS input ripple current of 0.223 A.
Icirms = Iout ´
ΔVin =
Vout
´
Vin min
(Vin min
- Vout )
Vin min
(38)
Iout max ´ 0.25
Cin ´ ¦ sw
(39)
Table 2. Capacitor Types
VENDOR
VALUE (μF)
1 to 2.2
Murata
1 to 4.7
1
1 to 2.2
1 10 1.8
Vishay
1 to 1.2
1 to 3.9
1 to 1.8
1 to 2.2
TDK
1.5 to 6.8
1 to 2.2
1 to 3.3
1 to 4.7
AVX
1
1 to 4.7
1 to 2.2
EIA Size
1210
1206
2220
2225
1812
1210
1210
1812
VOLTAGE
DIALECTRIC
100 V
COMMENTS
GRM32 series
50 V
100 V
GRM31 series
50 V
50 V
100 V
VJ X7R series
50 V
100 V
100 V
50 V
100 V
50 V
X7R
C series C4532
C series C3225
50 V
100 V
50 V
X7R dielectric series
100 V
8.2.2.6 Slow Start Capacitor
The slow start capacitor determines the minimum amount of time it will take for the output voltage to reach its
nominal programmed value during power up. This is useful if a load requires a controlled voltage slew rate. This
is also used if the output capacitance is large and would require large amounts of current to quickly charge the
capacitor to the output voltage level. The large currents necessary to charge the capacitor may make the
TPS57060-Q1 reach the current limit or excessive current draw from the input power supply may cause the input
voltage rail to sag. Limiting the output voltage slew rate solves both of these problems.
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The slow start time must be long enough to allow the regulator to charge the output capacitor up to the output
voltage without drawing excessive current. Equation 40 can be used to find the minimum slow start time, tss,
necessary to charge the output capacitor, Cout, from 10% to 90% of the output voltage, Vout, with an average
slow start current of Issavg. In the example, to charge the 47-μF output capacitor up to 3.3 V while only allowing
the average input current to be 0.125 A would require a 1-ms slow start time.
When the slow start time is known, the slow start capacitor value can be calculated using Equation 6. For the
example circuit, the slow start time is not too critical because the output capacitor value is 47 μF which does not
require much current to charge to 3.3 V. The example circuit has the slow start time set to an arbitrary value of
3.2 ms which requires a 0.01-μF capacitor.
Cout ´ Vout ´ 0.8
Tss >
Issavg
(40)
8.2.2.7 Bootstrap Capacitor Selection
A 0.1-μF ceramic capacitor must be connected between the BOOT and PH pins for proper operation. TI
recommends to use a ceramic capacitor with X5R or better grade dielectric. The capacitor should have a 10-V or
higher voltage rating.
8.2.2.8 Undervoltage Lockout Set Point
The undervoltage lockout (UVLO) can be adjusted using an external voltage divider on the EN pin of the
TPS57060-Q1. The UVLO has two thresholds, one for power up when the input voltage is rising and one for
power down or brown outs when the input voltage is falling. For the example design, the supply should turn on
and start switching when the input voltage increases above 8.9 V (enabled). After the regulator starts switching, it
should continue to do so until the input voltage falls below 7.9 V (UVLO stop).
The programmable UVLO and enable voltages are set using a resistor divider between Vin and ground to the EN
pin. Equation 2 through Equation 3 can be used to calculate the resistance values necessary. For the example
application, a 332-kΩ resistor between Vin and EN and a 56.2-kΩ resistor between EN and ground are required
to produce the 8.9-V and 7.9-V start and stop voltages.
8.2.2.9 Output Voltage and Feedback Resistors Selection
For the example design, 10 kΩ was selected for R2. Using Equation 1, R1 is calculated as 31.25 kΩ. The
nearest standard 1% resistor is 31.6 kΩ. Due to current leakage of the VSENSE pin, the current flowing through
the feedback network should be greater than 1 μA in order to maintain the output voltage accuracy. This
requirement makes the maximum value of R2 equal to 800 kΩ. Choosing higher resistor values will decrease
quiescent current and improve efficiency at low output currents but may introduce noise immunity problems.
8.2.2.10 Compensation
There are several methods used to compensate DC/DC regulators. The method presented here is easy to
calculate and ignores the effects of the slope compensation that is internal to the device. Because the slope
compensation is ignored, the actual cross over frequency will usually be lower than the cross over frequency
used in the calculations. This method assume the crossover frequency is between the modulator pole and the
esr zero and the esr zero is at least 10 times greater the modulator pole. Use SwitcherPro software for a more
accurate design.
To get started, the modulator pole, fpmod, and the esr zero, fz1 must be calculated using Equation 41 and
Equation 42. For Cout, use a derated value of 40 μF. Use equations Equation 43 and Equation 44, to estimate a
starting point for the crossover frequency, fco, to design the compensation. For the example design, fpmod is
603 Hz and fzmod is 796 kHz. Equation 43 is the geometric mean of the modulator pole and the esr zero and
Equation 44 is the mean of modulator pole and the switching frequency. Equation 43 yields 21.9 kHz and
Equation 44 gives 12.3 kHz. Use the lower value of Equation 43 or Equation 44 for an initial crossover frequency.
For this example, fco is 12.3 kHz. Next, the compensation components are calculated. A resistor in series with a
capacitor is used to create a compensating zero. A capacitor in parallel to these two components forms the
compensating pole.
Ioutmax
¦p mod =
2 × p × Vout × Cout
(41)
34
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¦ z mod =
1
2 ´ p ´ Resr × Cout
fco =
f p mod ´ f z mod
fco =
f p mod ´
(42)
(43)
f sw
2
(44)
To determine the compensation resistor, R4, use Equation 45. Assume the power stage transconductance,
gmps, is 1.9 A/V. The output voltage, Vo, reference voltage, VREF, and amplifier transconductance, gmea, are
3.3 V, 0.8 V and 97 μA/V, respectively. R4 is calculated to be 72.6 kΩ, use the nearest standard value of 73.2
kΩ. Use Equation 46 to set the compensation zero to the modulator pole frequency. Equation 46 yields 3600 pF
for compensating capacitor C7, a 3300 pF is used on the board.
æ 2 ´ p ´ fco ´ Cout
R4 = ç
gmps
è
C7 =
ö
ö æ
Vout
÷
÷´ç
ø è Vref ´ gmea ø
(45)
1
2 ´ p ´ R4 ´ f p m od
(46)
Use the larger value of Equation 47 and Equation 48 to calculate the C8, to set the compensation pole.
Equation 48 yields 8.7 pF so the nearest standard of 10 pF is used.
C ´ Re sr
C8 = o
R4
(47)
C8 =
1
R4 ´ f sw ´ p
(48)
8.2.2.11 Discontinuous Mode and Eco Mode Boundary
With an input voltage of 34 V, the power supply enters discontinuous mode when the output current is less than
60 mA. The power supply enters Eco-mode when the output current is lower than 38 mA.
The input current draw at no load is 228 μA.
8.2.3 Application Curves
Figure 53. Startup With VIN
Figure 52. Load Transient
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Figure 54. Output Ripple, CCM
Figure 55. Output Ripple, DCM
Figure 56. Output Ripple, PSM
Figure 57. Input Ripple CCM
90
80
70
Efficiency - %
60
VIN = 12 V
VIN = 24 V
50
VIN = 18 V
VIN = 34 V
VIN = 42
40
30
20
10
0
0
VOUT = 3.3 V
0.05
Figure 58. Input Ripple DCM
36
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0.10
0.15
0.20 0.25 0.30 0.35
IO - Output Current - A
0.40
0.45
0.50
Figure 59. Efficiency vs Load Current
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100
60
90
150
40
80
100
Phase
70
Vin = 18 V
50
Vin = 12 V
Vin = 24 V
Vin = 34 V
40
0
Phase - o
50
60
Gain - dB
Efficiency - %
20
0
Gain
-50
Vin = 42 V
-20
30
-100
20
-40
-150
VOUT = 3.3 V
10
0
0
0.02
0.04
0.06
IO - Output Current - A
0.10
0.08
-60
100
1-103
IO = 0.25 A
0.08
VI = 34 V
0.06
0.06
0.04
0.04
Regulation (%)
Regulation (%)
1-106
0.1
0.1
0.02
0
-0.02
0.02
0
-0.02
-0.04
-0.04
-0.06
-0.06
-0.08
-0.08
-0.1
0.00
1-105
Figure 61. Overall Loop Frequency Response
Figure 60. Light Load Efficiency
0.08
1-104
f - Frequency - Hz
-0.1
0.25
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.45
0.5
10
15
20
25
30
35
40
45
50
55
60
VI - Input Voltage - V
Load Current - A
Figure 62. Regulation vs Load Current
Figure 63. Regulation vs Input Voltage
9 Power Supply Recommendations
The input voltage for TPS57060-Q1 device is from of 3.5 V to 60 V. A ceramic capacitor, type X5R or X7R with
an effective capacitance of at least 3 µF must be used at the VIN pin. TI recommends adding an additional input
bulk capacitor depending on the board connection to the input supply.
10 Layout
10.1 Layout Guidelines
Layout is a critical portion of good power supply design. Several signals paths conduct fast changing currents or
voltages that can interact with stray inductance or parasitic capacitance to generate noise or degrade the power
supplies performance. Figure 64 shows the PCB layout example. Obtaining acceptable performance with
alternate PCB layouts may be possible, however this layout has been shown to produce good results and is
meant as a guideline.
The following layout guidelines should be followed to achieve good system performance:
• Providing a low-inductance, low-impedance ground path is critical. Therefore, use wide and short traces for
the main current paths.
• Care should be taken to minimize the loop area formed by the input bypass capacitor, VIN pin, PH pin, catch
diode, inductor, and output capacitors. Use thick planes and traces to connect these components. For
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Layout Guidelines (continued)
•
•
•
•
•
•
•
operation at a full-rated load, the top-side ground area must provide adequate heat dissipating area.
The GND pin should be tied directly to the thermal pad under the device and the thermal pad.
The thermal pad should be connected to any internal PCB ground planes using multiple vias directly under
the device.
The PH pin should be routed to the cathode of the catch diode and to the output inductor. Because the PH
connection is the switching node, the catch diode and output inductor should be located close to the PH pins,
Place the VSENSE voltage-divider resistor network away from switching node and route the feedback trace
with minimum interaction with any noise sources associated with the switching components.
The RT/CLK pin is sensitive to noise so the RT resistor should be located as close as possible to the device
and should be routed with minimal lengths of trace.
Place compensation network components away from switching components and route the connections away
from noisy area.
The bootstrap capacitor must be placed as close as possible to the IC pin.
10.2 Layout Example
Vout
Output
Capacitor
Topside
Ground
Area
Input
Bypass
Capacitor
Vin
UVLO
Adjust
Resistors
Slow Start
Capacitor
Output
Inductor
Route Boot Capacitor
Trace on another layer to
provide wide path for
topside ground
BOOT
Catch
Diode
PH
VIN
GND
EN
COMP
SS/TR
VSENSE
RT/CLK
PWRGD
Frequency
Set Resistor
Compensation
Network
Resistor
Divider
Thermal VIA
Signal VIA
Figure 64. PCB Layout Example
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10.3 Power Dissipation Estimate
The following formulas show how to estimate the device power dissipation under continuous conduction mode
(CCM) operation. These equations should not be used if the device is working in discontinuous conduction mode
(DCM).
The power dissipation of the device includes the parameters that follow:
• Conduction loss (Pcon)
Vout
Pcon = Io2 ´ RDS(on) ´
Vin
where
•
•
•
•
RDS(on) is the on-resistance of the high-side MOSFET (Ω).
VOUT is the output voltage (V).
VIN is the input voltage (V).
(49)
Switching loss (Psw)
Psw = Vin 2 ´ ¦ sw ´ lo ´ 0.25 ´ 10-9
where
•
•
•
fsw is the switching frequency (Hz).
Io is the output current (A).
(50)
Gate drive loss (Pgd)
Pgd = Vin ´ 3 ´ 10 -9 ´ ¦ sw
•
(51)
Supply current (Pq)
Pq = 116 ´ 10-6 ´ Vin
(52)
Therefore:
Ptot = Pcon + Psw + Pgd + Pq
where
•
Ptot is the total device power dissipation (W).
(53)
For given TA:
TJ = TA + Rth ´ Ptot
where
•
•
•
TJ is the junction temperature (°C).
TA is the ambient temperature (°C).
Rth is the thermal resistance of the package (°C/W).
(54)
For given TJMAX = 150°C:
TAmax = TJmax - Rth ´ Ptot
where
•
•
TJmax is maximum junction temperature (°C).
TAmax is maximum ambient temperature (°C).
(55)
Additional power losses occur in the regulator circuit because of the inductor AC and DC losses, the catch diode,
and trace resistance which impact the overall efficiency of the regulator.
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
11.1.2 Development Support
For the SwitcherPro software tool, go to www.ti.com/tool/SwitcherPro.
11.2 Documentation Support
11.2.1 Related Documentation
For related documentation see the following:
• Design Considerations for DC-DC Converters in Fast-Input Slew Rate Applications, SLVA693
• Passing CISPR25-Radiated Emissions Using TPS54160-Q1, SLVA629
• TPS54xx0-Q1 and TPS57xx0-Q1 Pin FMEA, SLVA615
11.3 Community Resource
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 Trademarks
Eco-mode, SwitcherPro, PowerPAD, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
40
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS57060QDGQRQ1
ACTIVE
HVSSOP
DGQ
10
2500
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
5706Q
TPS57060QDRCRQ1
ACTIVE
VSON
DRC
10
3000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
5706Q
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of