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TPS61093DSKT

TPS61093DSKT

  • 厂商:

    BURR-BROWN(德州仪器)

  • 封装:

    WSON10_2.5X2.5MM_EP

  • 描述:

    DC-DC电源芯片 Input=1.6V~6V Output=15V WSON10_2.5X2.5MM_EP

  • 数据手册
  • 价格&库存
TPS61093DSKT 数据手册
Order Now Product Folder Technical Documents Support & Community Tools & Software Reference Design TPS61093 SLVS992D – SEPTEMBER 2009 – REVISED APRIL 2019 TPS61093 Low-Input Boost Converter With Integrated Power Diode and Input/Output Isolation 1 Features 3 Description • • • • • • • • • • The TPS61093 is a 1.2-MHz, fixed-frequency boost converter designed for high integration and high reliability. The IC integrates a 20-V power switch, input/output isolation switch, and power diode. When the output current exceeds the overload limit, the isolation switch of the IC opens up to disconnect the output from the input, thus protecting the IC and the input supply. The isolation switch also disconnects the output from the input during shutdown to minimize leakage current. When the IC is shut down, the output capacitor is discharged to a low voltage level by internal diodes. Other protection features include 1.1-A peak overcurrent protection (OCP) at each cycle, output overvoltage protection (OVP), thermal shutdown, and undervoltage lockout (UVLO). 1 Input range: 1.6 V to 6 V Integrated power diode and isolation FET 20-V Internal switch FET with 1.1-A current Fixed 1.2-MHz switching frequency Efficiency at 15-V output up to 88% Overload and overvoltage protection Programmable soft start-up Load discharge path after IC shutdown 2.5 mm × 2.5 mm × 0.8 mm WSON package Create a custom design using the TPS61093 with the WEBENCH® Power Designer 2 Applications • • • With its 1.6-V minimum input voltage, the IC can be powered by two alkaline batteries, a single Li-ion battery, or 3.3-V and 5-V regulated supply. The output can be boosted up to 17 V. The TPS61093 is available in 2.5 mm × 2.5 mm VSON package with thermal pad. Glucose meters OLED power supplies 3.3-V to 12-V, 5-V to 12-V Boost converters Device Information(1) PART NUMBER TPS61093 PACKAGE WSON (10) BODY SIZE (NOM) 2.50 mm × 2.50 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Simplified Schematic VI 1.6 V to 6 V L1 10 mH C1 4.7 mF C3 R3 200 kW TPS61093 VIN SW CP1 VO CP2 OUT 100 nF C5 1 mF EN FB SS GND C2 0.1 mF VO 15 V/50 mA R1 294 kW C4 1 mF R2 10.2 kW 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TPS61093 SLVS992D – SEPTEMBER 2009 – REVISED APRIL 2019 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 3 6.1 6.2 6.3 6.4 6.5 6.6 3 4 4 4 5 5 Absolute Maximum Ratings ...................................... ESD Ratings.............................................................. Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics........................................... Typical Characteristics .............................................. Detailed Description .............................................. 7 7.1 Overview ................................................................... 7 7.2 Functional Block Diagram ......................................... 7 7.3 Feature Description................................................... 8 7.4 Device Functional Modes.......................................... 8 8 Application and Implementation .......................... 9 8.1 Application Information.............................................. 9 8.2 Typical Applications .................................................. 9 9 Power Supply Recommendations...................... 17 10 Layout................................................................... 17 10.1 Layout Guidelines ................................................. 17 10.2 Layout Example .................................................... 17 11 Device and Documentation Support ................. 18 11.1 11.2 11.3 11.4 11.5 11.6 Device Support...................................................... Receiving Notification of Documentation Updates Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 18 18 18 18 18 19 12 Mechanical, Packaging, and Orderable Information ........................................................... 19 4 Revision History Changes from Revision C (June 2015) to Revision D Page • Added links for Webench ....................................................................................................................................................... 1 • Changed Shutdown and Load Discharge output voltage value from "3.3 V" to "4.3 V"......................................................... 8 Changes from Revision B (December 2014) to Revision C Page • Changed Features From: VSON package To: WSON Package ............................................................................................ 1 • Changed the pinout title From "QFN Package 10 Pins" To: "DSK Package 10 Pins (WSON)" ............................................ 3 • Changed "VSON" to "WSON" in the Thermal Information table ........................................................................................... 5 • Deleted the Dissipation Ratings table..................................................................................................................................... 5 Changes from Revision A (October 2009) to Revision B • Page Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .................................................................................................. 1 Changes from Original (September 2009) to Revision A Page • Added information to OPERATION description...................................................................................................................... 7 • Changed Output Program description .................................................................................................................................. 10 • Changed Output Program equations.................................................................................................................................... 10 2 Submit Documentation Feedback Copyright © 2009–2019, Texas Instruments Incorporated Product Folder Links: TPS61093 TPS61093 www.ti.com SLVS992D – SEPTEMBER 2009 – REVISED APRIL 2019 5 Pin Configuration and Functions DSK Package 10 Pins (WSON) Top View 10 VO 9 SW 8 OUT CP1 4 7 FB EN 5 6 SS GND 1 VIN 2 CP2 3 Thermal Pad Pin Functions PIN NAME NO. CP1, CP2 3, 4 I/O DESCRIPTION Connect to flying capacitor for internal charge pump. EN 5 I Enable pin (HIGH = enable). When the pin is pulled low for 1 ms, the IC turns off and consumes less than 1-μA current. FB 7 I Voltage feedback pin for output regulation, 0.5-V regulated voltage. An external resistor divider connected to this pin programs the regulated output voltage. GND 1 – Ground of the IC. OUT 8 O Isolation switch is between this pin and VO pin. Connect load to this pin for input/output isolation during IC shutdown. See Without Isolation FET for the tradeoff between isolation and efficiency. SS 6 I Soft start pin. A RC network connecting to the SS pin programs soft start timing. See Start-Up. SW 9 I Switching node of the IC where the internal PWM switch operates. Thermal Pad – – It should be soldered to the ground plane. If possible, use thermal via to connect to ground plane for ideal power dissipation. VIN 2 I IC Supply voltage input. VO 10 O Output of the boost converter. When the output voltage exceeds the overvoltage protection (OVP) threshold, the power switch turns off until VO drops below the overvoltage protection hysteresis. 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature (unless otherwise noted) Supply voltage on pin VIN (2) MAX UNIT –0.3 7 V –0.3 7 V Voltage on pin CP1 and FB (2) –0.3 3 V –0.3 20 V –40 85 °C 150 °C 150 °C Voltage on pin SW, VO, and OUT (2) Operating temperature TJ Maximum operating junction temperature Tstg Storage temperature (2) MIN Voltage on pins CP2, EN, and SS (2) TA (1) (1) –55 Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to network ground terminal. Submit Documentation Feedback Copyright © 2009–2019, Texas Instruments Incorporated Product Folder Links: TPS61093 3 TPS61093 SLVS992D – SEPTEMBER 2009 – REVISED APRIL 2019 www.ti.com 6.2 ESD Ratings VALUE V(ESD) (1) (2) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±2000 Charged-device model (CDM), per JEDEC specification JESD22C101 (2) ±750 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN NOM 6 UNIT Vi Input voltage range Vo Output voltage range at VO pin L Inductor (1) 2.2 Cin Input capacitor 4.7 Co Output capacitor at OUT pin (1) Cfly Flying capacitor at CP1 and CP2 pins TJ Operating junction temperature –40 125 °C TA Operating free-air temperature –40 85 °C (1) 1.6 MAX 4.7 V 17 V 10 μH μF 1 10 10 μF nF These values are recommended values that have been successfully tested in several applications. Other values may be acceptable in other applications but should be fully tested by the user. 6.4 Thermal Information TPS61093 THERMAL METRIC (1) WSON UNIT 10 PINS RθJA Junction-to-ambient thermal resistance 49.2 RθJC(top) Junction-to-case (top) thermal resistance 63.3 RθJB Junction-to-board thermal resistance 23.4 ψJT Junction-to-top characterization parameter 1.1 ψJB Junction-to-board characterization parameter 23.0 RθJC(bot) Junction-to-case (bottom) thermal resistance 5.7 (1) 4 °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. Submit Documentation Feedback Copyright © 2009–2019, Texas Instruments Incorporated Product Folder Links: TPS61093 TPS61093 www.ti.com SLVS992D – SEPTEMBER 2009 – REVISED APRIL 2019 6.5 Electrical Characteristics VIN = 3.6 V, EN = VIN, TA = –40°C to 85°C, typical values are at TA = 25°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 0.9 1.5 mA 1 μA SUPPLY CURRENT VIN Input voltage range, VIN IQ Operating quiescent current into VIN Device PWM switching no load 1.6 ISD Shutdown current EN = GND, VIN = 6 V UVLO Undervoltage lockout threshold VIN falling Vhys Undervoltage lockout hysterisis 6 1.5 1.55 50 V V mV ENABLE AND PWM CONTROL VENH EN logic high voltage VIN = 1.6 V to 6 V VENL EN logic low voltage VIN = 1.6 V to 6 V REN EN pull down resistor Toff EN pulse width to shutdown 1.2 V 0.3 400 800 EN high to low V 1600 kΩ 1 ms VOLTAGE CONTROL VREF Voltage feedback regulation voltage IFB Voltage feedback input bias current fS Oscillator frequency Dmax Maximum duty cycle Tmin_on Minimum on pulse width 0.49 VFB = 0.1 V, TA = 85°C 0.5 1.0 1.2 90% 93% 0.51 V 100 nA 1.4 MHz 65 ns POWER SWITCH, ISOLATION FET RDS(ON)N N-channel MOSFET on-resistance VIN = 3 V 0.25 0.4 Ω RDS(ON)iso Isolation FET on-resistance VO = 5 V 2.5 4 Ω VO = 3.5 V 4.5 ILN_N N-channel leakage current VDS = 20 V, TA = 25°C 1 μA ILN_iso Isolation FET leakage current VDS = 20 V, TA = 25°C 1 μA VF Power diode forward voltage Current = 500 mA 0.8 V OC, ILIM, OVP SC AND SS ILIM N-Channel MOSFET current limit Vovp Overvoltage protection threshold Vovp_hys Overvoltage protection hysteresis IOL Overload protection Measured on the VO pin 0.9 1.1 18 19 1.5 A 0.6 V 200 300 mA V THERMAL SHUTDOWN Tshutdown Thermal shutdown threshold 150 °C Thysteresis Thermal shutdown hysteresis 15 °C 6.6 Typical Characteristics Table 1. Table Of Graphs Figure 1, L = TOKO #A915_Y-100M, unless otherwise noted FIGURE η Efficiency vs Load current at OUT = 15 V Figure 1 η Efficiency vs Load current at OUT = 10 V Figure 2 VFB FB voltage vs Free-air temperature Figure 3 VFB FB voltage vs Input voltage Figure 4 ILIM Switch current limit vs Free-air temperature Figure 5 Submit Documentation Feedback Copyright © 2009–2019, Texas Instruments Incorporated Product Folder Links: TPS61093 5 TPS61093 SLVS992D – SEPTEMBER 2009 – REVISED APRIL 2019 www.ti.com 100 100 OUT = 15 V 95 85 85 80 80 75 VI = 2.5 V 70 VI =1.8 V 65 70 60 55 50 50 45 45 100 40 1 1000 VI = 2.5 V VI =1.8 V 65 55 10 VI = 3.3 V 75 60 40 1 VI = 4.2 V 90 VI = 3.3 V Efficiency - % Efficiency - % 90 OUT = 10 V 95 VI = 4.2 V 10 Load - mA 100 1000 Load - mA Figure 1. Efficiency vs Load Figure 2. Efficiency vs Load 0.502 502 501.5 0.501 VFB - mV VFB - V 501 0.5 500.5 500 0.499 499.5 0.498 -40 -20 0 20 40 60 80 TA - Free-Air Temperature - ºC 100 120 499 1.6 Figure 3. FB Voltage vs Free-Air Temperature 2 2.4 2.8 3.2 3.6 4 4.4 4.8 5.2 5.6 VI - Input Voltage - V 6 Figure 4. FB Voltage vs Input Voltage 1.3 ILIM - A 1.2 1.1 1 0.9 0.8 -40 -20 0 20 40 60 80 TA - Free-Air Temperature - ºC 100 120 Figure 5. Switch Current Limit vs Free-Air Temperature 6 Submit Documentation Feedback Copyright © 2009–2019, Texas Instruments Incorporated Product Folder Links: TPS61093 TPS61093 www.ti.com SLVS992D – SEPTEMBER 2009 – REVISED APRIL 2019 7 Detailed Description 7.1 Overview The TPS61093 is a highly integrated boost regulator for up to 17-V output. In addition to the on-chip 1-A PWM switch and power diode, this IC also integrates an output-side isolation switch as shown in the functional block diagram. One common issue with conventional boost regulators is the conduction path from input to output even when the PWM switch is turned off. It creates three problems, which are inrush current during start-up, output leakage current during shutdown, and excessive overload current. In the TPS61093, the isolation switch turns off under shutdown-mode and overload conditions, thereby opening the current path. However, shorting the VO and OUT pins bypasses the isolation switch and enhances efficiency. Because the isolation switch is on the output side, the IC's VIN pin and power stage input power (up to 10 V) can be separated. The TPS61093 adopts current-mode control with constant pulse-width-modulation (PWM) frequency. The switching frequency is fixed at 1.2 MHz typical. PWM operation turns on the PWM switch at the beginning of each switching cycle. The input voltage is applied across the inductor and the inductor current ramps up. In this mode, the output capacitor is discharged by the load current. When the inductor current hits the threshold set by the error amplifier output, the PWM switch is turned off, and the power diode is forward-biased. The inductor transfers its stored energy to replenish the output capacitor. This operation repeats in the next switching cycle. The error amplifier compares the FB-pin voltage with an internal reference, and its output determines the duty cycle of the PWM switching. This closed-loop system requires frequency compensation for stable operation. The device has a built-in compensation circuit that can accommodate a wide range of input and output voltages. To avoid the sub-harmonic oscillation intrinsic to current-mode control, the IC also integrates slope compensation, which adds an artificial slope to the current ramp. 7.2 Functional Block Diagram FB EN CP2 CP1 SW OUT VO Soft Startup Ref. C/P EA Gate Driver PWM Control Gate Driver EN Precharge On/off control Oscillator Ramp Generator + SS Current Sensor GND VIN Submit Documentation Feedback Copyright © 2009–2019, Texas Instruments Incorporated Product Folder Links: TPS61093 7 TPS61093 SLVS992D – SEPTEMBER 2009 – REVISED APRIL 2019 www.ti.com 7.3 Feature Description 7.3.1 Shutdown and Load Discharge When the EN pin is pulled low for 1 ms, the IC stops the PWM switch and turns off the isolation switch, providing isolation between input and output. The internal current path consisting of the isolation switch’s body diode and several parasitic diodes quickly discharges the output voltage to less than 4.3 V. Afterwards, the voltage is slowly discharged to zero by the leakage current. This protects the IC and the external components from high voltage in shutdown mode. In shutdown mode, less than 1 μA of input current is consumed by the IC. 7.3.2 Overload and Overvoltage Protection If the overload current passing through the isolation switch is above the overload limit (IOL) for 3-μs (typical), the TPS61093 is switched off until the fault is cleared and the EN pin toggles. The function only is triggered 52 ms after the IC is enabled. To prevent the PWM switch and the output capacitor from exceeding maximum voltage ratings, an overvoltage protection circuit turns off the boost switch as soon as the output voltage at the VO pin exceeds the OVP threshold. Simultaneously, the IC opens the isolation switch. The regulator resumes PWM switching after the VO pin voltage falls 0.6 V below the threshold. 7.3.3 UVLO An undervoltage lockout prevents improper operation of the device for input voltages below 1.55 V. When the input voltage is below the undervoltage threshold, the entire device, including the PWM and isolation switches, remains off. 7.3.4 Thermal Shutdown An internal thermal shutdown turns off the isolation and PWM switches when the typical junction temperature of 150°C is exceeded. The thermal shutdown has a hysteresis of 15°C, typical. 7.4 Device Functional Modes The converter operates in continuous conduction mode (CCM) as soon as the input current increases above half the ripple current in the inductor, for lower load currents it switches into discontinuous conduction mode (DCM). If the load is further reduced, the part starts to skip pulses to maintain the output voltage. 8 Submit Documentation Feedback Copyright © 2009–2019, Texas Instruments Incorporated Product Folder Links: TPS61093 TPS61093 www.ti.com SLVS992D – SEPTEMBER 2009 – REVISED APRIL 2019 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 8.1 Application Information The device is a step up DC-DC converter with a PWM switch, a power diode and an input/output isolation switch integrated. TPS61093 supports up to 17-V output with the input range from 1.6 V to 6 V. The TPS61093 adopts the current-mode control with constant pulse-width-modulation (PWM) frequency. The switching frequency is fixed at 1.2 MHz typical. The isolation switch disconnects the output from the input during shutdown to minimize leakage current. However, shorting the VO and OUT pins bypasses the isolation switch and enhances efficiency. The following design procedure can be used to select component values for the TPS61093. 8.2 Typical Applications 8.2.1 15 V Output Boost Converter Vin 1.8V to 6V L1 10mH C1 TPS61093 4.7mF C3 100nF R3 200kW VIN SW CP1 VO CP2 OUT EN FB SS GND C2 0.1mF C5 1 mF Vo 15V/50mA R1 294kW C6 10nF C4 100mF R2 10.2kW Figure 6. 15 V Boost Converter with 100 µF Output Capacitor 8.2.1.1 Design Requirements Table 2. Design Parameters PARAMETERS VALUES Input voltage 4.2 V Output voltage 15 V Operating frequency 1.2 MHz Submit Documentation Feedback Copyright © 2009–2019, Texas Instruments Incorporated Product Folder Links: TPS61093 9 TPS61093 SLVS992D – SEPTEMBER 2009 – REVISED APRIL 2019 www.ti.com 8.2.1.2 Detailed Design Procedure 8.2.1.2.1 Custom Design With WEBENCH® Tools Click here to create a custom design using the TPS61093 device with the WEBENCH® Power Designer. 1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements. 2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial. 3. Compare the generated design with other possible solutions from Texas Instruments. The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time pricing and component availability. In most cases, these actions are available: • Run electrical simulations to see important waveforms and circuit performance • Run thermal simulations to understand board thermal performance • Export customized schematic and layout into popular CAD formats • Print PDF reports for the design, and share the design with colleagues Get more information about WEBENCH tools at www.ti.com/WEBENCH. 8.2.1.2.2 Output Program To program the output voltage, select the values of R1 and R2 (see Figure 7) according to Equation 1. æ R1 ö Vout = 0.5 V ´ ç +1÷ è R2 ø æ Vout ö R1 = R2 ´ ç - 1÷ è 0.5 V ø (1) A recommended value for R2 is approximately 10 kΩ which sets the current in the resistor divider chain to 0.5 V/10 kΩ = 50 μA. The output voltage tolerance depends on the VFB accuracy and the resistor divider. C2 C2 VO OUT TPS61093 VO Cff Option R1 C4 OUT TPS61093 FB R1 Cff Option FB R2 R2 (a) With isolation FET (b) Without isolation FET Figure 7. Resistor Divider to Program Output Voltage 8.2.1.2.3 Without Isolation FET The efficiency of the TPS61093 can be improved by connecting the load to the VO pin instead of the OUT pin. The power loss in the isolation FET is then negligible, as shown in Figure 8. The tradeoffs when bypassing the isolation FET are: • Leakage path between input and output causes the output to be a diode drop below the input voltage when the IC is in shutdown • No overload circuit protection When the load is connected to the VO pin, the output capacitor on the VO pin must be above 1 μF. 10 Submit Documentation Feedback Copyright © 2009–2019, Texas Instruments Incorporated Product Folder Links: TPS61093 TPS61093 www.ti.com SLVS992D – SEPTEMBER 2009 – REVISED APRIL 2019 100 95 90 Without isolation 85 Efficiency - % 80 With isolation 75 70 65 60 55 50 45 40 0 50 100 150 200 Load - mA 250 300 Figure 8. Efficiency vs Load 8.2.1.2.4 Start-Up The TPS61093 turns on the isolation FET and PWM switch when the EN pin is pulled high. During the soft-start period, the R and C network on the SS pin is charged by an internal bias current of 5 μA (typical). The RC network sets the reference voltage ramp up slope. Because the output voltage follows the reference voltage via the FB pin, the output voltage rise time follows the SS pin voltage until the SS pin voltage reaches 0.5 V. The soft-start time is given by Equation 2. 0.5 V ´ C5 tSS = 5 mA where • C5 is the capacitor connected to the SS pin (2) When the EN pin is pulled low to switch the IC off, the SS pin voltage is discharged to zero by the resistor R3. The discharge period depends on the RC time constant. Note that if the SS pin voltage is not discharged to zero before the IC is enabled again, the soft start circuit may not slow the output voltage startup and may not reduce the startup inrush current. 8.2.1.2.5 Switch Duty Cycle The maximum switch duty cycle (D) of the TPS61093 is 90% (minimum). The duty cycle of a boost converter under continuous conduction mode (CCM) is given by: Vout + 0.8 V - Vin D= Vout + 0.8 V (3) The duty cycle must be lower than the specification in the application; otherwise the output voltage cannot be regulated. Submit Documentation Feedback Copyright © 2009–2019, Texas Instruments Incorporated Product Folder Links: TPS61093 11 TPS61093 SLVS992D – SEPTEMBER 2009 – REVISED APRIL 2019 www.ti.com The TPS61093 has a minimum ON pulse width once the PWM switch is turned on. As the output current drops, the device enters discontinuous conduction mode (DCM). If the output current drops extremely low, causing the ON time to be reduced to the minimum ON time, the TPS61093 enters pulse-skipping mode. In this mode, the device keeps the power switch off for several switching cycles to keep the output voltage in regulation. See Figure 14. The output current when the IC enters skipping mode is calculated with Equation 4. Iout_skip = 2 Vin2 ´ Tmin_on ´ fSW 2 ´ (Vout + 0.8V - Vin) ´ L where • • • Tmin_on = Minimum ON pulse width specification (typically 65-ns); L = Selected inductor value; fSW = Converter switching frequency (typically 1.2-MHz) (4) 8.2.1.2.6 Inductor Selection Because the selection of the inductor affects steady state operation, transient behavior, and loop stability, the inductor is the most important component in power regulator design. There are three important inductor specifications, inductor value, saturation current, and dc resistance. Considering inductor value alone is not enough. The saturation current of the inductor should be higher than the peak switch current as calculated in Equation 5. DI IL_peak = IL_DC + L 2 Vout ´ Iout IL_DC = Vin ´ h 1 DIL = é 1 1 öù æ êL ´ ¦ SW ´ ç Vout + 0.8 V - VIN + VIN ÷ ú è øû ë where • • • • IL_peak = Peak switch current IL_DC = Inductor average current ΔIL = Inductor peak to peak current η = Estimated converter efficiency (5) Normally, it is advisable to work with an inductor peak-to-peak current of less than 30% of the average inductor current. A smaller ripple from a larger valued inductor reduces the magnetic hysteresis losses in the inductor and EMI. But in the same way, load transient response time is increased. Also, the inductor value should not be outside the 2.2 μH to 10 μH range in the recommended operating conditions table. Otherwise, the internal slope compensation and loop compensation components are unable to maintain small signal control loop stability over the entire load range. Table 3 lists the recommended inductor for the TPS61093. Table 3. Recommended Inductors for the TPS61093 12 PART NUMBER L (μH) DCR MAX (mΩ) SATURATION CURRENT (A) SIZE (L×W×H mm) VENDOR #A915_Y-4R7M 4.7 45 1.5 5.2x5.2x3.0 Toko #A915_Y-100M 10 90 1.09 5.2x5.2x3.0 Toko VLS4012-4R7M 4.7 132 1.1 4.0x4.0x1.2 TDK VLS4012-100M 10 240 0.82 4.0x4.0x1.2 TDK CDRH3D23/HP 10 198 1.02 4.0x4.0x2.5 Sumida LPS5030-103ML 10 127 1.4 5.0x5.0x3.0 Coilcraft Submit Documentation Feedback Copyright © 2009–2019, Texas Instruments Incorporated Product Folder Links: TPS61093 TPS61093 www.ti.com SLVS992D – SEPTEMBER 2009 – REVISED APRIL 2019 8.2.1.2.7 Input and Output Capacitor Selection The output capacitor is mainly selected to meet the requirements for output ripple and loop stability. This ripple voltage is related to the capacitor’s capacitance and its equivalent series resistance (ESR). Assuming a ceramic capacitor with zero ESR, the minimum capacitance needed for a given ripple can be calculated by: D ´ Iout Cout = Fs ´ Vripple where • Vripple = peak to peak output ripple (6) The ESR impact on the output ripple must be considered if tantalum or electrolytic capacitors are used. Care must be taken when evaluating a ceramic capacitor’s derating under dc bias, aging, and ac signal. For example, larger form factor capacitors (in 1206 size) have their self resonant frequencies in the range of the switching frequency. So the effective capacitance is significantly lower. The dc bias can also significantly reduce capacitance. A ceramic capacitor can lose as much as 50% of its capacitance at its rated voltage. Therefore, always leave margin on the voltage rating to ensure adequate capacitance at the required output voltage. A 4.7-μF (minimum) input capacitor is recommended. The output requires a capacitor in the range of 1 μF to 10 μF. The output capacitor affects the small signal control loop stability of the boost regulator. If the output capacitor is below the range, the boost regulator can potentially become unstable. The popular vendors for high value ceramic capacitors are: • TDK (http://www.component.tdk.com/components.php) • Murata (http://www.murata.com/cap/index.html) Submit Documentation Feedback Copyright © 2009–2019, Texas Instruments Incorporated Product Folder Links: TPS61093 13 TPS61093 SLVS992D – SEPTEMBER 2009 – REVISED APRIL 2019 www.ti.com 8.2.1.2.8 Small Signal Stability The TPS61093 integrates slope compensation and the RC compensation network for the internal error amplifier. Most applications are control loop stable if the recommended inductor and input/output capacitors are used. For those few applications that require components outside the recommended values, the internal error amplifier’s gain and phase are presented in Figure 9. 80 180 VFB VEA 135 Phase 60 90 Gain - dB 45 20 Gain 0 fzea 0 fp-ea -45 Phase - deg 40 -90 -20 -135 -40 10 100 1k 10k f - Frequency - Hz 100k -180 1M Figure 9. Bode Plot of Error Amplifier Gain and Phase The RC compensation network generates a pole fp-ea of 57 kHz and a zero fz-ea of 1.9 kHz, shown in Figure 9. Use Equation 7 to calculate the output pole, fP, of the boost converter. If fP
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