TPS61177ARGRR

Order Now Product Folder Support & Community Tools & Software Technical Documents TPS61177A SNVSA76B – MARCH 2015 – REVISED MARCH 2017 TPS61177A WLED Driver for Notebooks With PWM Interface and Mixed Dimming Mode 1 Features 3 Description • • • • The TPS61177A device provides a highly integrated white LED (WLED) driver solution for notebook LCD backlight. This device has a built-in high-efficiency boost regulator with integrated 1.8-A, 40-V power MOSFET. The six current sink regulators provide high precision current regulation and matching. In total, the device can support up to 72 WLEDs. In addition, the boost output automatically adjusts its voltage to the WLED forward voltage to optimize efficiency. 1 • • • • • • • • • • • • 2.5-V to 24-V Input Voltage Range 39-V Maximum Output Voltage Integrated 1.8-A, 40-V MOSFET 450-kHz to 1.2-MHz Programmable Switching Frequency Adaptive Boost Output to WLED Voltages 100-Hz to 25-kHz Wide Input PWM Dimming Frequency Range 1% Minimum Dimming Duty Cycle Small External Components Integrated Loop Compensation Six Current Sinks of 30 mA Maximum 1% (Typical) Current Matching Input PWM Glitch Filter PWM Brightness Interface Control Three Optional Dimming Methods, including Direct PWM Dimming, Analog Dimming, and Analog and PWM Mixed Dimming Built-in WLED Open Protection Thermal Shutdown The TPS61177A supports the analog dimming, analog and PWM dimming, and direct PWM dimming method. During analog dimming mode, each CS current linearly varies depending on the duty cycle information on the PWMB pin. During analog and PWM mixed dimming mode, the input PWM duty cycle information is translated to an analog signal to control the WLED current linearly over 25% to 100% brightness area. The device also allows adding PWM dimming when the analog current is down to 25%. Below 25%, the analog signal translates to PWM duty cycle information to control the on or off of WLED current and averages the WLED current down to 1%. The frequency of adding PWM dimming is same to input PWM frequency on the PWMB pin. While the TPS61177A also supports a direct PWM dimming method, in direct PWM dimming mode the WLED current is turned on or off, synchronized with the input PWM signal. 2 Applications • • • • • Notebook and Tablet LCD Display Backlights Patient Monitors Medical Displays HMI Test and Measurement Equipment Device Information(1) PART NUMBER TPS61177A PACKAGE VQFN (20) BODY SIZE (NOM) 3.50 mm x 3.50 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Typical Application – Analog and PWM Mixed Mode L1 10 μH VIN 2.5 V – 24 V D1 VOUT C2 4.7 μF C1 4.7 μF LXB VINB C4 1 μF PGND VLED VCC R1 10 kΩ R2 10 kΩ ENB PWMB 100 Hz – 25 KHz SDA CS1 SCL CS2 CS3 CS4 CS5 CS6 REF C5 470 nF AGND 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TPS61177A SNVSA76B – MARCH 2015 – REVISED MARCH 2017 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 4 6.1 6.2 6.3 6.4 6.5 6.6 6.7 4 4 4 4 5 7 8 Absolute Maximum Ratings ...................................... ESD Ratings.............................................................. Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics........................................... I2C Timing Requirements.......................................... Typical Characteristics .............................................. Detailed Description ............................................ 12 7.1 Overview ................................................................. 12 7.2 Functional Block Diagram ....................................... 12 7.3 Feature Description................................................. 12 7.4 Device Functional Modes........................................ 16 7.5 Programming........................................................... 18 7.6 Register Maps ......................................................... 18 8 Application and Implementation ........................ 27 8.1 Application Information............................................ 27 8.2 Typical Application ................................................. 28 9 Power Supply Recommendations...................... 30 10 Layout................................................................... 31 10.1 Layout Guidelines ................................................. 31 10.2 Layout Example .................................................... 31 11 Device and Documentation Support ................. 32 11.1 11.2 11.3 11.4 11.5 Device Support...................................................... Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 32 32 32 32 32 12 Mechanical, Packaging, and Orderable Information ........................................................... 32 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision A (March 2016) to Revision B • Changed layout example picture to show Vout connected to pin 14 of the device, not pin 13............................................ 31 Changes from Original (March 2015) to Revision A • 2 Page Page Added several items to "Applications" on page 1 .................................................................................................................. 1 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated Product Folder Links: TPS61177A TPS61177A www.ti.com SNVSA76B – MARCH 2015 – REVISED MARCH 2017 5 Pin Configuration and Functions RGR Package 20-Pin VQFN Top View Pin Functions PIN TYPE DESCRIPTION NAME NUMBER AGND 5, 9 — 6, 7, 8, 10, 11, 12 I Current sink regulation inputs. They are connected to the cathode of WLEDs. The PWM loop regulates the lowest VCS to 500 mV. Each channel is limited to 30-mA current. Connect any unused CS pin to AGND or leave it open. ENB 19 I Enable pin LXB 16, 17 I Drain connection of the internal PWM switch MOSFET and external Schottky diode. REF 4 O The reference pin for internal error amplifier. Connect a 470-nF ceramic capacitor to REF. PGND 15 — Power ground of the IC. Internally, it connects to the source of the PWM switch. Tie the ground of power stage components to this ground. PWMB 20 I Dimming control logic input. The dimming frequency range is from 100 Hz to 25 kHz. SCL 2 I Clock input for I2C interface SDA 1 I/O Data input for I2C interface VCC 3 I Internal pre-regulator and supply rail for the internal logic. Do not connect any capacitor to VCC pin. VINB 18 I Power supply to the IC VLED 14 I The voltage detect pin for VOUT. CS1, CS2, CS3, CS4, CS5, CS6 Signal ground of the device. Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated Product Folder Links: TPS61177A 3 TPS61177A SNVSA76B – MARCH 2015 – REVISED MARCH 2017 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) Voltage (2) (1) MIN MAX VINB –0.3 26.4 LXB, VLED, CS1, CS2, CS3, CS4, CS5, CS6 –0.3 40 ENB, PWMB –0.3 30 SDA, SCL, VCC –0.3 3.6 Continuous power dissipation –40 150 Storage temperature, Tstg –65 150 (2) V See Thermal Information Operating junction temperature (1) UNIT °C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to network ground terminal. 6.2 ESD Ratings VALUE Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 V(ESD) (1) (2) Electrostatic discharge (1) UNIT ±2000 Charged-device model (CDM), per JEDEC specification JESD22C101 (2) V ±1000 JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN MAX 2.5 24 VIN + 2 39 PWM input signal frequency 0.1 25 kHz PWM input signal minimum duty cycle 1% FBOOST Boost regulator switching frequency 450 1200 kHz TA Operating free-air temperature –40 85 TJ Operating junction temperature –40 125 VIN Input voltage VOUT Output voltage FPWM_I DMIN_I UNIT V °C 6.4 Thermal Information TPS61177A THERMAL METRIC (1) RGR (VQFN) UNIT 20 PINS RθJA Junction-to-ambient thermal resistance 34.4 °C/W RθJC(top) Junction-to-case (top) thermal resistance 46.8 °C/W RθJB Junction-to-board thermal resistance 12.2 °C/W ψJT Junction-to-top characterization parameter 0.5 °C/W ψJB Junction-to-board characterization parameter 12.3 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 1.0 °C/W (1) 4 For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated Product Folder Links: TPS61177A TPS61177A www.ti.com SNVSA76B – MARCH 2015 – REVISED MARCH 2017 6.5 Electrical Characteristics VINB = 12 V, PWMB/ENB = logic high, CS current = 20 mA, CS voltage = 500 mV, TA = –40°C to +85°C, typical values are at TA = 25°C (unless otherwise noted). PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY CURRENT VINB Input voltage range Iq_VINB Operating quiescent current into VIN ISD Shutdown current VINB_UVLO VIN_Hys VINB undervoltage lockout threshold, voltage ramp up 2.5 24 Device enable, no switching and no load, VINB = 12 V 3.5 VINB = 12 V, EN = low 10 VINB = 24 V, EN = low 15 UVLO = 000 2.1 2.25 2.4 UVLO = 001 2.4 2.55 2.7 UVLO = 010 2.8 3 3.2 UVLO = 011 3.3 3.5 3.7 Other case 3.8 4 4.2 VIN undervoltage lockout hysteresis 200 V mA µA V mV BOOST OUTPUT REGULATION VCS CS voltage regulation 500 600 VIN = 12 V 0.20 0.35 VIN = 3.3 V 0.30 0.40 2.2 2.6 A 5 µA RDS(ON) Switch FET on-resistance ILIM Switching MOSFET current limit D = Dmax ILEAK_LX Switch FET leakage current VSW = 40 V FLX Switching frequency DMAX Maximum duty cycle TF Slew rate of switching FET ON 1.8 FREQ = 00 0.36 0.45 0.54 FREQ = 01 0.48 0.6 0.72 FREQ = 10 0.64 0.8 0.96 1.44 FREQ = 11 0.96 1.2 FLX = 0.8 MHz 90% 95% SR = 00 4.6 SR = 01 3.5 SR = 10 2.5 SR = 11 1.3 ICS = 0000 15 ICS = 0001 16 … … mV Ω MHz V/ns CS CURRENT REGULATION ICS CSn current (See Figure 23) ICS = 1111 ICSA CSn current accuracy (ICSn – 20 mA × DPWM_I)/20 mA x DPWM_I mA 30 ICS = 20 mA, MODE = 00 and 01 DPWM_I = 100%, TA = 25°C –3% 3% ICS = 20 mA, MODE = 01 DPWM_I = 255/1023, TA = 25°C –3% 3% ICS = 20 mA, MODE = 10, DPWM_I = 255/1023, TA = 25°C –3% 3% ICS = 20 mA, MODE = 10, DPWM_I = 51/1023, TA = 25°C –5% 5% ICS = 20 mA, MODE = 10, DPWM_I = 10/1023, TA = 25°C –8% 8% Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated Product Folder Links: TPS61177A 5 TPS61177A SNVSA76B – MARCH 2015 – REVISED MARCH 2017 www.ti.com Electrical Characteristics (continued) VINB = 12 V, PWMB/ENB = logic high, CS current = 20 mA, CS voltage = 500 mV, TA = –40°C to +85°C, typical values are at TA = 25°C (unless otherwise noted). PARAMETER Current matching (ICSn – IAVG)/IAVG ICSM DC dimming resolution steps Brightness response time ICSLK CSn leakage current ICSIR CSn current inrush tMP Minimum dimming pulse tDEG Deglitch pulse width TEST CONDITIONS MIN TYP MAX ICS = 20 mA, MODE = 00 and 01, DPWM_I = 100%, TA = 25°C –2% 2% ICS = 20 mA, MODE = 01, DPWM_I = 255/1023, TA = 25°C –2% 2% ICS = 20 mA, MODE = 10, DPWM_I = 255/1023, TA = 25°C –2% 2% ICS = 20 mA, MODE = 10, DPWM_I = 51/1023, TA = 25°C –5% -5% ICS = 20 mA, MODE = 10, DPWM_I = 10/1023, TA = 25°C –5% 5% MODE = 01 and 10, FPWM_I = 0.1 to 5 kHz 1024 MODE = 01 and 10, FPWM_I = 5 to 10 kHz 512 MODE = 01 and 10, FPWM_I = 10 to 25 kHz 256 DPWM_I 10% to 90% MODE = mixed and DC, FPWM_I = 25 kHz 400 DPWM_I 10% to 90% MODE = mixed and DC, FPWM_I = 100 Hz 10.4 VCS = 40 V UNIT μs ms 5 μA 10% MODE = 00 400 ns 125 ns CONTROL AND PROTECTION VH ENB logic high threshold VINB = 2.7 V and 3.3 V VL ENB logic low threshold VINB = 2.7 V and 3.3 V VH PWMB logic high threshold VINB = 2.7 V and 3.3 V VL PWMB logic low threshold VINB = 2.7 V and 3.3 V Pulldown resistor on ENB ENB = 3.3 V 300 600 1200 Pulldown resistor on PWMB PWMB = 3.3 V 300 600 1200 39 39.5 40 RPD 1.8 0.5 1.8 0.5 VOVP Output overvoltage threshold Tshutdown Thermal shutdown threshold 150 Thermal shutdown hysteresis 15 FSAMPLE 6 Input sampling oscillator frequency 22 Submit Documentation Feedback V 25 kΩ V °C 29 MHz Copyright © 2015–2017, Texas Instruments Incorporated Product Folder Links: TPS61177A TPS61177A www.ti.com SNVSA76B – MARCH 2015 – REVISED MARCH 2017 6.6 I2C Timing Requirements MIN ADDR Configuration parameters slave address NOM Write 58h Read 59h MAX UNIT 0.75 V VIL Low level input voltage Supply = 2.5 V, VIN falling, standard and fast modes VIH High level input voltage Supply = 2.5 V, VIN rising, standard and fast modes 1.75 V VHYS Hysteresis Supply = 2.5 V, applicable to fast mode only 125 mV VOL Low level output voltage Sinking 3 mA CI Input capacitance ƒSCL Clock frequency tLOW Clock low period tHIGH Clock high period tBUF 500 mV 10 pF Standard mode 100 Fast mode 400 Standard mode 4.7 Fast mode 1.3 Standard mode 0.6 Bus free time between a STOP and a START condition Standard mode 4.7 Fast mode 1.3 thd:STA Hold time for a repeated START condition Standard mode tsu:STA Set-up time for a repeated START condition Standard mode tsu:DAT Data set-up time thd:DAT Data hold time tRCL1 tRCL Rise time of SCL tFCL Fall time of SCL tRDA Rise time of SDA tFDA Fall time of SDA tsu:STO Set-up time for STOP condition CB Capacitive load on SDA and SCL NWRITE Number of write cycles tWRITE Write time Fast mode µs 4 Fast mode µs µs 4 µs 0.6 4 µs Fast mode 0.6 Standard mode 250 Fast mode 100 Standard mode 0.05 3.45 Fast mode 0.05 0.9 Rise time of SCL after a repeated START Standard mode condition and after an ACK bit Fast mode 20+0.1CB 1000 20+0.1CB 1000 Standard mode 20+0.1CB 1000 Fast mode 20+0.1CB 300 Standard mode 20+0.1CB 300 Fast mode 20+0.1CB 300 Standard mode 20+0.1CB 1000 Fast mode 20+0.1CB 300 Standard mode 20+0.1CB 300 Fast mode 20+0.1CB 300 Data retention Standard mode Fast mode kHz ns 4 µs ns ns ns ns ns µs 0.6 Standard mode 400 Fast mode 400 pF 1000 100 Storage temperature = 150°C 100,000 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated Product Folder Links: TPS61177A ms hrs 7 TPS61177A SNVSA76B – MARCH 2015 – REVISED MARCH 2017 www.ti.com 6.7 Typical Characteristics Table 1. Table of Graphs TITLE DESCRIPTION FIGURE Figure 1 Efficiency vs PWM Duty in PWM Mode VIN = 3 V, 12 V, 21 V, VOUT = 6S6P, 8S6P, 10S6P, L = 10 µH Figure 2 Efficiency vs PWM duty in Mixed Mode VIN = 12 V, VOUT = 6S6P, 8S6P, 10S6P, ICS = 20 mA, L = 10 µH Figure 3 Efficiency vs PWM duty in Mixed Mode VIN = 3 V, 12 V, 21 V, VOUT = 6S6P, 8S6P, 10S6P, L = 10 µH Figure 4 Efficiency vs PWM duty in Analog Mode VIN = 12 V, VOUT = 6S6P, 8S6P, 10S6P, ICS = 20 mA, L = 10 µH Figure 5 Efficiency vs PWM duty in Analog Mode VIN = 3 V, 12 V, 21 V, VOUT = 6S6P, 8S6P, 10S6P, L = 10 µH Figure 6 Dimming Linearity in PWM Mode VIN = 12 V, VOUT = 10S6P , FDIM = 200 Hz and 20 kHz, L = 10 µH Figure 7 Dimming Linearity in Mixed Mode VIN = 12 V, VOUT = 10S6P , FDIM = 200 Hz and 20 kHz, L = 10 µH Figure 8 Dimming linearity in Analog Mode VIN = 12 V, VOUT = 10S6P , FDIM = 200 Hz and 20 kHz, L = 10 µH Figure 9 Switch Waveform VIN = 3 V, VOUT = 6S6P, Duty = 100%, L = 10 µH Figure 10 Switch Waveform VIN = 12 V, VOUT = 10S6P, Duty = 100%, L = 10 µH Figure 11 Mixed-Mode Dimming Ripple VIN = 12 V, VOUT = 10S6P, FDIM = 200 Hz, Duty = 50%, L = 10 µH Figure 12 Mixed-Mode Dimming Ripple VIN = 12 V, VOUT = 10S6P, FDIM = 200 Hz, Duty = 12.5%, L = 10 µH Figure 13 Mixed-Mode Dimming Ripple VIN = 12 V, VOUT = 10S6P, FDIM = 20 kHz, Duty = 12.5%, L = 10 µH Figure 14 PWM-Mode Dimming Ripple VIN = 12 V, VOUT = 10S6P, FDIM = 200 Hz, Duty = 50%, L = 10 µH Figure 15 PWM-Mode Dimming Ripple VIN = 12 V, VOUT = 10S6P, FDIM = 20 kHz, Duty = 50%, L = 10 µH Figure 16 100 100 90 90 80 80 Efficiency (%) Efficiency (%) Efficiency vs PWM Duty in PWM Mode VIN = 12 V, VOUT = 6S6P, 8S6P, 10S6P, ICS = 20 mA, L = 10 µH 70 60 6S6P 8S6P 10S6P 50 40 0 20 40 60 80 60 Vin V6S6P 6S6P V in ==33V 50 Vin 12VV8S6P 8S6P V in ==12 V Vin 21VV10S6P 10S6P in ==21 40 100 PWM Duty Cycle (%) 0 20 40 60 80 100 PWM Duty Cycle (%) C001 Figure 1. Efficiency vs PWM Duty in PWM Mode 8 70 C002 Figure 2. Efficiency vs PWM Duty in PWM Mode Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated Product Folder Links: TPS61177A TPS61177A SNVSA76B – MARCH 2015 – REVISED MARCH 2017 100 100 90 90 80 80 Efficiency (%) Efficiency (%) www.ti.com 70 60 6S6P 8S6P 10S6P 50 40 0 20 40 60 80 100 80 Efficiency (%) 80 70 60 6S6P 8S6P 10S6P 50 40 80 80 100 C004 60 Vin V6S6P 6S6P V in ==33V 50 Vin 12VV8S6P 8S6P V in ==12 V Vin 21VV10S6P 10S6P in ==21 40 0 20 Figure 5. Efficiency vs PWM Duty in Analog Mode 100 100 80 80 Current (mA) 120 40 200 Hz 60 80 100 C006 Figure 6. Efficiency vs PWM Duty in Analog Mode 120 60 40 PWM Duty Cycle (%) C005 20 60 70 100 PWM Duty Cycle (%) 40 Figure 4. Efficiency vs PWM Duty in Mixed Mode 90 60 20 PWM Duty Cycle (%) 90 40 V Vin 21VV10S6P 10S6P in ==21 0 100 20 Vin 12VV8S6P 8S6P V in ==12 C003 100 0 Vin V6S6P 6S6P V in ==33V 40 Figure 3. Efficiency vs PWM Duty in Mixed Mode Efficiency (%) 60 50 PWM Duty Cycle (%) Current (mA) 70 60 40 200 Hz 20 20 kHz 20 kHz 0 0 0 20 40 60 80 PWM Duty Cycle (%) 100 0 20 Figure 7. Dimming Linearity in PWM Mode 40 60 80 PWM Duty Cycle (%) C007 100 C008 Figure 8. Dimming Linearity in Mixed Mode Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated Product Folder Links: TPS61177A 9 TPS61177A SNVSA76B – MARCH 2015 – REVISED MARCH 2017 www.ti.com 120 VLED Voltage 100mV/div Current (mA) 100 80 LXB Voltage 10V/div 60 40 200 Hz 20 Inductor Current 300mA/div 20 kHz 0 0 20 40 60 80 PWM Duty Cycle (%) 100 C009 Time (1µs/div) Figure 9. Dimming Linearity in Analog Mode Figure 10. Switch Waveform VLED Voltage 100mV/div VLED Voltage 100mV/div PWMB Voltage 3V/div CS1 Voltage 1V/div LXB Voltage 10V/div CS Current 50mA/div Inductor Current 300mA/div Time (1µs/div) Time (5 ms/div) FDIM = 200 Hz Figure 11. Switch Waveform Figure 12. Mixed-Mode PWM Dimming VLED Voltage 100mV/div VLED Voltage 100mV/div PWMB Voltage 3V/div PWMB Voltage 3V/div CS1 Voltage 4V/div CS1 Voltage 4V/div IOUT Current 50mA/div IOUT Current 50mA/div Time (5 ms/div) FDIM = 200 Hz Time (50 µs/div) Duty = 12.5% FDIM = 20 kHz Figure 13. Mixed-Mode PWM Dimming 10 Duty = 50% Submit Documentation Feedback Duty = 12.5% Figure 14. Mixed-Mode PWM Dimming Copyright © 2015–2017, Texas Instruments Incorporated Product Folder Links: TPS61177A TPS61177A www.ti.com SNVSA76B – MARCH 2015 – REVISED MARCH 2017 VLED Voltage 200mV/div VLED Voltage 200mV/div PWMB Voltage 3V/div PWMB Voltage 3V/div CS1 Voltage 5V/div CS1 Voltage 5V/div IOUT Current 100mA/div IOUT Current 100mA/div Time (5 ms/div) FDIM = 200 Hz Time (50 µs/div) Duty = 50% FDIM = 20 kHz Figure 15. PWM Mode Dimming Duty = 50% Figure 16. PWM Mode Dimming Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated Product Folder Links: TPS61177A 11 TPS61177A SNVSA76B – MARCH 2015 – REVISED MARCH 2017 www.ti.com 7 Detailed Description 7.1 Overview The TPS61177A is a high-efficiency, high output voltage white-LED (WLED) driver for notebook panel backlighting applications. Due to the large number of white LEDs required to provide backlighting for medium-tolarge display panels, the LEDs must be arranged in parallel strings of several LEDs in series. Therefore, the backlight driver for battery-powered systems is almost always a boost regulator with multiple current-sink regulators. Having more WLEDs in series reduces the number of parallel strings, thus improving overall current matching. However, the efficiency of the boost regulator declines due to the need for high output voltage. Also, there must be enough white LEDs in series to ensure the output voltage stays above the input voltage range. The TPS61177A device has integrated all of the key function blocks to power and control up to 72 WLEDs. The device includes a 1.8-A, 40-V boost regulator, six 30-mA current sink regulators, and a protection circuit for overcurrent, overvoltage, open LED, short LED, and overtemperature failures. The TPS61177A integrates mixed mode dimming methods with the PWM interface to reduce the output ripple voltage and audible noise. Optional direct PWM and pure analog dimming modes are user selectable through the I2C programming. 7.2 Functional Block Diagram L D VIN VOUT C1 4.7μF C2 4.7μF LXB VLED VIN VCC Linear Regulator R Q S Slope Compensation Oscillator PGND Σ M U X EA GM REF PWM C3 470nF Vref 500mV CS1 CS2 CS3 CS4 CS5 CS6 CS1 25MHz ENB PWMB SDA SCL Decoder A0h A1h A2h A3h A4h A5h MODE CS UVLO FREQ SR Dimming Mode EA Current Reference ILIM I2C Interface AGND Current Sink Current Sink Current Sink Current Sink Current Sink CS2 CS3 CS4 CS5 CS6 7.3 Feature Description 7.3.1 Supply Voltage The TPS61177A device has a built-in linear regulator to supply the device analog and logic circuit. The VCC pin is recommended to be open without any capacitance load. VCC does not have high current sourcing capability for external use and typically is regulated at 3.3 V. 12 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated Product Folder Links: TPS61177A TPS61177A www.ti.com SNVSA76B – MARCH 2015 – REVISED MARCH 2017 Feature Description (continued) 7.3.2 Boost Regulator The fixed-frequency PWM boost converter uses current-mode control and has integrated loop compensation. The internal compensation ensures stable output over the full input and output voltage ranges assuming the recommended inductance and output capacitance values shown in Figure 36. The output voltage of the boost regulator is automatically set by the device to minimize voltage drop across the CS pins. The device regulates the lowest CS pin to 500 mV at 20-mA current and consistently adjusts the boost output voltage to account for any changes in LED forward voltages. If the input voltage is higher than the sum of the WLED forward voltage drops (at low duty cycles), the boost converter is not able to regulate the output due to its minimum duty cycle limitation. In this case, increase the number of WLEDs in series or include series ballast resistors in order to provide enough headroom for the converter to boost the output voltage. Since the TPS61177A integrates a 1.8A, 40-V power MOSFET, the boost converter can provide up to a 39-V output voltage. 7.3.3 Programmable Switch Frequency and Slew Rate Both switching frequency and slew rate of TPS61177A can be programmable by a E2PROM register value which is pre-set before device power up. The switching frequency has four options adjustable to 450 kHz, 600 kHz, 800 kHz, or 1200 kHz. The slew rate of switching FET from off to on also has four selections: 1.3 V/ns, 2.5 V/ns, 3.5 V/ns to 4.6 V/ns. See FREQ (A3h) and SR (A4h) for E2PROM address and data table of boost switching frequency programming and boost switching slew rate selection. The adjustable switching frequency feature provides the user with the flexibility of choosing either a faster switching frequency by using an inductor with smaller inductance and footprint or a slower switching frequency to get potentially higher efficiency due to lower switching losses. In additional, the selectable slew rate for switching gives flexibility to trade off between switching loss and electronic-magnetic interference (EMI) effects to the application system. 7.3.4 LED Current Sinks The six current sink regulators embedded in the TPS61177A can be collectively configured to provide up to a maximum of 30 mA each. These six specialized current sinks are accurate to within ±3% max for currents at 20 mA, with a string-to-string difference of ±2%. Each CS channel current must be programmed to the highest WLED current expected; each CS channel current is programmable from 15 mA to 30 mA by an E2PROM register through the I2C interface. See CS (A1h) for the E2PROM register table of CS current programming. 7.3.5 Enable and Start-Up Timing The internal regulator which provides VCC wakes up as soon as ENB is applied. VCC does not come to full regulation until VINB voltage is above UVLO. Before boost convert start-up, the TPS61177A checks the status of all current feedback channels and shuts down any unused feedback channels. It is recommended to short the unused channels to ground for faster start-up. After the device is enabled, if the PWM pin is left floating or grounded, the output voltage of the TPS61177A regulates to the minimum output voltage. Once the device detects a voltage on the PWM pin, the TPS61177A begins to regulate the CS pin current, as a pre-set per the E2PROM register data, according to the duty cycle of the signal on the PWMB pin. The boost converter output voltage rises to the appropriate level to accommodate the sum of the white LED string with the highest forward voltage drops plus the headroom of the current sink at that current. Pulling the ENB pin low shuts down the device, resulting in consumption of less than 10 µA in shutdown mode. The TPS61177A also integrates power-up sequence control for start-up. There is no specified power or control signal sequence requirement for VINB, ENB, and PWMB. Figure 17 provides the detail timing diagram for TPS61177A start-up and shutdown. Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated Product Folder Links: TPS61177A 13 TPS61177A SNVSA76B – MARCH 2015 – REVISED MARCH 2017 www.ti.com Feature Description (continued) VINB ENB PWMB VLED PWMB decoder delay No use detection 4 ms VCSn ICSn Figure 17. Start-up and Shutdown Timing Diagram The PWMB decoder delay time period is determined by different dimming mode, input duty cycle, and frequency on the PWMB pin. In PWM mode, the decoder delay time is zero. Once the rising edge is detected on the PWMB pin, the output voltage starts ramping up immediately. While in mixed dimming mode or analogdimming mode, the decoder delay time is equal to twice input PWM signal cycle time and 400 µs minimally. If PWM signal input keeps at high level after first rising edge, the decoder delay is about 20 ms. Figure 18 provides the detail timing diagram for TPS61177A start-up and shutdown when one of CS channel is open. The VLED voltage always ramps up to the overvoltage protection threshold which is 39.5 V typically, if one of CS pin is floating. The device then detects the zero current string, and removes it from the feedback loop. 14 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated Product Folder Links: TPS61177A TPS61177A www.ti.com SNVSA76B – MARCH 2015 – REVISED MARCH 2017 Feature Description (continued) VINB ENB PWMB 39.5 V VLED PWMB decoder delay 4 ms No use detection VCSn ICSn Figure 18. Start-Up and Shutdown Timing Diagram (Mixed Mode and DC Mode) 7.3.6 Input Undervoltage Protection (UVLO) The TPS61177A will not start up until the VINB voltage is higher than the UVLO threshold which is preset by E2PROM register data. During normal operation, if the VINB drops below UVLO with 200-mV hysteresis, the TPS61177A immediately shuts down. See UVLO (A2h) for E2PROM address and data table of UVLO threshold. 7.3.7 Overvoltage Protection (OVP) The TPS61177A integrates output OVP which is fixed at 39.5 V typically. Once the VLED pin detects the voltage higher than 39.5 V, the boost switching regulator stops switching until the voltage of VLED pin drop below 39.5 V with 500-mV hysteresis. 7.3.8 Current-Sink Open Protection If one of the device WLED strings is open, the device automatically detects and disables that string. The open WLED string is detected by sensing no current in the corresponding CS pin. As a result, the TPS61177A deactivates the open current sink and removes it from the voltage feedback loop. Subsequently, the output voltage drops and is regulated to the minimum voltage required for the connected WLED strings. The CS currents of the connected WLED strings remain in regulation. The device turns off if it detects that all of the WLED strings are open. If an open string is reconnected again, a power-on reset (POR) or ENB pin toggling is required to reactivate a previously deactivated string. 7.3.9 Overcurrent Protection The TPS61177A has a pulse-by-pulse overcurrent limit of 1.8 A (minimum). The PWM switch turns off when the inductor current reaches this current threshold. The PWM switch remains off until the beginning of the next switching cycle. This protects the device and external components during an overload condition. When there is a sustained overcurrent condition more than 2 ms, the device shuts down and requires a POR or EN pin toggling to restart. The overcurrent shutdown protection can be disabled by E2PROM register through I2C interface. See ILIM (A5h) for E2PROM register table of ILIM shutdown protection programming. Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated Product Folder Links: TPS61177A 15 TPS61177A SNVSA76B – MARCH 2015 – REVISED MARCH 2017 www.ti.com Feature Description (continued) 7.3.10 Thermal Protection When the junction temperature of the TPS61177A is over 150°C, the thermal protection circuit is triggered and shuts down the device immediately. The device automatically restarts when the junction temperature is back to less than 150°C with about 15°C hysteresis. 7.4 Device Functional Modes 7.4.1 Mode Selection The mixed-mode dimming method, analog dimming method, or direct PWM dimming method can be selected through the E2PROM register. See MODE (A0h) for E2PROM register table of dimming mode programming. 7.4.2 Analog and PWM Mixed Dimming Mode In analog and PWM mixed mode, the TPS61177A features both analog dimming and PWM digital dimming. Analog dimming can provide potentially a lower power requirement for the same WLED brightness output because of a low voltage drop across each WLED when the current is low. Digital PWM dimming provides less WLED color distortion since the WLED current is held at 25% of full scale when the WLED is on. The brightness control signal on the PWM pin is translated to a 10-bit digital signal and sent to control the six current regulators. Each current regulator outputs is DC, and PWM (25% < DPWM < 100%) modulates the amplitude of the currents from 25% to 100% of preset full-scale current. For DPWM < 25%, each CS turns on/off at translated duty cycle and same frequency to the input PWM, and in the WLED on duty current is regulated at 25% of full scale. Mixed-mode dimming provides the benefits of both the analog and PWM dimming. For 25% < DPWM < 100%, analog dimming benefits the low power requirement and increases the power to brightness transform efficiency. At light load conditions, DPWM < 25%, the PWM dimming provides both high accuracy brightness and low color distortion. Figure 19 provides the detailed timing diagram of the analog and PWM mixed dimming mode. D=100% D=80% PWM Input D=60% D=50% D=25% D=12.5% D=6.25% TON TPWM ILEDMAX 80% 60% 50% CSn D=50% D=25% 25% 0A Analog and PWM Mixed Dimming Mode Figure 19. Analog and PWM Mixed-Mode Dimming Diagram 7.4.3 Analog Dimming Mode In analog dimming mode, TPS61177A features pure analog dimming all over the brightness range of full-scale LED current. Analog dimming can provide potentially low power requirement for same WLED brightness output because of low voltage drop across each WLED when the current is low. In additional, the brightness control signal on the PWMB pin is translated to an up to 10-bits digital signal and sent to control the six current regulators. Each current regulator output DC modulates the amplitude of the currents from 1% to 100% of preset full-scale current. Figure 20 provides the detailed timing diagram of the analog dimming mode. 16 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated Product Folder Links: TPS61177A TPS61177A www.ti.com SNVSA76B – MARCH 2015 – REVISED MARCH 2017 Device Functional Modes (continued) D=100% PWM Input D=80% D=60% D=50% D=25% D=12.5% D=6.25% TON TPWM ILEDMAX 80% 60% 50% CSn 25% 12.5% 0A Analog Dimming Mode Figure 20. Analog-Mode Dimming Diagram 7.4.4 Direct PWM Dimming In direct PWM mode, all current feedback channels are turned on and off and are synchronized with the input PWM signal. Figure 21 provides the detailed timing diagram of the direct PWM dimming mode. D=100% PWM Input D=80% D=60% D=50% D=25% D=12.5% D=6.25% TON TPWM ILEDMAX CSn 0A Direct PWM Dimming Mode Figure 21. Direct PWM-Mode Dimming Diagram Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated Product Folder Links: TPS61177A 17 TPS61177A SNVSA76B – MARCH 2015 – REVISED MARCH 2017 www.ti.com 7.5 Programming 7.5.1 Configuration Parameters Table 2 shows the memory map of the configuration parameters. Table 2. Configuration Memory Map REGISTER ADDRESS REGISTER NAME FACTORY DEFAULT DESCRIPTION A0h MODE 01h Sets brightness dimming mode A1h CS 05h Sets the current sinks full scale current A2h UVLO 03h Sets the input voltage UVLO threshold A3h FREQ 01h Sets the boost switching frequency A4h SR 00h Sets the boost switching slew rate A5h ILIM 00h Enables/disables the shutdown protection for current limit FFh Control 00h Controls whether read and write operations access RAM or E2PROM registers. 7.6 Register Maps 7.6.1 MODE (A0h) The MODE register can be written to and read from. Figure 22. MODE Register Bit Allocation 7 6 5 4 3 2 1 RESERVED R/W-0 0 MODE R/W-1 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 3. MODE Register Bit Field Descriptions Bit Field Type Reset Description 7:2 RESERVED R/W 0 These bits are reserved for future use. During write operations, data intended for these bits are ignored, and during read operations 0 is returned. 1:0 MODE R/W 1 These bits configure the current sink dimming method for brightness control. 00 = Direct PWM dimming mode 01 = Analog and PWM mixed dimming mode 10 = Analog dimming mode 7.6.2 CS (A1h) The CS register can be written to and read from. Figure 23. CS Register Bit Allocation 7 6 5 4 3 2 RESERVED R/W-0 1 0 CS R/W-5 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 4. CS Register Bit Descriptions 18 Bit Field Type Reset 7:4 RESERVED R/W 0 Description These bits are reserved for future use. During write operations, data intended for these bits are ignored, and during read operations 0 is returned. Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated Product Folder Links: TPS61177A TPS61177A www.ti.com SNVSA76B – MARCH 2015 – REVISED MARCH 2017 Table 4. CS Register Bit Descriptions (continued) Bit Field Type Reset Description These bits select the full scale current for all six current sinks. 3:0 CS R/W 0000: 0001: 0010: 0011: 0100: 0101: 0110: 0111: 5 ICS = 15 ICS = 16 ICS = 17 ICS = 18 ICS = 19 ICS = 20 ICS = 21 ICS = 22 mA mA mA mA mA mA mA mA 1000: 1001: 1010: 1011: 1100: 1101: 1110: 1111: ICS = 23 ICS = 24 ICS = 25 ICS = 26 ICS = 27 ICS = 28 ICS = 29 ICS = 30 mA mA mA mA mA mA mA mA 7.6.3 UVLO (A2h) The UVLO register can be written to and read from. Figure 24. UVLO Register Bit Allocation 7 6 5 RESERVED R/W-0 4 3 2 1 UVLO R/W-3 0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 5. UVLO Register Bit Field Descriptions Bit Field Type Reset 7:3 RESERVED R/W 0 These bits are reserved for future use. During write operations data intended for these bits is ignored, and during read operations 0 is returned. 3 These bits select the UVLO threshold. 000: VUVLO = 2.25 V 001: VUVLO = 2.55 V 010: VUVLO = 3 V 011: VUVLO = 3.5 V 100: VUVLO = 4 V Others: VUVLO = 4 V 2:0 UVLO R/W Description 7.6.4 FREQ (A3h) The FREQ register can be written to and read from. Figure 25. FREQ Register Bit Allocation 7 6 5 4 3 2 1 RESERVED R/W-0 0 FREQ R/W-1 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 6. FREQ Register Bit Field Descriptions Bit Field Type Reset 7:2 RESERVED R/W 0 These bits are reserved for future use. During write operations, data intended for these bits are ignored, and during read operations 0 is returned. 1 These bits configure the switching frequency. 00: FLX = 450 kHz 01: FLX = 600 kHz 10: FLX = 800 kHz 11: FLX = 1200 kHz 1:0 FREQ R/W Description Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated Product Folder Links: TPS61177A 19 TPS61177A SNVSA76B – MARCH 2015 – REVISED MARCH 2017 www.ti.com 7.6.5 SR (A4h) The SR register can be written to and read from. Figure 26. SR Register Bit Allocation 7 6 5 4 3 2 1 RESERVED R/W-0 0 SR R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 7. SR Register Bit Field Descriptions Bit Field Type Reset 7:2 RESERVED R/W 0 These bits are reserved for future use. During write operations, data intended for these bits are ignored, and during read operations 0 is returned. 0 These bits configure the falling slew rate of switching voltage from OFF to ON. 00: SR = 4.6 V/ns 01: SR = 3.5 V/ns 10: SR = 2.5 V/ns 11: SR = 1.3 V/ns 1:0 SR R/W Description 7.6.6 ILIM (A5h) The ILIM register can be written to and read from. Figure 27. ILIM Register Bit Allocation 7 6 5 4 RESERVED R/W-0 3 2 1 0 ILIM R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 8. ILIM Register Bit Field Descriptions Bit Field Type Reset 7:1 RESERVED R/W 0 These bits are reserved for future use. During write operations, data intended for these bits are ignored, and during read operations 0 is returned. ILIM R/W 0 This bit configures the current limit shutdown protection. 0 = Disable current limit shutdown protection 1 = Enable current limit shutdown protection 0 20 Description Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated Product Folder Links: TPS61177A TPS61177A www.ti.com SNVSA76B – MARCH 2015 – REVISED MARCH 2017 7.6.7 Control (FFh) Figure 28. Control Register Bit Allocation 7 WED 6 5 4 3 2 1 0 RED R/W-0 RESERVED R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 9. Control Register Bit Field Descriptions Bit 7 6:1 0 Field Type Reset Description Setting this bit forces the contents of all registers to be copied into E2PROM, thereby making them the default values during power up. When the contents of all the registers have been written to E2PROM, the TPS61177A device automatically resets this bit. WED RESERVED R/W RED R/W 0 These bits are reserved for future use. During write operations, data intended for these bits are ignored, and during read operations 0 is returned. 0 The state of this bit determines whether read operations return the contents of the registers or the contents of the E2PROM. 0 = Read operations return the contents of the registers. 1 = Read operations return the contents of the E2PROM. 7.6.8 Example – Writing to a Single RAM Register 1. Bus master sends START condition 2. Bus master sends 7-bit slave address plus low R/W bit (58h) 3. TPS61177A acknowledges 4. Bus master sends address of RAM register (A0h) 5. TPS61177A acknowledges 6. Bus master sends data to be written 7. TPS61177A acknowledges 8. Bus master sends STOP condition 58h S A0h 7-Bit Slave Address 0 A RAM Register Address DATA A RAM Register Data A P Figure 29. Writing To A Single Ram Register Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated Product Folder Links: TPS61177A 21 TPS61177A SNVSA76B – MARCH 2015 – REVISED MARCH 2017 www.ti.com 7.6.9 Example – Writing to Multiple RAM Registers 1. Bus master sends START condition 2. Bus master sends 7-bit slave address plus low R/W bit (58h). 3. TPS61177A acknowledges 4. Bus master sends address of first RAM register to be written to (A0h) 5. TPS61177A acknowledges 6. Bus master sends data to be written to first RAM register 7. TPS61177A acknowledges 8. Bus master sends data to be written to RAM register at next higher address (auto-increment) 9. TPS61177A acknowledges 10. Steps (8) and (9) repeated until data for final RAM register has been sent 11. TPS61177A acknowledges 12. Bus master sends STOP condition 58h S A0h 7-Bit Slave Address 0 A DATA DATA RAM Register Address (n) A RAM Register Data (n) A RAM Register Data (n+1) A DATA RAM Register Data (Last) A P Figure 30. Writing To Multiple Ram Registers 7.6.10 Example – Saving Contents of all RAM Registers to E2PROM 1. Pull high the Enable pin of TPS61177A 2. Pull the PWM pin of TPS61177A to low 3. Bus master sends START condition 4. Bus master sends 7-bit slave address plus low R/W bit (58h) 5. TPS61177A acknowledges 6. Bus master sends address of Control Register (FFh) 7. TPS61177A acknowledges 8. Bus master sends data to be written to the Control Register (80h) 9. TPS61177A acknowledges 10. Bus master sends STOP condition 58h S 7-Bit Slave Address 80h FFh 0 A Control Register Address A Control Register Data A P Figure 31. Saving Contents Of All Ram Registers To E2PROM The TPS61177A needs a 50-ms time period after receiving STOP condition for saving all RAM registers data to E2PROM. If bus master send 7-bit slave address to call TPS61177A again within 50-ms period, the TPS61177A pulls down the SCL line to LOW until the all RAM registers data saving to E2PROM is completed. 22 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated Product Folder Links: TPS61177A TPS61177A www.ti.com SNVSA76B – MARCH 2015 – REVISED MARCH 2017 7.6.11 Example – Reading from a Single RAM Register 1. Bus master sends START condition 2. Bus master sends 7-bit slave address plus low R/W bit (58h) 3. TPS61177A acknowledges 4. Bus master sends address of Control Register (FFh) 5. TPS61177A acknowledges 6. Bus master sends data for Control Register (00h) 7. TPS61177A acknowledges 8. Bus master sends STOP condition 9. Bus master sends START condition 10. Bus master sends 7-bit slave address plus low R/W bit (58h) 11. TPS61177A acknowledges 12. Bus master sends address of RAM register (A0h) 13. TPS61177A acknowledges 14. Bus master sends REPEATED START condition 15. Bus master sends 7-bit slave address plus high R/W bit (59h) 16. TPS61177A acknowledges 17. TPS61177A sends RAM register data 18. Bus master not acknowledges 19. Bus master sends STOP condition 58h S 7-Bit Slave Address S 7-Bit Slave Address 00h FFh 0 A Control Register Address 0 A RAM Register Address 58h A Control Register Data A P 1 A 59h A0h A Sr 7-Bit Slave Address DATA RAM Register Data A P Figure 32. Reading From A Single Ram Register Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated Product Folder Links: TPS61177A 23 TPS61177A SNVSA76B – MARCH 2015 – REVISED MARCH 2017 www.ti.com 7.6.12 Example – Reading from a Single E2PROM Register 1. Bus master sends START condition 2. Bus master sends 7-bit slave address plus low R/W bit (58h) 3. TPS61177A acknowledges 4. Bus master sends address of Control Register (FFh) 5. TPS61177A acknowledges 6. Bus master sends data for Control Register (01h) 7. TPS61177A acknowledges 8. Bus master sends STOP condition 9. Bus master sends START condition 10. Bus master sends 7-bit slave address plus low R/W bit (58h) 11. TPS61177A acknowledges 12. Bus master sends address of RAM register (A0h) 13. TPS61177A acknowledges 14. Bus master sends REPEATED START condition 15. Bus master sends 7-bit slave address plus high R/W bit (59h) 16. TPS61177A acknowledges 17. TPS61177A sends E2PROM register data 18. Bus master not acknowledges 19. Bus master sends STOP condition 58h S 7-Bit Slave Address S 7-Bit Slave Address 01h FFh 0 A Control Register Address 0 A E PROM Register Address 58h A A P 1 A 59h A0h 2 Control Register Data A Sr DATA 7-Bit Slave Address 2 E PROM Register Address A P Figure 33. Reading From A Single E2PROM Register 24 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated Product Folder Links: TPS61177A TPS61177A www.ti.com SNVSA76B – MARCH 2015 – REVISED MARCH 2017 7.6.13 Example – Reading from Multiple RAM Registers 1. Bus master sends START condition 2. Bus master sends 7-bit slave address plus low R/W bit (58h) 3. TPS61177A acknowledges 4. Bus master sends address of Control Register (FFh) 5. TPS61177A acknowledges 6. Bus master sends data for Control Register (00h) 7. TPS61177A acknowledges 8. Bus master sends STOP condition 9. Bus master sends START condition 10. Bus master sends 7-bit slave address plus low R/W bit (58h) 11. TPS61177A acknowledges 12. Bus master sends address of RAM register (A0h) 13. TPS61177A acknowledges 14. Bus master sends REPEATED START condition 15. Bus master sends 7-bit slave address plus high R/W bit (59h) 16. TPS61177A acknowledges 17. TPS61177A sends contents of first RAM register to be read 18. Bus master acknowledges 19. TPS61177A sends contents of second RAM register to be read 20. Bus master acknowledges 21. TPS61177A sends contents of third (last) RAM register to be read 22. Bus master not acknowledges 23. Bus master sends STOP condition 58h S 7-Bit Slave Address S 7-Bit Slave Address FFh 0 A Control Register Address 0 A RAM Register Address (n) 58h 00h Control Register Data A A0h A P 1 A DATA 59h A Sr 7-Bit Slave Address A DATA DATA RAM Register Data (n+1) RAM Register Data (n) A RAM Register Data (Last) A P Figure 34. Reading From A Multiple Ram Register Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated Product Folder Links: TPS61177A 25 TPS61177A SNVSA76B – MARCH 2015 – REVISED MARCH 2017 www.ti.com 7.6.14 Example – Reading from Multiple E2PROM Registers 1. Bus master sends START condition 2. Bus master sends 7-bit slave address plus low R/W bit (58h) 3. TPS61177A acknowledges 4. Bus master sends address of Control Register (FFh) 5. TPS61177A acknowledges 6. Bus master sends data for Control Register (01h) 7. TPS61177A acknowledges 8. Bus master sends STOP condition 9. Bus master sends START condition 10. Bus master sends 7-bit slave address plus low R/W bit (58h) 11. TPS61177A acknowledges 12. Bus master sends address of E2PROM register (00h) 13. TPS61177A acknowledges 14. Bus master sends REPEATED START condition 15. Bus master sends 7-bit slave address plus high R/W bit (59h) 16. TPS61177A acknowledges 17. TPS61177A sends contents of first E2PROM register to be read 18. Bus master acknowledges 19. TPS61177A sends contents of second E2PROM register to be read 20. Bus master acknowledges 21. TPS61177A sends contents of third (last) E2PROM register to be read 22. Bus master not acknowledges 23. Bus master sends STOP condition 58h S 7-Bit Slave Address S 7-Bit Slave Address FFh Control Register Address 01h 0 A 0 A E PROM Register Address (n) A Sr 58h A Control Register Data A0h 2 A P 1 A DATA 59h 7-Bit Slave Address 2 E PROM Register Data (n) A DATA DATA 2 2 E PROM Register Data (n+1) A E PROM Register Data (Last) A P Figure 35. Reading From Multiple E2PROM Registers 26 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated Product Folder Links: TPS61177A TPS61177A www.ti.com SNVSA76B – MARCH 2015 – REVISED MARCH 2017 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 8.1 Application Information 8.1.1 CS Pin Unused The TPS61177A has open/short string detection. For an unused CS string, simply short it to ground or leave it open. If the CS pin is open, the boost output voltage ramps up to overvoltage threshold during start-up. The device then detects the zero current string and removes it from the feedback loop. If the CS pin is shorted to ground, the device detects the short and immediately removes it (or them) out of feedback loop within 4 ms after device enable, and the boost output voltage does not go up to overvoltage threshold. Instead, it ramps to the regulation voltage after soft start. Shorting unused CS pins to ground for faster start-up is recommended. 8.1.2 Brightness Dimming Control The TPS61177A has three dimming methods. See Mode Selection section for dimming mode selection. With analog and PWM mixed dimming or pure analog dimming through the PWM control interface, the internal decoder block detects duty information from the input PWM signal, saves it in an up to 10-bits register and delivers to either a mixed mode dimming control circuit or pure analog dimming control circuit. In mixed dimming mode, the output dimming control circuit sets the DC current of six current sinks linearly between 25% and 100% at same scale to the value in up to a 10-bits register. When the brightness level is below 25% to full-scale value, the dimming control circuit turns on/off six output current sinks at same frequency with PWMB and duty cycle out of shift register. See Analog and PWM Mixed Dimming Mode section for more explanation. While in pure analog dimming mode, the output dimming control circuit sets the DC current of six current sinks linearly between 1% and 100% at same scale to the value in up to a 10-bits register. See Analog Dimming Mode section for more detail explanation. The TPS61177A also has direct PWM dimming control through the PWM control interface. In direct PWM mode, each current sink turns on/off at the same frequency and duty cycle as the input PWM signal. See Direct PWM Dimming section for more explanation. When in analog and PWM mixed mode, insertion of a series 10-kΩ to 20-kΩ resistor close to PWMB pin is recommended. This resistor, together with an internal capacitor, forms a low pass R-C filter with a 30-ns to 60-ns time constant. This prevents possible high frequency noise being coupled into the input PWM signal and causing interference to the internal duty cycle decoding circuit. However, it is not necessary for direct PWM mode since the duty cycle decoding circuit is disabled during direct PWM mode. Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated Product Folder Links: TPS61177A 27 TPS61177A SNVSA76B – MARCH 2015 – REVISED MARCH 2017 www.ti.com 8.2 Typical Application L1 10 μH VIN 2.5 V – 24 V D1 VOUT C2 4.7 μF C1 4.7 μF LXB VINB C4 1 μF PGND VLED VCC R1 10 kΩ R2 10 kΩ ENB PWMB 100 Hz – 25 KHz SDA CS1 SCL CS2 CS3 CS4 CS5 CS6 REF C5 470 nF AGND Figure 36. TPS61177A Typical Application 8.2.1 Design Requirements 28 DESIGN PARAMETER EXAMPLE VALUE Inductor 10 µH Minimum input voltage 2.5 V Number of series LED 12 LED maximum forward voltage (Vf) 3.3 V Schottky diode forward voltage (Vf) 0.2 V Efficiency (η) 85% Switching frequency 600 kHz PWM input frequency 1 kHz Maximum LED string current 30 mA Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated Product Folder Links: TPS61177A TPS61177A www.ti.com SNVSA76B – MARCH 2015 – REVISED MARCH 2017 The TPS61177A is designed to support up to 2.2 A (typical) SW current. Thus, SW current must be carefully calculated with factors such as inductor, target efficiency, output voltage, load current, and so forth. In most cases, the voltage ratio between input and boost output must be < 10. 8.2.2 Detailed Design Procedure 8.2.2.1 Inductor Selection Because selection of the inductor affects power supply steady-state operation, transient behavior, and loop stability, the inductor is the most important component in switching power regulator design. There are three specifications most important to the performance of the inductor: inductor value, DC resistance, and saturation current. The TPS61177A is designed to work with inductor values between 4.7 µH and 22 µH. A 10-µH inductor is typically available in a smaller or lower profile package, while a 22-µH inductor may produce higher efficiency due to a slower switching frequency and/or lower inductor ripple. If the boost output current is limited by the overcurrent protection of the device, using a 10-µH inductor and the highest switching frequency maximizes controller output current capability. Internal loop compensation for PWM control is optimized for the external component values, including typical tolerances, recommended in Table 10. Inductor values can have ±20% tolerance with no current bias. When the inductor current approaches saturation level, its inductance can decrease 20% to 35% from the 0-A value depending on how the inductor vendor defines saturation. In a boost regulator, the inductor DC current can be calculated with Equation 1. V ´I IL(DC) = OUT OUT VIN ´ h where • • • • VOUT = boost output voltage IOUT = boost output current VIN = boost input voltage η = power conversion efficiency, use 90% for TPS61177A applications (1) The inductor current peak-to-peak ripple can be calculated with Equation 2. 1 DIL(P-P) = æ 1 1 ö + L´ç ÷ ´ FS V V V IN IN ø è OUT where • • • • • ΔIL(P-P) = inductor peak-to-peak ripple L = inductor value FS = Switching frequency VOUT = boost output voltage VIN = boost input voltage (2) Therefore, the peak current seen by the inductor is calculated with Equation 3. DIL(P - P) IL(P) = IL(DC) + 2 (3) Select an inductor with a saturation current over the calculated peak current. To calculate the worst-case inductor peak current, use the minimum input voltage, maximum output voltage, and maximum load current. Regulator efficiency is dependent on the resistance of its high current path and switching losses associated with the power FET switch and power diode. Although the TPS61177A device has optimized the internal switch resistances, the overall efficiency is affected by the inductor DC resistance (DCR). Lower DCR improves efficiency. However, there is a trade off between DCR and inductor footprint; furthermore, shielded inductors typically have higher DCR than unshielded ones. Table 10 lists the recommended inductors. Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated Product Folder Links: TPS61177A 29 TPS61177A SNVSA76B – MARCH 2015 – REVISED MARCH 2017 www.ti.com Table 10. Recommended Inductor L (µH) DCR (mΩ) ISAT (A) Size (L × W × H mm) 10 140 3 5.4 × 5.2 × 1.6 10 335 1.45 6 × 6 × 1.2 Cyntec PCMB051H-100MS Taiyo NRA6012T 100ME 8.2.2.2 Output Capacitor Selection The output capacitor is mainly selected to meet the requirement for output ripple and loop stability. This ripple voltage is related to the capacitance of the capacitor and its equivalent series resistance (ESR). Assuming a capacitor with zero ESR, the minimum capacitance needed for a given ripple can be calculated with Equation 4: (VOUT - VIN )´ IOUT COUT = VOUT ´ FS ´ Vripple where • Vripple = peak-to-peak output ripple. (4) The additional part of the ripple caused by ESR is calculated using: Vripple_ESR = IOUT × RESR Due to its low ESR, Vripple_ESR can be neglected for ceramic capacitors, but must be considered if tantalum or electrolytic capacitors are used. The controller output voltage also ripples due to the load transient that occurs during PWM dimming. The TPS61177A adopts a patented technology to limit this type of output ripple even with the minimum recommended output capacitance. In a typical application, the output ripple is less than 250 mV during PWM dimming with a 4.7-µF output capacitor. However, the output ripple decreases with higher output capacitances. 8.2.3 Application Curves VLED Voltage 10V/div VLED Voltage 10V/div PWMB Voltage 3V/div PWMB Voltage 3V/div CS1 Voltage 4V/div CS1 Voltage 4V/div Inductor Current 500mA/div Inductor Current 500mA/div Time (20 ms/div) Time (5 ms/div) Figure 37. Start-Up Waveform Figure 38. Start-Up Waveform 9 Power Supply Recommendations The power supply for applications using the TPS61177A device must be big enough considering output power and efficiency at a given input voltage condition. Minimum current requirement condition is (VOUT × IOUT)/(VIN × efficiency), and TI recommends a minimum current that is approximately 20% to 30% higher than this value. 30 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated Product Folder Links: TPS61177A TPS61177A www.ti.com SNVSA76B – MARCH 2015 – REVISED MARCH 2017 10 Layout 10.1 Layout Guidelines As for all switching power supplies, especially those providing high current and using high switching frequencies, layout is an important design step. If layout is not carefully done, the regulator could show instability as well as EMI problems. Therefore, use wide and short traces for high current paths. The input capacitor, C1 in the Typical Application , must not only to be close to the VIN pin, but also to the GND pin in order to reduce the input ripple seen by the device. The input capacitor, C4 in the Typical Application , must also be placed close to the inductor. C5 is the reference capacitor for the internal integration circuit. It must be placed as close between the REF and AGND pins as possible to prevent any noise insertion to the digital circuits. The LX pin carries high current with fast rising and falling edges. Therefore, the connection between the pin to the inductor and Schottky diode must be kept as short and wide as possible. It is also beneficial to have the ground of the output capacitor C2 close to the PGND pin because there is a large ground return current flowing between them. When laying out signal grounds, TI recommends using short traces separated from power ground traces, and connecting them together at a single point, for example on the DAP. The DAP must be soldered on to the PCB and connected to the GND pin of the device. An additional thermal via can significantly improve power dissipation of the device. 10.2 Layout Example VIN PGND VOUT ENB PWMB SDA SCL AGND 20 19 18 17 16 15 1 14 2 13 3 PGND 12 4 11 5 6 7 8 9 10 PGND CS1 CS2 CS3 AGND CS4 CS5 CS6 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated Product Folder Links: TPS61177A 31 TPS61177A SNVSA76B – MARCH 2015 – REVISED MARCH 2017 www.ti.com 11 Device and Documentation Support 11.1 Device Support 11.1.1 Third-Party Products Disclaimer TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE. 11.2 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 11.3 Trademarks E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. 11.4 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 11.5 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 32 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated Product Folder Links: TPS61177A PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) TPS61177ARGRR ACTIVE VQFN RGR 20 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 77AS (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of