Product
Folder
Sample &
Buy
Support &
Community
Tools &
Software
Technical
Documents
TPS62590-Q1
SLVSAO5B – DECEMBER 2010 – REVISED OCTOBER 2015
TPS62590-Q1 Automotive 2.25-MHz 1-A Step-Down Converter In 2-mm × 2-mm SON
Package
1 Features
3 Description
•
•
•
•
•
•
•
•
•
The TPS62590-Q1 device is a high-efficiency
synchronous step-down converter, optimized for
space constrained applications and very low
quiescent current requirements. It provides up to
1000-mA output current from preregulated low
voltage rails and consumes 15 uA (typical) in powersave mode.
1
Qualified for Automotive Applications
Output Current up to 1000 mA
Input Voltage Range from 2.5 V to 6 V
High Efficiency Step Down Converter
Output Voltage Accuracy in PWM mode ±2.5%
Typical 15-μA Quiescent Current
2.25 MHz Fixed Frequency Operation
Power Save Mode at Light Load Currents
100% Duty Cycle for Lowest Dropout
2 Applications
•
•
Automotive Infotainment and Cluster
– Head Unit
– Navigation
– Display
Advanced Driver Assistance System (ADAS)
– Front Cameras
– Blind Spot Monitoring
– Lane Departure Warning
– Park Assist
With an input voltage range of 2.5 V to 6 V and an
output voltage accuracy of 2.5%, the device is
targeted to power a large variety of automotive
applications.
The TPS62590-Q1 family operates at a 2.25-MHz
fixed switching frequency and enters a power-save
mode at light load currents to maintain a high
efficiency over the entire load current range.
The power-save mode is optimized for low outputvoltage ripple. For low-noise applications, the device
can be forced into fixed-frequency PWM mode by
pulling the MODE pin high. In the shutdown mode,
the current consumption is reduced to less than 1 µA.
The TPS62590-Q1 allows the use of small inductors
and capacitors to achieve a small solution size.
The TPS62590-Q1 is available in a 2-mm × 2-mm
6-pin SON package with a thermal pad for improved
thermal performance.
Device Information(1)
PART NUMBER
TPS62590-Q1
PACKAGE
SON (6)
BODY SIZE (NOM)
2.00 mm × 2.00
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Typical Application Schematic
100
VOUT
0.75 V to VIN
2.5 V to 6 V
4
CIN
10m F
2
EN
R1
FB 3
90
C1
VI = 5 V
80
22 pF
MODE
GND 6
R2
PwrPAD
Thermal
Pad
Efficiency vs Load Current
L
2.2 mH
COUT
10 mF
Efficiency - %
TPS62590DRV
5 VIN
SW 1
VIN
VI = 4.2 V
70
60
VI = 3.8 V
50
40
30
VOUT = 3.3 V,
MODE = GND,
20
10
0
0.0001
0.001
0.01
0.1
IO - Output Current - A
1
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS62590-Q1
SLVSAO5B – DECEMBER 2010 – REVISED OCTOBER 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
4
4
4
4
5
6
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics ..........................................
Typical Characteristics ..............................................
Parameter Measurement Information ................ 10
Detailed Description ............................................ 11
8.1 Overview ................................................................. 11
8.2 Functional Block Diagram ....................................... 11
8.3 Feature Description................................................. 11
8.4 Device Functional Modes........................................ 13
9
Application and Implementation ........................ 14
9.1 Application Information............................................ 14
9.2 Typical Application .................................................. 14
10 Power Supply Recommendations ..................... 18
11 Layout................................................................... 19
11.1 Layout Guidelines ................................................. 19
11.2 Layout Example .................................................... 19
12 Device and Documentation Support ................. 20
12.1
12.2
12.3
12.4
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
20
20
20
20
13 Mechanical, Packaging, and Orderable
Information ........................................................... 20
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (April 2012) to Revision B
Page
•
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section ................................................................................................. 1
•
Added additional features ...................................................................................................................................................... 1
•
Added 2.25 MHz in the title ................................................................................................................................................... 1
•
Deleted " Available in a 2-mm × 2-mm × 0,8-mm SON Package" and "For Improved Features Set, See TPS62290"
from the Features section....................................................................................................................................................... 1
•
Changed first two paragraphs of the Description section....................................................................................................... 1
•
Added Effective inductance, Effective output capacitance, and Feed-forward capacitance parameters in
Recommended Operating Conditions. .................................................................................................................................. 4
•
Updated values in Thermal Information ................................................................................................................................ 4
•
Added External Feed-Forward Capacitor section................................................................................................................. 15
•
Updated paragraph in Output Filter Design (Inductor and Output Capacitor) section ......................................................... 15
2
Submit Documentation Feedback
Copyright © 2010–2015, Texas Instruments Incorporated
Product Folder Links: TPS62590-Q1
TPS62590-Q1
www.ti.com
SLVSAO5B – DECEMBER 2010 – REVISED OCTOBER 2015
5 Pin Configuration and Functions
DRV Package
6-Pin SON With Exposed Thermal pad
Top View
SW
1
MODE
2
FB
3
Thermal Pad
6
GND
5
VIN
4
EN
Pin Functions
PIN
NO.
NAME
I/O
DESCRIPTION
1
SW
O
This is the switch pin and is connected to the internal MOSFET switches. Connect the external inductor
between this terminal and the output capacitor.
2
MODE
I
MODE pin = high forces the device to operate in fixed-frequency PWM mode. Mode pin = low enables the
power-save mode with automatic transition from PFM mode to fixed-frequency PWM mode.
3
FB
I
Feedback pin for the internal regulation loop. Connect the external resistor divider to this pin. In case of
fixed output-voltage option, connect this pin directly to the output capacitor.
4
EN
I
This is the enable pin of the device. Pulling this pin to low forces the device into shutdown mode. Pulling
this pin to high enables the device. This pin must be terminated.
5
VIN
PWR
VIN power supply pin
6
GND
GND
GND supply pin
—
Thermal
pad
—
Must be soldered to achieve appropriate power dissipation. Should be connected to GND.
Submit Documentation Feedback
Copyright © 2010–2015, Texas Instruments Incorporated
Product Folder Links: TPS62590-Q1
3
TPS62590-Q1
SLVSAO5B – DECEMBER 2010 – REVISED OCTOBER 2015
www.ti.com
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
VI
MIN
MAX
UNIT
Input voltage (2)
–0.3
7
V
Voltage range at EN, MODE
–0.3
VIN +0.3, ≤ 7
V
Voltage on SW
–0.3
7
V
Peak output current
Internally limited
A
TJ
Maximum operating junction temperature
–40
125
°C
Tstg
Storage temperature
–65
150
°C
(1)
(2)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to network ground terminal.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
Electrostatic discharge
Human-body model (HBM), per AEC Q100-002 (1)
±2000
Charged-device model (CDM), per AEC Q100-011
±1000
UNIT
V
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
MIN
VIN
Supply voltage
NOM
MAX
UNIT
2.5
6
V
Output voltage range for adjustable voltage
0.75
VIN
V
TA
Operating ambient temperature
–40
105
°C
TJ
Operating junction temperature
–40
125
°C
LOUT
Effective inductance
1.5
4.7
µH
COUT Effective output-capacitance
4.7
22
µF
Cf
Feed-forward capacitance
22
33
pF
CIN
Effective input-capacitance
10
µF
6.4 Thermal Information
TPS62590-Q1
THERMAL METRIC (1) (2)
DRV (SON)
UNIT
6 PINS
RθJA
Junction-to-ambient thermal resistance
67.8
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
88.5
°C/W
RθJB
Junction-to-board thermal resistance
37.2
°C/W
ψJT
Junction-to-top characterization parameter
2
°C/W
ψJB
Junction-to-board characterization parameter
37.6
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
7.9
°C/W
(1)
(2)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
Simulated values based on four layer FR4 board (2-oz, 1-oz, 1-oz, 2-oz copper) with size: 76 mm × 114 mm × 1.6 mm
Submit Documentation Feedback
Copyright © 2010–2015, Texas Instruments Incorporated
Product Folder Links: TPS62590-Q1
TPS62590-Q1
www.ti.com
SLVSAO5B – DECEMBER 2010 – REVISED OCTOBER 2015
6.5 Electrical Characteristics
Over full operating ambient temperature range, typical values are at TA = 25°C. Unless otherwise noted, specifications apply
for condition VIN = EN = 3.6 V. External components CIN = 10 μF 0603, COUT = 10 μF 0603, L = 2.2 μH; see Parameter
Measurement Information.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY
VI
Input voltage range
IO
Output current (1)
IQ
Operating quiescent current
ISD
Shutdown current
UVLO
Undervoltage lockout threshold
2.5
6
VIN 2.7 V to 6 V
V
1000
VIN 2.5 V to 2.7 V
mA
600
IO = 0 mA, PFM mode enabled
(MODE = GND) device not switching,
See (2)
15
μA
IO = 0 mA, switching with no load
(MODE = VIN) PWM mode,
VO = 1.8 V, VIN = 3 V
3.8
mA
0.5
μA
EN = GND
Falling
1.85
Rising
1.95
V
ENABLE, MODE
VIH
High-level input voltage, EN,
MODE
2.5 V ≤ VIN ≤ 6 V
1
VIN
V
VIL
Low-level input voltage, EN,
MODE
2.5 V ≤ VIN ≤ 6 V
0
0.4
V
II
Input bias current, EN, MODE
EN, MODE = GND or VIN
1
μA
0.01
POWER SWITCH
rDS(on)
ILIMF
TSD
High-side MOSFET on-resistance
Low-side MOSFET on-resistance
250
VIN = VGS = 3.6 V, TA = 25°C
mΩ
190
Forward current limit MOSFET
high-side and low-side
VIN = VGS = 3.6 V, TA = 25°C
Thermal shutdown
Increasing junction temperature
140
Thermal shutdown hysteresis
Decreasing junction temperature
20
1.19
1.4
1.78
A
°C
OSCILLATOR
fSW
Oscillator frequency
2.5 V ≤ VIN ≤ 6 V
2.25
MHz
OUTPUT
VO
Adjustable output voltage range
Vref
Reference voltage
0.75
VI
600
VFB(PWM)
Feedback voltage
MODE = VIN, PWM mode,
2.5 V ≤ VIN ≤ 6 V, See (3)
VFB(PFM)
Feedback voltage, PFM mode
MODE = GND, device in PFM mode,
1% voltage positioning active, See (2)
Load regulation
–2.5%
0%
2.5%
–1
tStart Up
Start-up time
tRamp
VO ramp-up time
Time to ramp from 5% to 95% of VO
250
Leakage current into SW pin
VI = 3.6 V, VI = VO = VSW, EN = GND,
See (4)
0.1
(1)
(2)
(3)
(4)
mV
1%
Time from active EN to reach 95% of
VO
Ilkg
V
500
%/A
μs
μs
1
μA
Not production tested.
In PFM mode, the internal reference voltage is set to typ. 1.01 × Vref . See Parameter Measurement Information.
For VIN = VO + 1 V
In fixed output-voltage versions, the internal resistor divider network is disconnected from the FB pin.
Submit Documentation Feedback
Copyright © 2010–2015, Texas Instruments Incorporated
Product Folder Links: TPS62590-Q1
5
TPS62590-Q1
SLVSAO5B – DECEMBER 2010 – REVISED OCTOBER 2015
www.ti.com
6.6 Typical Characteristics
Table 1. Table Of Graphs
FIGURE
vs Output Current VOUT = 1.8 V (Power-Save Mode)
Figure 1
vs Output Current VOUT = 1.8 V (Forced PWM Mode)
Figure 2
vs Output Current VOUT = 3.3 V (Power-Save Mode)
Figure 3
vs Output Current VOUT = 3.3 V (Forced PWM Mode)
Figure 4
vs Output Current VOUT = 1.8 V (Forced PWM Mode)
Figure 5
vs Output Current VOUT = 1.8 V (Power-Save Mode)
Figure 6
vs Output Current VOUT = 3.3 V (Forced PWM Mode)
Figure 7
vs Output Current VOUT = 3.3 V (Power-Save Mode)
Figure 8
PFM to PWM to PFM Load Transient
Figure 9
PWM Load Transient
Figure 10
PFM Line Transient
Figure 11
PWM Line Transient
Figure 12
Typical Performance – PFM Mode
Figure 13
Typical Performance – PWM Mode
Figure 14
Shutdown Current
into VIN vs. Input Voltage
Figure 15
Quiescent Current
vs Input Voltage
Figure 16
Static Drain-Source On-State
Resistance
vs Input Voltage
Efficiency
Output Voltage
Transient Behavior
6
Figure 17
Figure 18
Submit Documentation Feedback
Copyright © 2010–2015, Texas Instruments Incorporated
Product Folder Links: TPS62590-Q1
TPS62590-Q1
www.ti.com
SLVSAO5B – DECEMBER 2010 – REVISED OCTOBER 2015
100
100
VI = 2.7 V
90
90
VI = 3.6 V
80
VI = 3.3 V
70
Efficiency - %
70
Efficiency - %
80
VI = 4.5 V
VI = 5 V
60
50
40
30
10
0
0.0001
0.001
0.01
IO - Output Current - A
0.1
VI = 5 V
50
VI = 4.5 V
40
30
VOUT = 1.8 V,
MODE = GND,
L = 2.2 mH
20
VI = 2.7 V
60
VOUT = 1.8 V,
MODE = VIN,
L = 2.2 mH
20
10
0
0.001
1
0.01
0.1
IO - Output Current - A
Figure 1. Efficiency vs Output Current for
VOUT = 1.8 V (Power-Save Mode)
Figure 2. Efficiency vs Output Current
for VOUT = 1.8 V (Forced PWM Mode)
100
100
VI = 5 V
80
80
VI = 4.2 V
70
VI = 3.8 V
60
50
40
30
10
0
0.0001
0.001
VI = 5 V
0.01
IO - Output Current - A
0.1
60
VI = 4.5 V
50
40
VOUT = 3.3 V,
MODE = VIN,
L = 2.2 mH
30
VOUT = 3.3 V,
MODE = GND,
L = 2.2 mH
20
VI = 3.8 V
70
Efficiency - %
Efficiency - %
VI = 4.2 V
90
90
20
10
0
0.001
1
0.01
0.1
IO - Output Current - A
1
Figure 4. Efficiency vs Output Current
for VOUT = 3.3 V (Forced PWM Mode)
Figure 3. Efficiency vs Output Current
for VOUT = 3.3 V (Power-Save Mode)
1.9
1.85
VO = 1.8 V,
MODE = GND
VO = 1.8 V,
MODE = VI
1.88
1.81
VO - Output Voltage - V
1.83
VO - Output Voltage - V
1
VI = 2.7 V, TA = 25°C
1.79
VI = 4.5 V, TA = 25°C
VI = 3.6 V, TA = 25°C
1.77
1.86
PFM Mode, Voltage Positioning On
PWM Mode
1.84
1.82
VI = 4.5 V, TA = 25°C
VI = 3.6 V, TA = 25°C
1.8
VI = 2.7 V, TA = 25°C
1.75
0.00001
0.0001
0.001
0.01
IO - Output Current - A
0.1
1
Figure 5. Output Voltage vs Output Current
vs Input Voltage for VOUT = 1.8 V (Power Saver Mode)
1.78
0.00001
0.0001
0.001
0.01
IO - Output Current - A
0.1
1
Figure 6. Output Voltage vs Output Current
vs Input Voltage for VOUT = 1.8 V (Forced PWM Mode)
Submit Documentation Feedback
Copyright © 2010–2015, Texas Instruments Incorporated
Product Folder Links: TPS62590-Q1
7
TPS62590-Q1
SLVSAO5B – DECEMBER 2010 – REVISED OCTOBER 2015
www.ti.com
3.4
3.35
VO = 3.3 V,
MODE = GND
VO = 3.3 V,
MODE = VI
VO - Output Voltage - V
VO - Output Voltage - V
VI = 4.5 V, TA = 25°C
3.36
3.33
VI = 4.5 V, TA = 25°C
3.31
VI = 4.2 V, TA = 25°C
VI = 3.7 V, TA = 25°C
3.29
VI = 5 V, TA = 25°C
VI = 4.2 V, TA = 25°C
3.32
PFM Mode, Voltage Positioning On
PWM Mode
3.28
3.24
3.27
3.25
0.00001
0.0001
0.001
0.01
IO - Output Current - A
0.1
1
Figure 7. Output Voltage vs Output Current
vs Input Voltage for VOUT = 3.3 V (Forced PWM Mode)
SW 2V/Div
3.2
0.00001
0.0001
0.001
0.01
IO - Output Current - A
0.1
1
Figure 8. Output Voltage vs Output Current
vs Input Voltage for VOUT = 3.3 V (Power Saver Mode)
VIN 3.6 V,
VOUT 1.8 V,
IOUT 300 mA to 800 mA,
MODE = GND VOUT 100 mV/Div
VOUT 50 mV/Div
IOUT 500 mA/Div
VIN 3.6 V,
VOUT 1.8 V,
IOUT 50 mA to 250 mA,
250 mA
MODE = GND
800 mA
300 mA
IOUT 200 mA/Div
50 mA
Icoil 500 mA/Div
Icoil 500 mA/Div
Time Base - 20 ms/Div
Time Base - 20 ms/Div
Figure 10. PWM Load Transient
Figure 9. PFM to PWM to PFM Load Transient
VIN 3.6 V to 4.2 V
500 mV/Div
VIN 3.6 V to 4.2 V,
500 mV/Div
VOUT = 1.8 V,
50 mV/Div,
IOUT = 50 mA,
MODE = GND
VOUT = 1.8 V,
50 mV/Div,
IOUT = 250 mA,
MODE = GND
Time Base - 100 ms/Div
Time Base - 100 ms/Div
Figure 11. PFM Line Transient
8
Submit Documentation Feedback
Figure 12. PWM Line Transient
Copyright © 2010–2015, Texas Instruments Incorporated
Product Folder Links: TPS62590-Q1
TPS62590-Q1
www.ti.com
SLVSAO5B – DECEMBER 2010 – REVISED OCTOBER 2015
VIN 3.6 V,
VOUT 1.8 V, IOUT 150 mA,
VOUT 20 mV/Div
VOUT 10 mV/Div
L 2.2 mH, COUT 10 mF 0603
VIN 3.6 V,
VOUT 1.8 V, IOUT 10 mA,
SW 2 V/Div
L 2.2 mH, COUT 10 mF 0603
SW 2 V/Div
Icoil 200 mA/Div
Icoil 200 mA/Div
Time Base - 10 ms/Div
Time Base - 10 ms/Div
Figure 13. Typical Performance – PFM Mode
Figure 14. Typical Performance – PWM Mode
0.8
20
0.7
18
0.6
IQ – Quiescent Current – mA
ISD - Shutdown Current Into VIN − mA
EN = GND
o
TA = 85 C
0.5
0.4
0.3
0.2
o
TA = -40oC
TA = 25 C
MODE = GND,
EN = VIN,
Device Not Switching
o
TA = 85 C
16
o
TA = 25 C
14
12
o
TA = -40 C
10
0.1
0
2.5
3
3.5
4
4.5
5
8
2.5
5.5
3
3.5
4.5
4
5
5.5
Figure 15. Shutdown Current Into VIN vs Input Voltage
Figure 16. Quiescent Current vs Input Voltage
0.8
High Side Switching
0.7
0.6
o
TA = 85 C
0.5
o
TA = 25 C
0.4
0.3
0.2
0.1
0
2.5
o
TA = -40 C
3
3.5
4
4.5
5
VIN − Input Voltage − V
Figure 17. Static Drain-Source On-State Resistance vs Input
Voltage
RDS(on) - Static Drain-Source On-State Resistance − W
VIN − Input Voltage − V
RDS(on) - Static Drain-Source On-State Resistance − W
VIN − Input Voltage − V
0.4
Low Side Switching
0.35
0.3
o
TA = 85 C
0.25
o
TA = 25 C
0.2
0.15
0.1
o
0.05
0
2.5
TA = -40 C
3
3.5
4
4.5
5
VIN − Input Voltage − V
Figure 18. Static Drain-Source On-State Resistance vs Input
Voltage
Submit Documentation Feedback
Copyright © 2010–2015, Texas Instruments Incorporated
Product Folder Links: TPS62590-Q1
9
TPS62590-Q1
SLVSAO5B – DECEMBER 2010 – REVISED OCTOBER 2015
www.ti.com
7 Parameter Measurement Information
L
2.2 mH
TPS62590DRV
5
VIN
4
CIN
10 mF
2
VIN
SW
R1
EN
MODE
VOUT
1
FB
3
GND
6
C1
22 pF
R2
COUT
10 mF
Thermal Pad
10
Submit Documentation Feedback
Copyright © 2010–2015, Texas Instruments Incorporated
Product Folder Links: TPS62590-Q1
TPS62590-Q1
www.ti.com
SLVSAO5B – DECEMBER 2010 – REVISED OCTOBER 2015
8 Detailed Description
8.1 Overview
The TPS62590-Q1 step-down converter operates with typically 2.25-MHz fixed-frequency pulse-width modulation
(PWM) at moderate to heavy load currents. At light load currents, the converter can automatically enter powersave mode and operates then in PFM mode.
During PWM mode, the converter uses a unique fast-response voltage-mode controller scheme with inputvoltage feed-forward to achieve good line and load regulation, allowing the use of small ceramic input and output
capacitors. At the beginning of each clock cycle initiated by the clock signal, the high-side MOSFET switch is
turned on. The current flows now from the input capacitor via the high-side MOSFET switch through the inductor
to the output capacitor and load. During this phase, the current ramps up until the PWM comparator trips and the
control logic turns off the switch. The current-limit comparator also turns off the switch if the current limit of the
high-side MOSFET switch is exceeded. After a dead time preventing shoot-through current, the low-side
MOSFET rectifier is turned on and the inductor current ramps down. The current flows now from the inductor to
the output capacitor and to the load. It returns to the inductor through the low-side MOSFET rectifier.
The next cycle is initiated by the clock signal again turning off the low-side MOSFET rectifier and turning on the
high-side MOSFET switch.
8.2 Functional Block Diagram
VIN
EN
Thermal
Shutdown
Current
Limit Comparator
Softstart
VOUT RAMP
CONTROL
VIN
High Side
Reference
0.6 V VREF
PFM Comp
FB
VREF
MODE
Undervoltage
Lockout 1.8 V
MODE
Error Amp
Control
Stage
Gate Driver
Anti
Shoot-Through
SW
VREF
Integrator
FB
Zero-Pole
AMP.
PWM
Comp .
GND
Low Side
Sawtooth
Generator
2.25 MHz
Oscillator
Current
Limit Comparator
GND
8.3 Feature Description
8.3.1 Enable
The device is enabled setting EN pin to high. During start-up time tStart Up, the internal circuits are settled.
Afterwards, the device activates the soft-start circuit. The EN input can be used to control power sequencing in a
system with various dc/dc converters. The EN pin can be connected to the output of another converter, to drive
the EN pin high and get a sequencing of supply rails. With EN = GND, the device enters shutdown mode. In this
mode, all circuits are disabled. In fixed-output-voltage versions, the internal resistor divider network is
disconnected from the FB pin.
Submit Documentation Feedback
Copyright © 2010–2015, Texas Instruments Incorporated
Product Folder Links: TPS62590-Q1
11
TPS62590-Q1
SLVSAO5B – DECEMBER 2010 – REVISED OCTOBER 2015
www.ti.com
Feature Description (continued)
8.3.2 Mode Selection
The MODE pin allows mode selection between forced PWM mode and power-save mode.
Connecting this pin to GND enables the power-save mode with automatic transition between PWM and PFM
modes. Pulling the MODE pin high forces the converter to operate in fixed-frequency PWM mode even at light
load currents. This allows simple filtering of the switching frequency for noise-sensitive applications. In this mode,
the efficiency is lower compared to the power-save mode during light loads.
The condition of the MODE pin can be changed during operation and allows efficient power management by
adjusting the operation mode of the converter to the specific system requirements.
8.3.3 Soft Start
The TPS62590-Q1 has an internal soft-start circuit that controls the ramp-up of the output voltage. The output
voltage ramps up from 5% to 95% of its nominal value within typically 250 μs. This limits the inrush current in the
converter during ramp-up and prevents possible input voltage drops when a battery or high-impedance power
source is used. The soft-start circuit is enabled within start-up time tStart Up.
8.3.4 Short-Circuit Protection
The high-side and low-side MOSFET switches are short-circuit protected with maximum switch current = ILIMF.
The current in the switches is monitored by current-limit comparators. Once the current in the high-side MOSFET
switch exceeds the threshold of its current-limit comparator, it turns off and the low-side MOSFET switch is
activated to ramp down the current in the inductor and high-side MOSFET switch. The high-side MOSFET switch
can only turn on again once the current in the low-side MOSFET switch has decreased below the threshold of its
current-limit comparator.
8.3.5 100% Duty-Cycle Low-Dropout Mode
The device starts to enter 100% duty-cycle mode once the input voltage comes close the nominal output voltage.
To maintain the output voltage, the high-side MOSFET switch is turned on 100% for one or more cycles.
With further decreasing VIN, the high-side MOSFET switch is turned on completely. In this case, the converter
offers a low input-to-output voltage difference. This is particularly useful in battery-powered applications to
achieve longest operation time by taking full advantage of the whole battery voltage range.
The minimum input voltage to maintain regulation depends on the load current and output voltage, and can be
calculated as:
VINmin = VOmax + IOmax × (rDS(on)max + RL)
with
•
•
•
•
VOmax = nominal output voltage plus maximum output-voltage tolerance
IOmax = maximum output current plus inductor ripple current
rDS(on)max = maximum P-channel switch rDS(on)
RL = DC-resistance of the inductor
(1)
8.3.6 Undervoltage Lockout
The undervoltage lockout circuit prevents the device from malfunctioning at low input voltages and from
excessive discharge of the battery and disables the output stage of the converter. The undervoltage lockout
threshold is typically 1.85 V with falling VIN.
8.3.7 Thermal Shutdown
As soon as the junction temperature TJ exceeds 140°C (typical) the device goes into thermal shutdown. In this
mode, the high-side and low-side MOSFETs are turned off. The device continues its operation when the junction
temperature falls below the thermal shutdown hysteresis.
12
Submit Documentation Feedback
Copyright © 2010–2015, Texas Instruments Incorporated
Product Folder Links: TPS62590-Q1
TPS62590-Q1
www.ti.com
SLVSAO5B – DECEMBER 2010 – REVISED OCTOBER 2015
8.4 Device Functional Modes
8.4.1 Power-Save Mode
The power-save mode is enabled with the MODE pin set to low level. If the load current decreases, the converter
enters power-save mode automatically. During power-save mode, the converter skips switching and operates
with reduced frequency in PFM mode with a minimum quiescent current to maintain high efficiency. The
converter positions the output voltage 1% above the nominal output voltage typically. This voltage positioning
feature minimizes voltage drops caused by a sudden load step.
The transition from PWM mode to PFM mode occurs once the inductor current in the low-side MOSFET switch
becomes zero, which indicates discontinuous-conduction mode.
During the power-save mode, the output voltage is monitored with a PFM comparator. As the output voltage falls
below the PFM comparator threshold of VOUT nominal + 1%, the device starts a PFM current pulse. For this, the
high-side MOSFET switch turns on and the inductor current ramps up. After the on-time expires, the switch is
turned off and the low-side MOSFET switch is turned on until the inductor current becomes zero.
The converter effectively delivers a current to the output capacitor and the load. If the load is below the delivered
current, the output voltage rises. If the output voltage is equal to or higher than the PFM comparator threshold,
the device stops switching and enters a sleep mode with typical 15-μA current consumption.
If the output voltage is still below the PFM comparator threshold, a sequence of further PFM current pulses is
generated until the PFM comparator threshold is reached. The converter starts switching again once the output
voltage drops below the PFM comparator threshold.
With a fast single-threshold comparator, the output voltage ripple during PFM mode can be kept small. The PFM
pulse is time-controlled, which allows modifying the charge transferred to the output capacitor by the value of the
inductor. The resulting PFM output voltage ripple and PFM frequency depend in first order on the size of the
output capacitor and the inductor value. Increasing output capacitor values and inductor values minimizes the
output ripple. The PFM frequency decreases with smaller inductor values and increases with larger values.
The PFM mode is left and PWM mode entered in case the output current can no longer be supported in PFM
mode. The power-save mode can be disabled by setting the MODE pin to high. The converter then operates in
fixed-frequency PWM mode.
8.4.2 Dynamic Voltage Positioning
This feature reduces the voltage under- and overshoots at load steps from light to heavy load and vice versa. It
is active in power-save mode and regulates the output voltage 1% higher than the nominal value. This provides
more headroom for both the voltage drop at a load step, and the voltage increase at a load throw-off.
Output voltage
Voltage Positioning
Vout +1%
PFM Comparator
threshold
Light load
PFM Mode
Vout (PWM)
moderate to heavy load
PWM Mode
Figure 19. Operation In Power-Save Mode
Submit Documentation Feedback
Copyright © 2010–2015, Texas Instruments Incorporated
Product Folder Links: TPS62590-Q1
13
TPS62590-Q1
SLVSAO5B – DECEMBER 2010 – REVISED OCTOBER 2015
www.ti.com
9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The TPS62590-Q1 device is a highly efficient, synchronous step-down, DC-DC converter with an adjustable
output voltage and an output current of up to 1 A. The device can be used in buck converter applications with an
input range from 2.5 V to 6 V. The TPS62590-Q1 device is optimized for space constrained applications and
consumes 15-µA current (typ) in power-save mode.
9.2 Typical Application
L
2.2 mH
TPS62590DRV
5
VIN
2.5 V to 6 V
4
CIN
10 mF
2
VIN
SW
R1
EN
MODE
VOUT = 1.8 V
Up to 1 A
1
FB
3
GND
6
C1
360 kΩ
22 pF
COUT
R2
180 kΩ
Thermal Pad
10 mF
Figure 20. TPS62590-Q1DRV Adjustable 1.8 V
L
2.2 mH
TPS62590DRV
VIN
3.7 V to 6 V
5
4
CIN
10 mF
2
VIN
SW
R1
EN
MODE
VOUT = 3.3 V
IOUT,max = 1 A
1
FB
3
GND
6
C1
820 kΩ
22 pF
R2
182 kΩ
COUT
10 mF
Thermal Pad
Figure 21. TPS62590-Q1DRV Adjustable 3.3 V
9.2.1 Design Requirements
The input voltage for this device must be from 2.5 V to 6 V. The output voltage must be set using an external
voltage divider. The internal compensation network of the device is optimized for an LC output filter that is
composed of a 2.2-μH inductor and a 10-μF ceramic capacitor with a external feed-forward capacitor of 22 pF.
The Recommended Operating Conditions table specifies the allowed range for input voltages, output voltages,
output current, output inductor and output buffer capacitor. The values listed in this table must be followed when
designing the regulator. Low-ESR ceramic capacitors should be used at the input and output for better filtering
and ripple performance. The Detailed Design Procedure section provides the necessary equations and
guidelines for selecting external components for this regulator.
14
Submit Documentation Feedback
Copyright © 2010–2015, Texas Instruments Incorporated
Product Folder Links: TPS62590-Q1
TPS62590-Q1
www.ti.com
SLVSAO5B – DECEMBER 2010 – REVISED OCTOBER 2015
Typical Application (continued)
9.2.2 Detailed Design Procedure
Table 2 lists the recommended components for the circuit shown in Parameter Measurement Information.
Table 2. List of Components
COMPONENT REFERENCE
PART NUMBER
MANUFACTURER
VALUE
CIN
GRM188R60J106M
Murata
10-μF, 6.3-V. X5R ceramic
COUT
GRM188R60J106M
Murata
10-μF, 6.3-V. X5R ceramic
Murata
22-pF, ceramic
Coilcraft
2.2 μH, 110 mΩ
C1
L1
LPS3015
R1, R2
Values depending on the programmed output voltage
9.2.2.1 Output Voltage Setting
The output voltage can be calculated to:
æ
R1ö÷
V OUT = VREF x çç1 +
÷
çè
R2 ø÷
where
•
internal reference voltage VREF = 0.6 V typically
(2)
To minimize the current through the feedback divider network, R2 should be 180 kΩ or 360 kΩ. The sum of R1
and R2 should not exceed approximately 1 MΩ, to keep the network robust against noise.
9.2.2.2 External Feed-Forward Capacitor
An external feedforward capacitor C1 is required for optimum load-transient response. The value of C1 should be
in the range between 22 pF and 33 pF.
9.2.2.3 Output Filter Design (Inductor and Output Capacitor)
The Recommended Operating Conditions table lists the allowed range of inductor and capacitor. For stable
operation, L and C values of the output filter should not fall below 1-µH effective inductance and 3.5-µF effective
capacitance.
9.2.2.3.1 Inductor Selection
The inductor value has a direct effect on the ripple current. The selected inductor must be rated for its DC
resistance and saturation current. The inductor ripple current (ΔIL) decreases with higher inductance and
increases with higher VI or VO.
The inductor selection also impacts the output-voltage ripple in PFM mode. Higher inductor values lead to lower
output-voltage ripple and higher PFM frequency; lower inductor values lead to a higher output-voltage ripple but
lower PFM frequency.
Submit Documentation Feedback
Copyright © 2010–2015, Texas Instruments Incorporated
Product Folder Links: TPS62590-Q1
15
TPS62590-Q1
SLVSAO5B – DECEMBER 2010 – REVISED OCTOBER 2015
www.ti.com
Equation 3 calculates the maximum inductor current under static load conditions. The saturation current of the
inductor should be rated higher than the maximum inductor current as calculated with Equation 4. This is
recommended because during heavy load transients the inductor current rises above the calculated value.
V
1 - OUT
VIN
DIL = VOUT ´
L´f
(3)
IL max = IOUT max +
DIL
2
where
•
•
•
•
f = Switching frequency (2.25 MHz, typical)
L = Inductor Value
ΔIL = Peak-to-peak inductor ripple current
ILmax = Maximum inductor current
(4)
A more conservative approach is to select the inductor current rating just for the maximum switch current of the
corresponding converter.
Accepting larger values of ripple current allows the use of low inductance values, but results in higher output
voltage ripple, greater core losses, and lower output-current capability.
The total losses of the coil have a strong impact on the efficiency of the dc/dc conversion and consist of both the
losses in the dc resistance (R(DC)) and the following frequency-dependent components:
• The losses in the core material (magnetic hysteresis loss, especially at high switching frequencies)
• Additional losses in the conductor from the skin effect (current displacement at high frequencies)
• Magnetic field losses of the neighboring windings (proximity effect)
• Radiation losses
9.2.2.3.2 Output Capacitor Selection
The advanced fast-response voltage-mode control scheme of the TPS62590-Q1 allows the use of tiny ceramic
capacitors. Ceramic capacitors with low ESR values have the lowest output-voltage ripple and are
recommended. The output capacitor requires either an X7R or X5R dielectric. Y5V and Z5U dielectric capacitors,
aside from their wide variation in capacitance over temperature, become resistive at high frequencies.
At nominal load current, the device operates in PWM mode, and the RMS ripple current is calculated as:
V
1 - OUT
VIN
1
IRMSC OUT = VOUT ´
´
L´f
2´ 3
(5)
The overall output voltage ripple under the same conditions is the sum of the voltage spike caused by the output
capacitor ESR plus the voltage ripple caused by charging and discharging the output capacitor:
V
1 - OUT
VIN
æ
ö
1
DVOUT = VOUT ´
´ç
+ ESR ÷
L´f
è 8 ´ Cout ´ f
ø
(6)
At light load currents, the converter operates in power-save mode, and the output-voltage ripple is dependent on
the output capacitor and inductor values. Larger output capacitor and inductor values minimize the voltage ripple
in PFM mode and tighten dc output accuracy in PFM mode.
16
Submit Documentation Feedback
Copyright © 2010–2015, Texas Instruments Incorporated
Product Folder Links: TPS62590-Q1
TPS62590-Q1
www.ti.com
SLVSAO5B – DECEMBER 2010 – REVISED OCTOBER 2015
9.2.2.3.3 Input Capacitor Selection
The buck converter has a natural pulsating input current; therefore, a low ESR input capacitor is required for best
input voltage filtering and minimizing the interference with other circuits caused by high input voltage spikes. For
most applications, a 10-μF ceramic capacitor is recommended. The input capacitor can be increased without any
limit for better input voltage filtering.
Take care when using only small ceramic input capacitors. When a ceramic capacitor is used at the input and the
power is being supplied through long wires, such as from a wall adapter, a load step at the output or VIN step on
the input can induce ringing at the VIN pin. The ringing can couple to the output and be mistaken as loop
instability or could even damage the part by exceeding the maximum ratings.
9.2.3 Application Curves
100
100
VI = 2.7 V
90
90
VI = 3.6 V
80
60
80
VI = 3.3 V
VI = 4.5 V
70
Efficiency - %
Efficiency - %
70
VI = 5 V
50
40
30
10
0
0.0001
0.001
0.01
IO - Output Current - A
0.1
VOUT = 1.8 V,
MODE = VIN,
L = 2.2 mH
0
0.001
1
0.01
0.1
IO - Output Current - A
1
Figure 23. Efficiency vs Output Current for VOUT = 1.8 V
(Forced PWM Mode)
100
VI = 4.2 V
90
90
VI = 5 V
80
80
VI = 4.2 V
VI = 3.8 V
60
50
40
30
10
0.001
0.01
IO - Output Current - A
0.1
VI = 5 V
60
VI = 4.5 V
50
40
30
VOUT = 3.3 V,
MODE = GND,
L = 2.2 mH
20
VI = 3.8 V
70
Efficiency - %
Efficiency - %
VI = 4.5 V
40
10
100
0
0.0001
50
20
Figure 22. Efficiency vs Output Current for VOUT = 1.8 V
(Power-Save Mode)
70
VI = 5 V
30
VOUT = 1.8 V,
MODE = GND,
L = 2.2 mH
20
VI = 2.7 V
60
20
VOUT = 3.3 V,
MODE = VIN,
L = 2.2 mH
10
1
Figure 24. Efficiency vs Output Current for VOUT = 3.3 V
(Power-Save Mode)
0
0.001
0.01
0.1
IO - Output Current - A
1
Figure 25. Efficiency vs Output Current for VOUT = 3.3 V
(Forced PWM Mode)
Submit Documentation Feedback
Copyright © 2010–2015, Texas Instruments Incorporated
Product Folder Links: TPS62590-Q1
17
TPS62590-Q1
SLVSAO5B – DECEMBER 2010 – REVISED OCTOBER 2015
SW 2V/Div
www.ti.com
VIN 3.6 V,
VOUT 1.8 V,
IOUT 300 mA to 800 mA,
MODE = GND VOUT 100 mV/Div
VOUT 50 mV/Div
IOUT 500 mA/Div
VIN 3.6 V,
VOUT 1.8 V,
IOUT 50 mA to 250 mA,
250 mA
MODE = GND
800 mA
300 mA
IOUT 200 mA/Div
50 mA
Icoil 500 mA/Div
Icoil 500 mA/Div
Time Base - 20 ms/Div
Time Base - 20 ms/Div
Figure 27. PWM Load Transient
Figure 26. PFM to PWM to PFM Load Transient
VIN 3.6 V to 4.2 V
500 mV/Div
VIN 3.6 V to 4.2 V,
500 mV/Div
VOUT = 1.8 V,
50 mV/Div,
IOUT = 50 mA,
MODE = GND
VOUT = 1.8 V,
50 mV/Div,
IOUT = 250 mA,
MODE = GND
Time Base - 100 ms/Div
Time Base - 100 ms/Div
Figure 28. PFM Line Transient
Figure 29. PWM Line Transient
10 Power Supply Recommendations
The TPS62590-Q1 device is designed to operate for an input voltage range from 2.5 V to 6 V. For the VIN pin, TI
recommends a low ESR ceramic capacitor with a typical value of 10 μF for most applications. Capacitance
derating for aging, temperature, and DC bias must be taken into account while determining the capacitor value.
18
Submit Documentation Feedback
Copyright © 2010–2015, Texas Instruments Incorporated
Product Folder Links: TPS62590-Q1
TPS62590-Q1
www.ti.com
SLVSAO5B – DECEMBER 2010 – REVISED OCTOBER 2015
11 Layout
11.1 Layout Guidelines
As for all switching power supplies, the layout is an important step in the design. Proper function of the device
demands careful attention to PCB layout. Care must be taken in board layout to get the specified performance. If
the layout is not carefully done, the regulator could show poor line and/or load regulation, stability issues, and
EMI problems.
The following list details some generic layout guidelines for the TPS62590-Q1 device:
• It is critical to provide a low-inductance, low-impedance ground path and hence use wide and short traces for
the main current paths.
• The input capacitor, output capacitor, and inductor should be placed as close as possible to the IC pins.
• Connect the GND pin of the device to the thermal pad of the PCB and use this pad as a star point.
• Use a common power GND node and a different node for the signal GND to minimize the effects of ground
noise. Connect these ground nodes together at the thermal pad (star point) underneath the IC.
• Keep the traces to the GND pin, coming from small-signal components and the high current of the output
capacitors, as short as possible to avoid ground noise.
• The output feedback line should be connected close to the output capacitor and routed away from noisy
components and traces (for example, the SW line).
• Trace to the FB pin from voltage divider resistors center point should be as short as possible and should be
away from noise sources, such as the inductor or the SW line.
• Add multiple thermal via's on the device thermal pad for better thermal performance.
11.2 Layout Example
Figure 30. Layout
Submit Documentation Feedback
Copyright © 2010–2015, Texas Instruments Incorporated
Product Folder Links: TPS62590-Q1
19
TPS62590-Q1
SLVSAO5B – DECEMBER 2010 – REVISED OCTOBER 2015
www.ti.com
12 Device and Documentation Support
12.1 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.2 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
20
Submit Documentation Feedback
Copyright © 2010–2015, Texas Instruments Incorporated
Product Folder Links: TPS62590-Q1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS62590TDRVRQ1
ACTIVE
WSON
DRV
6
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 105
QWT
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
工商网监
湘ICP备2023018690号
