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TPS62290-Q1, TPS62293-Q1
SLVSAI5B – SEPTEMBER 2010 – REVISED JUNE 2016
TPS6229x-Q1 1-A Step Down Converter in 2-mm × 2-mm SON Package
1 Features
3 Description
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The TPS6229x-Q1 is a highly efficient synchronous
step-down buck converter optimized for automotive
low input voltage applications, and provides up to
1000-mA output current..
Qualified for Automotive Applications
High Efficiency Step-Down Converter
Output Current up to 1000 mA
VIN Range From 2.3 V to 6 V
2.25-MHz Fixed Frequency Operation
Power Save Mode at Light Load Currents
Output Voltage Accuracy in PWM mode ±1.5%
Fixed Output Voltage Options
Typical 15-µA Quiescent Current
100% Duty Cycle for Lowest Dropout
Voltage Positioning at Light Loads
Available in a 2-mm × 2-mm × 0.8-mm SON
Package
2 Applications
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•
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Automotive Infotainment and Clusters
– Instrument Clusters
– Head Units and Displays
– Radios and Navigation
Advanced Driver Assistance System (ADAS)
– Front Cameras
– Blind Spot Monitoring
– Lane Departure Warning
– Park Assist
HEV/EV Onboard Charger
SPACE
Typical Application Schematic
V(VIN) 2.7 V to 6.0 V
TPS62290DRV
VIN
CIN
SW
R1
EN
360 kW
10 mF
VOUT 1.8 V,
1000 mA
L1
2.2 mH
C1
22 pF
With an input voltage range of 2.3 V to 6 V, and an
output voltage accuracy of 1.5%, the device powers a
large variety of automotive applications.
The TPS6229x-Q1 operates at 2.25-MHz fixed
switching frequency and enters Power Save Mode
operation with typical quiescent current of 15 µA at
light load currents to maintain a high efficiency over
the entire load current range.
The Power Save Mode is optimized for low output
voltage ripple. For low noise applications, the device
can be forced into fixed frequency PWM mode by
pulling the MODE pin high. In the shutdown mode,
the current consumption is reduced to less than 1 µA.
The TPS6229x-Q1 allows the use of small inductors
and capacitors to achieve a small solution size.
The TPS6229x-Q1 is available in a 2-mm × 2-mm
6-pin SON package.
Device Information(1)
PART NUMBER
TPS6229x-Q1
MODE
BODY SIZE (NOM)
2.00 mm × 2.00 mm
Efficiency vs Output Current
100
VIN = 4.2 V
COUT
90
VIN = 3.8 V
10 mF
FB
GND
PACKAGE
SON (6)
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
R2
180 kW
Copyright © 2016, Texas Instruments Incorporated
80
Efficiency - %
1
70
VIN = 5 V
VIN = 4.5 V
60
50
40
VOUT = 3.3 V,
MODE = GND,
L = 2.2 mH
30
0.00001 0.0001 0.001
0.01
0.1
IO - Output Current - A
1
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION
DATA.
TPS62290-Q1, TPS62293-Q1
SLVSAI5B – SEPTEMBER 2010 – REVISED JUNE 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
4
4
4
4
5
6
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Parameter Measurement Information .................. 7
Detailed Description .............................................. 8
8.1 Overview ................................................................... 8
8.2 Functional Block Diagram ......................................... 8
8.3 Feature Description................................................... 9
8.4 Device Functional Modes........................................ 10
9
Application and Implementation ........................ 12
9.1 Application Information............................................ 12
9.2 Typical Applications ................................................ 12
10 Power Supply Recommendations ..................... 18
11 Layout................................................................... 18
11.1 Layout Guidelines ................................................. 18
11.2 Layout Example .................................................... 18
12 Device and Documentation Support ................. 19
12.1
12.2
12.3
12.4
12.5
12.6
12.7
Device Support......................................................
Related Links ........................................................
Receiving Notification of Documentation Updates
Community Resource............................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
19
19
19
19
19
19
19
13 Mechanical, Packaging, and Orderable
Information ........................................................... 19
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (April 2013) to Revision B
Page
•
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section ................................................................................................. 1
•
Deleted all references to TPS62291-Q1 ............................................................................................................................... 1
•
Changed description text for MODE in Pin Functions table ................................................................................................... 4
•
Added PowerPAD row to Pin Functions table ....................................................................................................................... 4
•
Changed Thermal Information table ...................................................................................................................................... 4
•
Deleted Dissipation Ratings .................................................................................................................................................. 5
•
Deleted List of Components table from Design Requirements ........................................................................................... 12
•
Deleted List of Inductors table from Inductor Selection........................................................................................................ 13
•
Deleted List of Capacitors table from Input Capacitor Selection ......................................................................................... 14
•
Deleted TPS62291DRV Fixed 3.3 V application from the data sheet.................................................................................. 17
Changes from Original (April 2013) to Revision A
•
2
Page
Deleted Ordering Information Table. ...................................................................................................................................... 1
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SLVSAI5B – SEPTEMBER 2010 – REVISED JUNE 2016
5 Pin Configuration and Functions
DRV Package
6-Pin SON
Top View
SW
1
MODE
FB
6
GND
2 PowerPAD 5
VIN
3
EN
4
Not to scale
Pin Functions
PIN
NO.
NAME
TYPE
DESCRIPTION
1
SW
O
This is the switch pin and is connected to the internal MOSFET switches. Connect the external inductor
between this terminal and the output capacitor.
2
MODE
I
Pulling this pin to high forces the device to operate in fixed-frequency PWM mode. Pulling this pin to low
enables the Power Save Mode with automatic transition from PFM mode to fixed-frequency PWM mode.
3
FB
I
Feedback Pin for the internal regulation loop. Connect the external resistor divider to this pin. In case of
fixed output voltage option, connect this pin directly to the output capacitor
4
EN
I
This is the enable pin of the device. Pulling this pin to low forces the device into shutdown mode. Pulling
this pin to high enables the device. This pin must be terminated.
5
VIN
PWR
VIN power supply pin.
6
GND
GND
GND supply pin
—
PowerPAD
GND
GND pin must be electrically connected to the exposed pad on the printed-circuit board for proper
operation.
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
VI
MIN
MAX
Input voltage (2)
–0.3
7
Voltage at EN, MODE
–0.3
VIN +0.3, ≤ 7
Voltage on SW (3)
–0.3
7
Peak output current
A
Maximum operating junction temperature
–40
125
Tstg
Storage temperature
–65
150
(2)
(3)
V
Internally limited
TJ
(1)
UNIT
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to network ground terminal.
I = Input, O = Output, GND = Ground, PWR = Power
6.2 ESD Ratings
VALUE
V(ESD)
(1)
Electrostatic discharge
Human-body model (HBM), per AEC Q100-002 (1)
±2000
Charged-device model (CDM), per AEC Q100-011
±1000
UNIT
V
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
MIN NOM
VIN
Supply voltage
Output voltage for adjustable voltage
TA
Operating ambient temperature
TJ
Operating junction temperature
MAX
UNIT
2.3
6
V
V
0.6
VIN
TPS62290IDRVRQ1
–40
85
TPS6229XTDRVRQ1
–40
105
–40
125
°C
°C
6.4 Thermal Information
TPS6229x-Q1
THERMAL METRIC
(1)
DRV (SON)
UNIT
6 PINS
RθJA
Junction-to-ambient thermal resistance
67.8
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
88.5
°C/W
RθJB
Junction-to-board thermal resistance
37.2
°C/W
ψJT
Junction-to-top characterization parameter
2
°C/W
ψJB
Junction-to-board characterization parameter
37.6
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
7.9
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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SLVSAI5B – SEPTEMBER 2010 – REVISED JUNE 2016
6.5 Electrical Characteristics
Over full operating ambient temperature range, typical values are at TA = 25°C. Unless otherwise noted, specifications apply
for condition VIN = EN = 3.6 V. External components CIN = 4.7 µF 0603, COUT = 10 µF 0603, L = 2.2 µH, see Parameter
Measurement Information.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
SUPPLY
VI
Input voltage
IO
Output current (1)
2.3
6
VIN 2.7 V to 6 V
1000
VIN 2.5 V to 2.7 V
600
VIN 2.3 V to 2.5 V
300
IO = 0 mA, PFM mode enabled
(MODE = GND) device not switching, See
IQ
Operating quiescent current
ISD
Shutdown current
UVLO
Undervoltage lockout threshold
(2)
IO = 0 mA, switching with no load,
(MODE = VIN)
PWM operation, VO = 1.8 V, VIN = 3V
EN = GND
V
TA = 25°C
mA
15
µA
3.8
mA
0.1
TA = 105°C
1
2.5
Falling
1.85
Rising
1.95
µA
V
ENABLE, MODE
VIH
High level input voltage, EN, MODE
2.3 V ≤ VIN ≤ 6 V
1
VIL
Low level input voltage, EN, MODE
2.3 V ≤ VIN ≤ 6 V
0
II
Input bias current, EN, MODE
EN, MODE = GND or VIN
VIN
V
0.4
V
0.01
1
µA
240
480
185
380
1.4
1.78
POWER SWITCH
RDS(on)
ILIMF
TSD
High-side MOSFET ON-resistance
Low-side MOSFET ON-resistance
VIN = VGS = 3.6 V, TA = 25°C
Forward current limit MOSFET high-side and
VIN = VGS = 3.6 V, TA = 25°C
low-side
1.19
Thermal shutdown
Increasing junction temperature
140
Thermal shutdown hysteresis
Decreasing junction temperature
20
mΩ
A
°C
OSCILLATOR
fSW
2.3 V ≤ VIN ≤ 6 V
Oscillator frequency
2
2.25
2.5 MHz
OUTPUT
VO
Adjustable output voltage range
Vref
Reference voltage
0.6
VI
600
VFB(PWM)
Feedback voltage
MODE = VIN, PWM operation,
2.3 V ≤ VIN ≤ 6 V, See (3)
VFB(PFM)
Feedback voltage PFM mode
MODE = GND, device in PFM mode, +1%
voltage positioning active, See (2)
–1.5%
Load regulation
0%
V
mV
1.5%
1%
–0.5
%/A
tStart Up
Start-up time
Time from active EN to reach 95% of VO
500
µs
tRamp
VO ramp-up time
Time to ramp from 5% to 95% of VO
250
µs
Leakage current into SW pin
VI = 3.6 V, VI = VO = VSW, EN = GND,
See (4)
0.1
Ilkg
(1)
(2)
(3)
(4)
1
µA
Not production tested.
In PFM mode, the internal reference voltage is set to 1.01 × Vref (typical). See Parameter Measurement Information.
For VIN = VO + 1 V
In fixed output voltage versions, the internal resistor divider network is disconnected from FB pin.
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6.6 Typical Characteristics
Table 1. Table of Graphs
FIGURE NO.
Shutdown Current into VIN
vs Input Voltage, (TA = 85°C, TA = 25°C, TA = –40°C)
Figure 1
Quiescent Current
vs Input Voltage, (TA = 85°C, TA = 25°C, TA = –40°C)
Figure 2
Static Drain-Source ON-State
Resistance
vs Input Voltage, (TA = 85°C, TA = 25°C, TA = –40°C)
0.8
Figure 3
Figure 4
20
MODE == GND,
GND
MODE
EN == VIN,
VIN
EN
Device Not
Not Switching
Switching
Device
0.7
0.6
IQ – Quiescent Current – mA
18
o
TA = 85 C
0.5
0.4
0.3
0.2
o
16
o
C
TTAA = 25 °C
14
12
C
TTAA == –40
-40o°C
o
TA = 25 C
TA = -40 C
10
0.1
0
2
2.5
3
3.5
4
4.5
5
5.5
8
8 222
6
2.5
3
VIN − Input Voltage − V
High Side Switching
0.7
0.6
o
TA = 85 C
0.5
o
TA = 25 C
0.4
0.3
0.2
o
TA = -40 C
0.1
0
2.5
3
3.5
4
4.5
5
VIN − Input Voltage − V
Figure 3. Static Drain-Source ON-State Resistance vs Input
Voltage
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55
4.5
4.5
44
5.5
5.5
66
Figure 2. Quiescent Current vs Input Voltage
RDS(on) - Static Drain-Source On-State Resistance − W
RDS(on) - Static Drain-Source On-State Resistance − W
0.8
2
3.5
V
VIN
InputVoltage
Voltage–−VV
IN–−Input
Figure 1. Shutdown Current into VIN vs Input Voltage
6
o
TTAA == 85
85°C
IQ - Quiescent Current − mA
ISD - Shutdown Current Into VIN − mA
EN = GND
0.4
Low Side Switching
0.35
0.3
o
TA = 85 C
0.25
o
TA = 25 C
0.2
0.15
0.1
o
TA = -40 C
0.05
0
2
2.5
3
3.5
4
4.5
5
VIN − Input Voltage − V
Figure 4. Static Drain-Source ON-State Resistance vs Input
Voltage
Copyright © 2010–2016, Texas Instruments Incorporated
Product Folder Links: TPS62290-Q1 TPS62293-Q1
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SLVSAI5B – SEPTEMBER 2010 – REVISED JUNE 2016
7 Parameter Measurement Information
L1
2 .2 mH
TPS62290DRV
VIN
C IN
10 mF
SW
R1
EN
GND
V OUT
C1
22 pF
C OUT
10 mF
FB
R2
MODE
L: LPS3015 2.2 mH, 110 mW
Copyright © 2016, Texas Instruments Incorporated
Figure 5. Parameter Measurement Test Setup
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8 Detailed Description
8.1 Overview
The TPS6229x-Q1 step-down converter operates with typically 2.25-MHz fixed frequency pulse width modulation
(PWM) at moderate to heavy load currents. At light-load currents, the converter can automatically enter Power
Save Mode and operates then in PFM mode.
During PWM operation, the converter uses a unique fast-response voltage mode controller scheme with input
voltage feedforward to achieve good line and load regulation, allowing the use of small ceramic input and output
capacitors. At the beginning of each clock cycle initiated by the clock signal, the high-side MOSFET switch is
turned on. The current flows now from the input capacitor through the high-side MOSFET switch through the
inductor to the output capacitor and load. During this phase, the current ramps up until the PWM comparator trips
and the control logic turns off the switch. The current limit comparator also turns off the switch if the current limit
of the high-side MOSFET switch is exceeded. After a dead time preventing shoot-through current, the low-side
MOSFET rectifier is turned on, and the inductor current ramps down. The current flows now from the inductor to
the output capacitor and to the load. It returns to the inductor through the low-side MOSFET rectifier.
The next cycle is initiated by the clock signal again turning off the low-side MOSFET rectifier and turning on the
high-side MOSFET switch.
8.2 Functional Block Diagram
VIN
Current
Limit Comparator
Thermal
Shutdown
EN
Undervoltage
Lockout 1.8 V
Reference
0.6 V VREF
Limit
High Side
FB
PFM Comp .
+1% Voltage positioning
VREF + 1%
MODE
Mode
Softstart
VOUT RAMP
CONTROL
Error Amp
Gate Driver
Anti
Shoot-Through
Control
Stage
SW
VREF
Integrator
FB
FB
Zero-Pole
AMP.
PWM
Comp .
Limit
RI1
RI3
Low Side
RI..N
Int. Resistor
Network
Sawtooth
Generator
Current
Limit Comparator
2.25 MHz
Oscillator
GND
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8
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8.3 Feature Description
8.3.1 Power Save Mode
The Power Save Mode is enabled with MODE Pin set to low level. If the load current decreases, the converter
enters Power Save Mode operation automatically. During Power Save Mode, the converter skips switching and
operates with reduced frequency in PFM mode with a minimum quiescent current to maintain high efficiency. The
converter positions the output voltage typically +1% above the nominal output voltage. This voltage positioning
feature minimizes voltage drops caused by a sudden load step.
The transition from PWM mode to PFM mode occurs once the inductor current in the low-side MOSFET switch
becomes zero, which indicates discontinuous conduction mode.
During the Power Save Mode the output voltage is monitored with a PFM comparator. As the output voltage falls
below the PFM comparator threshold of VOUT nominal +1%, the device starts a PFM current pulse. For this the
high-side MOSFET switch turns on and the inductor current ramps up. After the ON-time expires, the switch is
turned off, and the low-side MOSFET switch is turned on until the inductor current becomes zero.
The converter effectively delivers a current to the output capacitor and the load. If the load is below the delivered
current, the output voltage rises. If the output voltage is equal or higher than the PFM comparator threshold, the
device stops switching and enters a sleep mode with typical 15-µA current consumption.
If the output voltage is still below the PFM comparator threshold, a sequence of further PFM current pulses are
generated until the PFM comparator threshold is reached. The converter starts switching again once the output
voltage drops below the PFM comparator threshold.
With a fast single-threshold comparator, the output voltage ripple during PFM mode operation can be kept small.
The PFM Pulse is time controlled, which allows modification of the charge transferred to the output capacitor by
the value of the inductor. The resulting PFM output voltage ripple and PFM frequency depend in first order on the
size of the output capacitor and the inductor value. Increasing output capacitor values and inductor values
minimizes the output ripple. The PFM frequency decreases with smaller inductor values and increases with
larger values.
The PFM mode is left and PWM mode entered in case the output current can not longer be supported in PFM
mode. The Power Save Mode can be disabled through the MODE pin set to high. The converter then operates in
fixed frequency PWM mode.
8.3.1.1 Dynamic Voltage Positioning
This feature reduces the voltage undershoots and overshoots at load steps from light to heavy load and vice
versa. It is active in Power Save Mode and regulates the output voltage 1% higher than the nominal value. This
provides more headroom for both the voltage drop at a load step, and the voltage increase at a load throw-off.
Output voltage
Voltage Positioning
Vout +1%
PFM Comparator
threshold
Light load
PFM Mode
Vout (PWM)
moderate to heavy load
PWM Mode
Figure 6. Power Save Mode Operation
8.3.1.2 100% Duty Cycle Low Dropout Operation
The device starts to enter 100% duty cycle Mode once the input voltage comes close the nominal output voltage.
To maintain the output voltage, the high-side MOSFET switch is turned on 100% for one or more cycles.
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Feature Description (continued)
With further decreasing VIN, the high-side MOSFET switch is turned on completely. In this case, the converter
offers a low input-to-output voltage difference. This is particularly useful in battery-powered applications to
achieve longest operation time by taking full advantage of the whole range of the battery voltage.
The minimum input voltage to maintain regulation depends on the load current and output voltage, and can be
calculated using Equation 1.
V(VIN)min = VOmax + IOmax × (RDS(on)max + RL)
where
•
•
•
•
IOmax = maximum output current plus inductor ripple current
RDS(on)max = maximum P-channel switch RDS(on)
RL = DC resistance of the inductor
VOmax = nominal output voltage plus maximum output voltage tolerance
(1)
8.3.1.3 Undervoltage Lockout
The undervoltage lockout circuit prevents the device from malfunctioning at low input voltages and from
excessive discharge of the battery and disables the output stage of the converter. The undervoltage lockout
threshold is typically 1.85 V with falling VIN.
8.3.2 Enable
The device is enabled setting EN pin to high. During the start-up time, tStart Up, the internal circuits are settled.
Afterwards, the device activates the soft-start circuit. The EN input can be used to control power sequencing in a
system with various DC-DC converters. The EN pin can be connected to the output of another converter, to drive
the EN pin high and getting a sequencing of supply rails. With EN = GND, the device enters shutdown mode. In
this mode, all circuits are disabled. In fixed output voltage versions, the internal resistor divider network is
disconnected from FB pin.
8.3.3 Soft Start
The TPS6229x-Q1 has an internal soft-start circuit that controls the ramp-up of the output voltage. The output
voltage ramps up from 5% to 95% of its nominal value within typical 250 µs. This limits the inrush current in the
converter during ramp-up, and prevents possible input voltage drops when a battery or high-impedance power
source is used. The soft-start circuit is enabled within the start-up time (tStart Up).
8.3.4 Short-Circuit Protection
The high-side and low-side MOSFET switches are short-circuit protected with maximum switch current = ILIMF.
The current in the switches is monitored by current limit comparators. Once the current in the high-side MOSFET
switch exceeds the threshold of its current limit comparator, it turns off and the low-side MOSFET switch is
activated to ramp down the current in the inductor and high-side MOSFET switch. The high-side MOSFET switch
can only turn on again, once the current in the low-side MOSFET switch has decreased below the threshold of its
current limit comparator.
8.3.5 Thermal Shutdown
As soon as the junction temperature, TJ, exceeds 140°C (typical) the device goes into thermal shutdown. In this
mode, the high-side and low-side MOSFETs are turned off. The device continues its operation when the junction
temperature falls below the thermal shutdown hysteresis.
8.4 Device Functional Modes
The MODE pin allows mode selection between forced PWM mode and Power Save Mode.
Connecting this pin to GND enables the Power Save Mode with automatic transition between PWM and PFM
mode. Pulling the MODE pin high forces the converter to operate in fixed frequency PWM mode even at light
load currents. This allows simple filtering of the switching frequency for noise-sensitive applications. In this mode,
the efficiency is lower compared to the Power Save Mode during light loads.
10
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Device Functional Modes (continued)
The condition of the MODE pin can be changed during operation and allows efficient power management by
adjusting the operation mode of the converter to the specific system requirements.
Table 2. Device Functional Modes
MODE PIN
FUNCTIONAL MODE
0
Forced PWM
1
PFM mode at light loads
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The TPS6229x devices are high-efficiency, synchronous, step-down DC-DC converters featuring Power Save
Mode or 2.25-MHz fixed frequency operation.
9.2 Typical Applications
9.2.1 TPS62290DRV Adjustable 1.8 V
TPS62290DRV
V(VIN) 2.3 V to 6.0 V
VIN
CIN
2.2 mH
SW
R1
EN
10 mF
GND
L1
360 kW
C1
22 pF
COUT
FB
MODE
VOUT 1.8 V,
Up to 1 A
10 mF
R2
180 kW
Copyright © 2016, Texas Instruments Incorporated
Figure 7. TPS62290DRV Adjustable 1.8-V Schematic
9.2.1.1 Design Requirements
The design guideline provides a component selection to operate the device within the recommended operating
condition.
9.2.1.2 Detailed Design Procedure
9.2.1.2.1 Output Voltage Setting
The output voltage can be calculated by Equation 2:
æ
R ö
VOUT = VREF ´ ç 1 + 1 ÷
è R2 ø
(2)
with an internal reference voltage VREF typical 0.6 V.
To minimize the current through the feedback divider network, R2 must be 180 kΩ or 360 kΩ. The sum of R1 and
R2 must not exceed approximately 1 MΩ, to keep the network robust against noise. An external feedforward
capacitor C1 is required for optimum load transient response. The value of C1 must be in the range between 22
pF and 33 pF.
Route the FB line away from noise sources, such as the inductor or the SW line.
9.2.1.2.2 Output Filter Design (Inductor and Output Capacitor)
The TPS6229x-Q1 is designed to operate with inductors in the range of 1.5 µH to 4.7 µH and with output
capacitors in the range of 4.7 µF to 22 µF. The part is optimized for operation with a 2.2-µH inductor and 10-µF
output capacitor. Larger or smaller inductor values can be used to optimize the performance of the device for
specific operation conditions. For stable operation, the L and C values of the output filter must not fall below 1-µH
effective inductance and 3.5-µF effective capacitance.
12
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SLVSAI5B – SEPTEMBER 2010 – REVISED JUNE 2016
Typical Applications (continued)
9.2.1.2.2.1 Inductor Selection
The inductor value has a direct effect on the ripple current. The selected inductor has to be rated for its DC
resistance and saturation current. The inductor ripple current (ΔIL) decreases with higher inductance and
increases with higher VI or VO.
The inductor selection has also impact on the output voltage ripple in PFM mode. Higher inductor values lead to
lower output voltage ripple and higher PFM frequency, lower inductor values lead to a higher output voltage
ripple but lower PFM frequency.
Equation 3 calculates the maximum inductor current under static load conditions. The saturation current of the
inductor must be rated higher than the maximum inductor current as calculated with Equation 4. This is
recommended because during heavy load transient the inductor current rises above the calculated value.
VOUT
VIN
L´f
1DIL = VOUT ´
(3)
DI
= IOUTmax ´ L
2
ILmax
where
•
•
•
•
f = Switching Frequency (2.25 MHz typical)
L = Inductor Value
ΔIL = Peak to Peak inductor ripple current
ILmax = Maximum Inductor current
(4)
A more conservative approach is to select the inductor current rating just for the maximum switch current of the
corresponding converter.
Accepting larger values of ripple current allows the use of low inductance values, but results in higher output
voltage ripple, greater core losses, and lower output current capability.
The total losses of the coil have a strong impact on the efficiency of the DC-DC conversion and consist of both
the losses in the DC resistance (R(DC)) and the following frequency-dependent components.
• The losses in the core material (magnetic hysteresis loss, especially at high switching frequencies)
• Additional losses in the conductor from the skin effect (current displacement at high frequencies)
• Magnetic field losses of the neighboring windings (proximity effect)
• Radiation losses
9.2.1.2.2.2 Output Capacitor Selection
The advanced fast-response voltage mode control scheme of the TPS6229x-Q1 allows the use of tiny ceramic
capacitors. Ceramic capacitors with low ESR values have the lowest output voltage ripple and are
recommended. The output capacitor requires either an X7R or X5R dielectric. Y5V and Z5U dielectric capacitors,
aside from their wide variation in capacitance overtemperature, become resistive at high frequencies.
At nominal load current, the device operates in PWM mode and the RMS ripple current is calculated as shown in
Equation 5.
VOUT
VIN æ 1 ö
´ç
÷
L´f
è 2´ 3 ø
1IRMSCOUT = VOUT ´
(5)
At nominal load current, the device operates in PWM mode and the overall output voltage ripple is the sum of the
voltage spike caused by the output capacitor ESR plus the voltage ripple caused by charging and discharging the
output capacitor as shown in Equation 6:
VOUT
VIN æ
1
ö
´ç
+ ESR ÷
L´f
è 8 ´ Cout ´ f
ø
1DVOUT = VOUT ´
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(6)
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Typical Applications (continued)
At light load currents, the converter operates in Power Save Mode, and the output voltage ripple is dependent on
the output capacitor and inductor value. Larger output capacitor and inductor values minimize the voltage ripple
in PFM mode and tighten DC output accuracy in PFM mode.
9.2.1.2.2.3 Input Capacitor Selection
The buck converter has a natural pulsating input current; therefore, a low ESR input capacitor is required for best
input voltage filtering and minimizing the interference with other circuits caused by high input voltage spikes. For
most applications, TI recommends a 10-µF ceramic capacitor. The input capacitor can be increased without any
limit for better input voltage filtering.
Take care when using only small ceramic input capacitors. When a ceramic capacitor is used at the input and the
power is being supplied through long wires, such as from a wall adapter, a load step at the output or VIN step on
the input can induce ringing at the VIN pin. The ringing can couple to the output and be mistaken as loop
instability or could even damage the part by exceeding the maximum ratings.
9.2.1.3 Application Curves
100
100
VIN = 2.7 V
90
L = 2.2 mH
VIN = 3.3 V
80
VIN = 3.6 V
80
VIN = 3.3 V
VIN = 4.5 V
Efficiency - %
Efficiency - %
VOUT = 1.8 V,
MODE = VIN,
90
70
VIN = 5 V
60
50
VIN = 2.7 V
VIN = 5 V
60
VIN = 4.5 V
50
VIN = 3.6 V
40
VOUT = 1.8 V,
MODE = GND,
L = 2.2 mH
40
30
0.01
70
30
20
0.1
100
10
1
IO - Output Current - mA
1000
Figure 8. Efficiency (Power Save Mode) vs Output Current
100
10
IO - Output Current - mA
1
1000
Figure 9. Efficiency (Forced PWM Mode) vs Output Current
1.854
1.90
MODE = VIN,
MODE = GND,
L = 2.2 mH
L = 2.2 mH
1.836
1.88
VIN = 3.6 V, TA = -40°C
1.818
DC Output Voltage - V
DC Output Voltage - V
VIN = 2.7 V, TA = -40°C
VIN = 4.5 V, TA = -40°C
1.8
1.782
VIN = 2.7 V,
TA = 25°C
VIN = 3.6 V,
TA = 25°C
1.764
1.746
0.01
VIN = 4.5 V,
TA = 85°C
VIN = 4.5 V,
TA = 25°C
0.1
VIN = 3.6 V,
TA = 85°C
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VI = 3.6 V, TA = -40°C
1.84
1.82
VI = 2.7 V, TA = -40°C
VI = 4.5 V, TA = -40°C
PWM Mode
VI = 4.5 V, TA = 85°C
VI = 3.6 V, TA = 85°C
VI = 4.5 V, TA = 25°C
1000
Figure 10. Output Voltage Accuracy (1.8-V Forced PWM
Mode) vs Output Current
14
PFM Mode, Voltage Positioning On
1.80 VI = 2.7 V, TA = 85°C
VIN = 2.7 V,
TA = 85°C
1
10
100
IO - Output Current - mA
1.86
1.78
0.01
VI = 3.6 V, TA = 25°C
VI = 2.7 V, TA = 25°C
0.1
1
10
100
IO - Output Current - mA
1000
Figure 11. Output Voltage Accuracy (1.8-V Power Save
Mode) vs Output Current
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SLVSAI5B – SEPTEMBER 2010 – REVISED JUNE 2016
Typical Applications (continued)
SW 2V/Div
VIN 3.6 V,
VOUT 1.8 V,
IOUT 300 mA to 800 mA,
MODE = GND VOUT 100 mV/Div
VOUT 50 mV/Div
IOUT 500 mA/Div
VIN 3.6 V,
VOUT 1.8 V,
IOUT 50 mA to 250 mA,
250 mA
MODE = GND
800 mA
300 mA
IOUT 200 mA/Div
50 mA
Icoil 500 mA/Div
Icoil 500 mA/Div
Time Base - 20 ms/Div
Time Base - 20 ms/Div
Figure 12. PFM Load Transient
VIN 3.6 V to 4.2 V
500 mV/Div
Figure 13. PFM Line Transient
VIN 3.6 V to 4.2 V,
500 mV/Div
VOUT = 1.8 V,
50 mV/Div,
IOUT = 50 mA,
MODE = GND
VOUT = 1.8 V,
50 mV/Div,
IOUT = 250 mA,
MODE = GND
Time Base - 100 ms/Div
Time Base - 100 ms/Div
Figure 14. PWM Load Transient
Figure 15. PWM Line Transient
VIN 3.6 V,
VOUT 1.8 V, IOUT 150 mA,
VOUT 20 mV/Div
VOUT 10 mV/Div
L 2.2 mH, COUT 10 mF 0603
VIN 3.6 V,
VOUT 1.8 V, IOUT 10 mA,
SW 2 V/Div
L 2.2 mH, COUT 10 mF 0603
SW 2 V/Div
Icoil 200 mA/Div
Icoil 200 mA/Div
Time Base - 10 ms/Div
Time Base - 10 ms/Div
Figure 16. Typical Operation vs PFM Mode
Figure 17. Typical Operation vs PWM Mode
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Typical Applications (continued)
9.2.2 TPS62290DRV Adjustable 3.3 V
TPS62290DRV
V(VIN) 3.9 V to 6.0 V
VIN
CIN
GND
2.2 mH
SW
VOUT 3.3 V,
Up to 1 A
C1
22 pF
R1
EN
10 mF
L1
820 kW
COUT
FB
MODE
10 mF
R2
182 kW
Copyright © 2016, Texas Instruments Incorporated
Figure 18. TPS62290DRV Adjustable 3.3-V Schematic
9.2.2.1 Design Requirements
For a 3.3-V output, the only change compared to the previous example is the feedback divider. A higher supply
voltage is required to support the dropout to 3.3 V.
9.2.2.2 Detailed Design Procedure
For a 3.3-V output, the feedback-divider must be selected to provide the reference voltage of 0.6 V at FB-pin.
Here, 820 kΩ for the upper resistor and 182 kΩ for the lower resistor was chosen.
9.2.2.3 Application Curves
100
100
VIN = 4.2 V
90
VIN = 3.8 V
VIN = 4.5 V
60
60
VIN = 4.5 V
50
40
30
50
VOUT = 3.3 V,
MODE = GND,
L = 2.2 mH
40
20
VOUT = 3.3 V,
MODE = VIN,
10
L = 2.2 mH
0
0.1
100
10
1
IO - Output Current - mA
1000
Figure 19. Efficiency (Power Save Mode) vs Output
Current
16
VIN = 5 V
70
70
30
0.01
VIN = 3.8 V
80
VIN = 5 V
Efficiency - %
Efficiency - %
80
VIN = 4.2 V
90
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100
10
IO - Output Current - mA
1
1000
Figure 20. Efficiency (Forced PWM Mode) vs Output
Current
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SLVSAI5B – SEPTEMBER 2010 – REVISED JUNE 2016
Typical Applications (continued)
1.854
1.90
MODE = VIN,
MODE = GND,
L = 2.2 mH
L = 2.2 mH
1.836
1.88
VIN = 3.6 V, TA = -40°C
1.818
DC Output Voltage - V
DC Output Voltage - V
VIN = 2.7 V, TA = -40°C
VIN = 4.5 V, TA = -40°C
1.8
1.782
VIN = 2.7 V,
TA = 25°C
VIN = 4.5 V,
TA = 85°C
VIN = 3.6 V,
TA = 25°C
1.764
1.746
0.01
VIN = 3.6 V,
TA = 85°C
VIN = 4.5 V,
TA = 25°C
0.1
1.86
PFM Mode, Voltage Positioning On
VI = 3.6 V, TA = -40°C
1.84
1.82
VI = 2.7 V, TA = -40°C
VI = 4.5 V, TA = -40°C
PWM Mode
VI = 4.5 V, TA = 85°C
VI = 3.6 V, TA = 85°C
1.80 VI = 2.7 V, TA = 85°C
VIN = 2.7 V,
TA = 85°C
1
10
100
IO - Output Current - mA
VI = 4.5 V, TA = 25°C
1.78
0.01
1000
Figure 21. Output Voltage Accuracy (1.8-V Forced PWM
Mode) vs Output Current
VI = 3.6 V, TA = 25°C
VI = 2.7 V, TA = 25°C
0.1
1
10
100
IO - Output Current - mA
1000
Figure 22. Output Voltage Accuracy (1.8-V Power Save
Mode) vs Output Current
9.2.3 TPS62293DRV Fixed 1.8 V
TPS62290DRV
V(VIN) 2.3 V to 6.0 V
VIN
CIN
2.2 mH
SW
R1
EN
10 mF
GND
MODE
L1
360 kW
C1
22 pF
FB
R2
VOUT 1.8 V,
Up to 1 A
COUT
10 mF
180 kW
Copyright © 2016, Texas Instruments Incorporated
Figure 23. TPS62293DRV Fixed 1.8-V Schematic
9.2.3.1 Design Requirements
For a fixed 1.8-V output, the feedback dividers are not required. Obviously, a higher supply voltage is required to
support the dropout to 1.8 V.
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10 Power Supply Recommendations
Apply a preregulated voltage of 2.3 V to 6 V to the VIN-pin of the device. For higher output voltages, the supply
voltage must support the dropout.
11 Layout
11.1 Layout Guidelines
As for all switching power supplies, the layout is an important step in the design. If the layout is not carefully
done, the regulator could show poor line or load regulation, stability issues, as well as EMI problems. It is critical
to provide a low-inductance, low-impedance ground path. Therefore, use wide and short traces for the main
current paths. The input capacitor must be placed as close as possible to the IC pins as well as the inductor and
output capacitor.
Connect the GND Pin of the device to the PowerPAD of the PCB and use this pad as a star point. Use a
common Power GND node and a different node for the Signal GND to minimize the effects of ground noise.
Connect these ground nodes together to the PowerPAD (star point) underneath the IC. Keep the common path
to the GND PIN, which returns the small signal components and the high current of the output capacitors as
short as possible to avoid ground noise. The FB line must be connected right to the output capacitor and routed
away from noisy components and traces (for example, SW line).
11.2 Layout Example
VOUT
R2
GND
C1
R1
COUT
CIN
VIN
L
G
N
D
U
Figure 24. Layout Recommendation
18
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SLVSAI5B – SEPTEMBER 2010 – REVISED JUNE 2016
12 Device and Documentation Support
12.1 Device Support
12.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
12.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 3. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
TPS62290-Q1
Click here
Click here
Click here
Click here
Click here
TPS62293-Q1
Click here
Click here
Click here
Click here
Click here
12.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.4 Community Resource
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.5 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.6 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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19
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS62290IDRVRQ1
ACTIVE
WSON
DRV
6
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
QVI
TPS62290TDRVRQ1
ACTIVE
WSON
DRV
6
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 105
QVJ
TPS62293TDRVRQ1
ACTIVE
WSON
DRV
6
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 105
QTO
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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