TPS62750, TPS62751
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High Efficiency Step-Down Converter for USB Applications
Check for Samples :TPS62750, TPS62751
FEATURES
APPLICATIONS
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1
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Efficiency > 90% at Nominal Operating
Conditions
Programmable Average Input Current Limits
for USB Applications
– 50mA to 300mA for Low Current Limit
Range
– 300mA to 1.3A for High Current Limit
Range
– ±10% Current Accuracy
Stable Output Voltage for Load Transients to
Minimize Overshoot at Load Step Response
Hot Plug and Reverse Current Protection
Automatic PFM/PWM Mode transition
(TPS62750)
Forced PWM for Noise Sensitive Applications
(TPS62751)
VIN Range From 2.9V to 6V
Adjustable VOUT From 0.8V to 0.85×VIN
Softstart for Inrush Current Prevention
2.25 MHz Fixed Frequency Operation
Short Cicruit and Thermal Shutdown
Protection
Available in a 2.5 × 2.5 10 pin SON Package
USB Wireless Modems
Portable USB peripherals
Handheld Computers
DESCRIPTION
The TPS6275x device is a highly efficient
synchronous step down dc-dc converter optimized for
USB powered portable applications. It can provide up
to 1300mA average input current and is ideal for
applications connected to a USB host.
With an input voltage range of 2.9 V to 6.0V, the
device supports batteries with extended voltage
range and is ideal for powering USB applications
where USB compliance is required.
The TPS62750 operates at 2.25-MHz fixed switching
frequency and enters Power Save Mode operation at
light load currents to maintain high efficiency over the
entire load current range. The TPS62751 operates in
Forced PWM mode allowing use in applications that
are noise sensitive. An output discharge allows the
load to discharge in shutdown.
The 10% accurate average input current limit can be
programmed with an external resistor, allowing use in
applications such as USB, where the current drawn
from the bus must be limited to 500mA.
The TPS6275x allows the use of small inductors and
capacitors to achieve a small solution size. The
TPS6275x is available in a 2,5mm × 2,5mm 10-pin
SON package.
TPS62750
VIN 5.0V
VIN
2.2 µH
L
AV IN
EN
Ilim_U
CIN
Ilim_L
R3
FB
H/L
GND
PGND
L1
VOUT 3.6V
R1
R2
Cff
CO
CBULK
R4
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2009, Texas Instruments Incorporated
TPS62750, TPS62751
SLVS955A – JULY 2009 – REVISED SEPTEMBER 2009 ................................................................................................................................................. www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
Table 1. ORDERING INFORMATION (1)
TA
PART NUMBER
-40°C to 85°C
(2)
OUTPUT
VOLTAGE (3)
PACKAGE
PACKAGE
DESIGNATOR
ORDERING
Adjustable
SON 2.5×2.5 -10
DSK
TPS62750DSK
NXJ
TPS62751DSK
DAL
TPS62750
TPS62751
(1)
(2)
(3)
PACKAGE
MARKING
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com
The DSK (SON-10) package is available in tape on reel. Add R suffix to order quantities of 3000 parts per reel.
Contact TI for other fixed output voltage options
ABSOLUTE MAXIMUM RATINGS
Over operating free-air temperature range (unless otherwise noted) (1)
Input voltage range VIN, AVIN
(2)
Voltage range at EN, H/L, FB
Voltage on L, ILim_U, ILim_L
Peak output current
VALUE
UNIT
–0.3 to 7.0
V
–0.3 to VIN +0.3, ≤7.0
V
–0.3 to 7.0
V
Internally limited
A
HBM Human body model
ESD rating (3)
4
CDM Charge device model
kV
1.5
200
V
Maximum operating junction temperature, TJ
Machine model
–40 to 125
°C
Storage temperature range, Tstg
–65 to 150
°C
(1)
(2)
(3)
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.
All voltage values are with respect to network ground terminal.
The human body model is a 100pF capacitor discharged through a 1.5 kΩ resistor into each pin. The machine model is a 200pF
capacitor discharged directly into each pin.
DISSIPATION RATINGS (1)
(2)
PACK
AGE
THERMAL
RESISTANCE
RθJA
THERMAL
RESISTANCE
RθJP
THERMAL
RESISTANCE
RθJC
POWER
RATING
FOR TA ≤ 25°C
DERATING
FACTOR
ABOVE TA =
25°C
DSK
60.6°C/W
6.3°C/W
40°C/W
1650mW
17mW/°C
(1)
(2)
Maximum power dissipation is a function of TJ(max), θJA and TA. The maximum allowable power
dissipation at any allowable ambient temperature is PD = [TJ(max) - TA]/θJA
This thermal data is measured with a high-K board (4 layer board according to JESD51-7 JEDEC
standard).
RECOMMENDED OPERATING CONDITIONS
MIN
NOM
MAX
UNIT
Supply Voltage VIN
2.9
6
V
Output voltage range for adjustable voltage
0.8
0.85 ×
VIN
V
Operating ambient temperature, TA
–40
85
°C
Operating virtual junction temperature, TJ
–40
125
°C
2
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ELECTRICAL CHARACTERISTICS
Over full operating ambient temperature range, typical values are at TA = 25°C. Unless otherwise noted, specifications apply
for condition VIN = EN = 5.0V. External components CIN = 10μF 0603, CO = 10μF 0603, CBULK = 1.5mF, L = 2.2μH, refer to
parameter measurement information.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
6.0
V
745
960
μA
30
mA
3.0
μA
SUPPLY
VIN
Input Voltage Range
IQ
Operating Quiescent Current
2.9
IOUT = 0 mA, device not switching
(TPS62750) (1)
IOUT = 0 mA, device not switching
(TPS62751) (1)
ISD
Shutdown Current
VUVLO
Undervoltage Lockout Threshold
EN = GND
Falling
0.2
2.4
V
Rising
2.9
V
ENABLE, H/L
VIH
High Level Input Voltage
2.9 V ≤ VIN ≤ 6.0V
VIL
Low Level Input Voltage
2.9 V ≤ VIN ≤ 6.0 V
IIN
Input bias Current
Pin tied to GND or VIN
High side MOSFET On-Resistance
(H/L=HI)
1.0
V
0.4
V
0.01
1.0
μA
VIN = 5.0 V, VGS = 6.5 V
130
290
mΩ
High side MOSFET On-Resistance
(H/L=LO)
VIN = 5.0 V, VGS = 6.5 V
282
550
mΩ
58
125
mΩ
1500
1800
mA
POWER SWITCH
RDS(ON)
Low Side MOSFET On-Resistance
VIN = VGS = 5.0 V
ILIMF
Forward Current Limit High-Side and Low
side
VIN = VGS = 5.0 V
IIN(MAX)
Programmable Input current Range
ILIM_U selected, H/L = High
300
1300
ILIM_L selected, H/L = Low
50
300
–10
10
ILIM_U selected, Current limit accuracy
TSD
1200
mA
%
Thermal shutdown
Increasing junction temperature
150
°C
Thermal shudown hysteresis
Decreasing junction temperature
20
°C
OSCILLATOR
fSW
Oscillator Frequency
2.9 V ≤ VIN ≤ 6.0 V
2.0
2.25
2.5
MHz
OUTPUT
VOUT
Adjustable Output Voltage Range
Vref
Reference Voltage
VFB(PWM)
Feedback Voltage
PWM operation, 2.9 V ≤ VIN ≤ 6.0V (2)
R(DIS_CH)
Internal discharge resistor
Activated with EN = GND
(1)
0.8
0.85 ×
VIN
600
–1.5%
85
V
mV
1.5%
235
300
Ω
In PFM mode, the internal reference voltage is set to typ. 1.01 × Vref. See the parameter measurement information.
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DEVICE INFORMATION
PIN ASSIGNMENTS
DSK PACKAGE
(TOP VIEW)
10
AD
1
9
4
Po
3
we
r
P
2
5
8
7
6
PIN FUNCTIONS
PIN
I/O
DESCRIPTION
NAME
NO.
PGND
1
L
2
OUT
H/L
3
IN
H/L pin = high enables the upper current limit threshold set by RSET_H. H/L pin = low enables the lower current
limit threshold set by RSET_L. This pin must be terminated.
EN
4
IN
This is the enable pin of the device. Pulling this pin to low forces the device into shutdown mode. Pulling this pin
to high enables the device. This pin must be terminated.
FB
5
IN
Feedback Pin for the internal regulation loop. Connect the external resistor divider to this pin. In case of fixed
output voltage option, connect this pin directly to the output capacitor
AGND
6
ISET_L
7
IN
Sets the lower average input current limit by external resistor.
ISET_U
8
IN
Sets the upper average input current limit by external resistor.
PVIN
9
IN
VIN power supply pin for the Output stage
AVIN
10
IN
VIN low noise analog supply for the internal analog circuitry. This pin must be connected to PVIN
4
Power GND Pin for the N-MOSFET
This is the switch pin and is connected to the internal MOSFET switches. Connect the external inductor between
this terminal and the output capacitor.
Analog GND Pin for the internal analog circuitry.
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FUNCTIONAL BLOCK DIAGRAM
ILIM_L
SOFTSTART
ILIM_U
AVIN
Current
Limit Comparator
Undervoltage
Lockout 1.8V
Thermal
Shutdown
PVIN
Limit
High Side
EN
PFM Comparator
FB
VREF
H/L
Control Logic
L
Gate Driver
Anti
Shoot-Through
Control
Stage
Error Amp.
VREF
Integrator
FB
PWM
Comp.
Zero-Pole
AMP.
Reference
0.6V VREF
VREF
Limit
Low Side
Sawtooth
Generator
Current
Limit Comparator
3MHz
Clock
SHUTDOWN
DRIVER
AGND
RDischarge
PGND
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PARAMETER MEASUREMENT INFORMATION
TPS62750
VIN 5.0V
VIN
2.2 µH
L
AV IN
EN
Ilim_U
CIN
Ilim_L
R3
L1
FB
H/L
GND
PGND
VOUT 3.6V
R1
R2
Cff
CO
CBULK
R4
Table 2. List of Components
COMPONENT REFERENCE
PART NUMBER
MANUFACTURER
VALUE
CIN
GRM188R60J106M
Murata
10μF
COUT
GRM188R60J106M
Murata
10μF
Cff
C1608C0G1H471J
TDK
470pF
6TPG150M
Sanyo POSCAP
10 × 150μF
592D158X06R3X2T25H
Vishay
1.5mF
LPS3015-222ML
Coilcraft
2.2μH
CBULK
L1
6
R1, R2
Depending on output voltage required. Equation 1 can be used to calculate the output voltage with
different R1 and R2 values.
R3, R4
Depending on the upper and lower current limits required. Equations 7 and 8 can be used for these
calculations.
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TYPICAL CHARACTERISTICS
TABLE OF GRAPHS
Figure
Maximum Output Current
vs Input voltage
Figure 1
Efficiency
vs Output Current, Vin = [4.0V; 4.5V; 5.0V; 5.5V], Vout = 3.6V, H/L = High
Figure 2
vs Output Current, Vin = [4.0V; 4.5V; 5.0V; 5.5V], Vout = 3.6V, H/L = Low
Figure 3
vs Output Current, Vin = [4.0V; 4.5V; 5.0V; 5.5V], Vout = 2.5V, H/L = High
Figure 4
vs Output Current, Vin = [4.0V; 4.5V; 5.0V; 5.5V], Vout = 2.5V, H/L = Low
Figure 5
vs Input Voltage, Vout = 3.6V, Iout = [200mA, 400mA, 500mA, 700mA, 1000mA]
Figure 6
Input Current
vs Output Current, Vout =3.6V, Vin = [4.0V; 4.5V; 5.0V; 5.5V]
Figure 7
Output Voltage
vs Output Current, Vout = 3.6V, Vin = [4.5V; 5.0V; 5.5V], H/L = High
Figure 8
vs Output Current, Vout = 3.6V, Vin = [4.5V; 5.0V; 5.5V], H/L = Low
Figure 9
vs Input Voltage, Iload = 300mA, Vout = 3.6V H/L=high
Figure 10
vs Input Voltage, Iload = 500mA, Vout = 3.6V H/L=high
Figure 11
vs Input Voltage, Iload = 100μA, Vout = 3.6V H/L=low
Figure 12
vs Input Voltage, Iload = 80mA, Vout = 3.6V H/L=low
Figure 13
Output Voltage Ripple, PFM Mode Iout = 50mA
Figure 14
Output Voltage Ripple, PWM Mode Iout = 500mA
Figure 15
Load Transient Vin = 5.0V, Vout = 3.6V, H/L = High, 50mA - 2A & 2A - 50mA,
Pulse Load period = 4.6ms, duty cycle 12.5%
Figure 16
Load Transient Vin = 5.0V, Vout = 3.6V, H/L = High, 50mA - 2A & 2A - 50mA,
Pulse Load period = 4.6ms, duty cycle 25%
Figure 17
Line Transient, Vin = 4.5V - 5.0V, Iout = 80mA, H/L = Low
Figure 18
Line Transient, Vin = 4.5V - 5.0V, Iout = 200mA, H/L = Low
Figure 19
Line Transient, Vin = 4.5V - 5.0V, Iout = 500mA, H/L = High
Figure 20
Average Input current Limit vs RLIM_L
Figure 21
Average Input current Limit vs RLIM_U
Figure 22
Startup after Enable, Vin = 5.0V, Vout = 3.6V, Load = 80mA, H/L=Low
Figure 23
Startup after Enable, Vin = 5.0V, Vout = 3.6V, Load = 500mA, H/L=High
Figure 24
Output Discharge, Vin = 5.0V, Vout = 3.6V, No Load
Figure 25
Waveforms
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100
1000
VO = 3.6 V,
H/L = High
950
900
VI = 5 V
850
Imax = 25°C
800
750
700
650
600
550
500
50
40
30
400
350
20
3.3
3.7
4.1
4.5
4.9
5.3
VI - Output Voltage - V
0
0.2
5.7
0.4
0.6
0.8
1
1.2
IO - Output Current - A
1.4
1.6
Figure 2. Efficiency vs Output Current
100
100
VO = 3.6 V,
H/L Pin = Low
70
60
VI = 4 V
VI = 4.5 V
VI = 5 V
80
VI = 4 V
70
VI = 5 V
VI = 5.5 V
50
40
40
20
20
10
10
Figure 3. Efficiency vs Output Current
1
VI = 4.5 V
50
30
0.01
0.1
0.001
IO - Output Current - A
VI = 3.5 V
60
30
0
0.0001
VI = 5.5 V
90
Efficiency - %
80
Efficiency - %
VO = 3.6 V,
H/L = High
10
Figure 1. Maximum Output Current
8
VI = 4.5 V
60
450
90
VI = 4 V
70
Imax = 85°C
300
250
200
2.9
VI = 5.5 V
80
Efficiency - %
IO - Output Current - mA
90
Imax = -40°C
0
0.2
VO = 2.5 V,
H/L Pin = High
0.4
0.6
0.8
1
1.2
IO - Output Current - A
1.4
1.6
Figure 4. Efficiency vs Output Current
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100
VI = 3.5 V
VI = 4 V
80
80
VI = 4.5 V
70
Efficiency - %
90
VI = 5 V
60
VI = 5.5 V
50
40
400 mA
50
40
30
20
20
10
10
0.001
0.01
0.1
IO - Output Current - A
VO = 3.6 V,
H/L Pin = High
0
2.9
1
500 mA
60
30
0
0.0001
1A
700 mA
200 mA
70
Efficiency - %
90
100
VO = 2.5 V,
H/L Pin = Low
Figure 5. Efficiency vs Output Current
3.4
3.9
4.4
4.9
VI - Input Voltage - V
5.4
5.9
Figure 6. Efficiency vs Input Voltage
3.7
0.6
VO = 3.6 V,
H/L Pin = High
VO = 3.6 V,
H/L Pin = High
0.5
VO - Output Voltage DC - V
II - input Current - A
VI = 4 V
VI = 4.5 V
0.4
VI = 5 V
VI = 5.5 V
0.3
0.2
3.6
VI = 4.5 V
VI = 5 V
3.5
VI = 5.5 V
0.1
0
0.2
0.4
0.6
0.8
1
1.2
IO - Output Current - A
1.4
Figure 7. Input Current vs Output Current
1.6
3.4
0.2
0.3
0.4
0.5
0.6
IO - Output Current - A
0.7
0.8
Figure 8. Output Voltage vs Output Current
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3.7
3.744
3.708
VO = 3.6 V,
Iload = 300 mA,
H/L Pin = High
Limit +3%
3.672
VO - Output Voltage - V
VO - Output Voltage DC - V
VO = 3.6 V,
H/L Pin = Low
3.6
3.636
VI = 5 V
25°C
85°C
3.564
VI = 5.5 V
3.5
3.6
VI = 4.5 V
- 40°C
3.528
Limit -3%
3.492
3.4
0.0001
3.456
3.6 3.8
0.1001
IO - Output Current - A
Figure 9. Output Voltage vs Output Current
4 4.2 4.4 4.6 4.8 5 5.2 5.4 5.6 5.8
VI - Input Voltage - V
Figure 10. Output Voltage vs Input Voltage
3.744
3.744
Limit +3%
Limit +3%
3.708
3.708
3.672
VO = 3.6 V,
Iload = 500 mA,
H/L Pin = High
3.636
3.6
VO - Output Voltage - V
VO - Output Voltage - V
3.672
3.564
25°C
- 40°C
Iload = 100 mA,
H/L Pin = High
3.6
25°C
3.564
85°C
3.528
VO = 3.6 V,
3.636
- 40°C
3.528
85°C
Limit -3%
Limit -3%
3.492
3.492
3.456
3.6 3.8
4 4.2 4.4 4.6 4.8 5 5.2 5.4 5.6 5.8
VI - Input Voltage - V
Figure 11. Output Voltage vs Input Voltage
10
6
6
3.456
3.6 3.8
4 4.2 4.4 4.6 4.8 5 5.2 5.4 5.6 5.8
VI - Input Voltage - V
6
Figure 12. Output Voltage vs Input Voltage
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3.744
VIN = 5 V,
VOUT = 3.6 V,
IOUT = 50 mA
Limit +3%
3.708
VO - Output Voltage - V
3.672
VO = 3.6 V,
Iload = 80 mA,
H/L Pin = Low
3.636
3.6
VOUT = 10 mV/div
- 40°C
3.564
25°C
85°C
3.528
Limit -3%
3.492
ICOIL = 100 mA/div
3.456
3.6 3.8
4 4.2 4.4 4.6 4.8 5 5.2 5.4 5.6 5.8
VI - Input Voltage - V
Figure 13. Output Voltage vs Input Voltage
VIN = 5 V,
VOUT = 3.6 V,
IOUT = 500 mA
t - Time - 400 ns/div
6
Figure 14. Output Voltage Ripple – PFM Mode
VOUT = 200 mV/div
IIN = 500 mA/div
VOUT = 10 mV/div
ICOIL = 200 mA/div
VIN = 5 V, VOUT = 3.6 V,
IOUT = 50 mA - 2A
ICOIL = 100 mA/div
t - Time - 1 ms/div
t - Time - 400 ns/div
Figure 15. Output Voltage Ripple – PWM Mode
Figure 16. Load Transient
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VOUT = 200 mV/div
IIN = 500 mA/div
IIN = 200 mV/div
VOUT = 10 mV/div
ICOIL = 200 mA/div
VIN = 5 V, VOUT = 3.6 V,
IOUT = 50 mA - 2 A
VIN = 4.5 V - 5 V,
VOUT = 3.6 V, IOUT = 80 mA
t - Time - 1 ms/div
t - Time - 1 ms/div
Figure 17. Load Transient
VIN =200 mV/div
Figure 18. Line Transient
VIN = 200 mV/div
VOUT = 10 mV/div
VOUT = 10 mV/div
VIN = 4.5 V - 5 V,
VOUT = 3.6 V, IOUT = 500 mA
VIN = 4.5 V - 5 V,
VOUT = 3.6 V, IOUT = 200 mA
t - Time - 1 ms/div
t - Time - 1 ms/div
Figure 19. Line Transient
12
Figure 20. Line Transient
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1.4
Average Input Current Limit - A
Average Input Current Limit - A
0.3
0.25
0.2
0.15
0.1
0.05
0
0
60
80
40
100 120 140
RLIM_L - Lower Limit Resistance - kW
20
Figure 21. Average Input Current Limit
1.2
1
0.8
0.6
0.4
0.2
0
0
20
40
60
80
100
RLIM_U - Upper Limit Resistance - kW
Figure 22. Average Input Current Limit
EN = 200 mV/div
EN = 5 V/div
VOUT = 1 mV/div
VOUT = 1 mV/div
VIN = 5 V,
VOUT = 3.6 V,
IOUT = 80 mA
ICOIL = 100 mA/div
ICOIL = 200 mA/div
IIN = 50 mA/div
IIN = 100 mA/div
VIN = 5 V,
VOUT = 3.6 V,
IOUT = 500 mA
t - Time - 10 ms/div
t - Time - 10 ms/div
Figure 23. Startup After Enable
Figure 24. Startup After Enable
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EN = 5 V/div
VIN = 5 V,
VOUT = 3.6 V,
IOUT = no load
VOUT = 1 mV/div
ICOIL = 200 mA/div
t - Time - 200 ms/div
Figure 25. Output Discharge
14
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DETAILED DESCRIPTION
OPERATION
The TPS6275x step down converter operates with typically 2.25MHz fixed frequency pulse width modulation
(PWM) at moderate to heavy load currents. At light load currents the converter can automatically enter Power
Save Mode and operates then in PFM (Pulse Frequency Mode) mode.
During PWM operation, the converter uses a unique fast response voltage mode controller scheme with input
voltage feed-forward to achieve good line and load regulation allowing the use of small ceramic input and output
capacitors. At the beginning of each clock cycle initiated by the clock signal, the High Side MOSFET switch is
turned on. The current flows from the input capacitor via the High Side MOSFET switch through the inductor to
the output capacitor and load. During this phase, the current ramps up until the PWM comparator trips and the
control logic will turn off the switch.
The current limit comparator will also turn off the switch in case the current limit of the High Side MOSFET switch
is exceeded. After a dead time preventing shoot through current, the Low Side MOSFET rectifier is turned on
and the inductor current will ramp down. The current flows now from the inductor to the output capacitor and to
the load. It returns back to the inductor through the Low Side MOSFET rectifier.
The next cycle will be initiated by the clock signal again turning off the Low Side MOSFET rectifier and turning on
the on the High Side MOSFET switch.
POWER SAVE MODE
If the load current decreases, the converter will enter Power Save Mode operation automatically. During Power
Save Mode the converter skips switching and operates with reduced frequency in PFM mode with a minimum
quiescent current to maintain high efficiency.
The transition from PWM mode to PFM mode occurs once the inductor current in the Low Side MOSFET switch
becomes zero, which indicates discontinuous conduction mode.
During the Power Save Mode the output voltage is monitored with a PFM comparator. As the output voltage falls
below the PFM comparator threshold of VOUT nominal +1%, the device starts a PFM current pulse. For this the
High Side MOSFET switch will turn on and the inductor current ramps up. After the On-time expires the switch
will be turned off and the Low Side MOSFET switch will be turned on until the inductor current becomes zero.
The converter effectively delivers a current to the output capacitor and the load. If the load is below the delivered
current the output voltage will rise. If the output voltage is equal or higher than the PFM comparator threshold,
the device stops switching and enters a sleep mode.
In case the output voltage is still below the PFM comparator threshold, further PFM current pulses will be
generated until the PFM comparator threshold is reached. The converter starts switching again once the output
voltage drops below the PFM comparator threshold.
With a fast single threshold comparator, the output voltage ripple during PFM mode operation can be kept very
small. The PFM Pulse is timing controlled, which allows to modify the charge transferred to the output capacitor
by the value of the inductor. The resulting PFM output voltage ripple depends in first order on the size of the
output capacitor and the inductor value. Increasing output capacitor values and/or inductor values will minimize
the output ripple.
The PFM mode is left and PWM mode entered in case the output current can not longer be supported in PFM
mode.
ENABLE
The device is enabled setting EN pin to high. During the start up time tstart-up the internal circuits are settled.
Afterwards the device activates the soft start circuit. The EN input can be used to control power sequencing in a
system with various DC/DC converters.
The EN pin can be connected to the output of another converter, to drive the EN pin high and getting a
sequencing of supply rails. With EN = GND, the device enters shutdown mode. In this mode, all circuits are
disabled. In fixed output voltage versions, the internal resistor divider network is disconnected from FB pin.
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OUTPUT CAPACITOR DISCHARGE
With EN = GND, the device enters shutdown mode and all internal circuits are disabled. The SW pin is
connected to PGND via an internal resistor (typically 235Ω) to discharge the output capacitor.
SOFT START
The TPS62750 has an internal soft start circuit that controls the ramp up of the output voltage. The output
voltage ramps up from 5% to 95% of its nominal value in a controlled manner. This limits the inrush of current in
the converter during start-up and prevents possible voltage drops when a battery or high impedance power
source is used.
During soft start, the target average input current limit is reduced to 1/3 of its nominal value (ILIM_L or ILIM_U) until
the output voltage reaches 1/3 of its nominal value. Once the output voltage trips this threshold, the device
operates with its set target average input current limit.
The Soft-Start circuit is enabled after the start-up time tstart-up has expired.
HOT-PLUG PROTECTION
In many applications it may be necessary to remove modules or pc boards while the main unit is still operating.
These are considered hot-plug applications. Such implementations require the control of current surges seen by
the main power supply and the card being inserted. The most effective way to control these surges is to limit and
slowly ramp the current and voltage being applied to the card, similar to the way in which a power supply
normally turns on.
Due to the controlled rise times and fall times and input over-voltage clamping of the TPS62750, these devices
can be used to provide a softer start-up to devices being hot-plugged into a powered system. The UVLO feature
of the TPS62750 also ensures that the switch is off after the card has been removed, and that the switch is off
during the next insertion. The UVLO feature insures a soft start with a controlled rise time for every insertion of
the card or module.
REVERSE CURRENT PROTECTION
The USB specification does not allow an output device to source current back into the USB port. However, the
TPS62750 is designed to safely power non-compliant devices. When disabled, each output is switched to a
high-impedance state, blocking reverse current flow from the output back to the input.
SHORT-CIRCUIT PROTECTION
During normal operation the High Side and Low Side MOSFET switches are protected by its current limits ILIMF.
Once the High Side MOSFET switch reaches its current limit, it is turned off and the Low Side MOSFET switch is
turned on. The High Side MOSFET switch can only turn on again, once the current in the Low Side MOSFET
switch decreases below its current limit. The device is capable to provide peak inductor currents up to its internal
current limit ILIMF.
As soon as the output voltage falls below 1/3 of the nominal output voltage due to overload or short circuit
condition, the converter current limit is reduced to 1/3 of the nominal value ILIMF. Due to the short-circuit
protection is enabled during start-up, the device does not deliver more than 1/3 of its nominal current limit ILIMF
until the output voltage exceeds 1/3 of the nominal output voltage. This needs to be considered when a load is
connected to the output of the converter, which acts as a current sink.
THERMAL SHUTDOWN
As soon as the junction temperature, TJ, exceeds 150°C (typical) the device goes into thermal shutdown. In this
mode, the High Side and Low Side MOSFETs are turned-off. The device continues its operation when the
junction temperature falls below the thermal shutdown hysteresis.
16
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APPLICATION INFORMATION
Wireless Module
PA
TPS62750
USB
5.0V
ILIM_U
ILIM_L
C IN
10µF
R LIM_U
3.7V
R1
AV IN
EN
2.2µH
Wireless
BB + PMIC
VOUT
VIN
FB
H/L
GND
PGND
R2
Cff
CO
CBUFF
RLIM_L
PMU, DCDC, LDO
Figure 26. TPS62750DSK in a typical USB Datacard application
A growing variety of applications in notebooks, PCs and other mobile systems, TDMA data communication
techniques, which require peak current (typically 2A) during the transmission of signals that can exceed the
maximum current specified by the USB standard. Therefore, the application must be designed to limit the input
power and draw on card-based storage for most of the energy requirement during a typical transmission cycle.
A typical GSM signal is transmitted over the carrier at a rate of 216 Hz (4.616ms pulse repetition interval). The
transmission period is divided into eight time slots and depending on the power class being used, the duty cycle
of this high current pulse can range anywhere between one-eighth of the cycle (577us) up to half of the
transmission cycle (2.308ms).
The TPS62750 external current limit programming resistors can be easily used to adjust the required input
current limit, thereby allowing the user to stay well within the specification requirement stipulated by USB. The
TPS62750 is a high efficiency buck converter with programmable input average current limit that provides the
needed flexibility when designing a GSM/GPRS power supply solution. The high efficiency of the converter
maximizes the average output power without overloading the bus. A bulk output capacitor is used to supply the
energy and maintain the output voltage during the high current pulses
OUTPUT VOLTAGE SETTING
æ
R ö
VOUT = VREF ´ ç 1 + 1 ÷ with an internal reference voltage VREF typical 0.6V
R2 ø
è
(1)
To minimize the current through the feedback divider network, we recommend that the R2 resistor value be 180k.
The sum of R1 and R2 should not exceed ~1.5MΩ, to keep the network robust against noise.
An external feed forward capacitor Cff is required for optimum load transient response. The value of Cff should be
a minimum of 470pF (see table below). Route the FB line away from noise sources, such as the inductor or the
SW line.
OUTPUT CAPACITOR
FEEDFORWARD CAPACITOR
1 mF – 2.5 mF
470 pF
> 2.5 mF
1 nF
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INDUCTOR SELECTION
The inductor value has a direct effect on the ripple current. The selected inductor has to be rated for its dc
resistance and saturation current. The inductor ripple current (ΔIL) decreases with higher inductance and
increases with higher VIN or VOUT.
The inductor selection has also impact on the output voltage ripple in PFM mode. Higher inductor values will lead
to lower output voltage ripple and higher PFM frequency, lower inductor values will lead to a higher output
voltage ripple but lower PFM frequency.
Equation 2 calculates the maximum inductor current under static load conditions. The saturation current of the
inductor should be rated higher than the maximum inductor current as calculated with Equation 3. This is
recommended because during heavy load transient the inductor current will rise above the calculated value.
Vout
1Vin
D IL = Vout ´
L ´ ¦
(2)
ILmax = Ioutmax +
DIL
2
(3)
With:
f = Switching Frequency (2.25MHz typical)
L = Inductor Value
ΔIL= Peak to Peak inductor ripple current
ILmax = Maximum Inductor current
A more conservative approach is to select the inductor current rating just for the maximum switch current of the
corresponding converter. Accepting larger values of ripple current allows the use of low inductance values, but
results in higher output voltage ripple, greater core losses, and lower output current capability. The device has
been optimized to operate with inductance values between 1.0μH and 4.7μH. It is recommended that inductance
values of at least 1.0μH is used, even if Equations 2 and 3 yield something lower.
The total losses of the coil have a strong impact on the efficiency of the DC/DC conversion and consist of both
the losses in the dc resistance (R(DC)) and the following frequency-dependent components:
• The losses in the core material (magnetic hysteresis loss, especially at high switching frequencies)
• Additional losses in the conductor from the skin effect (current displacement at high frequencies)
• Magnetic field losses of the neighboring windings (proximity effect)
• Radiation losses
Table 3. List of Inductors
MANUFACTURER
INDUCTOR TYPE
DIMENSIONS [mm]
Coilcraft
LPS3015-222ML
3.0 x 3.0 x 1.5
TOKO
1127AS-2R2M
3.5 x 3.7 x 1.8
Murata
LQH32PN1R0N0
3.2 x 2.5 x 1.7
TOKO
DB3015 Series
3.2 x 3.2 x 1.5
INPUT CAPACITOR SELECTION
Because of the nature of the buck converter having a pulsating input current, a low ESR input capacitor is
required for best input voltage filtering and minimizing the interference with other circuits caused by high
input voltage spikes. For most applications a 4.7μF to 10μF ceramic capacitor is recommended. The input
capacitor can be increased without any limit for better input voltage filtering.
Take care when using only small ceramic input capacitors. When a ceramic capacitor is used at the input
and the power is being supplied through long wires, such as from a wall adapter, a load step at the output or
VIN step on the input can induce ringing at the VIN pin. This ringing can couple to the output and be
mistaken as loop instability or could even damage the part by exceeding the maximum ratings.
18
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OUTPUT CAPACITOR SELECTION
The TPS62750 has been specifically internally compensated to operate with large capacitance values. But to
maintain loop stability of the device, it is recommended to use a small ceramic capacitor placed as close as
possible to the VOUT and GND pins of the IC in parallel with the large holdup capacitor. To get an estimate of the
small ceramic recommended minimum output capacitance, Equation 4 can be used.
(
I
× VOUT - VIN
Cmin = OUT
f × ΔV × VOUT
)
(4)
Parameter f is the switching frequency and ΔV is the maximum allowed ripple.
With a chosen ripple voltage of 10 mV, a minimum effective capacitance of 2.7 μF is needed. The total ripple is
larger due to the ESR of the output capacitor. This additional component of the ripple can be calculated using Δ
VESR = IOUT x RESR.
A capacitor with a value in the range of the calculated minimum should be used. This is required to maintain
control loop stability. There are no additional requirements regarding minimum ESR. There is no upper limit for
the output capacitance value. Larger capacitors cause lower output voltage ripple as well as lower output voltage
drop during load transients.
Note that ceramic capacitors have a DC Bias effect, which will have a strong influence on the final effective
capacitance needed. Therefore the right capacitor value has to be chosen very carefully. Package size and
voltage rating in combination with material are responsible for differences between the rated capacitor value and
the effective capacitance.
To calculate the value of the effective capacitance required to buffer a GSM transmission pulse, the following
equations can be used:
Capacitance =
I× Dt
DV
(5)
Assuming the DCDC supplies ~700mA, the rest of the energy to supply the GSM transmission pulse must come
from the capacitor.
ICAP = IGSM - IDCDC
ICAP = 2A - 700mA = 1.3A
Assuming a GSM transmission pulse width of 1.154ms and allowing a maximum voltage drop on the output of
350mV, the effective capacitance required is:
Capacitance =
1.3A ×1.154ms
= 4.2mF
350mV
(6)
Table 4. List of Capacitors
COMPONENT REFERENCE
PART NUMBER
MANUFACTURER
VALUE
CO
GRM188R60J106M69D
Murata
10μF
6TPG150M
Sanyo POSCAP
150μF
CBULK
592D158X06R3X2T25H
Vishay
1.5mF
592D228X06R3X2T22H
Vishay
2.2mF
AVERAGE INPUT CURRENT LIMIT
The average input current is set by selecting the correct external resistor value correlating to the required current
limit. The current limit can be selected between a high current limit (ILIM_U) and a lower limit (ILIM_L) by toggling
the H/L pin high or low. This has the added benefit that of allowing a device first plugged into the USB port to
enumerate at 100mA before switching over to the high power mode (500mA). The equations below are a
guideline for selecting the correct resistor value:
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æ 1.23
Upper range: RLIM_U = ç
ç ILIM_U
è
ö
÷ ´ 20000
÷
ø
(7)
æ 1.23
= ç
ç ILIM_L
è
ö
÷ ´ 5400
÷
ø
(8)
Lower range: RLIM_L
Examples of different input current limit values selectable are given in the table below:
AVERAGE INPUT
CURRENT REQUIRED
RESISTOR VALUE
50 mA
132.8 K
100 mA
66.5 K
400 mA
61.5 K
500 mA
49.2 K
600 mA
41 K
700 mA
35.1 K
CHECKING LOOP STABILITY
The first step of circuit and stability evaluation is to look from a steady-state perspective at the following signals:
• Switching node, SW
• Inductor current, IL
• Output ripple voltage, VO(AC)
These are the basic signals that need to be measured when evaluating a switching converter. When the
switching waveform shows large duty cycle jitter or the output voltage or inductor current shows oscillations, the
regulation loop may be unstable. This is often a result of board layout and/or L-C combination.
As a next step in the evaluation of the regulation loop, the load transient response is tested. The time between
the application of the load transient and the turn on of the P-channel MOSFET, the output capacitor must supply
all of the current required by the load. VO immediately shifts by an amount equal to ΔI(LOAD) × ESR, where ESR is
the effective series resistance of CO. ΔI(LOAD) begins to charge or discharge CO generating a feedback error
signal used by the regulator to return VO to its steady-state value. The results are most easily interpreted when
the device operates in PWM mode.
During this recovery time, VO can be monitored for settling time, overshoot or ringing that helps judge the
converter’s stability. Without any ringing, the loop has usually more than 45° of phase margin. Because the
damping factor of the circuitry is directly related to several resistive parameters (e.g., MOSFET RDSon) that are
temperature dependant, the loop stability analysis has to be done over the input voltage range, load current
range, and temperature range.
+
+
Ω
470pF
Ω
Ω
Ω
Ω
Ω
Figure 27. Checking Loop Stability
20
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LAYOUT CONSIDERATIONS
As for all switching power supplies, the layout is an important step in the design. Proper function of the device
demands careful attention to PCB layout. Care must be taken in board layout to get the specified performance. If
the layout is not carefully done, the regulator could show poor line and/or load regulation, stability issues as well
as EMI problems. It is critical to provide a low inductance, impedance ground path. Therefore, use wide and
short traces for the main current paths. The input capacitor should be placed as close as possible to the IC pins
as well as the inductor and output capacitor.
Connect the GND Pin of the device to the Power Pad of the PCB and use this Pad as a star point. Use a
common Power GND node and a different node for the Signal GND to minimize the effects of ground noise.
Connect these ground nodes together to the Power Pad (star point) underneath the IC. Keep the common path
to the GND PIN, which returns the small signal components and the high current of the output capacitors as
short as possible to avoid ground noise. The FB line should be connected right to the output capacitor and routed
away from noisy components and traces (e.g., SW line).
R2
R3
C3
R4
R1
VIN
COUT
CIN
GND
VOUT
L1
Current select
Enable
Figure 28. Suggested Layout
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THERMAL INFORMATION
Implementation of integrated circuits in low-profile and fine-pitch surface-mount packages typically requires
special attention to power dissipation. Many system-dependant issues such as thermal coupling, airflow, added
heat sinks, and convection surfaces, and the presence of other heat-generating components, affect the
power-dissipation limits of a given component. Three basic approaches for enhancing thermal performance are
listed below:
•
•
•
Improving the power dissipation capability of the PCB design
Improving the thermal coupling of the component to the PCB
Introducing airflow into the system
For more details on how to use the thermal parameters in the dissipation ratings table please check the Thermal
Characteristics Application Note (SZZA017) and the IC Package Thermal Metrics Application Note (SPRA953).
22
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Changes from Original (July 2009) to Revision A ........................................................................................................... Page
•
Added TPS62751 device ...................................................................................................................................................... 1
•
Added TPS62751 specification ............................................................................................................................................. 2
•
Added TPS62751 specification ............................................................................................................................................. 3
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PACKAGE OPTION ADDENDUM
www.ti.com
23-Apr-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS62750DSKR
ACTIVE
SON
DSK
10
3000
RoHS & Green NIPDAU | NIPDAUAG
Level-1-260C-UNLIM
-40 to 85
NXJ
TPS62750DSKT
ACTIVE
SON
DSK
10
250
RoHS & Green NIPDAU | NIPDAUAG
Level-1-260C-UNLIM
-40 to 85
NXJ
TPS62751DSKR
ACTIVE
SON
DSK
10
3000
RoHS & Green
NIPDAUAG
Level-1-260C-UNLIM
-40 to 85
DAL
TPS62751DSKT
ACTIVE
SON
DSK
10
250
RoHS & Green
NIPDAUAG
Level-1-260C-UNLIM
-40 to 85
DAL
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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