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TPS65011
SLVS501B – FEBRUARY 2004 – REVISED SEPTEMBER 2015
TPS65011 Power and Battery Management IC For Li-Ion Powered Systems
1 Features
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Linear Charger Management for Single Li-Ion or
Li-Polymer Cells
Dual Input Ports for Charging and From USB or
From Wall Plug, Handles 100-mA / 500-mA USB
Requirements
Charge Current Programmable Via External
Resistor
1-A, 95% Efficient Step-Down Converter for I/O
and Peripheral Components (VMAIN)
400-mA, 90% Efficient Step-Down Converter for
Processor Core (VCORE)
2x 200-mA LDOs for I/O and Peripheral
Components, LDO Enable via Bus
Serial Interface Compatible With I2C, Supports
100-kHz, 400-kHz Operation
LOW_PWR Pin to Lower or Disable Processor
Core Supply Voltage in Deep Sleep Mode
70-µA Quiescent Current
1% Reference Voltage
Thermal Shutdown Protection
2 Applications
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All Single Li-Ion Cell-Operated Products Requiring
Multiple Supplies Including:
– PDA
– Cellular and Smart Phone
– Internet Audio Player
– Digital Still Camera
Digital Radio Player
Split Supply DSP and µP Solutions
The TPS65011 also has a highly integrated and
flexible Li-Ion linear charger and system power
management. It offers integrated USB-port and ACadapter supply management with autonomous powersource selection, power FET and current sensor, high
accuracy current and voltage regulation, charge
status, and charge termination.
Device Information(1)
PART NUMBER
TPS65011
PACKAGE
VQFN (48)
BODY SIZE (NOM)
7.00 mm × 7.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Key Graphic
MAX(AC,USB,VBAT)
AC
VBAT
USB
PG
Linear Charge Controller
ISET
TS
SCLK
SDAT
AGND2
Serial
Interface
IFLSB
Thermal
Shutdown
VINMAIN
PS_SEQ
LOW_PWR
PB_ONOFF
BATT_COVER
HOT_RESET
TPOR
VMAIN
Control
Step-Down
Converter
RESPWRON
MPU_RESET
VCC
AGND3
VINCORE
INT
PWRFAIL
GPIO1
GPIO2
GPIO3
GPIO4
VIB
UVLO
VREF
OSC
L2
VCORE
VCORE
Step-Down
Converter
The TPS65011 device is an integrated power and
battery management IC for applications powered by
one Li-Ion or Li-Polymer cell and which require
multiple power rails. The TPS65011 provides two
highly efficient, 1.25-MHz step-down converters
targeted at providing the core voltage and peripheral,
I/O rails in a processor-based system. Both stepdown converters enter a low-power mode at light load
for maximum efficiency across the widest possible
range of load currents.
DEFCORE
PGND2
GPIOs
VINLDO1
VLDO1
200-mA LDO
3 Description
L1
VMAIN
DEFMAIN
PGND1
VLDO1
VFB_LDO1
AGND1
LED2
VINLDO2
VLDO2
VLDO2
200-mA LDO
The TPS65011 also integrates two 200-mA LDO
voltage regulators, which are enabled via the serial
interface. Each LDO operates with an input voltage
range between 1.8 V and 6.5 V, allowing them to be
supplied from one of the step-down converters or
directly from the battery.
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS65011
SLVS501B – FEBRUARY 2004 – REVISED SEPTEMBER 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
7
1
1
1
2
3
5
Absolute Maximum Ratings ...................................... 5
ESD Ratings.............................................................. 5
Recommended Operating Conditions....................... 5
Thermal Information .................................................. 6
Electrical Characteristics........................................... 6
Battery Charger Electrical Characteristics ................ 9
Serial Interface Timing Requirements..................... 11
Dissipation Ratings ................................................ 11
Typical Characteristics ............................................ 12
Detailed Description ............................................ 17
7.1 Overview ................................................................. 17
7.2 Functional Block Diagram ....................................... 18
7.3 Feature Description................................................. 19
7.4 Device Functional Modes........................................ 27
7.5 Programming........................................................... 35
7.6 Register Maps ......................................................... 40
8
Application and Implementation ........................ 48
8.1 Application Information............................................ 48
8.2 Typical Applications ................................................ 49
8.3 System Examples ................................................... 52
9
Power Supply Recommendations...................... 53
9.1 LDO1 Output Voltage Adjustment........................... 53
10 Layout................................................................... 53
10.1 Layout Guidelines ................................................. 53
10.2 Layout Example .................................................... 54
11 Device and Documentation Support ................. 55
11.1
11.2
11.3
11.4
11.5
Third-Party Products Disclaimer ...........................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
55
55
55
55
55
12 Mechanical, Packaging, and Orderable
Information ........................................................... 55
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (January 2005) to Revision B
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2
Page
Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1
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SLVS501B – FEBRUARY 2004 – REVISED SEPTEMBER 2015
5 Pin Configuration and Functions
LOW_PWR
INT
PWRFAIL
RESPWRON
MPU_RESET
HOT_RESET
SCLK
SDAT
IFLSB
TPOR
GPIO1
GPIO2
36
35
34
33
32
31
30
29
28
27
26
25
RGZ Package
48-Pin VQFN With Exposed Thermal Pad
Top View
ISET 37
24
VLDO1
TS
38
23
VFB_LDO1
BATT_COVER
39
22
VINLDO1
AC
40
21
AGND1
VBAT_A
41
20
VLDO2
VBAT_B
42
19
VINLDO2
USB
43
18
GPIO3
AGND2
44
17
GPIO4
AGND3
45
16
PGND1_B
PGND2
46
15
PGND1_A
PB_ONOFF
47
14
PS_SEQ
VCORE
48
13
VMAIN
4
5
6
7
8
9
10
L2
VINCORE
VCC
VINMAIN_A
VINMAIN_B
L1_A
L1_B
12
3
VIB
DEFMAIN
2
LED2
PG 11
1
DEFCORE
Thermal
Pad
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SLVS501B – FEBRUARY 2004 – REVISED SEPTEMBER 2015
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Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
Charger input voltage from AC adapter. The AC pin can be left open or can be connected to
ground if the charger is not used.
CHARGER SECTION
AC
40
I
AGND2
44
—
ISET
37
I
External charge current setting resistor connection for use with AC adapter
PG
11
O
Indicates when a valid power supply is present for the charger (open drain)
Thermal Pad
Analog ground connection. All analog ground pins are connected internally on the chip.
-
—
Connect the thermal pad to GND
TS
38
I
Battery temperature sense input
USB
43
I
Charger input voltage from USB port. The USB pin can be left open or can be connected to
ground if the charger is not used.
VBAT_A
41
I
Sense input for the battery voltage. Connect directly with the battery.
VBAT_B
42
O
Power output of the battery charger. Connect directly with the battery.
—
Analog ground connection. All analog ground pins are connected internally on the chip.
—
Switch pin of VMAIN converter. The VMAIN inductor is connected here.
—
Switch pin of VCORE converter. The VCORE inductor is connected here.
—
Power ground for VMAIN converter
Power ground for VCORE converter
SWITCHING REGULATOR SECTION
AGND3
45
L1_A
9
L1_B
10
L2
4
PGND1_A
15
PGND1_B
16
PGND2
46
—
VCC
6
I
Power supply for digital and analog circuitry of MAIN and CORE DC-DC converters. This
must be connected to the same voltage supply as VINCORE and VINMAIN. Also supplies
serial interface block
VCORE
48
I
VCORE feedback voltage sense input, connect directly to VCORE
VINCORE
5
I
Input voltage for VCORE step-down converter. This must be connected to the same voltage
supply as VINMAIN and VCC.
VINMAIN_A
7
VINMAIN_B
8
I
Input voltage for VMAIN step-down converter. This must be connected to the same voltage
supply as VINCORE and VCC.
VMAIN
13
I
VMAIN feedback voltage sense input, connect directly to VMAIN
LDO REGULATOR SECTION
AGND1
21
—
VFB_LDO1
23
I
Analog ground connection. All analog ground pins are connected internally on the chip.
Feedback input from external resistive divider for LDO1
VINLDO1
22
I
Input voltage for LDO1
VINLDO2
19
I
Input voltage for LDO2
VLDO1
24
O
Output voltage for LDO1
VLDO2
20
O
Output and feedback voltage for LDO2
LED2
2
O
LED driver, with blink rate programmable via serial interface
VIB
3
O
Vibrator driver, enabled via serial interface
DRIVER SECTION
CONTROL AND I2C SECTION
BATT_COVER
39
I
Indicates if battery cover is in place
DEFCORE
1
I
Input signal indicating default VCORE voltage, 0 = 1.3 V, 1 = 1.6 V
DEFMAIN
12
I
Input signal indicating default VMAIN voltage, 0 = 1.8 V, 1 = 3.3 V
GPIO1
26
I/O
General-purpose open-drain input/output
GPIO2
25
I/O
General-purpose open-drain input/output
GPIO3
18
I/O
General-purpose open-drain input/output
GPIO4
17
I/O
General-purpose open-drain input/output
HOT_RESET
31
I
4
Push-button reset input used to reboot or wakeup processor via TPS65013
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Pin Functions (continued)
PIN
NAME
I/O
NO.
DESCRIPTION
IFLSB
28
I
LSB of serial interface address used to distinguish two devices with the same address
INT
35
O
Indicates a charge fault or termination, or if any of the regulator outputs are below the lower
tolerance level, active low (open drain)
LOW_PWR
36
I
Input signal indicating deep-sleep mode, VCORE is lowered to predefined value or disabled
MPU_RESET
32
O
Open-drain reset output generated by user activated HOT_RESET
PB_ONOFF
47
I
Push-button enable pin, also used to wakeup processor from low-power mode
PS_SEQ
14
I
Sets power-up/down sequence of step-down converters
PWRFAIL
34
O
Open-drain output. Active low when UVLO comparator indicates low VBAT condition or
when shutdown is about to occur due to an overtemperature condition or when the battery
cover is removed (BATT_COVER has gone low).
RESPWRON
33
O
Open-drain system reset output, generated according to the state of the VMAIN output
voltage. If the main output is disabled, RESPWRON is active (i.e., low).
SCLK
30
I
Serial interface clock line
SDAT
29
I/O
TPOR
27
I
Serial interface data/address
Sets the reset delay time at RESPWRON. TPOR = 0: Tn(RESPWRON) = 100 ms.
TPOR = 1: Tn(RESPWRON) = 1 s.
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range unless otherwise noted (1)
MIN
Input voltage on VAC pin with respect to AGND
Input voltage range on all other pins except AGND/PGND pins with respect to AGND
-0.3
MAX
UNIT
20
V
7
V
1
kV
Current at AC, VBAT, VINMAIN, L1, PGND1
1800
mA
Peak current at all other pins
1000
mA
Continuous power dissipation
See Dissipation
Ratings
Operating free-air temperature, TA
-40
HBM and CDM capabilities at pins VIB, PG, and LED2
Maximum junction temperature, TJ
Storage temperature range, Tstg
(1)
-65
85
°C
125
°C
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001
V(ESD)
(1)
(2)
Electrostatic discharge
(1)
Charged device model (CDM), per JEDEC specification JESD22C101 (2)
VALUE
UNIT
1000
V
1000
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
MIN
NOM
MAX
UNIT
V(AC)
Supply voltage from AC adapter
4.5
5.5
V
V(USB)
Supply voltage from USB
4.4
5.25
V
V(BAT)
Voltage at battery charger
2.5
4.2
V
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Recommended Operating Conditions (continued)
MIN
NOM
MAX
UNIT
VI(MAIN),VI(CORE),VCC
Input voltage range step-down converters
2.5
6.0
V
VI(LDO1), VI(LDO2)
Input voltage range for LDOs
1.8
6.5
V
TA
Operating ambient temperature
-40
85
°C
TJ
Operating junction temperature
-40
125
°C
R(CC)
Resistor from VI(main),VI(core) to VCC used for
filtering, CI(VCC) = 1 µF
100
Ω
10
6.4 Thermal Information
TPS65011
THERMAL METRIC
(1)
RGZ (VQFN)
UNIT
48 PIN
RθJA
Junction-to-ambient thermal resistance
27.0
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
14.3
°C/W
RθJB
Junction-to-board thermal resistance
4.6
°C/W
ψJT
Junction-to-top characterization parameter
0.2
°C/W
ψJB
Junction-to-board characterization parameter
4.6
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
1.1
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.5 Electrical Characteristics
VI(MAIN) = VI(CORE) = VCC = VI(LDO1) = VI(LDO2) = 3.6 V, TA = -40°C to 85°C, typical values are at TA = 25°C battery charger
specifications are valid in the range 0°C V(DO-MAX),
I2C register CHGCONFIG = 0
80
100
mA
V(CHG)min ≥ 4.5 V, VI(BAT) > V(LOWV),
VUSB - VI(BAT) > V(DO-MAX),
I2C register CHGCONFIG = 1
400
500
mA
825
8250
Ω
Resistor range at ISET pin
PRECHARGE CURRENT REGULATION, SHORT-CIRCUIT CURRENT, AND BATTERY DETECTION CURRENT
V(LOWV)
Precharge to fast-charge transition threshold,
voltage on VBAT pin.
V(CHG)min ≥ 4.5V
2.8
3.0
3.2
V
De-glitch time
V(CHG)min ≥ 4.5 V, VI(OUT) decreasing
below threshold; 100-ns fall time, 10mV overdrive
8.8
23
60
ms
0 ≤ VI(OUT) < V(LOWV), t < t(PRECHG)
10
100
mA
270
mV
(2)
I(PRECHG)
Precharge current
I(DETECT)
Battery detection current
V(SET-PRECHG)
Voltage at ISET pin
IO(AC) =
0 ≤ VI(OUT) < V(LOWV), t < t(PRECHG)
240
255
µA
KSET ´ V(SET)
(1)
I(PRECHG) =
(2)
200
R(ISET)
KSET ´ V(SET _ PRECHG)
R(ISET)
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Battery Charger Electrical Characteristics (continued)
VO(REG) + V(DO-MAX)≤ V(CHG) = V(AC) or V(USB), I(TERM) V(RCH), t < t(TAPER)
10
V(SET_TAPER)
Voltage at ISET pin for charge TAPER
detection
VI(OUT) > V(RCH), t < t(TAPER)
235
250
265
mV
V(SET_TERM)
Voltage at ISET pin for charger termination
detection (4)
VI(OUT) > V(RCH)
11
18
25
mV
De-glitch time for I(TAPER)
V(CHG)min ≥ 4.5V, charging current
increasing or decreasing above and
below; 100-ns fall time, 10-mV
overdrive
8.8
23
60
ms
De-glitch time for I(TERM)
V(CHG)min ≥ 4.5 V, charging current
decreasing below;100-ns fall time,
10-mV overdrive
8.8
23
60
ms
2.50
2.525
TEMPERATURE COMPARATOR
V(LTF)
Low (cold) temperature threshold
2.475
V
V(HTF)
High (hot) temperature threshold
0.485
0.5
0.515
V
I(TS)
TS current source
95
102
110
µA
De-glitch time for temperature fault
8.8
23
60
ms
VO(REG) 0.115
VO(REG) 0.1
VO(REG) 0.085
8.8
23
60
BATTERY RECHARGE THRESHOLD
V(RCH)
Recharge threshold
V(CHG)min≥ 4.5 V
V
De-glitch time
V(CHG)min ≥ 4.5 V, VI(OUT) decreasing
below threshold; 100-ns fall time,
10-mV overdrive
t(PRECHG)
Precharge timer
V(CHG)min ≥ 4.5 V
1500
1800
2160
s
t(TAPER)
Taper timer
V(CHG)min≥ 4.5 V
1500
1800
2160
s
t(CHG)
Charge timer
V(CHG)min≥ 4.5 V
15000
18000
21600
s
V(CHG)≤
VI(OUT)
+150 mV
V
ms
TIMERS
SLEEP AND STANDBY
V(SLP-ENTRY)
Sleep-mode entry threshold, PG output =
high
2.3 V≤ VI(OUT) ≤ VO(REG)
V(SLP_EXIT)
Sleep-mode exit threshold,PG output = low
2.3 V≤ VI(OUT)≤ VO(REG)
De-glitch time for sleep mode entry and exit
AC or USB decreasing below
threshold; 100-ns fall time, 10-mV
overdrive
V(CHG)≥
VI(OUT)+19
0 mV
8.8
Delay between valid USB voltage being
applied and start of charging process from
USB
t(USB_DEL)
V
23
60
5
ms
ms
CHARGER POWER-ON-RESET, UVLO, AND V(IN) RAMP RATE
V(CHGUVLO)
Charger undervoltage lockout
V(CHG) decreasing
Hysteresis
V(CHGOVLO)
2.27
2.5
2.75
27
Charger overvoltage lockout
V(AC) increasing
6.6
Hysteresis
V
mV
V
0.5
V
CHARGER OVERTEMPERATURE SUSPEND
T(suspend)
Temperature at which charger suspends
operation
T(hyst)
Hysteresis of suspend threshold
145
°C
20
°C
LOGIC SIGNALS DEFMAIN, DEFCORE, PS_SEQ, IFLSB
I(TAPER) =
(3)
I(TERM) =
(4)
10
KSET ´ V(SET _ TAPER)
R(ISET)
KSET ´ V(SET _ TERM)
R(ISET)
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Battery Charger Electrical Characteristics (continued)
VO(REG) + V(DO-MAX)≤ V(CHG) = V(AC) or V(USB), I(TERM) UVOL,
TjUVLO ?
BATT_COVER
High ?
UVLO_TEMP
Timer Done ?
No
VCC>UVLO ?
BATT_COVER
High ?
Release
RESPWRON,
PWRFAIL, INT,
MPU_RESET
Yes
Yes
Value
PS_SEQ ?
1
0
Shutdown VCORE,
VMAIN + LDOs
According to
PS_SEQ
Yes
Boot VCORE
Converter + LDOs
Boot VMAIN
Converter + LDOs
Boot VCORE
Converter
Boot VCORE
Converter
LOW_PWR
De-asserted,
PB_ONOFF
Button Pressed
Processor Initiated
Shutdown ∗3
LOW_
POWER
Mode
LOW_PWR
Asserted ∗2
ON
HOT_RESET
Button Pressed
∗1: All registers are reset to their default values in WAIT Mode
∗2: ENABLE_LP bit, VDCDC1 Must be set.
If AC or USB power is present, AUA bit, CHGCONFIG must also be set.
Raise the low power pin to enter low power mode.
∗3: ENABLE_SUPPLY bit, VDCDC1 must be cleared.
ENABLE_LP bit, VDCDC1 must be set.
LDO2OFF/SLP and LDO1OFF/SLP must be set or LDOs and voltage
reference remain enabled and registers not reset.
If AC or USB power is present, AUA bit, CHGCONFIG must also be set.
Raise the low power pin to enter low power mode.
ENABLE_LP default: cleared
ENABLE_SUPPLY default: set
AUA default: cleared
LDO1OFF/SLP default: cleared
LDO2OFF/SLP default: cleared
No
Release
MPU_RESET
VCORE Voltage
Good ?
Yes
Yes
MPU_RESET
Timer Done ?
Set MPU_RESET
Low, Start
MPU_RESET Timer
No
Figure 29. TPS65011 Power-On State Diagram
7.3.6 System Reset and Control Signals
The RESPWRON signal is used as a global reset for the application. It is an open drain output. The
RESPWRON signal is generated according to the Power Good comparator linked to VMAIN and remains low for
tn(RESPWRON) seconds after VMAIN has stabilized. When RESPWRON is low, PWRFAIL, MPU_RESET and INT
are also held low.
26
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If the output voltage of MAIN is less than 90% of its nominal value, as RESPWRON is generated, and if the
output voltage of MAIN is programmed to a higher value, which causes the output voltage to fall out of the 90%
window, then a RESPWRON signal is generated.
The PWRFAIL signal indicates when VCC < UVLO or when the TPS65011 junction temperature has exceeded a
reliable value or if BATT_COVER is taken low. This open drain output can be connected at a fast interrupt pin for
immediate attention by the application processor. All supplies are disabled t(uvlo), t(overtemp) or t(batt_cover) seconds
after PWRFAIL has gone low, giving time for the application processor to shut down cleanly.
BATT_COVER is used to detect whether the battery cover is in place or not. If the battery cover is removed, the
TPS65011 generates a warning to the processor that the battery is likely to be removed and that it may be
prudent to shut down the system. If not required, this feature may be disabled by connecting the BATT_COVER
pin to the VCC pin. BATT_COVER is de-bounced internally. Typical de-bounce time is 56 ms. BATT_COVER
has an internal 2-MΩ pulldown resistor.
The HOT_RESET input is used to generate an MPU_RESET signal for the application processor. The
HOT_RESET pin could be connected to a user-activated button in the application. It can also be used to exit lowpower mode. In this case, the TPS65011 waits until the VCORE voltage has stabilized before generating the
MPU_RESET pulse. The MPU_RESET pulse is active low for t(mpu_nreset) seconds. HOT_RESET has an internal
1-MΩ pullup resistor to VCC.
The PB_ONOFF input can be used to exit low-power MODE. It is typically driven by a user-activated push-button
in the application. Both HOT_RESET and PB_ONOFF are de-bounced internally by the TPS65011. Typical debounce time is 56 ms. PB_ONOFF has an internal 1-MΩ pulldown resistor.
PB_ONOFF, BATT_COVER and UVLO events also cause a normal, maskable interrupt to be generated and are
noted in the REGSTATUS register.
7.3.7 Vibrator Driver
The VIB open-drain output is provided to drive a vibrator motor, controlled via the serial interface register
VDCDC2. It has a maximum dropout of 0.5 V at 100-mA load. Typically, an external resistor is required to limit
the motor current, and a freewheel diode to limit the VIB overshoot voltage at turnoff.
7.4 Device Functional Modes
7.4.1 TPS65011 Power States Description
7.4.1.1 State 1: No Power
No batteries are connected to the TPS65011. When main power is applied, the bandgap reference, LDOs, and
UVLO comparator start up. The RESPWRON, PWRFAIL, INT and MPU_RESET signals are held low. When
BATT_COVER goes high (de-bounced internally by the TPS65011), indicating that the battery cover has been
put in place and if VCC > UVLO, the power supplies are ramped in the sequence defined by PS_SEQ.
RESPWRON, PWRFAIL, INT and MPU_RESET are released when the RESPWRON timer has timed out after
tn(RESPWRON) sec. If VCC remains valid and no OVERTEMP condition occurs, then the TPS65011 arrives in State
2: ON. If VCC < UVLO, the TPS65011 keeps the bandgap reference and UVLO comparator active such that
when VCC>UVLO (during battery charge) the supplies are automatically activated.
7.4.1.2
State 2: ON
In this state, TPS65011 is fired up and ready to go. The switching converters can have their output voltages
programmed. The LDOs can be disabled or programmed. TPS65011 can exit this state either due to an
overtemperature condition, by an undervoltage condition at VCC, by BATT_COVER going low, or by the
processor programming low-power mode. State 2 is left temporarily if the user activates the HOT_RESET pin.
7.4.1.3
State 3: Low-Power Mode
This state is entered via the processor setting the ENABLE_LP bit in the serial interface and then raising the
LOW_PWR pin. The TPS65011 actually uses the rising edge of the internal signal formed by a logical AND of
the LOW_PWR and ENABLE LP signals to enter low-power mode. The VMAIN switching converter remains
active, but the VCORE converter may be disabled in low-power mode via the serial interface by setting the
LP_COREOFF bit in the VDCDC2 register. If left enabled, the VCORE voltage is set to the value predefined by
the CORELP0/1 bits in the VDCDC2 register. The LDO1OFF/nSLP and LDO2OFF/nSLP bits in the VREGS1
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Device Functional Modes (continued)
register determine whether the LDOs are turned off or put in a reduced power mode (transient speed-up circuitry
disabled in order to minimize quiescent current) in low-power mode. All TPS65011 features remain addressable
via the serial interface. TPS65011 can exit this state either due to an undervoltage condition at VCC, due to
BATT_COVER going low, due to an OVERTEMP condition, by the processor deasserting the LOW_POWER pin,
or by the user activating the HOT_RESET pin or the PB_ONOFF pin.
7.4.1.4
State 4: Shutdown
There are two scenarios for entering this state. The first is from State 1: No Power. As soon as main battery
power is applied, the device automatically enters the WAIT mode.
The second scenario occurs when the device is in ON mode and the processor initiates a shutdown by resetting
the ENABLE SUPPLY bit in the VDCDC1 register (ENABLE_LP must be high), and then raising the LOW_PWR
pin. When this happens, the power rails are ramped down in the predefined sequence, and all circuitry is then
disabled. In this state, the TPS65011 waits for the PB_ONOFF or HOT_RESET pin to be activated before
enabling any of the supply rails. When the PB_ONOFF or HOT_RESET pin is activated, the TPS65011 powers
up the supplies according to the same constraints as at the initial application of power. Complete shutdown is
only achieved by setting the LDO1OFF/nSLP and LDO2OFF/nSLP bits high in the VREGS1 register before
activating the shutdown.
In this case, the I2C interface is deactivated and the registers are reset to their default value after leaving the
WAIT mode.
To enter the WAIT mode when USB or AC is present, the AUA bit (CHCONFIG) must be set. The WAIT
mode is automatically left if Bit 7 in register CHCONFIG is set to 0 (default), and a voltage is present at either the
AC pin or the USB pin in the appropriate range for charging, and the voltage at VCC is above the UVLO
threshold. This feature allows the converters to start up automatically if the device is plugged in for charging.
If all supplies are turned off in WAIT mode, the internal bandgap is switched off, and the internal registers are
reset to their default state when the device returns to ON mode.
Table 3 shows possible configurations in LOW-POWER mode and WAIT mode.
Table 3. TPS65011 Possible Configurations
•
•
CONVERTER
MAIN
CORE
LDO1
LDO2
LOW POWER mode
1
0/1
0/1
0/1
WAIT mode
0
0
0/1
0/1
0 = converter is disabled
1 = converter is enabled
Table 4 indicates the typical quiescent current consumption in each power state.
Table 4. TPS65011 Typical Current Consumption
STATE
28
TOTAL QUIESCENT
CURRENT
QUIESCENT CURRENT BREAKDOWN
1
0
2
30 µA-70 µA
VMAIN (12 µA) + VCORE (12 µA) + LDOs (20 µA each, max 2) + UVLO + reference +
PowerGood
3
30 µA-55 µA
VMAIN (12 µA) + VCORE (12 µA) + LDOs (10 µA each, max 2) + UVLO + reference +
PowerGood
4
13 µA
UVLO + reference circuitry
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VCC
BATT
COVER
BATT COVER
DEG*
t(GLITCH)
PB_ONOFF
REFSYS
EN*
t(GLITCH)
UVLO*
ENABLE
SUPPLIES*
VCORE
98%
VCORE
VMAIN
95%
VMAIN
VLDO1
VLDO2
RESPWRON
MPU_RESET
PWREFAIL
INT
tn(RESPWRON)
*.... internal signal
Figure 30. State 1 to State 2 Transition (PS_SEQ=0, VCC > VUVLO + HYST)
Valid for LDO1 supplied from VMAIN as described in Application Information.
If 2.4 ms after application, VCC is still below the default UVLO threshold (3.15 V for VCC rising), then start up is as
shown in Figure 31.
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AC (or USB)
VCC
UVLO Threshold
BATT COVER
t(GLITCH)
BAT COVER
DEG *
REFSYS
EN*
UVLO*
ENABLE
SUPPLIES*
VCORE
98%
VCORE
VMAIN
95%
VMAIN
VLDO1
VLDO2
RESPWRON
MPU_RESET
PWRFAIL
INT
tn(RESPWRON)
*.... internal signal
Figure 31. State1-State4-State 2 Transition (Power Up Behavior When Charge Voltage is Applied)
Valid for LDO1 supplied from VMAIN as described in Application Information.
30
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VCC
UVLO Threshold With 400 mV Hysteresis
UVLO*
PWPFAIL
INT
tUVLO
ENABLE
SUPPLIES*
VCORE
VMAIN
VMAIN
~0.8 V
VLDO1
VLDO2
RESPWRON
MPU_RESET
* ... internal signal
Figure 32. State2-State4 Transition
Valid for LDO1 supplied from VMAIN as described in Application Information.
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ENABLE
LOW_POWER
LDO2
OFF/SLP
LOW_POWER
VMAIN
VCORE
95% VCORE
VLDO1
VLDO2
95% VLDO2
INT
Figure 33. State 2 to State 3 Transition. VCORE Lowered, LDO2 Disabled. Subsequent State 3 to State 2
Transition When LOW-POWER Is De-Asserted.
32
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PB_ONOFF
PB_ONOFF
DEGLITCH
tGLITCH
VCORE
VMAIN
VLDO1
VLDO2
INT
Figure 34. State 3 to State 2 Transition. PB_ONFF Activated (See Interrupt Management for INT Behavior)
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HOT_RESET
HOT_RESET
DEGLITCH
VCORE
t(GLITCH)
95% VCORE
VMAIN
VLDO1
VLDO2
95% VLDO2
INT
MPU_RESET
t(MPU_RESET)
Figure 35. State 3 to State 2 Transition (HOT_RESET Activated, See Interrupt Management for INT
Behavior)
34
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ENABLE
LOW
POWER*
LDO1
OFF/SLP*
LDO2
OFF/SLP*
MAIN
DISCHARGE*
ENABLE
SUPPLY*
LOW POWER
VMAIN
VMAIN < ca 0.8 V
VCORE
VCORE < ca 0.4 V
VLDO1
VLDO2
RESPWRON
MPU_RESET
PWRFAIL
INT
REFSYS
ENABLE*
* ... internal signal
Figure 36. State 1 to State 4 Transition
7.5 Programming
7.5.1 LED2 Output
The LED2 output can be programmed in the same way as the PG output to blink or to be permanently on or off.
The LED2_ON and LED2_PER registers are used to control the blink rate. For both PG and LED2, the minimum
blink-on time is 10 ms and this can be increased in 127 10-ms steps to 1280 ms. For both PG and LED2, the
minimum blink period is 100 ms and this can be increased in 127 100-ms steps to 12800 ms.
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Programming (continued)
7.5.2 Interrupt Management
The open-drain INT pin is used to combine and report all possible conditions via a single pin. Battery and chip
temperature faults, precharge timeout, charge timeout, taper timeout, and termination current are each capable
of setting INT low, i.e., active. INT can also be activated if any of the regulators are below the regulation
threshold. Interrupts can also be generated by any of the GPIO pins programmed to be inputs. These inputs can
be programmed to generate an interrupt either at the rising or falling edge of the input signal. It is possible to
mask an interrupt from any of these conditions individually by setting the appropriate bits in the MASK1, MASK2,
or MASK3 registers. By default, all interrupts are masked. Interrupts are stored in the CHGSTATUS,
REGSTATUS, and DEFGPIO registers in the serial interface. CHGSTATUS and REGSTATUS interrupts are
acknowledged by reading these registers. If a 1 is present in any location, then the TPS65011 automatically sets
the corresponding bit in the ACKINT1 or ACKINT2 registers and releases the INT pin. The ACKINT register
contents are self-clearing when the condition, which caused the interrupt, is removed. The applications processor
should not normally need to access the ACKINT1 or ACKINT2 registers.
Interrupt events are always captured; thus when an interrupt source is unmasked, INT may immediately go active
due to a previous interrupt condition. This can be prevented by first reading the relevant STATUS register before
unmasking the interrupt source.
If an interrupt condition occurs, then the INT pin is set low. The CHGSTATUS, REGSTATUS, and DEFGPIO
registers should be read. Bit positions containing a 1 (or possibly a 0 in DEFGPIO) are noted by the CPU and the
corresponding situation resolved. The reading of the CHGSTATUS and REGSTATUS registers automatically
acknowledges any interrupt condition in those registers and blocks the path to the INT pin from the relevant
bit(s). No interrupt should be missed during the read process since this process starts by latching the contents of
the register before shifting them out at SDAT. Once the contents have been latched (takes a couple of
nanoseconds), the register is free to capture new interrupt conditions. Hence, the probability of missing anything
is, for practical purposes, zero.
The following describes how registers 0x01 (CHGSTATUS) and 0x02 (REGSTATUS) are handled:
• CHGSTATUS(5,0) are positive edge set. Read of set CHGSTATUS(5,0) bits sets ACKINT1(5,0) bits.
• CHGSTATUS(7-6,4-1) are level set. Read of set CHGSTATUS(7-6,4-1) bits sets ACKINT1(7-6,4-1) bits.
• CHGSTATUS(5,0) clear when input signal low, and ACKINT1(5,0) bits are already set.
• CHGSTATUS(7-6,4-1) clear when input signal is low.
• ACKINT1(7-0) clear when CHGSTATUS(7-0) is clear.
• REGSTATUS(7-5) are positive edge set. Read of set REGSTATUS(7-5) bits sets ACKINT2(7-5) bits.
• REGSTATUS(3-0) are level set. Read of set REGSTATUS(3-0) bits sets ACKINT2(3-0) bits.
• REGSTATUS(7-5) clear when input signal low, and ACKINT1(7-5) bit are already set.
• REGSTATUS(3-0) clear when input signal is low.
• ACKINT2(7-0) clear when REGSTATUS(7-0) is clear.
The following describes the function of the 0x05 (ACKINT1) and 0x06 (ACKINT2) registers. These are not
usually written to by the CPU since the TPS65011 internally sets/clears these registers:
• ACKINT1(7:0) - Bit is set when the corresponding CHGSTATUS set bit is read via I2C.
• ACKINT1(7:0) - Bit is cleared when the corresponding CHGSTATUS set bit clears.
• ACKINT2(7:0) - Bit is set when the corresponding REGSTATUS set bit is read via I2C.
• ACKINT2(7:0) - Bit is cleared when the corresponding REGSTATUS set bit clears.
• ACKINT1(7:0) - a bit set masks the corresponding CHGSTATUS bit from INT.
• ACKINT2(7:0) - a bit set masks the corresponding REGSTATUS bit from INT.
The following describes the function of the 0x03 (MASK1), 0x04 (MASK2) and 0x0F (MASK3) registers:
• MASK1(7:0) - a bit set in this register masks CHGSTATUS from INT.
• MASK2(7:0) - a bit set in this register masks REGSTATUS from INT.
• MASK3(7:4) - a bit set in this register detects a rising edge on GPIO.
• MASK3(7:4) - a bit cleared in this register detects a falling edge on GPIO.
• MASK3(3:0) - a bit set in this register clears GPIO Detect signal from INT.
36
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Programming (continued)
GPIO interrupts are located by reading the 0x10 (DEFGPIO) register. The application CPU stores, or can read
from DEFGPIO, which GPIO is set to input or output. This information together with the information on
which edge the interrupt was generated (the CPU either knows this or can read it from MASK3) determines
whether the CPU is looking for a 0 or a 1 in DEFGPIO. A GPIO interrupt is blocked from the INT pin by
setting the relevant MASK3 bit; this must be done by the CPU, there is no auto-acknowledge for the GPIO
interrupts.
7.5.3 Serial Interface
The serial interface is compatible with the standard and fast mode I2C specifications, allowing transfers at up to
400 kHz. The interface adds flexibility to the power supply solution, enabling most functions to be programmed to
new values depending on the instantaneous application requirements and charger status to be monitored.
Register contents remain intact as long as VCC remains above 2 V. The TPS65011 has a 7-bit address with the
LSB set by the IFLSB pin, this allows the connection of two devices with the same address to the same bus. The
6 MSBs are 100100. Attempting to read data from register addresses not listed in this section results in FFh
being read out.
For normal data transfer, DATA is allowed to change only when CLK is low. Changes when CLK is high are
reserved for indicating the start and stop conditions. During data transfer, the data line must remain stable
whenever the clock line is high. There is one clock pulse per bit of data. Each data transfer is initiated with a start
condition and terminated with a stop condition. When addressed, the TPS65011 device generates an
acknowledge bit after the reception of each byte. The master device (microprocessor) must generate an extra
clock pulse that is associated with the acknowledge bit. The TPS65011 device must pull down the DATA line
during the acknowledge clock pulse so that the DATA line is a stable low during the high period of the
acknowledge clock pulse. The DATA line is a stable low during the high period of the acknowledge-related clock
pulse. Setup and hold times must be taken into account. During read operations, a master must signal the end of
data to the slave by not generating an acknowledge bit on the last byte that was clocked out of the slave. In this
case, the slave TPS65011 device must leave the data line high to enable the master to generate the stop
condition.
The I2C interface accepts data as soon as the voltage at VCC is higher than the undervoltage lockout threshold
and one power rail of the converter (main, core, or one of the LDOs) is operating. Therefore, the I2C interface is
not operating after applying the battery voltage as the device automatically enters the WAIT mode with all rails
off.
When the device is in WAIT mode, the I2C registers are reset to their default values if all voltage rails are off. If
the device is in WAIT mode and one power rail is left on, the I2C interface is operating and the registers are not
reset after leaving the WAIT mode.
DATA
CLK
Data Line
Stable
Data Valid
Change
of Data
Allowed
Figure 37. Bit Transfer on the Serial Interface
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Programming (continued)
CE
DATA
CLK
S
P
START Condition
STOP Condition
Figure 38. START and STOP Conditions
...
SCLK
A6
SDAT
A5
...
A4
...
A0
R/W
ACK
0
R7
R6
... R0
R5
ACK
0
D7
D6
... D0
D5
ACK
0
Slave Address
Start
...
0
Register Address
Data
Stop
NOTE: SLAVE = TPS65011
Figure 39. Serial Interface WRITE to TPS65011 Device
...
SCLK
A6
SDAT
..
...
A0
R/W
ACK
0
0
R7
R0
ACK
A6
..
...
A0
0
Register
Address
Slave Address
Start
..
...
R/W
ACK
1
0
..
D7
D0
Slave
Drives
The Data
Slave Address
ACK
Master
Stop
Drives
ACK and Stop
NOTE: SLAVE = TPS65011
Figure 40. Serial Interface READ From TPS65011: Protocol A
...
SCLK
SDAT
A6
Start
..
...
A0
R/W
ACK
0
0
Slave Address
R7
..
..
R0
Register
Address
ACK
0
...
A6
Stop Start
..
A0
R/W
1
Slave Address
ACK
0
D7
..
D0
Slave
Drives
The Data
ACK
Master
Stop
Drives
ACK and Stop
NOTE: SLAVE = TPS65011
Figure 41. Serial Interface READ From TPS65011: Protocol B
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Programming (continued)
DATA
t(BUF)
th(STA)
t(LOW)
tr
tf
CLK
th(STA)
STO
STA
t(HIGH)
th(DATA)
tsu(STA)
tsu(STO)
tsu(DATA)
STA
STO
Figure 42. Serial Interface Timing Diagram
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7.6 Register Maps
7.6.1 CHGSTATUS Register (Address: 01h—Reset: 00h)
CHGSTATUS
B7
B6
B5
B4
B3
B2
B1
B0
Name
USB charge
AC charge
Thermal
Suspend
Term Current
Taper
Timeout
Chg Timeout
Prechg
Timeout
BattTemp
error
Default
0
0
0
0
0
0
0
0
Read/write
R
R
R
R
R/W
R/W
R/W
R
The CHGSTATUS register contents indicate the status of charge.
Bit 7 - USB charge:
• 0 = inactive.
• 1 = USB source is present and in the range valid for charging. B7 remains active as long as the charge
source is present.
Bit 6 - AC charge:
• 0 = wall plug source is not present and/or not in the range valid for charging.
• 1 = wall plug source is present and in the range valid for charging. B6 remains active as long as the charge
source is present.
Bit 5 - Thermal suspend:
• 0 = charging is allowed
• 1 = charging is momentarily suspended due to excessive power dissipation on chip.
Bit 4 - Term current:
• 0 = charging, charge termination current threshold has not been crossed.
• 1 = charge termination current threshold has been crossed and charging has been stopped. This can be due
to a battery reaching full capacity, or to a battery removal condition.
Bit
•
•
•
•
3 - 1 Prechg Timeout, Chg Timeout, Taper Timeout:
If CHCONFIG=0: Bit3 equals the output of the taper voltage comparator directly, without any timer delay.
If CHCONFIG=1: there is a delay of 30 minutes because the timers have to time out first.
0 = charging, timers did not time out
1 = one of the timers has timed out and charging has been terminated.
Bit 0 - BattTemp error: Battery temperature error
• 0 = battery temperature is inside the allowed range and that charging is allowed.
• 1 = battery temperature is outside of the allowed range and that charging is suspended.
B1-4 may be reset via the serial interface in order to force a reset of the charger. Any attempt to write to B0 and
B5-7 is ignored. A 1 in B sets the INT pin active unless the corresponding bit in the MASK register is set.
7.6.2 REGSTATUS Register (Address: 02h—Reset: 00h)
REGSTATUS
Bit name
B7
PB_ONOFF
B6
B5
BATT_COVER
B4
UVLO
B3
B2
B1
B0
PGOOD
LDO2
PGOOD
LDO1
PGOOD
MAIN
PGOOD
CORE
Default
0
0
0
0
0
0
0
0
Read/write
R
R
R
R
R
R
R
R
Bit 7 - PB_ONOFF:
• 0 = inactive
• 1 = user activated the PB_ONOFF switch to request that all rails are shut down.
Bit 6 - BATT_COVER:
• 0 = BATT_COVER pin is high.
• 1 = BATT_COVER pin is low.
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Bit 5 - UVLO:
• 0 = voltage at the VCC pin above UVLO threshold.
• 1 = voltage at the VCC pin has dropped below the UVLO threshold.
Bit 4 - not implemented
Bit 3 - PGOOD LDO2:
• 0 = LDO2 output in regulation, or LDO2 disabled with VREGS1 < 7 > = 0
• 1 = LDO2 output out of regulation.
Bit 2 - PGOOD LDO1:
• 0 = LDO1 output in regulation, or LDO1 disabled with VREGS1 < 3 > = 0
• 1 = LDO1 output out of regulation.
Bit 1 - PGOOD MAIN:
• 0 = Main converter output in regulation.
• 1 = Main converter output out of regulation.
Bit 0 - PGOOD CORE:
• 0 = Core converter output in regulation.
• 1 = Core converter output out of regulation, or VDCDC2 < 7 > = 1 in low-power mode
A rising edge in the REGSTATUS register contents causes INT to be driven low if it is not masked in the MASK2.
7.6.3 MASK1 Register (Address: 03h—Reset: FFh)
MASK1
B7
B6
B5
B4
B3
B2
B1
B0
Bit name
Mask USB
Mask AC
Mask Thermal
Suspend
Mask Term
Mask Taper
Mask Chg
Mask Prechg
Mask
BattTemp
Default
1
1
1
1
1
1
1
1
Read/write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
The MASK1 register is used to mask all or any of the conditions in the corresponding CHGSTATUS
positions being indicated at the INT pin. Default is to mask all.
7.6.4 MASK2 Register (Address: 04h—Reset: FFh)
MASK2
B7
B6
Bit name
Mask
PB_ONOFF
Mask
BATT_COVER
Read/write
B5
B4
Mask UVLO
B3
B2
B1
B0
Mask PGOOD
LDO2
Mask PGOOD
LDO1
Mask PGOOD
MAIN
Mask PGOOD CORE
Default
1
1
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
The MASK2 register is used to mask all or any of the conditions in the corresponding REGSTATUS
positions being indicated at the INT pin. Default is to mask all.
7.6.5 ACKINT1 Register (Address: 05h—Reset: 00h)
ACKINT1
Bit name
B7
Ack USB
B6
B5
Ack AC
Ack Thermal
Shutdown
B4
Ack Term
B3
Ack Taper
B2
Ack Chg
B1
B0
Ack Prechg
Ack
BattTemp
Default
0
0
0
0
0
0
0
0
Read/write
R
R
R
R
R
R
R
R
The ACKINT1 register is internally used to acknowledge any of the interrupts in the corresponding
CHGSTATUS positions. When this is done, the acknowledged interrupt is no longer fed through to the INT
pin and so the INT pin becomes free to indicate the next pending interrupt. If none exists, then the INT pin goes
high, else it will remain low. A 1 at any position in ACKINT1 is automatically cleared when the corresponding
interrupt condition in CHGSTATUS is removed. The application processor should not normally need to access
the ACKINT1 register.
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7.6.6 ACKINT2 Register (Address: 06h—Reset: 00h)
ACKINT2
B7
B6
B5
B4
B3
B2
B1
B0
Bit name & function
Ack
PB_ONOFF
Ack BATT_
COVER
Ack UVLO
Default
0
0
0
0
0
0
0
0
Read/write
R
R
R
R
R
R
R
R
Ack PGOOD Ack PGOOD Ack PGOOD Ack PGOOD
LDO2
LDO1
MAIN
CORE
The ACKINT2 register is internally used to acknowledge any of the interrupts in the corresponding
REGSTATUS positions. When this is done, the acknowledged interrupt is no longer fed through to the INT
pin and so the INT pin becomes free to indicate the next pending interrupt. If none exists, then the INT pin goes
high, else it will remain low. A 1 at any position in ACKINT2 is automatically cleared when the corresponding
interrupt condition in REGSTATUS is removed. The application processor should not normally need to access
the ACKINT2 register.
7.6.7 CHGCONFIG Register Address: 07h—Reset: 1Bh
CHGCONFIG
B7
B6
B5
B4
B3
B2
B1
B0
Bit name
AUA
Charger reset
Fast charge
timer + taper
timer enabled
MSB charge
current
LSB charge
current
USB / 100
mA 500 mA
USB charge
allowed
Charge
enable
Default
0
0
0
1
1
0
1
1
Read/write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
The CHGCONFIG register is used to configure the charger.
Bit 7 - AUA:
• 0 = If a voltage is present at AC or USB in the appropriate range for charging, and if VCC > UVLO, the
TPS65011 is forced into ON mode. The WAIT mode is disabled.
• 1 = If a voltage source at AC or USB is present, the WAIT mode is enabled, and the TPS65011 does not
automatically turn on the converters.
Bit 6 - Charger reset:
• Clears all the timers in the charger and forces a restart of the charge algorithm.
• 0 / 1 = This bit must be set and then reset via the serial interface.
Bit 5 - Fast charge timer + taper timer enabled:
• 0 = fast charge timer disabled (default), CHSTATUS < 3 >= status of the taper detect comparator output.
• 1 = enables the fast charge timer and taper timer. CHSTATUS < 3 >= status of the taper timer.
Bit 4, Bit 3 - MSB/LSB Charge current:
• Used to set the constant current in the current regulation phase.
B4:B3
CHARGE CURRENT RATE
11
Maximum current set by the external resistor at the ISET pin
10
75% of maximun
01
50% of maximun
00
25% of maximun
Bit 2 - USB 100 mA / 500 mA:
• 0 = sets the USB charging current to max 100 mA.
• 1 = sets the USB charging current to max 500 mA. B2 is ignored if B1 = 0.
Bit 1 - USB charge allowed:
• 0 = prevents any charging from the USB input.
• 1 = charging from the USB input is allowed.
Bit 0 - Charge enable:
• 0 = charging is not allowed.
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1 = charger is free to charge from either of the two input sources. If both sources are present and valid, the
TPS65011 charges from the AC pin source.
7.6.8 LED1_ON Register (Address: 08h—Reset: 00h)
LED1_ON
B7
B6
B5
B4
B3
B2
B1
B0
Bit name
PG1
LED1 ON6
LED1 ON5
LED1 ON4
LED1 ON3
LED1 ON2
LED1 ON1
LED1 ON 0
Default
0
0
0
0
0
0
0
0
Read/write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
The LED1_ON and LED1_PER registers can be used to take control of the PG open drain output normally
controlled by the charger.
Bit 7 - PG1: Control of the PG pin is determined by PG1 and PG2 according to the table under LED1_PER
register
Bit 6 - BIT 0 - LED1_ON are used to program the on-time of the open drain output transistor at the PG pin.
The minimum on-time is typically 10 ms and one LSB corresponds to a 10-ms step change in the on-time.
7.6.9 LED1_PER Register (Address: 09h—Reset: 00h)
LED1_PER
B7
B6
B5
B4
B3
B2
B1
B0
Bit name
PG2
LED1 PER6
LED1 PER5
LED1 PER4
LED1 PER3
LED1 PER2
LED1 PER1
LED1 PER 0
Default
0
0
0
0
0
0
0
0
Read/write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit 7 - PG2: Control of the PG pin is determined by PG1 and PG2 according to the following table. Default shown
in bold.
PG1
PG2
BEHAVIOR OF PG OPEN DRAIN OUTPUT
0
0
Under charger control
0
1
Blink
1
0
Off
1
1
Always On
Bit 6-Bit 0 - LED1_PER are used to program the time period of the open-drain output transistor at the PG
pin. The minimum period is typically 100 ms and one LSB corresponds to a 100-ms step change in the period.
7.6.10 LED2_ON Register (Address: 0Ah—Reset: 00h)
LED2_ON
B7
B6
B5
B4
B3
B2
B1
B0
Bit name
LED21
LED2 ON6
LED2 ON5
LED2 ON4
LED2 ON3
LED2 ON2
LED2 ON1
LED2 ON0
Default
0
0
0
0
0
0
0
0
Read/write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
The LED2_ON and LED2_PER registers are used to control the LED2 open-drain output.
Bit 7 LED22: Control is determined by LED21 and LED22 according to the table under LED2_PER register.
Bit 6-Bit 0 - LED2_ON are used to program the on-time of the open drain output transistor at the LED2 pin.
The minimum on-time is typically 10 ms and one LSB corresponds to a 10-ms step change in the on-time.
7.6.11 LED2_PER (Register Address: 0Bh—Reset: 00h)
LED2_PER
B7
B6
B5
B4
B3
B2
B1
B0
Bit name
LED22
LED2 PER6
LED2 PER5
LED2 PER4
LED2 PER3
LED2 PER2
LED2 PER1
LED2 PER 0
Default
0
0
0
0
0
0
0
0
Read/write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
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Bit 7 LED22: Control is determined by LED21 and LED22 according to the table. Default shown in bold.
Bit 6-Bit 0 - LED2_ON are used to program the on-time of the open drain output transistor at the LED2 pin.
The minimum on-time is typically 100 ms and one LSB corresponds to a 100-ms step change in the on-time.
LED21
LED22
0
0
Off
0
1
Blink
1
0
Off
1
1
Always On
7.6.12
BEHAVIOR OF LED2 OPEN DRAIN OUTPUT
VDCDC1 Register (Address: 0Ch—Reset: 32h/33h)
VDCDC1
B7
B6
B5
B4
B3
B2
B1
B0
Bit name
FPWM
UVLO1
UVLO0
ENABLE
SUPPLY
ENABLE
LP
MAIN
DISCHARGE
MAIN1
MAIN0
Default
0
0
1
1
0
0
1
DEFMAIN
Read/write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
The VDCDC1 register is used to program the VMAIN switching converter.
Bit 7 - FPWM: forced PWM mode for DC-DC converters.
• 0 = MAIN and the CORE DC-DC converter are allowed to switch into PFM mode.
• 1 = MAIN and the CORE DC-DC converter operate with forced fixed frequency PWM mode and are not
allowed to switch into PFM mode, at light load.
Bit 6-Bit 5 - UVLO: The undervoltage threshold voltage is set by UVLO1 and UVLO0 according to the
below table, with the reset in bold.
UVLO1
UVLO0
0
0
VUVLO
2.5 V
0
1
2.75 V
1
0
3.0 V
1
1
3.25 V
Bit 4 - ENABLE SUPPLY (selects between LOW-POWER mode and WAIT mode):
• 0 = WAIT mode allowed, activated when LOW_PWR pin = 1 and VDCDC1 < 3 >= 1.
• 1 = The TPS65011 enters LOW-POWER mode when LOW_PWR pin = 1 and VDCDC1 < 3 >= 1.
Bit 3 - ENABLE LP:
• 0 = disables the low-power function of the LOW_PWR pin.
• 1 = enables the low power function of the LOW_PWR pin.
Bit 2 - MAIN DISCHARGE:
• 0 = disable the active discharge of the VMAIN converter output.
• 1 = enable the active discharge of the VMAIN converter output, when the converter is disabled (i.e., in WAIT
mode).
Bit 1-Bit 0 - MAIN: The VMAIN converter output voltages are set according to the following table, with the
reset in bold set by the DEFMAIN pin. The default voltage can subsequently be over-written via the serial
interface after start-up.
44
MAIN1
MAIN0
VMAIN
0
0
2.5 V
0
1
2.75 V
1
0
3.0 V
1
1
3.3 V
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7.6.13 VDCDC2 Register (Address: 0Dh—Reset: 60h/70h)
VDCDC2
B7
Bit name
B6
LP_COREOFF
B5
CORE2
B4
B3
CORE1
CORE0
B2
CORELP1
CORELP0
B1
B0
VIB
CORE
DISCHARGE
Default
0
1
1
DEFCORE
1
0
0
0
Read/write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
The VDCDC2 register is used to program the VCORE switching converter output voltage. It is programmable in 8
steps between 0.85 V and 1.8 V. The reset is governed by the DEFCORE pin; DEFCORE=0 sets an output
voltage of 1.5 V. DEFCORE=1 sets an output voltage of 1.8 V.
Bit 7 - LP_COREOFF:
• 0 = VCORE converter is enabled in low power mode.
• 1 = VCORE converter is disabled in low power mode.
Bit 6-Bit 4 - CORE: The following table shows all possible values of VCORE. The reset can subsequently
be overwritten via the serial interface after start-up.
CORE2
CORE1
CORE0
VCORE
0
0
0
0.85 V
0
0
1
1.0 V
0
1
0
1.1 V
0
1
1
1.2 V
1
0
0
1.3 V
1
0
1
1.4 V
1
1
0
1.5 V
1
1
1
1.8 V
Bit 3-Bit 2 - CORELP: CORELP1 and CORELP0 can be used to set the VCORE voltage in low power
mode. In low power mode, CORE2 is effectively 0, and CORE1, CORE0 take on the values programmed at
CORELP1 and CORELP0, default 10 giving VCORE = 1.1 V as default in low power mode. When low power
mode is exited, VCORE reverts to the value set by CORE2, CORE1, and CORE0.
Bit 1 - VIB:
• 0 = disables the VIB output transistor.
• 1 = enables the VIB output transistor to drive the vibrator motor.
Bit 0 - CORE DISCHARGE:
• 0 = disables the active discharge of the VCORE converter output.
• 1 = enables the active discharge of the VCORE converter output in WAIT mode, or if VDCDC2 < 7 >= 1 in
LOW-POWER mode.
7.6.14 VREGS1 Register (Address: 0Eh—Reset: 88h)
VREGS1
B7
B6
B5
B4
B3
B2
B1
B0
Bit name
LDO2 enable
LDO2 OFF /
nSLP
LDO21
LDO20
LDO1 enable
LDO1 OFF /
nSLP
LDO11
LDO10
Default
1
0
0
0
1
0
0
0
Read/write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
The VREGS1 register is used to program and enable LDO1 and LDO2 and to set their behavior when low-power
mode is active. The LDO output voltages can be set either on the fly, while the relevant LDO is disabled, or
simultaneously when the relevant enable bit is set. Note that both LDOs are per default ON.
Bit 7-Bit 6 - The function of the LDO2 enable and LDO2 OFF/nSLP bits is shown in the following table. See the
Power-Up Sequencing section for details of low-power mode.
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LDO2 ENABLE
LDO2 OFF / nSLP
LDO STATUS IN NORMAL MODE
LDO STATUS IN LOW-POWER MODE
0
X
OFF
OFF
1
0
ON, full power
ON, reduced power / performance
1
1
ON, full power
OFF
Bit 5-Bit 4 - LDO2: LDO2 has a default output voltage of 1.8 V. If so desired, this can be changed at the
same time as it is enabled via the serial interface.
LDO21
LDO20
VLDO2
0
0
1.8 V
0
1
2.5 V
1
0
3.0 V
1
1
3.3 V
Bit 3-Bit 2 - The function of the LDO1 enable and LDO1 OFF / nSLP bits is shown in the following table. See the
Power-Up Sequencing section for details of low-power mode. Note that programming LDO1 to a higher voltage
may force a system power-on reset if the increase is in the 10% or greater range.
LDO1 ENABLE
LDO1 OFF / nSLP
LDO STATUS IN NORMAL MODE
LDO STATUS IN LOW-POWER MODE
0
X
OFF
OFF
1
0
ON, full power
ON, reduced power and performance
1
1
ON, full power
OFF
Bit 1-Bit 0 - LDO1: The LDO1 output voltage is per default set externally. If so desired, this can be changed
via the serial interface.
LDO11
LDO10
VLDO1
0
0
ADJ
0
1
2.5 V
1
0
2.75 V
1
1
3.0 V
7.6.15 MASK3 Register (Address: 0Fh—Reset: 00h)
MASK3
B7
B6
B5
B4
B3
B2
B1
B0
Bit name
Edge trigger
GPIO4
Edge trigger
GPIO3
Edge trigger
GPIO2
Edge trigger
GPIO1
Mask GPIO4
Mask GPIO3
Mask GPIO2
Mask GPIO1
Default
0
0
0
0
0
0
0
0
Read/write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
The MASK3 register must be considered when any of the GPIO pins are programmed as inputs.
Bit 7-Bit 4 - Edge trigger GPIO: determine whether the respective GPIO generates an interrupt at a rising or
a falling edge.
• 0 = falling edge triggered.
• 1 = rising edge triggered.
Bit 3-Bit 0 - Mask GPIO: can be used to mask the corresponding interrupt. Default is unmasked (mask
GPIOx = 0).
7.6.16
DEFGPIO Register Address: (10h—Reset: 00h)
DEFGPIO
B7
B6
B5
B4
B3
B2
B1
B0
Bit name
IO4
IO3
IO2
IO1
Value GPIO4
Value GPIO3
Value GPIO2
Value GPIO1
Default
0
0
0
0
0
0
0
0
Read/write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
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The DEFGPIO register is used to define the GPIO pins to be either input or output.
Bit 7-Bit 4 - IO:
• 0 = sets the corresponding GPIO to be an input.
• 1 = sets the corresponding GPIO to be an output.
Bit 3-Bit 0 - Value GPIO: If a GPIO is programmed to be an output, then the signal output is determined by
the corresponding bit. The output circuit for each GPIO is an open drain NMOS requiring an external pullup
resistor.
• 1 = activates the relevant NMOS, hence forcing a logic low signal at the GPIO pin.
• 0 = turns the open drain transistor OFF, hence the voltage at the GPIO pin is determined by the voltage to
which the pullup resistor is connected.
If a particular GPIO is programmed to be an input, then the contents of the relevant bit in B3-0 is defined by the
logic level at the GPIO pin. A logic low forces a 0 and a logic high forces a 1. If a GPIO is programmed to be an
input, then any attempt to write to the relevant bit in B3-0 is ignored.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The VCORE and VMAIN converter are always enabled in a typical application. The VCORE output voltage can
be disabled or reduced from 1.5 V to a lower, preset voltage under processor control. When the processor enters
the sleep mode, a high signal on the LOW_PWR pin initiates the change.
VCORE typically supplies the digital part of the audio codec. When the processor is in sleep or low-power mode,
the audio codec is powered off, so the VCORE voltage can be programmed to lower voltages without a problem.
A typical audio codec (e.g., TI AIC23) consumes about 20-mA to 30-mA current from the VCORE power supply.
Supply LDO1 from VMAIN as shown in Figure 43. If this is not done, then subsequent to a UVLO, OVERTEMP,
or BATT_COVER = 0 condition, the RESPWRON signal goes high before the VCORE rail has ramped and
stabilized. Therefore, the processor core does not receive a power-on-reset signal.
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8.2 Typical Applications
AC Adapter
AC
BATT+
1 mF
X5R
VBAT
USB port
0.1 mF
BATT−
USB
1 mF
X5R
TPS65011
ISET
TS
TEMP
PG
GND
CHARGER
POWER GOOD
PS_SEQ
GND
DEFCORE
VBAT
DEFMAIN
VBAT
LED2
VCC
1 mF
X5R
BATT_COVER
10 R
VINCORE
VCORE 1.5 V
L2
VBAT
PB_ONOFF
GND
HOT_RESET
10 mH
22 mF
X5R
10 mF
X5R
VCORE
VINMAIN
VMAIN 3.3 V
LOW_PWR
L1
VBAT
6.2 mH
22 mF
X5R
VMAIN
GPIO1
INT
GPIO2
GPIO3
nPOR
RESPWRON
GPIO4
MPU_RESET
VBAT
1 mF
X5R
VIB
VMAIN
0.1 mF
VINLDO1
VMAIN
0.1 mF
VINLDO2
GND/VCC
CHARGER/REG INTERRUPT
PWRFAIL
VLDO2
RESET to MPU
Battery Fail, Battery Cover
Removed, Over Temp.
2.2 mF
X5R
1 M Each
VLDO1
2.2 mF
X5R
IFLSB
VFB_LDO1
SDAT
SCL
SDA
SCLK
PGND
AGND
Figure 43. Typical Application Circuit
8.2.1 Design Requirements
Each DC-DC converter requires an external inductor and filter capacitor, capable of sustain the intended current
with an acceptable voltage ripple. LDOs must have external filter capacitors, and LDO1 requires an external
feedback network for regulation. Every input supply rail requires a decoupling capacitor close to the pin, and to
avoid unintended states, logic inputs without internal resistors must not be left floating.
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Typical Applications (continued)
8.2.2 Detailed Design Procedure
8.2.2.1 Inductor Selection for the Main and the Core Converter
The main and the core converters in the TPS65011 typically use a 6.2-µH and a 10-µH output inductor,
respectively. Larger or smaller inductor values can be used to optimize the performance of the device for specific
operation conditions. The selected inductor has to be rated for its dc resistance and saturation current. The dc
resistance of the inductance influences directly the efficiency of the converter. Therefore, an inductor with lowest
dc resistance is selected for highest efficiency.
Equation 3 calculates the maximum inductor current under static load conditions. The saturation current of the
inductor must be rated higher than the maximum inductor current as calculated with Equation 3. This is needed
because during heavy load transient, the inductor current rises above the value calculated under Equation 3.
V
1- O
VI
DIL = VO ´
L´ƒ
(3)
IL(max) = IO(max) +
DIL
2
where
•
•
•
•
•
f = Switching frequency (1.25 MHz typical)
L = Inductor value
ΔIL= Peak-to-peak inductor ripple current
ILmax = Maximum inductor current
(4)
The highest inductor current occurs at maximum VI.
Open core inductors have a soft saturation characteristic, and they can usually handle higher inductor currents
versus a comparable shielded inductor.
A more conservative approach is to select the inductor current rating just for the maximum switch current of the
TPS65011 (2 A for the main converter and 0.8 A for the core converter). Keep in mind that the core material from
inductor to inductor differs and has an impact on the efficiency especially at high switching frequencies.
Refer to Table 5 and the typical applications for possible inductors
Table 5. Tested Inductors
DEVICE
INDUCTOR VALUE
DIMENSIONS
COMPONENT SUPPLIER
10 µH
6,0 mm × 6,0 mm × 2,0 mm
Sumida CDRH5D18-100
Core converter
Main converter
10 µH
5,0 mm × 5,0 mm × 3,0 mm
Sumida CDRH4D28-100
4.7 µH
5,5 mm × 6,6 mm x 1,0 mm
Coilcraft LPO1704-472M
4.7 µH
5,0 mm × 5,0 mm × 3,0 mm
Sumida CDRH4D28C-4.7
4.7 µH
5,2 mm × 5,2 mm × 2,5 mm
Coiltronics SD25-4R7
5.3 µH
5,7 mm × 5,7 mm × 3,0 mm
Sumida CDRH5D28-5R3
6.2 µH
5,7 mm × 5,7 mm × 3,0 mm
Sumida CDRH5D28-6R2
6.0 µH
7,0 mm × 7,0 mm × 3,0 mm
Sumida CDRH6D28-6R0
8.2.2.2 Output Capacitor Selection
The advanced fast response voltage mode control scheme of the inductive converters implemented in the
TPS65011 allow the use of small ceramic capacitors with a typical value of 22 µF for the main converter and 10
µF for the core converter without having large output voltage under and overshoots during heavy load transients.
Ceramic capacitors having low ESR values have the lowest output voltage ripple and are recommended. If
required tantalum capacitors with an ESR < 100 ΩR may be used as well.
Refer to Table 6 for recommended components.
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If ceramic output capacitors are used, the capacitor RMS ripple current rating always meet the application
requirements. Just for completeness the RMS ripple current is calculated as:
V
1- O
VI
1
IRMSC(out) = VO ´
´
L´ ƒ 2´ 3
(5)
At nominal load current, the inductive converters operate in PWM mode and the overall output voltage ripple is
the sum of the voltage spike caused by the output capacitor ESR plus the voltage ripple caused by charging and
discharging the output capacitor:
V
1- O
ö
VI æ
1
DVO = VO ´
´ç
+ ESR ÷
L ´ ƒ è 8 ´ CO ´ ƒ
ø
(6)
Where the highest output voltage ripple occurs at the highest input voltage VI.
At light load currents, the converters operate in power save mode and the output voltage ripple is independent of
the output capacitor value. The output voltage ripple is set by the internal comparator thresholds. The typical
output voltage ripple is 1% of the nominal output voltage. If the output voltage for the core converter is
programmed to its lowest voltage of 0.85 V, the output capacitor must be increased to 22 µF for low output
voltage ripple. This is because the current in the inductor decreases slowly during the off-time and further
increases the output voltage even when the PMOS is off. This effect increases with low output voltages.
8.2.2.3 Input Capacitor Selection
A pulsating input current is the nature of the buck converter. Therefore, a low ESR input capacitor is required for
best input voltage filtering. It also minimizes the interference with other circuits caused by high input voltage
spikes. The main converter needs a 22-µF ceramic input capacitor and the core converter a 10-µF ceramic
capacitor. The input capacitor for the main and the core converter can be combined and one 22-µF capacitor can
be used instead, because the two converters operate with a phase shift of 270 degrees. The input capacitor can
be increased without any limit for better input voltage filtering. The VCC pin must be separated from the input for
the main and the core converter. A filter resistor of up to 100 Ω and a 1-µF capacitor is used for decoupling the
VCC pin from switching noise.
Table 6. Possible Capacitors
CAPACITOR VALUE
CASE SIZE
COMPONENT SUPPLIER
COMMENTS
22 µF
1206
TDK C3216X5R0J226M
Ceramic
22 µF
1206
Taiyo Yuden JMK316BJ226ML
Ceramic
22 µF
1210
Taiyo Yuden JMK325BJ226MM
Ceramic
8.2.3 Application Curves
100
100
90
VO = 1.6 V
90
80
80
60
VO = 0.85 V
50
40
VO = 2.5 V
60
50
40
30
30
Core:
VI = 3.8 V,
TA = 25°C,
FPWM = 0
20
10
0
0.01
VO = 3.3 V
70
VO = 1.2 V
Efficiency - %
Efficiency - %
70
0.10
1
10
100
Main:
VI = 3.8 V,
TA = 25°C,
FPWM = 0
20
10
1k
0
0.01
0.10
1
10
100
1k
10 k
IO - Output Current - mA
IO - Output Current - mA
Figure 44. Efficiency vs Output Current
Figure 45. Efficiency vs Output Current
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8.3 System Examples
AC Adapter
Touchscreen
Controller
AC
BATT+
VBAT
USB port
BATT−
USB
USB DP, Camera i/f
TPS65011
ISET
TS
TEMP
PG
VBAT
CHARGER
POWER GOOD
TPOR
GND
PS_SEQ
GND
VBAT
DEFCORE
DEFMAIN
LED2
VCC
OMAP1510
VBAT
BATT_COVER
VBAT
PB_ONOFF
GND
HOT_RESET
VINCORE
VCORE 1.5V
L2
VDD, VDD1,
VDD2, VDD3
VCORE
VINMAIN
LOW_PWR
VBAT
VMAIN 3.3V
VDDSHV2,8
L1
VMAIN
GPIO1
INT
CHARGER/REG INTERRUPT
GPIO
GPIO2
GPIO3
RESPWRON
GPIO4
MPU_RESET
VBAT
VIB
VMAIN
VINLDO1
VMAIN
VINLDO2
GND/VCC
PWRFAIL
nPOR
RESPWRON
RESET to MPU
MPU_RESET
Battery Fail, Battery Cover
Removed, Overtemp.
FIQ_PWRFAIL
VLDO2
VDDSHV4,5
VLDO1
VDDSHV1,3,6,7,9
IFLSB
VFB_LDO1
SDAT
SCL
SDA
SCLK
PGND
ARMIO_5/LOW_POWER
AGND
ARMIO,LCD,
Keyboard, USB
Host, SDIO
SDRAM, FLASH i/f
@ 1.8 V/2.8 V
Figure 46. Typical Application Circuit in Low-Power Mode
52
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9 Power Supply Recommendations
9.1 LDO1 Output Voltage Adjustment
The output voltage of LDO1 is set with a resistor divider at the feedback pin. The sum of the two resistors must
not exceed 1 MΩ to minimize voltage changes due to leakage current into the feedback pin. The output voltage
for LDO1 after start up is the voltage set by the external resistor divider. It can be reprogrammed with the I2C
interface to the three other values defined in the register VREGS1.
10 Layout
10.1 Layout Guidelines
The input capacitors for the DC-DC converters should be placed as close as possible to the VINMAIN,
VINCORE, and VCC pins.
• The inductor of the output filter should be placed as close as possible to the device to provide the shortest
switch node possible, reducing the noise emitted into the system and increasing the efficiency.
• Sense the feedback voltage from the output at the output capacitors to ensure the best DC accuracy.
Feedback must be routed away from noisy sources such as the inductor. If possible route on the opposite
side from the switch node and inductor and place a GND plane between the feedback and the noisy sources
or keep-out underneath them entirely.
• Place the output capacitors as close as possible to the inductor to reduce the feedback loop. This will ensure
best regulation at the feedback point.
• Place the device as close as possible to the most demanding or sensitive load. The output capacitors should
be placed close to the input of the load. This will ensure the best AC performance possible.
• The input and output capacitors for the LDOs should be placed close to the device for best regulation
performance.
• Use vias to connect thermal pad to ground plane.
• TI recommends using the common ground plane for the layout of this device. The AGND can be separated
from the PGND but, a large low parasitic PGND is required to connect the PGNDx pins to the CIN and
external PGND connections. If the AGND and PGND planes are separated, have one connection point to
reference the grounds together. Place this connection point close to the device.
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10.2 Layout Example
L2 Feedback
L2 to Inductor
L2 Filter Cap
L1 Filter Cap
L1 to Inductor
Connect
thermal pad to
GND layer with
vias
L1 Feedback
Figure 47. EVM Layout
54
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SLVS501B – FEBRUARY 2004 – REVISED SEPTEMBER 2015
11 Device and Documentation Support
11.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
11.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS65011RGZR
ACTIVE
VQFN
RGZ
48
2500
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TPS65011
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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