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TPS65132
SLVSBM1H – JUNE 2013 – REVISED NOVEMBER 2016
TPS65132 Single Inductor - Dual Output Power Supply
1 Features
2 Applications
•
•
•
1
•
•
•
•
•
•
•
Input Voltage Range: 2.5 V to 5.5 V
VPOS Boost Converter:
4 V to 6 V (0.1-V step)
VNEG Inverting Buck-Boost Converter:
–6 V to –4 V (0.1-V step)
Maximum Output Current:
80 mA or 150 mA
Outstanding Combined Efficiency
– > 85% at IOUT > 10 mA
– > 90% at IOUT > 40 mA
Excellent Performance
– Outstanding Transient Response
– 1% Output Voltage Accuracy over
Full Temperature Range
2
I C Interface
– Programmable Power-Up / -Down
Sequencing Options
– Flexible Output Voltage Programming
– Programmable Active Output Discharge
– > 1000x Programmable Non-Volatile Memory
Under-Voltage Lock-Out and Thermal Protection
Two Package Options
– 15-Ball CSP Package
– 20-Pins QFN Package
•
Small-, Medium-Size Bipolar LCD Displays
– Smartphone, Tablet
– Camera, GPS
– Home Automation, Point-of-Sales
– Wearables (Smart Watch, Activity Tracker)
General Split-Rail Power Supply
– Differential Audio, Headphone Amplifier
– Instrumentation, Operational Amplifier,
Comparator
– DAC / ADC
3 Description
The TPS65132 family is designed to supply
positive/negative driven applications. The device uses
a single inductor scheme for both outputs to provide
the user smallest solution size, a small bill-of-material
as well as high efficiency. The devices offer best line
and load regulation at low noise. With its input
voltage range of 2.5 V to 5.5 V, it is optimized for
products powered by single-cell batteries (Li-Ion, NiLi, Li-Polymer) and fixed 3.3-V and 5-V rails. The
TPS656132 family provides 80 mA and 150 mA
output current options with programmability to 40 mA.
There are both CSP and QFN package options
available.
Device Information
(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM.)
TPS65132
-B, -L, -T, -S
DSBGA (15)
2.11 mm × 1.51 mm
TPS65132W
WQFN (20)
4.00 mm × 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
space
space
Typical Application
Efficiency vs Output Current
L
4.7 µH
100
95
90
VIN
2.5V to 5.5 V
C1
4.7 µF
SW
VPOS
OUTP
ENP
REG
ENN
SCL
C2
4.7 µF
C3
4.7 µF
VNEG
OUTN
SDA
PGND
CFLY1
AGND
CFLY2
5.4 V/40 mA
C4
2.2 µF
C5
4.7 µF
–5.4 V/40 mA
Efficiency (%)
VIN
85
80
75
70
65
VIN = 4.5V
60
VIN = 3.7V
55
VIN = 2.8V
50
0
5
10
15
20
IOUT (mA)
25
30
35
40
C003
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION
DATA.
TPS65132
SLVSBM1H – JUNE 2013 – REVISED NOVEMBER 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
4
5
8
7.1
7.2
7.3
7.4
7.5
7.6
Absolute Maximum Ratings ...................................... 8
ESD Ratings.............................................................. 8
Recommended Operating Conditions....................... 8
Thermal Information .................................................. 8
Electrical Characteristics........................................... 9
I2C Interface Timing Requirements / Characteristics
................................................................................. 10
7.7 Typical Characteristics ............................................ 11
8
Detailed Description ............................................ 12
8.1
8.2
8.3
8.4
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
12
12
12
16
8.5 Programming........................................................... 17
8.6 Register Maps ......................................................... 19
9
Application and Implementation ........................ 26
9.1 Application Information............................................ 26
9.2 Typical Applications ................................................ 26
10 Power Supply Recommendations ..................... 53
11 Layout................................................................... 54
11.1 Layout Guidelines ................................................. 54
11.2 Layout Example .................................................... 54
12 Device and Documentation Support ................. 55
12.1
12.2
12.3
12.4
12.5
12.6
Device Support......................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
55
55
55
55
55
55
13 Mechanical, Packaging, and Orderable
Information ........................................................... 55
13.1 CSP Package Summary ...................................... 56
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision G (August 2015) to Revision H
Page
•
Removed Product Preview from TPS65132S. ....................................................................................................................... 1
•
Changed Device Comparison Table ...................................................................................................................................... 4
•
Added description of clock stretching .................................................................................................................................. 17
•
Deleted detailed I2C interface description ........................................................................................................................... 17
•
Added that the DLYx Register is only valid for TPS65132Sx versions. .............................................................................. 22
•
Changed Table 6 ................................................................................................................................................................. 23
Changes from Revision F (June 2015) to Revision G
•
Page
Changed scope figures for Boost Converter switching. ...................................................................................................... 13
Changes from Revision E (November 2014) to Revision F
Page
•
Added TPS65132L1 device to Device Comparison table ..................................................................................................... 4
•
Added TPS65132T6 device to the Device Comparison Table. ............................................................................................. 4
•
Separated LOGIC SCL, SDA spec MIN/MAX from LOGIC EN, ENN, ENP, SYNC spec MIN/MAX ..................................... 9
•
Changed DAC Registers section for clarity ......................................................................................................................... 19
•
Added High-current Applications (≤ 150 mA) section........................................................................................................... 44
Changes from Revision D (October 2014) to Revision E
•
2
Page
Added TPS65132L0 device to Device Comparison table ..................................................................................................... 4
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Changes from Revision C (July 2014) to Revision D
•
Page
Changed package type to industry standard identifier in the Device Information table ........................................................ 1
Changes from Revision B (May 2014) to Revision C
Page
•
Added note to Device Comparison Table .............................................................................................................................. 4
•
Added reference to Power-Down And Discharge (LDO) and Power-Down And Discharge (CPN) .................................... 12
•
Added Table 1 and various references to it ......................................................................................................................... 14
•
Added "Power-Down And Discharge (CPN) shows the VNEG discharge behavior of each device variant".......................... 16
•
Added Table 2 and various references to it ........................................................................................................................ 16
•
Added note to Figure 18 ...................................................................................................................................................... 23
Changes from Revision A (August 2013) to Revision B
Page
•
Formatted to the new data sheet standard ........................................................................................................................... 1
•
Added new package option (QFN) to Device Information table ............................................................................................ 1
•
Added new package option (QFN) to Pin Configurations section ......................................................................................... 7
•
Added the ESD Ratings table ................................................................................................................................................ 8
Changes from Original (June 2013) to Revision A
•
Page
Added TPS65132Bx devices to the Device Comparison table .............................................................................................. 4
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3
TPS65132
SLVSBM1H – JUNE 2013 – REVISED NOVEMBER 2016
5
Device Comparison Table
PREPROGRAMMED
IOUT
PREPROGRAMMED
ACTIVE
DISCHARGE (2)
STARTUP
TIME
VPOS / VNEG
ISD
PACKAGE
80 mA
40 mA
VPOS / VNEG
FAST
30 µA
CSP
80 mA
40 mA
VPOS / VNEG
FAST
130 nA
CSP
80 mA
40 mA
VPOS / VNEG
SLOW
130 nA
CSP
VPOS = 5.1 V
VNEG = –5.1 V
80 mA
40 mA
VPOS / VNEG
SLOW
130 nA
CSP
TPS65132T6
VPOS = 5.6 V
VNEG = –5.6 V
80 mA
80 mA
VPOS / VNEG
SLOW
130 nA
CSP
TPS65132S
VPOS = 5.4 V
VNEG = –5.4 V
150 mA
80 mA
VPOS / VNEG
SLOW
130 nA
CSP
TPS65132W
VPOS = 5.4 V
VNEG = –5.4 V
80 mA
80 mA
VPOS / VNEG
SLOW
130 nA
QFN
PART NUMBER (1)
(1)
(2)
(3)
(4)
PREPROGRAMMED
OUTPUT
VOLTAGES
TPS65132A
VPOS = 5.4 V
VNEG = –5.4 V
TPS65132A0
VPOS = 5.0 V
VNEG = –5.0 V
TPS65132B
VPOS = 5.4 V
VNEG = –5.4V
TPS65132B0
VPOS = 5.0 V
VNEG = –5.0 V
TPS65132B5
VPOS = 5.5 V
VNEG = –5.5 V
TPS65132B2
VPOS = 5.2 V
VNEG = –5.2 V
TPS65132L
VPOS = 5.4 V
VNEG = –5.4 V
TPS65132L0
VPOS = 5.0 V
VNEG = –5.0 V
TPS65132L1
4
www.ti.com
(4)
IOUT_MAX
(3)
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com
See Power-Down And Discharge (LDO) and Power-Down And Discharge (CPN) for a detailed description of how each device variant
implements the active discharge function.
Please refer to Power-Up And Soft-Start (LDO) and Power-Up And Soft-Start (CPN) for more details.
Product preview.
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SLVSBM1H – JUNE 2013 – REVISED NOVEMBER 2016
6 Pin Configuration and Functions
YFF Package
15 Bumps
(bottom view)
TPS65132Ax / Bx / Lx / Tx
(top view)
TPS65132Ax / Bx / Lx / Tx
OUTP
REG
PGND
E
E
PGND
REG
OUTP
REG
AGND
SW
D
D
SW
AGND
REG
CFLY1
SDA
VIN
C
C
VIN
SDA
CFLY1
PGND
SCL
ENP
B
B
ENP
SCL
PGND
CFLY2
OUTN
ENN
A
A
ENN
OUTN
CFLY2
3
2
1
1
2
3
(bottom view)
TPS65132Sx
(top view)
TPS65132Sx
OUTP
REG
PGND
E
E
PGND
REG
OUTP
REG
AGND
SW
D
D
SW
AGND
REG
CFLY1
SDA
VIN
C
C
VIN
SDA
CFLY1
PGND
SCL
EN
B
B
EN
SCL
PGND
CFLY2
OUTN
SYNC
A
A
SYNC
OUTN
CFLY2
3
2
1
1
2
3
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TPS65132
SLVSBM1H – JUNE 2013 – REVISED NOVEMBER 2016
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Pin Functions
PIN
I/O
DESCRIPTION
NAME
Ax, Bx, Lx, Tx
Sx
AGND
D2
D2
—
Analog ground
CFLY1
C3
C3
I/O
Negative charge pump flying capacitor pin
CFLY2
A3
A3
I/O
Negative charge pump flying capacitor pin
EN
—
B1
ENN
A1
—
I
Enable pin for VNEG rail
ENP
B1
B1
I
Enable pin for VPOS rail
OUTP
E3
E3
O
Output pin of the LDO (VPOS)
OUTN
A2
A2
O
Output pin of the negative charge pump (VNEG)
B3
B3
E1
E1
—
Power ground
D3
D3
E2
E2
I/O
Boost converter output pin
PGND
REG
Enable pin (sequence programmed)
SCL
B2
B2
I/O
I²C interface clock signal pin
SDA
C2
C2
I/O
I²C interface data signal pin
SW
D1
D1
I/O
Switch pin of the boost converter
SYNC
—
A1
I
Synchronization pin. 150 mA current enabled if this pin is pulled HIGH.
VIN
C1
C1
I
Input voltage supply pin
6
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SLVSBM1H – JUNE 2013 – REVISED NOVEMBER 2016
QFN Package
20 Pins
RVC package
(top view)
SW
SW
REG
AGND
AGND
REG
SW
SW
RVC package
(bottom view)
20
19
18
17
17
18
19
20
PGND
1
16
OUTP
OUTP
16
1
PGND
PGND
2
15
OUTP
OUTP
15
2
PGND
AGND
3
14
REG
REG
14
3
AGND
PowerPAD
PowerPAD
ENP
5
12
PGND
PGND
12
5
ENP
ENN
6
11
PGND
PGND
11
6
ENN
7
8
9
10
10
9
8
7
SDA
VIN
SCL
4
OUTN
13
CFLY2
CFLY1
CFLY2
CFLY1
OUTN
13
SCL
4
SDA
VIN
Pin Functions
PIN
NAME
AGND
Wx
3
17
I/O
DESCRIPTION
—
Analog ground
CFLY1
13
I/O
Negative charge pump flying capacitor pin
CFLY2
10
I/O
Negative charge pump flying capacitor pin
ENN
6
I
Enable pin for VNEG rail
ENP
5
I
Enable pin for VPOS rail
O
Output pin of the LDO (VPOS)
O
Output pin of the negative charge pump (VNEG)
—
Power ground
I/O
Boost converter output pin
OUTP
OUTN
16
15
9
1
PGND
2
11
12
REG
14
18
SCL
8
I/O
I²C interface clock signal pin
SDA
7
I/O
I²C interface data signal pin
I/O
Switch pin of the boost converter
SW
VIN
19
20
4
I
Input voltage supply pin
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SLVSBM1H – JUNE 2013 – REVISED NOVEMBER 2016
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7 Specifications
7.1 Absolute Maximum Ratings (1) (2)
over operating free-air temperature range (unless otherwise noted)
VALUE
Voltage range
CFLY1, EN, ENN, ENP, OUTP, REG, SCL, SDA, SW, SYNC,
VIN
MAX
–0.3
7
V
–7
0.3
V
CFLY2, OUTN
Continuous total power dissipation
UNIT
MIN
See Thermal Information
Operating junction temperature, TJ
–40
150
°C
Operating ambient temperature, TA
–40
85
°C
Storage temperature, Tstg
–65
150
°C
(1)
(2)
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.
All voltage values are with respect to ground.
7.2 ESD Ratings
(1)
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins
VESD
(1)
(2)
Charged device model (CDM) per JEDEC specification JESD22C101, all pins (2)
VALUE
UNIT
±2000
V
±500
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
MIN
TYP
MAX
UNIT
VIN
Input voltage range
2.5
5.5
V
L
Inductor (1)
2.2
4.7
µH
CIN
Input capacitor (1) (2)
(1) (2)
4.7
µF
2.2
µF
CFLY
Flying capacitor
COUTP, COUTN, CREG
Output capacitors (1) (2)
4.7
TA
Operating ambient temperature
–40
85
°C
TJ
Operating junction temperature
–40
125
°C
(1)
(2)
µF
Please see Detailed Description section for further information.
X7R (or better dielectric material) is recommended.
7.4 Thermal Information
TPS65132
THERMAL METRIC (1)
TPS65132
YFF
RVC
(15) BALLS
(20) PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
76.5
39.0
°C/W
RθJCtop
Junction-to-case (top) thermal resistance
0.2
42.7
°C/W
RθJB
Junction-to-board thermal resistance
44
13.6
°C/W
ψJT
Junction-to-top characterization parameter
1.6
0.6
°C/W
ψJB
Junction-to-board characterization parameter
43.4
13.6
°C/W
RθJCbot
Junction-to-case (bottom) thermal resistance
N/A
3.8
°C/W
(1)
8
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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7.5 Electrical Characteristics
VIN = 3.7 V, EN = ENN = ENP = VIN, VPOS = 5.4 V, VNEG = –5.4 V, TA = –40°C to 85°C; typical values are at TA = 25°C
(unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY CURRENT
VIN
Input voltage range
2.5
5.5
VIN rising
2.3
2.5
VIN falling
2.1
2.3
V
VUVLO
Undervoltage lockout threshold
IQ
Quiescent current
0.54
mA
Thermal shutdown
140
°C
5
°C
Thermal shutdown hysteresis
V
LOGIC EN, ENN, ENP, SYNC
VIH
High level input voltage
VIL
Low level input voltage
REN
Pulldown resistors
VIN = 2.5 V to 5.5 V
1.1
0.4
200
V
kΩ
LOGIC SCL, SDA
VIH
High level input voltage
VIL
Low level input voltage
VIN = 2.5 V to 5.5 V
1.1
0.54
V
BOOST CONVERTER
ILIM
Boost converter valley current limit
fSW
Boost converter switching frequency
0.9
1.2
1.5
A
1.35
1.80
2.25
MHz
V
LDO OUTPUT VPOS
VPOS
Positive output voltage range
4.0
6.0
VPOS_acc
Positive output voltage accuracy
–1 %
+1 %
IPOS
Positive output current capability
200
VDO
Dropout voltage
VREG = VPOS(NOM) = 5.4V, IOUT = 150 mA
160
Line regulation
VIN = 2.5 V to 5.5 V, IOUT = 40 mA
2.7
mV
Load regulation
ΔIOUT = 80 mA
3.4
%/A
70
Ω
RD
Discharge resistor
mA
mV
NEGATIVE CHARGE PUMP OUTPUT VNEG
VNEG
Negative output voltage range
VNEG_acc
Negative output voltage accuracy
INEG
Negative output current capability
INEG
Negative output current capability
fOSC
Negative charge pump switching
frequency
RD
–6.0
–4.0
–1 %
+1 %
40mA MODE
40
80mA MODE
80
TPS65132Sx, SYNC = HIGH
mA
150
0.8
V
mA
1.0
1.2
MHz
Line regulation
VIN = 2.5 V to 5.5 V, IOUT = 40 mA
3.3
mV
Load regulation
ΔIOUT = 80 mA
6.1
%/A
20
Ω
Discharge resistor
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7.6 I2C Interface Timing Requirements / Characteristics
PARAMETER
fSCL
TEST CONDITIONS
LOW period of the SCL clock
tHIGH
HIGH period of the SCL clock
Bus free time between a STOP and START condition
tsu;STA
tsu;DAT
Hold time for a repeated START condition
Setup time for a repeated START condition
Data setup time
thd;DAT Data hold time
tRCL1
tRCL
Rise time of SCL signal after a repeated START condition
and after an acknowledge bit
Rise time of SCL signal
tFCL
Fall time of SCL signal
tRDA
Rise time of SDA signal
tFDA
Fall time of SDA signal
tsu;STO Setup time for STOP condition
CB
(1)
TYP
Fast mode
tLOW
thd;STA
MIN
Standard mode
SCL clock frequency
tBUF
(1)
MAX
UNIT
100
kHz
400
kHz
Standard mode
4.7
µs
Fast mode
1.3
µs
Standard mode
4.0
µs
Fast mode
600
ns
Standard mode
4.7
µs
Fast mode
1.3
µs
Standard mode
4.0
µs
Fast mode
600
ns
Standard mode
4.7
µs
Fast mode
600
ns
Standard mode
250
ns
Fast mode
100
ns
Standard mode
0.05
3.45
µs
Fast mode
0.05
0.9
µs
Standard mode
20 +
0.1CB
1000
ns
Fast mode
20 +
0.1CB
1000
ns
Standard mode
20 +
0.1CB
1000
ns
Fast mode
20 +
0.1CB
300
ns
Standard mode
20 +
0.1CB
300
ns
Fast mode
20 +
0.1CB
300
ns
Standard mode
20 +
0.1CB
1000
ns
Fast mode
20 +
0.1CB
300
ns
Standard mode
20 +
0.1CB
300
ns
Fast mode
20 +
0.1CB
300
ns
Standard mode
4.0
Fast mode
600
µs
ns
Capacitive load for SDA and SCL
0.4
nF
Industry standard I2C timing characteristics according to I2C-Bus Specification, Version 2.1, January 2000. Not tested in production.
SDA
tf
tLOW
tf
tsu;DAT
tr
tBUF
tr
thd;STA
SCL
S
thd;STA
thd;DAT
tsu;STA
HIGH
tsu;STO
Sr
P
S
Figure 1. Serial Interface Timing For F/S-Mode
10
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7.7 Typical Characteristics
VIN= 3.7 V, VPOS= 5.4 V, VNEG= –5.4 V, unless otherwise noted
3
0.6
VIN = 2.9 V
VIN = 2.9 V
0.58
VIN = 3.7 V
2.5
VIN = 4.5 V
0.54
Iq (mA)
2
Isd (µA)
VIN = 3.7 V
0.56
VIN = 4.5 V
1.5
1
0.52
0.5
0.48
0.46
0.44
0.5
0.42
0
0.4
-40
-20
0
20
40
60
80
Ta (ƒC)
-40
-20
20
40
60
80
Ta (ƒC)
Figure 2. Shutdown Current (all versions but Ax)
C04
Figure 3. Quiescent Current
1.2
2.5
VIN = 2.9 V
1.15
UVLO_rising
VIN = 3.7 V
1.1
UVLO_falling
2.45
VIN = 4.5 V
2.4
1.05
VIN (V)
Fosc (MHz)
0
C04
1
0.95
2.35
2.3
0.9
2.25
0.85
0.8
2.2
-40
10
60
Ta (ƒC)
-40
C03
Figure 4. Main Oscillator Frequency
-20
0
20
40
60
80
Ta (ƒC)
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Figure 5. UVLO
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8 Detailed Description
8.1 Overview
The TPS65132, supporting input voltage range from 2.5 V to 5.5 V, operates with a single inductor scheme to
provide a high efficiency with a small solution size. The synchronous boost converter generates a positive
voltage that is regulated down by an integrated LDO, providing the positive supply rail (VPOS). The negative
supply rail (VNEG) is generated by an integrated negative charge pump (or CPN) driven from the boost converter
output pin, REG. The operating mode can be selected between 40mA and 80mA in order to select the necessary
output current capability and to get the best efficiency possible based on the application. The device topology
allows a 100% asymmetry of the output currents.
8.2 Functional Block Diagram
SW
VIN
(battery voltage)
SYNC
BOOST
ENP
ENN
CFLY1
VPOS
5.4 V/40 mA
OUTN
CPN
PGND
SCL
SDA
OUTP
LDO
VNEG
–5.4 V/40 mA
CFLY2
VIN
REG
AGND
8.3 Feature Description
8.3.1 Undervoltage Lockout (UVLO)
The TPS65132 integrates an undervoltage lockout block (UVLO) that enables the device once the voltage on the
VIN pin exceeds the UVLO threshold (2.5 V maximum). No output voltage will be generated as long as the
enable signals are not pulled HIGH. The device, as well as all converters (boost converter, LDO, CPN), will be
disabled as soon as the VIN voltage falls below the UVLO threshold. The UVLO threshold is designed in a way
that the TPS65132 will continue operating as long as VIN stays above 2.3 V. This guarantees a proper operation
even in the event of extensive line transients when the battery gets suddenly heavily loaded.
For TPS65132Ax, a 40 ms delay is starting as soon as the UVLO threshold is reached. This delay prevents the
device to be disabled and enabled by an unwanted VIN voltage spike. Once this delay has passed, the output
rails can be enabled and disabled as desired with the enable signals without any delay.
8.3.2 Active Discharge
An active discharge of the positive rail and/or the negative rail can be programmed (DISP and DISN bits
respectively - refer to Registers). If programmed to be active, the discharge will occur at power down, when the
enable signals go LOW (Figure 37 and Figure 38 for TPS65132Ax, Bx, Lx, Tx, Wx — Figure 105 and Figure 104
for TPS65132Sx). See Power-Down And Discharge (LDO) and Power-Down And Discharge (CPN) for a detailed
description of how each device variant implements the active discharge function.
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Feature Description (continued)
8.3.3 Boost Converter
8.3.3.1 Boost Converter Operation
The synchronous boost converter uses a current mode topology and operates at a quasi-fixed frequency of
typically 1.8 MHz, allowing chip inductors such as 2.2 µH or 4.7 µH to be used. The converter is internally
compensated and provides a regulated output voltage automatically adjusted depending on the programmed
VPOS and VNEG voltages. The boost converter operates either in continuous conduction mode (CCM) or Pulse
Frequency Modulation mode (PFM), depending on the load current in order to provide the highest efficiency
possible. The switch node waveforms for CCM and DCM operation are shown in Figure 6 and Figure 7.
8.3.3.2 Power-Up And Soft-Start (Boost Converter)
The boost converter starts switching as soon as one enable signal is pulled HIGH and the voltage on VIN pin is
above the UVLO threshold. For TPS65132Ax, in the case where one enable signal is already HIGH when VIN
reaches the UVLO threshold, the boost converter will only start switching after a 40 ms delay has passed (see
Undervoltage Lockout (UVLO)).
The boost converter starts up with an integrated soft-start to avoid drawing excessive inrush current from the
supply. The output voltage VREG is slowly ramped up to its target value. Typical startup waveforms for low-current
applications are shown in Figure 33 and Figure 35.
8.3.3.3 Power-Down (Boost Converter)
The boost converter stops switching when VIN is below the UVLO threshold or when both output rails are
disabled. For example, due to a special sequencing, the LDO might still be operating while the CPN is already
disabled, in which case, the boost will continue operating until the LDO has been disabled. Typical power-down
waveforms for low-current applications are shown in Figure 34 and Figure 36.
8.3.3.4 Isolation (Boost Converter)
The boost converter output (REG) is isolated from the input supply VIN, providing a true shutdown.
8.3.3.5 Output Voltage (Boost Converter)
The output voltage of the boost converter is automatically adjusted depending on the programmed VPOS and
VNEG voltages.
8.3.3.6 Advanced Power-Save Mode For Light-Load Efficiency And PFM
The TPS65132 device integrates a power save mode to improve efficiency at light load. In power save mode the
converter stops switching when the inductor current reaches 0 A. The device resumes its switching activity with
one or more pulses once the VREG voltage falls below its regulation level, and goes again into power save mode
once the inductor current reaches 0 A. The pulse duration remains constant, but the frequency of these pulses
varies according to the output load. This operating mode is also known as Pulse Frequency Modulation or PFM.
Figure 6 provides plots of the inductor current and the switch node in PFM mode.
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Feature Description (continued)
TPS65132B - Low-Current Application
TPS65132B - Low-Current Application
2
2
VREG_AC
VREG_AC
VSW
VSW
3
3
IL
IL
4
4
Ch2 50.0 mV/div
Ch3 2.00 V/div
Ch4 100 mA/div
Ch4 100 mA/div
Ch2 50.0 mV/div
Ch3 2.00 V/div
1 µs/div
1 µs/div
Figure 7. Boost Converter — Heavy Load (40 mA)
Figure 6. Boost Converter - Light Load (1 mA)
8.3.4 LDO Regulator
8.3.4.1 LDO Operation
The Low Dropout regulator (or LDO) generates the positive voltage rail, VPOS, by regulating down the output
voltage of the boost converter (VREG). Its inherent power supply rejection helps filtering the output ripple of the
boost converter in order to provide on OUTP pin a clean voltage, e.g. to supply the source driver IC of the
display.
8.3.4.2 Power-Up And Soft-Start (LDO)
The LDO starts operating as soon as the ENP signal is pulled HIGH, VIN voltage is above the UVLO threshold
and the boost converter has reached its Power Good threshold.
In the case where the enable signal is already HIGH when VIN exceeds the UVLO threshold, the boost converter
will start first and the LDO will only start after the boost converter has reached its target voltage. For
TPS65132Ax, the boost will start after the 40 ms delay has passed (see Undervoltage Lockout (UVLO)).
For TPS65132Sx the LDO startup is defined by the setting of the DLYx register and the SEQU bits, see
Registers for more details.
The LDO integrates a soft-start that slowly ramps up its output voltage VPOS regardless of the output capacitor
and the target voltage, as long as the LDO current limit is not reached. For TPS65132Ax and TPS65132Bx
(except TPS65132B2), the typical startup time is 140 µs. For TPS65132B2, TPS65132Lx, TPS65132Sx,
TPS65132Tx and TPS65132Wx, the typical ramp-up time is 500 µs and the inrush current is also reduced by a
factor of 3. Typical startup waveforms for the low-current application are shown in Figure 33 to Figure 35.
8.3.4.3 Power-Down And Discharge (LDO)
The LDO stops operating when VIN is below the UVLO threshold or when ENP is pulled LOW. Or for
TPS65132Sx when EN is pulled LOW, and the internal sequencing has passed.
The positive rail can be actively discharged to GND during power-down if required. A discharge selection bit is
available to enable or disable this function. See Registers for more details, as well as waveforms in Figure 37
and Figure 38. Table 1 shows the VPOS active discharge behavior of each device variant.
Table 1. VPOS Active Discharge Behavior
PART NUMBER
TPS65132Ax
14
VIN
ENP (or EN)
ENN (or SYNC)
VPOS DISCHARGE
< VUVLO
Don't Care
Don't Care
On
Low
Low
Determined by DISP bit
Low
High
Determined by DISP bit
High
Low
Off
High
High
Off
> VUVLO
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Feature Description (continued)
Table 1. VPOS Active Discharge Behavior (continued)
PART NUMBER
TPS65132Bx
TPS65132Lx
TPS65132Sx
TPS65132Tx
TPS65132Wx
VIN
ENP (or EN)
ENN (or SYNC)
VPOS DISCHARGE
< VUVLO
Don't Care
Don't Care
On
> VUVLO
Low
Low
On
Low
High
Determined by DISP bit
High
Low
Off
High
High
Off
8.3.4.4 Isolation (LDO)
The LDO is isolating the VPOS rail from VREG (boost converter output) as long as the rail is not enabled in order to
ensure flexible startup like VNEG before VPOS.
8.3.4.5 Setting The Output Voltage (LDO)
The output voltage of the LDO is programmable via a I2C compatible interface, from –6.0 V to –4.0 V in 100 mV
steps. For more details, please refer to the VPOS Register – Address: 0x00
8.3.5 Negative Charge Pump
8.3.5.1 Operation
The negative charge pump (CPN) generates the negative voltage rail, VNEG, by inverting and regulating the
output voltage of the boost converter (VREG). The charge pump uses 4 switches and an external flying capacitor
to generate the negative rail. Two of the switches are turned on in the first phase to charge the flying capacitor
up to VREG, and in the second phase they are turned-off and the two others turn on to pump the energy
negatively out of the OUTN capacitor.
8.3.5.2 Power-Up And Soft-Start (CPN)
The CPN starts operating as soon as the ENN signal is pulled HIGH, VIN voltage is above the UVLO threshold
and the boost converter has reached its Power Good threshold.
In the case where the enable signal is already HIGH when VIN reaches the UVLO threshold, the boost converter
will start first and the CPN will only start after the boost converter has reached its target voltage. For
TPS65132Ax, the boost will start after the 40 ms delay has passed (see Undervoltage Lockout (UVLO)).
For TPS65132Sx the CPN startup is defined by the setting of the DLYx register and the SEQU bits, see
Registers for more details.
The CPN integrates a soft-start that slowly ramps up its output voltage VNEG within a time defined by the selected
mode (40mA or 80mA), the output voltage and the output capacitor value. For TPS65132Ax and TPS65132Bx
(except TPS65132B2), the startup current charging the output capacitor in 40mA mode is 50 mA, and 100 mA
typically in 80mA mode. For TPS65132B2, TPS65132Lx, TPS65132Tx, and TPS65132Wx, the typical ramp-up
times are slowed down by a factor of 4 (i.e 12.5 mA and 25 mA typical output current for 40mA and 80mA modes
respectively) and the inrush current is also reduced by a factor of about 4. Typical startup waveforms for the lowcurrent application are shown in Figure 39 to Figure 42.
For TPS65132Sx, the negative rail starts-up in 40mA or 80mA mode, thus the startup current is set by the mode
the device is programmed to, and not related to the SYNC pin state. The full current of 150 mA minimum is only
released once both rails (VPOS and VNEG) have reached their Power Good levels.
t STARTUP =
The estimated startup time can be calculated using the following formula:
COUT ´ VNEG
ISTARTUP
Where:
tSTARTUP = startup time of the VNEG rail
COUT = output capacitance of the VNEG rail
VNEG = target output voltage
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ISTARTUP = output current of the VNEG rail charging up the output capacitor at startup (12.5 mA, 25 mA, 50 mA
or 100 mA as described above)
8.3.5.3 Power-Down And Discharge (CPN)
The CPN stops operating when VIN is below the UVLO threshold or when ENN is pulled LOW.
Or when EN is pulled LOW in the TPS65132Sx, and the internal sequencing has passed.
The negative rail can be actively discharged to GND during power-down if required. A discharge selection bit is
available to enable or disable this function. See for more details, as well as waveforms Figure 37 and Figure 38.
Table 2 shows the VNEG discharge behavior of each device variant.
Table 2. VNEG Active Discharge Behavior
PART NUMBER
TPS65132Ax
VIN
ENP (or EN)
ENN (or SYNC)
VNEG DISCHARGE
< VUVLO
Don't Care
Don't Care
On
Low
Low
Determined by DISN bit
Low
High
Off
High
Low
Determined by DISN bit
> VUVLO
< VUVLO
TPS65132Bx
TPS65132Lx
TPS65132Tx
TPS65132Wx
> VUVLO
< VUVLO
TPS65132Sx
> VUVLO
High
High
Off
Don't Care
Don't Care
On
Low
Low
On
Low
High
Off
High
Low
Determined by DISN bit
High
High
Off
Don't Care
Don't Care
On
Low
Low
On
Low
High
Determined by DISN bit
High
Low
Off
High
High
Off
8.3.5.4 Isolation (CPN)
The CPN isolates the VNEG rail from VREG (boost converter output) as long as the rail is not enabled in order to
ensure flexible startup like VPOS before VNEG.
8.3.5.5 Setting The Output Voltage (CPN)
The output voltage of the CPN is programmable via a I2C compatible interface, from –4.0 V to –6.0 V in 100 mV
steps. For more details, please refer to the VNEG Register – Address 0x01.
8.4 Device Functional Modes
8.4.1 Enabling and Disabling the Device
At startup (VIN goes above UVLO and at least one of the enable pins (ENP, ENN, or EN) goes HIGH), the
EEPROM content is loaded into the DAC registers and the IC starts with these default values. The TPS65132 is
enabled as long as the VIN voltage is above the UVLO and one of the enable pins (ENP, ENN, or EN) is HIGH.
Pulling ENP or ENN LOW disables either rail (VPOS or VNEG respectively); and, pulling both pins LOW disables
the device entirely (the internal oscillator of the TPS65132Ax continues running to allow access to the I²C
interface).
For TPS65132Sx, pulling EN LOW disables the device.
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8.5 Programming
8.5.1 I2C Serial Interface Description
The TPS65132 communicates through an industry standard I2C compatible interface, to receive data in slave
mode. I2C is a 2-wire serial interface developed by Philips Semiconductor (see I2C-Bus Specification, Version
2.1, January 2000).
The TPS65132 integrates a non-volatile memory (EEPROM) that allows the storage of the register values with a
capability of up to 1000 programming cycles. At startup the TPS65132 loads first the EEPROM content into the
registers and uses these voltages to start.
It is recommended to stop I2C communication with the TPS65132 for 50 ms after the command "Write EEPROM
data" was sent. If the device is accessed via I2C during EEPROM programming, the device will pull down the
SCL line (clock stretch) after it recognized its I2C address. The SCL line will be released after EEPROM
programming is finished.
The TPS65132 works as a slave and supports the following data transfer modes, as defined in the I2C-Bus
specification: standard mode (100 kbps) and fast mode (400 kbps). The data transfer protocol for standard and
fast modes is exactly the same, therefore they are referred to as F/S-mode in this document. The TPS65132
supports 7-bit addressing. The device 7-bit address is 3E (see Figure 8), and the LSB enables the write or read
function.
Figure 8. TPS65132 Slave Address Byte
MSB
0
R/W = R/(W)
TPS65132
1
1
Address
1
1
1
0
LSB
R/W
NOTE
With TPS65132Ax, the I2C interface is accessible as long as the input voltage is above
the undervoltage lockout threshold. In all other versions, the I2C interface is accessible
only as soon as one of the enable pins is pulled HIGH while the input voltage is above the
undervoltage lockout.
8.5.2 I2C Interface Protocol
1
7
1
1
8
1
S
Slave Address
R/W
A
Register Address
A
8
Data Register
1
1
A
P
“0” Write
From Master to Slave
From Slave to Master
A
A
S
Sr
P
= Acknowledge (SDA LOW)
= Not Acknowledge (SDA HIGH)
= START condition
= REPEATED START condition
= STOP condition
Figure 9. “Write" Data To DAC – Transfer Format In F/S-Mode
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1
7
1
1
8
1
8
1
S
Slave Address
R/W
A
Register Address (n)
A
Data nth Register
A
8
1
Data (n+1)th Register
A
“0” Write
8
Data (Last) Register
A
A
S
Sr
P
From Master to Slave
From Slave to Master
1
1
A
P
= Acknowledge (SDA LOW)
= Not Acknowledge (SDA HIGH)
= START condition
= REPEATED START condition
= STOP condition
Figure 10. "Write" Data To DAC – Transfer Format In F/S-Mode
Featuring Register Address Auto-Increment
1
7
1
1
S
Slave Address
R/W
A
8
1
8
1
1
CR Address
A
CR Data (1xxxxxxx)
A
P
“1” Write all DAC data to EEPROM
“0” Write
A
A
S
Sr
P
From Master to Slave
From Slave to Master
= Acknowledge (SDA LOW)
= Not Acknowledge (SDA HIGH)
= START condition
= REPEATED START condition
= STOP condition
Figure 11. “Write” Data To EEPROM – Transfer Format In F/S-Mode
1
7
1
1
8
1
8
1
1
S
Slave Address
R/W
A
CR Address
A
CR data (0xxxxxx0)
A
P
“0” Read from DAC Register
“1” Read from EEPROM Register
“0” Write
1
7
1
1
8
1
1
7
1
1
8
1
1
S
Slave Address
R/W
A
Register Address
A
Sr
Slave Address
R/W
A
Data
A
P
“0” Write
“1” Read
From Master to Slave
From Slave to Master
A
A
S
Sr
P
= Acknowledge (SDA LOW)
= Not Acknowledge (SDA HIGH)
= START condition
= REPEATED START condition
= STOP condition
Figure 12. “Read” Data From DAC/EEPROM – Transfer Format In F/S-Mode
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1
7
1
S
Slave Address
R/W
1
8
1
8
1
1
A
CR Address
A
CR data (0xxxxxx0)
A
P
“0” Read from DAC Register
“1” Read from EEPROM Register
“0” Write
7
1
S
1
Slave Address
8
1
R/W
A
1
Register Address
A
7
1
Sr
1
Slave Address
R/W
8
1
th
A
Data n Register
8
1
8
th
A
“0” Write
1
A
“1” Read
Data (n+1) Register
A
A
S
Sr
P
From Master to Slave
From Slave to Master
Data (Last) Register
1
1
A
P
= Acknowledge (SDA LOW)
= Not Acknowledge (SDA HIGH)
= START condition
= REPEATED START condition
= STOP condition
Figure 13. “Read” Data From DAC/EEPROM – Transfer Format In F/S-Mode
Featuring Register Address Auto-Increment
8.6 Register Maps
The TPS65132 has a non-volatile memory (EEPROM) which contains the initial values and one volatile memory
(Registers) which contains the actual settings. The EEPROM and the Registers are accessed with the same
address.
Startup option: At power-up, the values contained in the EEPROM are loaded into the Registers to the last
stored setting within less than 20 µs. The programmed factory value of the EEPROM of each address is
described in section Factory Default Register Value.
Write description: The user has to program all Registers first (0×00 to 0×03), then set the WED (Write
EEPROM Data) bit to 1. A dead time of 50 ms is then initiated during which the register content or all registers
(0×00 ~ 0×03) are stored into the non-volatile EEPROM cells. During that time, there should be no data flowing
through the I2C because the I2C interface is momentarily not responding.
After the 50 ms have passed, the WED bit is automatically reset to 0, and the user is able to read the values or
program again.
Slave address: 0x3E
X = R/W
R/W = 1 → read mode
R/W = 0 → write mode
8.6.1 Registers
Attempting to read data from register addresses not listed in the following section will result in 0x00 being read
out.
8.6.1.1 VPOS Register – Address: 0x00
Figure 14. VPOS Register
7
RSVD
0
6
RSVD
0
R
5
RSVD
0
4
3
0
1
2
VPOS[4:0]
1
R/W
1
0
1
0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
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Table 3. VPOS Register Field Descriptions
Bit
Field
Description
7:5
RSVD[2:0]
Reserved, always set to 0
VPOS output voltage adjustment
4:0
20
VPOS[4:0]
VPOS[4:0] Value
(binary)
VPOS Output Voltage
(V)
VPOS[4:0] Value
(binary)
VPOS Output Voltage
(V)
00000
4.0
01011
5.1
00001
4.1
01100
5.2
00010
4.2
01101
5.3
00011
4.3
01110
5.4
00100
4.4
01111
5.5
00101
4.5
10000
5.6
00110
4.6
10001
5.7
00111
4.7
10010
5.8
01000
4.8
10011
5.9
01001
4.9
10100
6.0
01010
5.0
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8.6.1.2 VNEG Register – Address 0x01
Figure 15. VNEG Register
7
RSVD
0
6
RSVD
0
R
5
RSVD
0
4
3
0
1
2
VNEG[4:0]
1
R/W
1
0
1
0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 4. VNEG Register Field Descriptions
Bit
Field
Description
7:5
RSVD[2:0]
Reserved, always set to 0
VNEG output voltage adjustment
4:0
VNEG[4:0]
VNEG[4:0] Value
(binary)
VNEG Output Voltage
(V)
VNEG[4:0] Value
(binary)
VNEG Output Voltage
(V)
00000
–4.0
01011
–5.1
00001
–4.1
01100
–5.2
00010
–4.2
01101
–5.3
00011
–4.3
01110
–5.4
00100
–4.4
01111
–5.5
00101
–4.5
10000
–5.6
00110
–4.6
10001
–5.7
00111
–4.7
10010
–5.8
01000
–4.8
10011
–5.9
01001
–4.9
10100
–6.0
01010
–5.0
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8.6.1.3 DLYx Register – Address 0x02 (Only valid for TPS65132Sx)
Figure 16. DLYx Register
7
DLYP2
0
6
DLYP2
0
5
DLYN2
0
4
DLYN2
0
3
DLYP1
0
2
DLYP1
0
1
DLYN1
0
0
DLYN1
1
R/W
Table 5. DLYx Register Field Descriptions
Bit
Field
7:6
DLYP2[1:0]
5:4
DLYN2[1:0]
3:2
DLYP1[1:0]
1:0
DLYN1[1:0]
DLYx[1:0]
22
Description
Delay in milliseconds
DLYx Value (binary)
DLYx Delay (ms)
00
0
01
1
10
5
11
10
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8.6.1.4 APPS - SEQU - SEQD - DISP - DISN Register – Address 0x03
Figure 17. APPS - SEQU - SEQD - DISP - DISN Register
7
RSVD
0
R
6
APPS
0
R/W
5
SEQU
0
R/W
4
SEQU
0
R/W
3
SEQD
0
R/W
2
SEQD
0
R/W
1
DISP
1
R/W
0
DISN
0
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 6. APPS - SEQU - SEQD - DISP - DISN Field Descriptions
Field
Description
7
RSVD
Reserved, always set to 0
6
APPS
Application
5:4
3:2
1
0
(1)
(2)
Value
(binary)
Bit
SEQU (1)
SEQD (1)
DISP (2)
DISN (2)
Sequencing at
Startup
Sequencing at
Shutdown
Discharge VPOS
Discharge VNEG
APPS
Value
SEQU
Value
SEQD
Value
DISP Value
DISN Value
Action
0
40mA
1
80mA
00
VPOS and VNEG simultaneously (DLYP1 after EN goes HIGH)
01
VPOS (DLYP1 after EN goes HIGH) and then VNEG (DLYN1 after VPOS)
10
VNEG (DLYN1 after EN goes HIGH) and then VPOS (DLYP1 after VNEG)
11
VPOS only
00
VPOS and VNEG simultaneously (DLYP2 after EN goes LOW)
01
VPOS (DLYP2 after EN goes LOW) and then VNEG (DLYN2 after VPOS)
10
VNEG (DLYN2 after EN goes LOW) and then VPOS (DLYP2 after VNEG)
11
Ignored
0
No discharge
1
VPOS actively discharged
0
No discharge
1
VNEG actively discharged
SEQU and SEQD bits are just valid for TPS65132Sx
See Power-Down And Discharge (LDO) and Power-Down And Discharge (CPN) for a detailed description of how each device variant
implements the active discharge function.
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8.6.1.5 Control Register – Address 0xFF
Figure 18. Control Register
7
WED
6
5
4
3
2
RSVD[6:1]
1
0
EE/(DR)
The Reserved bits are ignored when written and return either 0 or 1 when read.
Table 7. Control Register Field Descriptions
Bit
Field
7
WED
6:1
0
24
RSVD[6:1]
EE/(DR)
Value
(binary)
Description
0
No action
1
Write EEPROM Data
Reserved
0
Read from Registers
1
Read from EEPROM
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8.6.2 Factory Default Register Value
Register address
Part number
0x00
0x01
0x02
0x03
TPS65132A
0x0E
0x0E
—
0x03
TPS65132A0
0x0A
0x0A
—
0x03
TPS65132B
0x0E
0x0E
—
0x03
TPS65132B0
0x0A
0x0A
—
0x03
TPS65132B2
0x0C
0x0C
—
0x03
TPS65132B5
0x0F
0x0F
—
0x03
TPS65132L
0x0E
0x0E
—
0x03
TPS65132L0
0x0A
0x0A
—
0x03
0x0B
0x0B
—
0x03
TPS65132L1
(1)
TPS65132S
0x0E
0x0E
0x00
0x43
TPS65132T6
0x10h
0x10h
—
0x43
TPS65132W
0x0E
0x0E
—
0x43
(1)
Product preview.
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The TPS65132xx devices, primarily intended to supplying TFT LCD displays, can be used for any application
that requires positive and negative supplies, ranging from ±4 V to ±6 V and current up to 80 mA (150 mA for the
TPS65132Sx version). Both output voltages can be set independently and their sequencing is also independent.
The following section presents the different operating modes that the device can support as well as the different
features that the user can select.
9.2 Typical Applications
9.2.1 Low-current Applications (≤ 40 mA)
The TPS65132 can be programmed to 40mA mode with the APPS bit to support applications that require output
currents up to 40 mA (refer to Figure 17). The 40mA mode limits the negative charge pump output current to 40
mA DC in order to provide the highest efficiency possible. The VPOS rail can deliver up to 200 mA DC regardless
of the mode. Output peak currents are supported by the output capacitors.
L
4.7 µH
VIN
VIN
2.5V to 5.5 V
C1
4.7 µF
SW
VPOS
OUTP
ENP
REG
ENN
SCL
C3
4.7 µF
C2
4.7 µF
VNEG
OUTN
SDA
PGND
CFLY1
AGND
CFLY2
5.4 V/40 mA
C4
2.2 µF
C5
4.7 µF
–5.4 V/40 mA
Figure 19. Typical Low-current Application Circuit
9.2.1.1 Design Requirements
Table 8. Design Parameters
PARAMETERS
26
EXAMPLE VALUES
Input Voltage Range
2.5 V to 5.5 V
Output Voltages
4.0 V to 6.0 V, –4.0 V to –6.0 V
Output Current Rating
40 mA
Boost Converter Switching Frequency
1.8 MHz
Negative Charge Pump Switching Frequency
1.0 MHz
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9.2.1.2 Detailed Design Procedure
9.2.1.2.1 Sequencing
Each output rail (VPOS and VNEG) is enabled and disabled using an external enable signal. If not explicitly
specified, the enable signal in the rest of the document refers to ENN or ENP: ENP for the positive rail VPOS and
ENN for the negative rail VNEG. Figure 33 to Figure 36 show the typical sequencing waveforms.
NOTE
In the case where VIN falls below the UVLO threshold while one of the enable signals is
still high, all converters will be shut down instantaneously and both VPOS and VNEG output
rails will be actively discharged to GND.
9.2.1.2.2 Boost Converter Design Procedure
The first step in the design procedure is to verify whether the maximum possible output current of the boost
converter supports the specific application requirements. A simple approach is to estimate the converter
efficiency, by taking the efficiency number from the provided efficiency curves at the application's maximum load
or to use a worst case assumption for the expected efficiency, e.g., 85%.
1. Duty Cycle: D = 1 -
VIN_min ´ η
VV
REG
S
2. Inductor ripple current: ΔIL =
VIN_min ´ D
fSW ´ L
DIL ö
æ
´ (1 - D )
3. Maximum output current: IOUT_max = ç ILIM_min +
2 ÷ø
è
I
DI
4. Peak switch current of the application: ISWPEAK = OUT + L
2
1- D
η = Estimated boost converter efficiency (use the number from the efficiency plots or 85% as an estimation)
ƒSW = Boost converter switching frequency (1.8 MHz)
L = Selected inductor value for the boost converter (see the Inductor Selection section)
ISWPEAK = Boost converter switch current at the desired output current (must be < [ ILIM_min + ΔIL])
ΔIL = Inductor peak-to-peak ripple current
VREG = max (VPOS, |VNEG|) + 200 mV (in 40mA mode — + 300 mV in 80mA mode — + 500 mV with
TPS65132Sx with SYNC = HIGH)
IOUT = IOUT_VPOS + | IOUT_VNEG| (IOUT_max being the maximum current delivered on each rail)
The peak switch current is the current that the integrated switch and the inductor have to handle. The calculation
must be done for the minimum input voltage where the peak switch current is highest.
9.2.1.2.2.1 Inductor Selection (Boost Converter)
Saturation current: the inductor must handle the maximum peak current (IL_SAT > ISWPEAK, or IL_SAT > [ ILIM_min +
ΔIL] as conservative approach)
DC Resistance: the lower the DCR, the lower the losses
Inductor value: in order to keep the ratio IOUT/ΔIL low enough for proper sensing operation purpose, it is
recommended to use a 4.7 µH inductor for 40mA mode (a 2.2 µH might however be used, but the efficiency
might be lower than with 4.7 µH at light loads depending on the inductor characteristics).
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Table 9. Inductor Selection Boost (1)
(1)
L
(µH)
SUPPLIER (1)
COMPONENT CODE
EIA SIZE
DCR TYP
(mΩ)
ISAT
(A)
2.2
Toko
1269AS-H-2R2N=P2
1008
130
2.4
2.2
Murata
LQM2HPN2R2MG0
1008
80
1.3
2.2
Murata
LQM21PN2R2NGC
0805
250
0.8
4.7
Toko
1269AS-H-4R7N=P2
1008
250
1.6
4.7
Murata
LQM21PN4R7MGR
0805
230
0.8
4.7
FDK
MIPS2520D4R7
1008
280
0.7
See Third-Party Products Disclaimer
9.2.1.2.2.2 Input Capacitor Selection (Boost Converter)
For best input voltage filtering low ESR ceramic capacitors are recommended. TPS65132 has an analog input
pin VIN. A 4.7 µF minimum bypass capacitor is required as close as possible from VIN to GND. This capacitor is
also used as the boost converter input capacitor.
For better input voltage filtering, this value can be increased or two capacitors can be used: one 4.7 µF input
capacitor for the boost converter as well as a 1 µF bypass capacitor close to the VIN pin. Refer to the
Recommended Operating Conditions, Table 10 and Figure 19 for input capacitor recommendations.
9.2.1.2.2.3 Output Capacitor Selection (Boost Converter)
For the best output voltage filtering, low-ESR ceramic capacitors are recommended. A minimum of 4.7 µF
ceramic output capacitor is required. Higher capacitor values can be used to improve the load transient
response. Refer to the Recommended Operating Conditions, Table 10 and Figure 19 for output capacitor
recommendations.
Table 10. Input And Output Capacitor Selection (1)
(1)
CAPACITOR
(µF)
SUPPLIER
COMPONENT CODE
EIA SIZE (Thickness
max.)
VOLTAGE RATING
(V)
COMMENTS
2.2
Murata
GRM188R61C225KAAD
0603 (0.9 mm)
16
CFLY
4.7
Murata
GRM188R61C475KAAJ
0603 (0.95 mm)
16
CIN, CNEG, CPOS,
CREG
10
Murata
GRM219R61C106KA73
0603 (0.95 mm)
16
CNEG, CREG
See Third-Party Products Disclaimer
9.2.1.2.3 Input Capacitor Selection (LDO)
The LDO input capacitor is also the boost converter output capacitor. Refer to the Recommended Operating
Conditions, Table 10 and Figure 19.
9.2.1.2.4 Output Capacitor Selection (LDO)
The LDO is designed to operate with a 4.7 µF minimum ceramic output capacitor. Refer to the Recommended
Operating Conditions, Table 10 and Figure 19.
9.2.1.2.5 Input Capacitor Selection (CPN)
The CPN input capacitor is also the boost converter output capacitor. Refer to the Recommended Operating
Conditions, Table 10 and Figure 19.
9.2.1.2.6 Output Capacitor Selection (CPN)
The CPN is designed to operate with a 4.7 µF minimum ceramic output capacitor. Refer to the Recommended
Operating Conditions, Table 10 and Figure 19.
28
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9.2.1.2.7 Flying Capacitor Selection (CPN)
The CPN needs an external flying capacitor. The minimum value is 2.2 µF. Special care must be taken while
choosing the flying capacitor as it will directly impact the output voltage accuracy and load regulation
performance. Therefore, a minimum capacitance of 1 µF must be achieved by the capacitor at a DC bias voltage
of │VNEG│ + 300 mV. For proper operation, the flying capacitor value must be lower than the output capacitor of
the boost converter on REG pin.
9.2.1.3 Application Curves
VIN = 3.7 V, VPOS = 5.4 V, VNEG = –5.4 V, unless otherwise noted
Table 11. Component List Used For The Application Curves
REFERENCE
C
L
U1
(1)
MANUFACTURER AND PART NUMBER (1)
DESCRIPTION
2.2 µF, 16 V, 0603, X5R, ceramic
Murata - GRM188R61C225KAAD
4.7 µF, 16 V, 0603, X5R, ceramic
Murata - GRM188R61C475KAAJ
10 μF, 16 V, 0603, X5R, ceramic
Murata - GRM188R61E106MA73
2.2 µH, 2.4 A, 130 mΩ, 2.5 mm × 2.0 mm × 1.0 mm
Toko - DFE252010C (1269AS-H-2R2N=P2)
4.7 µH, 1.6 A, 250 mΩ, 2.5 mm × 2.0 mm × 1.0 mm
Toko - DFE252010C (1269AS-H-4R7N=P2)
TPS65132AYFF
Texas Instruments
See Third-Party Products Disclaimer
Table 12. Table Of Graphs
PARAMETER
CONDITIONS
Figure
EFFICIENCY
Efficiency vs. Output
Current
± 5.0 V — 40mA Mode — L = 4.7 µH
Figure 20
Efficiency vs. Output
Current
± 5.4 V — 40mA Mode — L = 4.7 µH
Figure 21
Efficiency vs. Output
Current
± 5.0 V — 40mA Mode — L = 2.2 µH
Figure 22
Efficiency vs. Output
Current
± 5.4 V — 40mA Mode — L = 2.2 µH
Figure 23
CONVERTERS WAVEFORMS
VNEG Output Ripple
INEG = 2 mA / 20 mA / 40 mA — 40mA Mode — COUT = 4.7 µF
Figure 24
VNEG Output Ripple
INEG = 2 mA / 20 mA / 40 mA — 40mA Mode — COUT = 2 × 4.7 µF
Figure 25
VPOS Output Ripple
Any load
Figure 26
Load Transient
VIN = 2.9 V — IPOS = –INEG = 5 mA → 35 mA → 5 mA — 40mA Mode — L = 4.7 µH
Figure 27
Load Transient
VIN = 3.7 V — IPOS = –INEG = 5 mA → 35 mA → 5 mA — 40mA Mode — L = 4.7 µH
Figure 28
Load Transient
VIN = 4.5 V — IPOS = –INEG = 5 mA → 35 mA → 5 mA — 40mA Mode — L = 4.7 µH
Figure 29
Line Transient
VIN = 2.8 V → 4.5 V → 2.8 V — IPOS = –INEG = 0 mA — 40mA Mode — L = 4.7 µH
Figure 30
Line Transient
VIN = 2.8 V → 4.5 V → 2.8 V — IPOS = –INEG = 5 mA — 40mA Mode — L = 4.7 µH
Figure 31
Line Transient
VIN = 2.8 V → 4.5 V → 2.8 V — IPOS = –INEG = 35 mA — 40mA Mode — L = 4.7 µH
Figure 32
LOAD TRANSIENT
LINE TRANSIENT
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Table 12. Table Of Graphs (continued)
PARAMETER
CONDITIONS
Figure
POWER SEQUENCING
Power-up Sequencing
Simultaneous — no load
Figure 33
Power-down Sequencing
Simultaneous — no load with Active Discharge
Figure 34
Power-up Sequencing
Sequential — no load
Figure 35
Power-down Sequencing
Sequential — no load with Active Discharge
Figure 36
Power-up/down
Sequencing
Simultaneous — no load with Active Discharge
Figure 37
Power-up/down
Sequencing
Simultaneous — no load without Active Discharge
Figure 38
Inrush Current
Simultaneous — no load — 40mA Mode
Figure 39
Inrush Current
Sequential — no load — 40mA Mode
Figure 40
Inrush Current
Simultaneous — no load — 40mA Mode — TPS65132B2, –Lx, –Sx, –Tx, –Wx
Figure 41
Inrush Current
Sequential — no load — 40mA Mode — TPS65132B2, –Lx, –Sx, –Tx, –Wx
Figure 42
VPOS vs Output Current
VPOS = 5.0 V — 40mA Mode — IPOS = 0 mA to 40 mA — L = 4.7 µH and 2.2 µH
Figure 43
VPOS vs Output Current
VPOS = 5.4 V — 40mA Mode — IPOS = 0 mA to 40 mA — L = 4.7 µH and 2.2 µH
Figure 44
VNEG vs Output Current
VNEG = –5.0 V — 40mA Mode — INEG = 0 mA to 40 mA — L = 4.7 µH and 2.2 µH
Figure 45
VNEG vs Output Current
VNEG = –5.4 V — 40mA Mode — INEG = 0 mA to 40 mA — L = 4.7 µH and 2.2 µH
Figure 46
VPOS vs Output Voltage
VIN = 2.5 V to 5.5 V — VPOS = 5.0 V — 40mA Mode — IPOS = 20 mA — L = 4.7 µH and 2.2
µH
Figure 47
VPOS vs Output Voltage
VIN = 2.5 V to 5.5 V — VPOS = 5.4 V — 40mA Mode — IPOS = 20 mA — L = 4.7 µH and 2.2
µH
Figure 48
VNEG vs Output Voltage
VIN = 2.5 V to 5.5 V — VNEG = –5.0 V — 40mA Mode — INEG = 20 mA — L = 4.7 µH and 2.2
µH
Figure 49
VNEG vs Output Voltage
VIN = 2.5 V to 5.5 V — VNEG = –5.4 V — 40mA Mode — INEG = 20 mA — L = 4.7 µH and 2.2
µH
Figure 50
INRUSH CURRENT
LOAD REGULATION
LINE REGULATION
spacer
100
100
95
95
90
90
85
85
Efficiency (%)
Efficiency (%)
NOTE
In this section, IOUT means that the outputs are loaded with IPOS = –INEG simultaneously.
80
75
70
65
VIN = 4.5V
60
VIN = 3.7V
55
75
70
65
VIN = 4.5V
60
VIN = 3.7V
55
VIN = 2.8V
50
VIN = 2.8V
50
0
5
10
15
20
25
30
35
IOUT (mA)
± 5.0 V
40
0
5
10
L = 4.7 µH
15
20
25
30
35
IOUT (mA)
C005
± 5.4 V
Figure 20. Combined Efficiency — 40mA Mode
30
80
40
C006
L = 4.7 µH
Figure 21. Combined Efficiency — 40mA Mode
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100
100
95
95
90
90
85
85
Efficiency (%)
Efficiency (%)
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80
75
70
65
VIN = 4.5V
60
VIN = 3.7V
55
80
75
70
65
VIN = 4.5V
60
VIN = 3.7V
55
VIN = 2.8V
50
VIN = 2.8V
50
0
5
10
15
20
25
30
35
40
IOUT (mA)
± 5.0 V
0
5
10
15
20
25
30
35
40
IOUT (mA)
C003
L = 2.2 µH
± 5.4 V
Figure 22. Combined Efficiency — 40mA Mode
C004
L = 2.2 µH
Figure 23. Combined Efficiency — 40mA Mode
VNEG_AC [INEG = 2mA]
VNEG_AC [INEG = 2mA]
1
1
VNEG_AC [INEG = 20mA]
VNEG_AC [INEG = 20mA]
R2
R1
R2
R1
VNEG_AC [INEG = 40mA]
L = 4.7 µH
VNEG_AC [INEG = 40mA]
R1
20.0mV
AC
BW
R1
20.0mV
AC
BW
R2
20.0mV
AC
BW
R2
20.0mV
AC
BW
L = 4.7 µH
COUT = 4.7 µF
Figure 24. VNEG Output Voltage Ripple — 40mA Mode
COUT = 2 × 4.7 µF
Figure 25. VNEG Output Voltage Ripple — 40mA Mode
VPOS_AC
1
Figure 26. VPOS Output Voltage Ripple
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VPOS_AC
VPOS_AC
1
1
VNEG_AC
VNEG_AC
2
2
IPOS = - INEG
IPOS = - INEG
4
4
VIN = 2.9 V
ΔIOUT = 30 mA
VIN = 3.7 V
Figure 27. Load Transient — 40mA Mode
ΔIOUT = 30 mA
Figure 28. Load Transient — 40mA Mode
VPOS_AC
VPOS_AC
1
1
VNEG_AC
VNEG_AC
2
2
IPOS = - INEG
4
3
VIN = 4.5 V
ΔIOUT = 30 mA
VIN
IOUT = 0 mA
Figure 29. Load Transient — 40mA Mode
Figure 30. Line Transient — 40mA Mode
VPOS_AC
VPOS_AC
1
1
VNEG_AC
VNEG_AC
2
2
3
VIN
IOUT = 5 mA
3
ΔVIN = 1.7 V
VIN
IOUT = 35 mA
Figure 31. Line Transient — 40mA Mode
32
ΔVIN = 1.7 V
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Figure 32. Line Transient — 40mA Mode
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ENP
ENP
1
1
ENN
ENN
R2
R2
VREG
2
2
VPOS
VSW
VPOS
3
4
3
4
VNEG
R2
VNEG
5.0V
R2
Figure 33. Power-Up Sequencing — Simultaneous
5.0V
Figure 34. Power-Down Sequencing — Simultaneous
(with Active Discharge)
ENP
ENP
1
1
ENN
ENN
R2
R2
VREG
2
2
VPOS
VSW
VPOS
3
4
3
4
VNEG
VNEG
R2
R2
5.0V
Figure 35. Power-Up Sequencing — Sequential
5.0V
Figure 36. Power-Down Sequencing — Sequential
(with Active Discharge)
ENP
ENP
1
1
ENN
ENN
R2
R2
VSW
VSW
2
2
VPOS
VPOS
3
4
3
4
VNEG
VNEG
R2
R2
5.0V
Figure 37. Power-Up/Down With Active Discharge
5.0V
Figure 38. Power-Up/Down Without Active Discharge
(TPS65132Ax only)
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VREG
VREG
1
1
VPOS
VPOS
2
3
2
3
VNEG
VNEG
IIN
IIN
4
4
Figure 39. Inrush Current — Simultaneous
Figure 40. Inrush Current — Sequential
VREG
VREG
1
1
VPOS
VPOS
2
3
2
3
VNEG
VNEG
IIN
IIN
4
4
Figure 41. Inrush Current — Simultaneous
(TPS65132B2, –Lx, –Sx, –Tx, –Wx)
Figure 42. Inrush Current — Sequential
(TPS65132B2, –Lx, –Sx, –Tx, –Wx)
5.45
5.05
40mA Mode ; 4.7 µH
5.04
40mA Mode ; 2.2 µH
5.43
5.02
5.42
5.01
5.41
VPOS (V)
VPOS (V)
5.03
40mA Mode ; 4.7 µH
5.44
40mA Mode ; 2.2 µH
5.00
4.99
5.40
5.39
4.98
5.38
4.97
5.37
4.96
5.36
5.35
4.95
0
5
10
15
20
25
30
IOUT (mA)
35
40
0
10
15
20
25
30
IOUT (mA)
35
40
C009
VPOS = 5.4 V
VPOS = 5 V
Figure 44. Load Regulation
Figure 43. Load Regulation
34
5
C008
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-4.95
-5.35
40mA Mode ; 4.7 µH
-4.96
40mA Mode ; 2.2 µH
-4.97
40mA Mode ; 2.2 µH
-5.37
-5.38
VNEG (V)
-4.98
VNEG (V)
40mA Mode ; 4.7 µH
-5.36
-4.99
-5.00
-5.01
-5.39
-5.40
-5.41
-5.02
-5.42
-5.03
-5.43
-5.04
-5.44
-5.05
-5.45
0
5
10
15
20
25
30
35
IOUT (mA)
40
0
5
10
15
20
VNEG = –5 V
35
40
C01
Figure 46. Load Regulation
5.02
5.42
40mA Mode ; 4.7 µH
40mA Mode ; 4.7 µH
40mA Mode ; 2.2 µH
5.01
40mA Mode ; 2.2 µH
5.41
5.00
VPOS (V)
VPOS (V)
30
VNEG = –5.4 V
Figure 45. Load Regulation
4.99
4.98
5.40
5.39
5.38
4.97
5.37
2.5 2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9 5.1 5.3 5.5
VIN (V)
2.5 2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9 5.1 5.3 5.5
VIN (V)
C01
VPOS = 5 V
C01
VPOS = 5.4 V
Figure 47. Line Regulation
Figure 48. Line Regulation
-4.96
-5.36
40mA Mode ; 4.7 µH
40mA Mode ; 4.7 µH
40mA Mode ; 2.2 µH
40mA Mode ; 2.2 µH
-5.37
VNEG (V)
-4.97
VNEG (V)
25
IOUT (mA)
C01
-4.98
-4.99
-5.00
-5.38
-5.39
-5.40
-5.01
-5.41
2.5 2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9 5.1 5.3 5.5
VIN (V)
2.5 2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9 5.1 5.3 5.5
VIN (V)
C01
VNEG = –5 V
C01
VNEG = –5.4 V
Figure 49. Line Regulation
Figure 50. Line Regulation
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9.2.2 Mid-current Applications (≤ 80 mA)
The TPS65132 can be programmed to 80mA mode with the APPS bit to support applications that require output
currents up to 80 mA (refer to Figure 17). The 80mA mode is limiting the negative charge pump (CPN) output
current to 80 mA DC in order to provide the highest efficiency possible where the V(POS) rail can deliver up to 200
mA DC regardless of the mode. Output peak currents are supported by the output capacitors.
L
2.2 µH
VIN
VIN
2.5V to 5.5 V
C1
4.7 µF
SW
VPOS
OUTP
ENP
REG
ENN
SCL
C3
10 µF
C2
10 µF
VNEG
OUTN
SDA
PGND
CFLY1
AGND
CFLY2
5.4 V/80 mA
C4
4.7 µF
C5
10 µF
–5.4 V/80 mA
Figure 51. Typical Mid-current Application Circuit
9.2.2.1 Design Requirements
Table 13. Design Parameters
PARAMETERS
EXAMPLE VALUES
Input Voltage Range
2.5 V to 5.5 V
Output Voltages
4.0 V to 6.0 V, –4.0 V to –6.0 V
Output Current Rating
80 mA
Boost Converter Switching Frequency
1.8 MHz
Negative Charge Pump Switching Frequency
1.0 MHz
9.2.2.2 Detailed Design Procedure
The design procedure for the mid-current applications (80mA mode) is identical to the one for the low-current
applications (40mA mode), except for the BOM (bill of materials). Refer to the Detailed Design Procedure for
details about the sequencing and the general component selection.
9.2.2.2.1 Boost Converter Design Procedure
9.2.2.2.1.1 Inductor Selection (Boost Converter)
In order to keep the ratio IOUT/ΔIL low enough for proper sensing operation purpose, it is recommended to use a
2.2 µH inductor for 80mA mode. For details, see Inductor Selection (Boost Converter).
9.2.2.2.1.2 Input Capacitor Selection (Boost Converter)
A 4.7 µF minimum bypass capacitor is required as close as possible from VIN to GND. This capacitor is also
used as the boost converter input capacitor.
For better input voltage filtering, this value can be increased or two capacitors can be used: one 4.7 µF input
capacitor for the boost converter as well as a 1 µF bypass capacitor close to the VIN pin. Refer to the
Recommended Operating Conditions, Table 10 and Figure 51 for input capacitor recommendations.
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9.2.2.2.1.3 Output Capacitor Selection (Boost Converter)
For best output voltage filtering low ESR ceramic capacitors are recommended. A minimum of 10 µF ceramic
output capacitor is required. Higher capacitor values can be used to improve the load transient response. Refer
to the Recommended Operating Conditions, Table 10 and Figure 51 for output capacitor recommendations.
9.2.2.2.2 Input Capacitor Selection (LDO)
The LDO input capacitor is also the boost converter output capacitor. Refer to the Recommended Operating
Conditions, Table 10 and Figure 51.
9.2.2.2.3 Output Capacitor Selection (LDO)
The LDO is designed to operate with a 4.7 µF minimum ceramic output capacitor. Refer to the Recommended
Operating Conditions, Table 10 and Figure 51.
9.2.2.2.4 Input Capacitor Selection (CPN)
The CPN input capacitor is also the boost converter output capacitor. Refer to the Recommended Operating
Conditions, Table 10 and Figure 51.
9.2.2.2.5 Output Capacitor Selection (CPN)
The CPN is designed to operate with a 10 µF minimum ceramic output capacitor. Refer to the Recommended
Operating Conditions, Table 10 and Figure 51.
9.2.2.2.6 Flying Capacitor Selection (CPN)
The CPN needs an external flying capacitor. The minimum value is 4.7 µF. Special care must be taken while
choosing the flying capacitor as it will directly impact the output voltage accuracy and load regulation
performance. Therefore, a minimum capacitance of 2.2 µF must be achieved by the capacitor at a DC bias
voltage of │VNEG│ + 300 mV. For proper operation, the flying capacitor value must be lower than the output
capacitor of the boost converter on REG pin.
9.2.2.3 Application Curves
VIN = 3.7 V, VPOS = 5.4 V, VNEG = –5.4 V, unless otherwise noted
Table 14. Component List For Typical Characteristics Circuits
REFERENCE
C
L
U1
(1)
MANUFACTURER AND PART NUMBER (1)
DESCRIPTION
2.2 µF, 16 V, 0603, X5R, ceramic
Murata - GRM188R61C225KAAD
4.7 µF, 16 V, 0603, X5R, ceramic
Murata - GRM188R61C475KAAJ
10 μF, 16 V, 0603, X5R, ceramic
Murata - GRM188R61E106MA73
2.2 µH, 2.4 A, 130 mΩ, 2.5 mm × 2.0 mm × 1.0 mm
Toko - DFE252010C (1269AS-H-2R2N=P2)
TPS65132AYFF
Texas Instruments
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Table 15. Table Of Graphs
PARAMETER
CONDITIONS
Figure
EFFICIENCY
Efficiency vs. Output
Current
± 5.0 V — 80mA Mode — L = 2.2 µH
Figure 52
Efficiency vs. Output
Current
± 5.4 V — 80mA Mode — L = 2.2 µH
Figure 53
CONVERTERS WAVEFORMS
VNEG Output Ripple
INEG = 4 mA / 40 mA / 80 mA — 80mA Mode — COUT = 10 µF
Figure 54
VNEG Output Ripple
INEG = 4 mA / 40 mA / 80 mA — 80mA Mode — COUT = 2 × 10 µF
Figure 55
VPOS Output Ripple
IPOS = 150 mA — 80mA Mode
Figure 56
Load Transient
VIN = 2.9 V — IPOS = –INEG = 10 mA → 70 mA → 10 mA — 80mA Mode — L = 2.2 µH
Figure 57
Load Transient
VIN = 3.7 V — IPOS = –INEG = 10 mA → 70 mA → 10 mA — 80mA Mode — L = 2.2 µH
Figure 58
Load Transient
VIN = 4.5 V — IPOS = –INEG = 10 mA → 70 mA → 10 mA — 80mA Mode — L = 2.2 µH
Figure 59
Line Transient
VIN = 2.8 V → 4.5 V → 2.8 V — IPOS = –INEG = 0 mA — 80mA Mode — L = 2.2 µH
Figure 60
Line Transient
VIN = 2.8 V → 4.5 V → 2.8 V — IPOS = –INEG = 40 mA — 80mA Mode — L = 2.2 µH
Figure 61
Line Transient
VIN = 2.8 V → 4.5 V → 2.8 V — IPOS = –INEG = 70 mA — 80mA Mode — L = 2.2 µH
Figure 62
Power-up Sequencing
Simultaneous — no load
Figure 63
Power-down Sequencing
Simultaneous — no load with Active Discharge
Figure 64
Power-up Sequencing
Sequential — no load
Figure 65
Power-down Sequencing
Sequential — no load with Active Discharge
Figure 66
Power-up/down
Sequencing
Simultaneous — no load with Active Discharge
Figure 67
Power-up/down
Sequencing
Simultaneous — no load without Active Discharge
Figure 68
Inrush Current
Simultaneous — no load — 80mA Mode
Figure 69
Inrush Current
Sequential — no load — 80mA Mode
Figure 70
Inrush Current
Simultaneous — no load — 80mA Mode — TPS65132B2, –Lx, –Sx, –Tx, –Wx
Figure 71
Inrush Current
Sequential — no load — 80mA Mode — TPS65132B2, –Lx, –Sx, –Tx, –Wx
Figure 72
VPOS vs Output Current
VPOS = 5.0 V — 80mA Mode — IPOS = 0 mA to 80 mA — L = 2.2 µH
Figure 73
VPOS vs Output Current
VPOS = 5.4 V — 80mA Mode — IPOS = 0 mA to 80 mA — L = 2.2 µH
Figure 74
VNEG vs Output Current
VNEG = –5.0 V — 80mA Mode — INEG = 0 mA to 80 mA — L = 2.2 µH
Figure 75
VNEG vs Output Current
VNEG = –5.4 V — 80mA Mode — INEG = 0 mA to 80 mA — L = 2.2 µH
Figure 76
VPOS vs Output Voltage
VIN = 2.5 V to 5.5 V — VPOS = 5.0 V — 80mA Mode — IPOS = 60 mA — L = 2.2 µH
Figure 77
VPOS vs Output Voltage
VIN = 2.5 V to 5.5 V — VPOS = 5.4 V — 80mA Mode — IPOS = 60 mA — L = 2.2 µH
Figure 78
VNEG vs Output Voltage
VIN = 2.5 V to 5.5 V — VNEG = –5.0 V — 80mA Mode — INEG = 60 mA — L = 2.2 µH
Figure 79
VNEG vs Output Voltage
VIN = 2.5 V to 5.5 V — VNEG = –5.4 V — 80mA Mode — INEG = 60 mA — L = 2.2 µH
Figure 80
LOAD TRANSIENT
LINE TRANSIENT
POWER SEQUENCING
INRUSH CURRENT
LOAD REGULATION
LINE REGULATION
spacer
NOTE
In this section, IOUT means that the outputs are loaded with IPOS = –INEG simultaneously.
38
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100
100
95
95
90
90
85
85
Efficiency (%)
Efficiency (%)
www.ti.com
80
75
70
65
70
VIN = 4.5V
60
VIN = 3.7V
55
75
65
VIN = 4.5V
60
80
VIN = 3.7V
55
VIN = 2.8V
50
VIN = 2.8V
50
0
5
10 15 20 25 30 35 40 45 50 55 60 65 70 75 80
IOUT (mA)
±5V
0
5
10 15 20 25 30 35 40 45 50 55 60 65 70 75 80
IOUT (mA)
C001
L = 2.2 µH
± 5.4 V
Figure 52. Combined Efficiency — 80mA Mode
C002
L = 2.2 µH
Figure 53. Combined Efficiency — 80mA Mode
VNEG_AC [INEG = 4mA]
VNEG_AC [INEG = 4mA]
1
1
VNEG_AC [INEG = 40mA]
VNEG_AC [INEG = 40mA]
R2
R1
VNEG_AC [INEG = 80mA]
R2
R1
VNEG_AC [INEG = 80mA]
L = 2.2 µH
R1
20.0mV
AC
BW
R1
20.0mV
AC
BW
R2
20.0mV
AC
BW
R2
20.0mV
AC
BW
L = 2.2 µH
COUT = 10 µF
Figure 54. VNEG Output Voltage Ripple — 80mA Mode
COUT = 2 × 10 µF
Figure 55. VNEG Output Voltage Ripple — 80mA Mode
VPOS_AC
1
Figure 56. VPOS Output Voltage Ripple
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VPOS_AC
VPOS_AC
1
1
VNEG_AC
VNEG_AC
2
4
2
4
IPOS = - INEG
VIN = 2.9 V
ΔIOUT = 60 mA
IPOS = - INEG
VIN = 3.7 V
Figure 57. Load Transient — 80mA Mode
Figure 58. Load Transient — 80mA Mode
VPOS_AC
VPOS_AC
1
1
VNEG_AC
VNEG_AC
2
4
2
3
IPOS = - INEG
VIN = 4.5 V
ΔIOUT = 60 mA
VIN
IOUT = 0 mA
Figure 59. Load Transient — 80mA Mode
VPOS_AC
1
VNEG_AC
VNEG_AC
2
2
VIN
IOUT = 40 mA
3
ΔVIN = 1.7 V
VIN
IOUT = 70 mA
Figure 61. Line Transient — 80mA Mode
40
ΔVIN = 1.7 V
Figure 60. Line Transient — 80mA Mode
VPOS_AC
1
3
ΔIOUT = 60 mA
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ΔVIN = 1.7 V
Figure 62. Line Transient — 80mA Mode
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ENP
ENP
1
1
ENN
ENN
R2
R2
VREG
2
2
VPOS
VSW
VPOS
3
4
3
4
VNEG
R2
VNEG
5.0V
R2
Figure 63. Power-Up Sequencing — Simultaneous
5.0V
Figure 64. Power-Down Sequencing — Simultaneous
(with Active Discharge)
ENP
ENP
1
1
ENN
ENN
R2
R2
VREG
2
2
VPOS
VSW
VPOS
3
4
3
4
VNEG
VNEG
R2
R2
5.0V
Figure 65. Power-Up Sequencing — Sequential
5.0V
Figure 66. Power-Down Sequencing — Sequential
(with Active Discharge)
ENP
ENP
1
1
ENN
ENN
R2
R2
VSW
VSW
2
2
VPOS
VPOS
3
4
3
4
VNEG
VNEG
R2
R2
5.0V
Figure 67. Power-Up/Down With Active Discharge
5.0V
Figure 68. Power-Up/Down Without Active Discharge
(TPS65132Ax only)
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VREG
VREG
1
1
VPOS
VPOS
2
3
2
3
VNEG
VNEG
IIN
IIN
4
4
Figure 69. Inrush Current — Simultaneous
Figure 70. Inrush Current — Sequential
VREG
VREG
1
1
VPOS
VPOS
2
3
2
3
VNEG
VNEG
IIN
IIN
4
4
Figure 71. Inrush Current — Simultaneous
(TPS65132B2, –Lx, –Sx, –Wx)
Figure 72. Inrush Current — Sequential
(TPS65132B2, –Lx, –Sx, –Wx)
5.05
5.45
80mA Mode ; 2.2 µH
80mA Mode ; 2.2 µH
5.44
5.03
5.43
5.02
5.42
5.01
5.41
VPOS (V)
VPOS (V)
5.04
5.00
4.99
5.40
5.39
4.98
5.38
4.97
5.37
4.96
5.36
4.95
5.35
0
5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80
IOUT (mA)
VPOS = 5 V
0
IOUT (mA)
C017
VPOS = 5.4 V
Figure 73. Load Regulation
42
5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80
C016
Figure 74. Load Regulation
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-4.95
-5.35
80mA Mode ; 2.2 µH
80mA Mode ; 2.2 µH
-5.36
-4.97
-5.37
-4.98
-5.38
VNEG (V)
VNEG (V)
-4.96
-4.99
-5.00
-5.01
-5.39
-5.40
-5.41
-5.02
-5.42
-5.03
-5.43
-5.04
-5.44
-5.05
-5.45
0
5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80
IOUT (mA)
0
5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80
IOUT (mA)
C01
VNEG = –5 V
Figure 75. Load Regulation
Figure 76. Load Regulation
5.01
5.41
80mA Mode ; 2.2 µH
5.00
5.40
4.99
5.39
VPOS (V)
VPOS (V)
80mA Mode ; 2.2 µH
4.98
4.97
5.38
5.37
4.96
5.36
2.5 2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9 5.1 5.3 5.5
VIN (V)
2.5 2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9 5.1 5.3 5.5
VIN (V)
C02
VPOS = 5 V
C02
VPOS = 5.4 V
Figure 77. Line Regulation
Figure 78. Line Regulation
-4.97
-5.37
80mA Mode ; 2.2 µH
80mA Mode ; 2.2 µH
-5.38
VNEG (V)
-4.98
VNEG (V)
C01
VNEG = –5.4 V
-4.99
-5.00
-5.01
-5.39
-5.40
-5.41
-5.02
-5.42
2.5 2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9 5.1 5.3 5.5
VIN (V)
VNEG = –5 V
2.5 2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9 5.1 5.3 5.5
VIN (V)
C02
C02
VNEG = –5.4 V
Figure 79. Line Regulation
Figure 80. Line Regulation
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9.2.3 High-current Applications (≤ 150 mA)
The TPS65132Sx version allows output current up to 150 mA on both VPOS and VNEG when the SYNC pin is
pulled HIGH. If the SYNC pin is pulled LOW, the TPS65132Sx can be programmed to 40mA or 80mA mode with
the APPS bit to lower the output current capability of the VNEG rail if needed (in the case the efficiency is an
important parameter). See Low-current Applications (≤ 40 mA) and Mid-current Applications (≤ 80 mA) for more
details about the 40mA and 80mA modes.
L
2.2 µH
VIN
VIN
2.5V to 5.5 V
C1
4.7 µF
SW
VPOS
OUTP
EN
REG
SYNC
SCL
C2
10 µF
VNEG
OUTN
SDA
PGND
CFLY1
AGND
CFLY2
5.4 V/150 mA
C3
10 µF
C5
10 µF
C4
4.7 µF
–5.4 V/150 mA
Figure 81. Typical Application Circuit For High Current
9.2.3.1 Design Requirements
Table 16. Design Parameters
PARAMETERS
EXAMPLE VALUES
Input Voltage Range
2.5 V to 5.5 V
Output Voltages
4.0 V to 6.0 V, –4.0 V to –6.0 V
Output Current Rating
150 mA
Boost Converter Switching Frequency
1.8 MHz
Negative Charge Pump Switching Frequency
1.0 MHz
9.2.3.2 Detailed Design Procedure
The design procedure and BOM list of the TPS65132Sx is identical to the 80mA mode. Please refer to the Midcurrent Applications (≤ 80 mA) for more details about the general component selection.
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9.2.3.2.1 Sequencing
The output rails (VPOS and VNEG) are enabled and disabled using an external logic signal on the EN pin. The
power-up and power-down sequencing events are programmable. Please refer to Programmable Sequencing
Scenarios for the different sequencing as well as Registers for the programming options. Figure 98 to Figure 103
show the typical sequencing waveforms.
VPOS
Power-Down Sequencing
Power-Up Sequencing
Simultaneous
VIN
VNEG
VNEG
VIN
EN
VIN
EN
EN
DLYP1
VPOS
VNEG
DLYP1
VPOS
VNEG
DLYP1
VPOS
VNEG
DLYN1
DLYN1
VIN
VIN
VIN
EN
EN
EN
VPOS
VPOS
VPOS
DLYP2
DLYP2
DLYP2
VNEG
VPOS
VNEG
VNEG
DLYN2
DLYN2
Figure 82. Programmable Sequencing Scenarios
•
•
NOTE
In the case where the UVLO falling threshold is triggered while the enable signal is still
HIGH (EN), all converters will be shut down instantaneously and both VPOS and VNEG
output rails will be actively discharged to GND.
The power-up and power-down sequencing must be finalized (all delays have passed)
before re-toggling the EN pin.
9.2.3.2.2 SYNC = HIGH
When the SYNC pin is pulled HIGH, the boost converter voltage increases instantaneously to allow enough
headroom to deliver the 150 mA. See Figure 88 to Figure 91 for detailed waveforms.
When SYNC pin is pulled LOW, the boost converter keeps its offset for 300 µs typically, and during this time, the
device is still capable if supplying 150 mA on both output rail. After these 300 µs have passed, current limit
settles at 40 mA or 80 mA maximum, depending on the application mode it is programmed to (40mA or 80mA —
see Low-current Applications (≤ 40 mA) and Mid-current Applications (≤ 80 mA) for more details ) and the boost
output voltage regulates down to its nominal value.
9.2.3.2.3 Startup
The TPS65132Sx can startup with SYNC = HIGH, however, the boost offset as well as the 150 mA output
current capability will only be available as soon as the last rail to start is in regulation.
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9.2.3.3 Application Curves
VIN= 3.7 V, VPOS= 5.4 V, VNEG= –5.4 V, unless otherwise noted
Table 17. Component List For Typical Characteristics Circuits
REFERENCE
C
L
U1
DESCRIPTION
MANUFACTURER AND PART NUMBER
2.2 µF, 16 V, 0603, X5R, ceramic
Murata - GRM188R61C225KAAD
4.7 µF, 16 V, 0603, X5R, ceramic
Murata - GRM188R61C475KAAJ
10 μF, 16 V, 0603, X5R, ceramic
Murata - GRM188R61E106MA73
2.2 µH, 2.4 A, 130 mΩ, 2.5 mm × 2.0 mm × 1.0 mm
Toko - DFE252010C (1269AS-H-2R2N=P2)
TPS65132SYFF
Texas Instruments
Table 18. Table Of Graphs
PARAMETER
CONDITIONS
Figure
EFFICIENCY
Efficiency vs.
Output Current
± 5.0 V — SYNC = HIGH — L = 2.2 µH
Figure 83
Efficiency vs.
Output Current
± 5.4 V — SYNC = HIGH — L = 2.2 µH
Figure 84
CONVERTERS WAVEFORMS
VPOS Output
Ripple
IPOS = 150 mA — SYNC = HIGH
Figure 85
VNEG Output
Ripple
INEG = 10mA / 80 mA / 150 mA — SYNC = HIGH — COUT = 10 µF
Figure 86
VNEG Output
Ripple
INEG = 4 mA / 40 mA / 80 mA — SYNC = HIGH — COUT = 2 × 10 µF
Figure 87
SYNC = HIGH Signal
SYNC = HIGH
IPOS = –INEG = 10 mA
Figure 88
SYNC = HIGH
IPOS = –INEG = 150 mA
Figure 89
SYNC = HIGH
Zoom
IPOS = –INEG = 10 mA
Figure 90
SYNC = LOW
Zoom
IPOS = –INEG = 10 mA
Figure 91
LOAD TRANSIENT
Load Transient
VIN = 2.9 V — IPOS = –INEG = 10 mA → 150 mA → 10 mA — SYNC = HIGH — L = 2.2 µH
Figure 92
Load Transient
VIN = 3.7 V — IPOS = –INEG = 10 mA → 150 mA → 10 mA — SYNC = HIGH — L = 2.2 µH
Figure 93
Load Transient
VIN = 4.5 V — IPOS = –INEG = 10 mA → 150 mA → 10mA — SYNC = HIGH — L = 2.2 µH
Figure 94
Line Transient
VIN = 2.8 V → 4.5 V → 2.8 V — IPOS = –INEG = 10 mA — SYNC = HIGH — L = 2.2 µH
Figure 95
Line Transient
VIN = 2.8 V → 4.5 V → 2.8 V — IPOS = –INEG = 100 mA — SYNC = HIGH — L = 2.2 µH
Figure 96
Line Transient
VIN = 2.8 V → 4.5 V → 2.8 V — IPOS = –INEG = 150 mA — SYNC = HIGH — L = 2.2 µH
Figure 97
LINE TRANSIENT
POWER SEQUENCING
Power-up
Sequencing
Simultaneous — no load
Figure 98
Power-down
Sequencing
Simultaneous — no load with Active Discharge
Figure 99
Power-up
Sequencing
Sequential (VPOS → VNEG) — no load
Figure 100
Power-down
Sequencing
Sequential (VNEG → VPOS) — no load with Active Discharge
Figure 101
Power-up
Sequencing
Sequential (VNEG → VPOS) — no load
Figure 102
Power-down
Sequencing
Sequential (VPOS → VNEG) — no load with Active Discharge
Figure 103
46
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Table 18. Table Of Graphs (continued)
PARAMETER
CONDITIONS
Figure
Power-up/down
Sequencing
Simultaneous — no load without Active Discharge
Figure 104
Power-up/down
Sequencing
Simultaneous — no load with Active Discharge
Figure 105
INRUSH CURRENT
Inrush Current
Simultaneous — no load — SYNC = HIGH — L = 2.2 µH
Figure 106
Inrush Current
Sequential — no load — SYNC = HIGH — L = 2.2 µH
Figure 107
LOAD REGULATION
VPOS vs Output
Current
VPOS = 5.0 V — SYNC = HIGH — IPOS = 0 mA to 150 mA — L = 2.2 µH
Figure 108
VPOS vs Output
Current
VPOS = 5.4 V — SYNC = HIGH — IPOS = 0 mA to 150 mA — L = 2.2 µH
Figure 109
VNEG vs Output
Current
VNEG = –5.0 V — SYNC = HIGH — INEG = 0 mA to 150 mA — L = 2.2 µH
Figure 110
VNEG vs Output
Current
VNEG = –5.4 V — SYNC = HIGH — INEG = 0 mA to 150 mA — L = 2.2 µH
Figure 111
LINE REGULATION
VPOS vs Output
Voltage
VIN = 2.5 V to 5.5 V — VPOS = 5.0 V — SYNC = HIGH — IPOS = 120 mA — L = 2.2 µH
Figure 112
VPOS vs Output
Voltage
VIN = 2.5 V to 5.5 V — VPOS = 5.4 V — SYNC = HIGH — IPOS = 120 mA — L = 2.2 µH
Figure 113
VNEG vs Output
Voltage
VIN = 2.5 V to 5.5 V — VNEG = –5.0 V — SYNC = HIGH — INEG = 120 mA — L = 2.2 µH
Figure 114
VNEG vs Output
Voltage
VIN = 2.5 V to 5.5 V — VNEG = –5.4 V — SYNC = HIGH — INEG = 120 mA — L = 2.2 µH
Figure 115
spacer
NOTE
In this section, IOUT means that the outputs are loaded with IPOS = –INEG simultaneously.
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100
100
95
95
90
90
85
85
Efficiency (%)
Efficiency (%)
SLVSBM1H – JUNE 2013 – REVISED NOVEMBER 2016
80
75
70
65
70
VIN = 4.5V
60
VIN = 3.7V
55
75
65
VIN = 4.5V
60
80
VIN = 3.7V
55
VIN = 2.8V
50
VIN = 2.8V
50
0 10 20 30 40 50 60 70 80 90 100110120130140150
IOUT (mA)
0 10 20 30 40 50 60 70 80 90 100110120130140150
IOUT (mA)
C02
Figure 83. Combined Efficiency — ± 5.0 V — SYNC = HIGH
L = 2.2 µH
C02
Figure 84. Combined Efficiency — ± 5.4 V — SYNC = HIGH
L = 2.2 µH
VNEG_AC [INEG = 10mA]
1
VNEG_AC [INEG = 80mA]
VPOS_AC
R2
1
VNEG_AC [INEG = 150mA]
R1
R1R1
R2
Figure 85. VPOS Output Voltage Ripple — SYNC = HIGH
50.0mV
50.0mVACACBWBW
50.0mV
AC
BW
Figure 86. VNEG Output Voltage Ripple — SYNC = HIGH —
L = 2.2 µH — COUT = 10 µF
VNEG_AC [INEG = 10mA]
1
VNEG_AC [INEG = 80mA]
R2
VNEG_AC [INEG = 150mA]
R1
R1
50.0mV
AC
BW
R2
50.0mV
AC
BW
Figure 87. VNEG Output Voltage Ripple — SYNC = HIGH —
L = 2.2 µH — COUT = 2 × 10 µF
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SYNC
SYNC
1
1
VREG_AC
VREG_AC
2
2
VPOS
VPOS
3
3
VNEG
VNEG
4
4
Figure 88. SYNC Signal — IOUT = 10 mA
Figure 89. SYNC Signal — IOUT = 150 mA
SYNC
SYNC
1
1
VREG
2
2
VPOS
VPOS
3
3
VNEG
VNEG
4
4
Figure 90. SYNC = HIGH (zoom)
1
VREG
VPOS_AC
Figure 91. SYNC = LOW (zoom) with Delay
1
VPOS_AC
VNEG_AC
VNEG_AC
2
2
IPOS = - INEG
IPOS = - INEG
4
4
Figure 92. Load Transient — VIN = 2.9 V
SYNC = HIGH — ΔIOUT = 140 mA
Figure 93. Load Transient — VIN = 3.7 V
SYNC = HIGH — ΔIOUT = 140 mA
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VPOS_AC
VPOS_AC
1
VNEG_AC
VNEG_AC
2
2
IPOS = - INEG
3
4
VIN
Figure 94. Load Transient — VIN = 4.5 V
SYNC = HIGH — ΔIOUT = 140 mA
Figure 95. Line Transient — IOUT = 10 mA
SYNC = HIGH — ΔVIN = 1.7 V
VPOS_AC
VPOS_AC
1
1
VNEG_AC
VNEG_AC
2
3
2
VIN
3
Figure 96. Line Transient — IOUT = 100 mA
SYNC = HIGH — ΔVIN = 1.7 V
VIN
Figure 97. Line Transient — IOUT = 150 mA
SYNC = HIGH — ΔVIN = 1.7 V
EN
1
EN
1
VSW
2
VREG
2
VPOS
3
VPOS
VNEG
3
4
VNEG
4
Figure 98. Power-Up Sequencing — Simultaneous
SYNC = HIGH
50
Figure 99. Power-Down Sequencing — Simultaneous
SYNC = HIGH
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EN
1
EN
VSW
1
2
VREG
2
VPOS
3
VPOS
3
4
VNEG
VNEG
4
Figure 100. Power-Up Sequencing — Sequential
VPOS → VNEG — SYNC = HIGH
Figure 101. Power-Down Sequencing — Sequential
VNEG → VPOS— SYNC = HIGH
EN
1
EN
VSW
1
2
VREG
2
VPOS
3
VPOS
3
4
VNEG
VNEG
4
Figure 102. Power-Up Sequencing — Sequential
VNEG → VPOS — SYNC = HIGH
Figure 103. Power-Down Sequencing — Sequential
VPOS → VNEG — SYNC = HIGH
EN
EN
1
1
VSW
VSW
2
2
VPOS
VPOS
3
3
VNEG
VNEG
4
4
Figure 104. Power-Up/Down Without Active Discharge —
SYNC = HIGH
Figure 105. Power-Up/Down With Active Discharge —
SYNC = HIGH
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VREG
VREG
1
1
VPOS
VPOS
2
3
2
3
VNEG
VNEG
IIN
IIN
4
4
Figure 106. Inrush Current — Simultaneous —
SYNC = HIGH
Figure 107. Inrush Current — Sequential
SYNC = HIGH
5.05
5.45
SYNC = HIGH_2.2µH
5.43
5.02
5.42
5.01
5.41
5.00
4.99
5.40
5.39
4.98
5.38
4.97
5.37
4.96
5.36
4.95
5.35
0 10 20 30 40 50 60 70 80 90 100110120130140150
IOUT (mA)
0 10 20 30 40 50 60 70 80 90 100110120130140150
IOUT (mA)
C02
Figure 108. Load Regulation VPOS = 5.0 V — SYNC = HIGH
-5.35
SYNC = HIGH_2.2µH
-4.96
SYNC = HIGH_2.2µH
-5.36
-4.97
-5.37
-4.98
-5.38
VNEG (V)
VNEG (V)
C02
Figure 109. Load Regulation VPOS = 5.4 V — SYNC = HIGH
-4.95
-4.99
-5.00
-5.01
-5.39
-5.40
-5.41
-5.02
-5.42
-5.03
-5.43
-5.04
-5.44
-5.05
-5.45
0 10 20 30 40 50 60 70 80 90 100110120130140150
IOUT (mA)
0 10 20 30 40 50 60 70 80 90 100110120130140150
IOUT (mA)
C02
Figure 110. Load Regulation VNEG = –5.0 V — SYNC =
HIGH
52
SYNC = HIGH_2.2µH
5.44
5.03
VPOS (V)
VPOS (V)
5.04
C02
Figure 111. Load Regulation VNEG = –5.4 V — SYNC =
HIGH
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5.03
-4.97
SYNC = HIGH_2.2 µH
5.02
-4.98
5.01
-4.99
VNEG (V)
VNEG (V)
SYNC = HIGH_2.2 µH
5.00
-5.00
4.99
-5.01
4.98
-5.02
4.97
-5.03
2.5 2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9 5.1 5.3 5.5
VIN (V)
2.5 2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9 5.1 5.3 5.5
VIN (V)
C03
Figure 113. Line Regulation VPOS = 5.4 V — SYNC = HIGH
-4.97
-5.37
SYNC = HIGH_2.2 µH
80mA Mode ; 2.2 µH
-5.38
VNEG (V)
-4.98
VNEG (V)
C03
Figure 112. Line Regulation VPOS = 5.0 V — SYNC = HIGH
-4.99
-5.00
-5.39
-5.40
-5.41
-5.01
-5.42
-5.02
2.5 2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9 5.1 5.3 5.5
VIN (V)
2.5 2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9 5.1 5.3 5.5
VIN (V)
C02
Figure 114. Line Regulation VNEG = –5.0 V — SYNC = HIGH
C03
Figure 115. Line Regulation VNEG = –5.4 V — SYNC = HIGH
10 Power Supply Recommendations
The devices are designed to operate from an input voltage supply range between 2.5 V and 5.5 V. This input
supply must be well regulated. A ceramic input capacitor with a value of 4.7 μF is a typical choice.
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11 Layout
11.1 Layout Guidelines
PCB layout is an important task in the power supply design. Good PCB layout minimizes EMI and allows very
good output voltage regulation. For the TPS65132 the following PCB layout guidelines are recommended.
• Keep the power ground plane on the top layer (all capacitor grounds and PGND pins must be
connected together with one uninterrupted ground plane).
• AGND and PGND must be connected together on the same ground plane.
• Place the flying capacitor as close as possible to the IC.
• Always avoid vias when possible. They have high inductance and resistance. If vias are necessary, always
use more than one in parallel to decrease parasitics especially for power lines.
• Connect REG pins together.
• For high dv/dt signals (switch pin traces): keep copper area to a minimum to prevent making unintentional
parallel plate capacitors with other traces or to a ground plane. Best to route signal and return on same layer.
• For high di/dt signals: keep traces short, wide and closely spaced. This will reduce stray inductance and
decrease the current loop area to help prevent EMI.
• Keep input capacitor close to the IC with low inductance traces.
• Keep trace from switching node pin to inductor short if possible: it reduces EMI emissions and noise that
may couple into other portions of the converter.
• Isolate analog signal paths from power paths.
11.2 Layout Example
C5
C2
L1
C4
AGND
PGND
REG
ENP
C1
CFLY2
SW
OUTN
SW
ENN
20
19
18
17
SCL
VIN
CFLY1
SDA
SW
REG
PGND
1
16
OUTP
PGND
2
15
OUTP C3
14
REG
CFLY1
AGND
L1
PGND
REG
OUTP
C3
AGND
C1
3
PowerPAD
C2
VIN
4
13
ENP
5
12
ENN
6
11
PGND
8
9
SCL
OUTN
PGND
10
CFLY2
7
SDA
C4
Via to signal layer on internal or bottom layer.
C5
Via to signal layer on internal or bottom layer.
Figure 116. PCB Layout Example for CSP Package
54
Figure 117. PCB Layout Example for QFN Package
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12 Device and Documentation Support
12.1 Device Support
12.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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13.1 CSP Package Summary
CHIP SCALE PACKAGE
(top view)
CHIP SCALE PACKAGE
(bottom view)
65132xx
TPS
D
TIYMLLLL S
E
E1
E2
E3
D1
D2
D3
C1
C2
C3
B1
B2
B3
A1
A2
A3
Ball A1
Code:
TI -- TI letters
YM -- Year-Month date code
LLLL -- Lot trace code
S -- Assembly site code
xx -- Revision code (contains alpha-numeric characters - can be left
blank), refer to the Ordering Information section for detailed information)
13.1.1 Chip Scale Package Dimensions
The TPS65132 device is available in a 15-bump chip scale package (YFF, NanoFree™). The package
dimensions are given as:
• D = 2108 ±30 μm
• E = 1514 ±30 μm
56
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CSP Package Summary (continued)
13.1.2 RVC Package Summary
QFN PACKAGE
(top view)
QFN PACKAGE
(bottom view)
11
12
13
14
15
16
10
18
9
65132xx
TI YMS
LLLL
17
PowerPAD
8
19
7
20
6
5
4
3
2
1
Pin 1
Code:
TI -- TI letters
YM -- Year-Month date code
LLLL -- Lot trace code
S -- Assembly site code
xx -- Revision code (contains alpha-numeric characters - can be left
blank), refer to the Ordering Information section for detailed information)
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS65132A0YFFR
ACTIVE
DSBGA
YFF
15
3000
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 85
TPS
65132A0
TPS65132AYFFR
ACTIVE
DSBGA
YFF
15
3000
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 85
TPS
65132A
TPS65132B0YFFR
ACTIVE
DSBGA
YFF
15
3000
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 85
TPS
65132B0
TPS65132B2YFFR
ACTIVE
DSBGA
YFF
15
3000
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 85
TPS
65132B2
TPS65132B5YFFR
ACTIVE
DSBGA
YFF
15
3000
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 85
TPS
65132B5
TPS65132BYFFR
ACTIVE
DSBGA
YFF
15
3000
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 85
TPS
65132B
TPS65132L0YFFR
ACTIVE
DSBGA
YFF
15
3000
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 85
TPS
65132L0
TPS65132L0YFFT
ACTIVE
DSBGA
YFF
15
250
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 85
TPS
65132L0
TPS65132LYFFR
ACTIVE
DSBGA
YFF
15
3000
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 85
TPS
65132L
TPS65132SYFFR
ACTIVE
DSBGA
YFF
15
3000
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 85
TPS
65132S
TPS65132T6YFFR
ACTIVE
DSBGA
YFF
15
3000
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 85
TPS
65132T6
TPS65132T6YFFT
ACTIVE
DSBGA
YFF
15
250
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 85
TPS
65132T6
TPS65132WRVCR
ACTIVE
WQFN
RVC
20
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
65132YA
TPS65132WRVCT
ACTIVE
WQFN
RVC
20
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
65132YA
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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