TI Confidential - NDA Restrictions
TPS65178
TPS65178A
www.ti.com
SLVSAP8D – JULY 2011 – REVISED JULY 2012
Fully Programmable LCD Bias IC for TV
with 6-Channel Gamma Buffer, Vcom Reference and Dynamic Gain
Check for Samples: TPS65178, TPS65178A
FEATURES
•
1
•
•
•
•
•
•
•
•
2
•
•
8.6V to 14.7V Input Voltage Range
Boost Converter VDD: 12.8V…19V (6-Bit)
Integrated Input-to-Output Isolation Switch
Buck Converter HVDD: VDD tracking
Buck Converter VCC: 3.0V…3.7V (3-Bit)
Buck Converter VCORE: 0.9V…2.4V (4-Bit)
Buck Converter VEPI: 0.9V…2.4V (4-Bit)
Positive Charge Pump VGH:
– 19V…34V for Low Temperature (4-Bit)
– 17V…32V for High Temperature (4-Bit)
Temperature Compensation for VGH
Negative Charge Pump VGL: –1.8V…–8.1V
(6-Bit)
•
•
•
•
•
•
•
6-Ch Gamma Buffer:
– 3-Ch: VDD…HVDD (9-Bit)
– 3-Ch: HVDD...GND (9-Bit)
9-Bit VCOM Reference
2-Bit VCOM Gain
Selectable Dynamic Gain
Reset Signal With Programmable Delay Time
Programmable Sequencing Delays (3 × 3-Bit)
Thermal Shutdown
48-Pin 6-mm × 6-mm QFN Package
APPLICATIONS
•
•
LCD TVs
LCD Monitors
DESCRIPTION
The TPS65178/A provides a simple and economic power supply solution for a wide variety of LCD bias
applications. The device provides all supply rails needed by a TFT-LCD panel but also 6 gamma references, a
supply rail for LVDS support, as well as a Vcom reference and its programmable dynamic gain. The solution is
delivered in a small 6x6mm QFN package.
VIN
12 V
I²C
compatible
{
Boost Converter
VDD
(Integrated Isolation FET)
16 V/800 mA
VCC
Buck Converter 1
3.3 V/2.0 A
VCORE
Sync. Buck Converter 2
1.0 V/500 mA
(*1.8 V for TPS65178A)
HVDD
Sync. Buck Converter 3
8 V/500 mA
VEPI
Sync. Buck Converter 4
1.8 V/100 mA
Positive Charge Pump Controller
VGH
Temperature Compensation
24 V/100 mA
Negative Charge Pump Controller
-6 V/100 mA
VGL
6
6-Ch Gamma Buffer
VCOM reference & gain
Reset
VGMA1..6
VCOM
7.5 V
RST
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2011–2012, Texas Instruments Incorporated
TI Confidential - NDA Restrictions
TPS65178
TPS65178A
SLVSAP8D – JULY 2011 – REVISED JULY 2012
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
DESCRIPTION (CONTINUED)
The TPS65178/A provides a simple and economic power supply solution for a wide variety of LCD bias
applications. The device provides all supply rails needed by a TFT-LCD panel. VCC, VCORE and RST for the TCon. VDD and HVDD for the Source Driver. VGH and VGL for the Gate Driver or the Level Shifter. The VGH voltage
can be compensated for low and high temperatures, if GIP (Gate In Panel) technology is used.The transition
from one programmed VGH value to another is made using an external thermistor connected to the IC. In
addition, a 6-channel Gamma Buffer is integrated as well as the VCOM reference and programmable gain (fixed or
dynamic). A VEPI supply rail is also integrated. All output rails and delay times are programmable by a two-wire
interface: a single BOM (Bill of Material) can cover several panel types and sizes whose desired output levels
can be programmed in production and stored in a non-volatile memory embedded into the TPS65178/A. VCORE,
VEPI and HVDD are generated by synchronous buck converters which support chip inductors for an optimized
solution size. The solution is delivered in a small 6x6mm QFN package.
ORDERING INFORMATION (1)
TA
–40°C to 85°C
(1)
ORDERING
TPS65178RSLR
TPS65178ARSLR
PACKAGE
48-Pin 6x6 QFN
PACKAGE
MARKING
TPS65178
TPS65178A
TRANSPORT MEDIA,
QUANTITY
VCORE DEFAULT
VALUE
1.0 V
Tape and reel , 3000
1.8 V
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
(1)
VALUE
UNIT
MIN
MAX
Input voltage range AVIN, PVINB1, PVINB3 (2)
–0.3
20
V
Voltage range on pin CTRLP, TCOMP, VGH (2)
–0.3
40
V
Voltage range on pins DYN, GMA1–GMA6, NEG, OUT3, POS, SW, SWB1, SWB3, SWI, SWN,
SWO, SWP, VCOM, VCOMFB (2)
–0.3
20
V
Voltage on pin COMP, CTRLN, OUT1, OUT2, OUT4, RST, SCL, SDA, SS, SWB2, SWB4, VL (2)
–0.3
7
V
Voltage on pin VGL (2)
–10
0.3
V
ESD rating HBM (Human Body Model)
2
kV
ESD rating MM (Machine Model)
200
V
ESD rating CDM (Charged Device Model)
700
V
Continuous power dissipation
See the Thermal Table
Operating junction temperature range
–40
150
°C
Storage temperature range
–65
150
°C
(1)
(2)
2
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating
conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
With respect to the GND pin.
Submit Documentation Feedback
Copyright © 2011–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS65178 TPS65178A
TI Confidential - NDA Restrictions
TPS65178
TPS65178A
www.ti.com
SLVSAP8D – JULY 2011 – REVISED JULY 2012
THERMAL INFORMATION
TPS65178/A
THERMAL METRIC (1)
RSL
UNITS
48 PINS
θJA
Junction-to-ambient thermal resistance
29.1
θJCtop
Junction-to-case (top) thermal resistance
17.2
θJB
Junction-to-board thermal resistance
5.3
ψJT
Junction-to-top characterization parameter
0.2
ψJB
Junction-to-board characterization parameter
5.3
θJCbot
Junction-to-case (bottom) thermal resistance
1.7
°C/W
spacing
(1)
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
AVIN
Input voltage range
CVL
Input capacitor on internal regulator input pin VL
MIN
TYP
MAX
UNIT
8.6
12
14.7
V
1
µF
BOOST CONVERTER
VDD
Boost output voltage range
12.8
19
V
L
CIN_BOOST
Boost converter inductor
10
22
µH
Input capacitor on boost converter input
20
COUT_BOOST
Output capacitor on boost converter output on SWI pin
10
20
µF
COUT_ISO
Output capacitor on isolation MosFET output on SWO pin
30
40
µF
µF
BUCK 1 CONVERTER
VCC
Buck 1 converter output voltage range
3.0
3.7
V
L1
Buck 1 converter inductor
10
22
µH
CIN_BUCK1
Input capacitor on buck 1 converter input pin PVINB1
10
COUT_BUCK1
Output capacitor on buck 1 converter output
30
µF
40
µF
BUCK 2 CONVERTER
VCORE
Buck 2 converter output voltage range
0.9
2.4
V
L2
Buck 2 converter inductor
1.0
2.2
µH
CIN_BUCK2
Input capacitor on buck 2 converter input pin OUT1
1.0
4.7
COUT_BUCK2
Output capacitor on buck 2 converter output
2.2
4.7
µF
20
µF
6.8
µH
BUCK 3 CONVERTER
HVDD
Buck 3 converter output voltage range
L3
Buck 3 converter inductor
CIN_BUCK3
Input capacitor on buck 3 converter input pin PVINB3
COUT_BUCK3
Output capacitor on buck 3 converter output
VDD/2
4.7
V
10
4.7
10
µF
20
µF
BUCK 4 CONVERTER
VEPI
Buck 4 converter output voltage range
0.9
2.4
V
L4
Buck 4 converter inductor
1.0
2.2
µH
CIN_BUCK4
Input capacitor on buck 4 converter input pin OUT1
1.0
4.7
COUT_BUCK4
Output capacitor on buck 4 converter output
2.2
4.7
µF
20
µF
POSITIVE CHARGE PUMP CONTROLLER
VGH_LT
Positive charge pump output voltage range Low Temperature
19
34
V
VGH_HT
Positive charge pump output voltage range High Temperature
17
32
V
CFLY_CP
Charge pump flying capacitor
220
Copyright © 2011–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS65178 TPS65178A
Submit Documentation Feedback
nF
3
TI Confidential - NDA Restrictions
TPS65178
TPS65178A
SLVSAP8D – JULY 2011 – REVISED JULY 2012
www.ti.com
RECOMMENDED OPERATING CONDITIONS (continued)
over operating free-air temperature range (unless otherwise noted)
MIN
TYP
MAX
UNIT
CSTOR_CP
Charge pump storage capacitor
100
nF
COUT_CP
Charge pump output capacitor
4.7
µF
NEGATIVE CHARGE PUMP CONTROLLER
VGL
Negative charge pump output voltage range
–1.8
–8.1
V
CFLY_CP
Charge pump flying capacitor
220
CSTOR_CP
Charge pump storage capacitor
100
nF
COUT_CP
Charge pump output capacitor
4.7
µF
nF
TEMPERATURE
TA
Operating ambient temperature
–40
85
°C
TJ
Operating junction temperature
–40
125
°C
ELECTRICAL CHARACTERISTICS
AVIN = PVINB1 = PVINB3 = 12V, VDD = 16V, HVDD = 8V , VCC = 3.3V, VCORE = 1V, VEPI = 1.8V, VGH_LT = 28V, VGH_HT = 26V
VGL = –5V, TA = –40°C to 85°C, typical values are at TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER SUPPLY
VIN
Input voltage range
IQ_AVIN
Supply quiescent current AVIN
Device not switching
3.2
mA
IQ_PVINB1
Supply quiescent current PVINB1
Device not switching
0.1
mA
IQ_PVINB3
Supply quiescent current PVINB3
Device not switching
1.6
mA
IQ_OUT1
Supply quiescent current OUT1
Device not switching
50
µA
IQ_SWI
Supply quiescent current SWI
Device not switching
Undervoltage lockout
VIN rising
VUVLO
8.6
14.7
5
Undervoltage lockout hysteresis
V
mA
8.3
8.6
8.9
V
0.3
0.8
1.3
V
TSD
Thermal shutdown
TJ rising
138
°C
THYS
Thermal shutdown hysteresis
TJ falling
8
°C
LOGIC SIGNAL DYN, SCL, SDA
VIH1
High level input voltage DYN
AVIN = 8.6 V to 14.7 V
VIL1
Low level input voltage DYN
AVIN = 8.6 V to 14.7 V
VIH2
High level input voltage SCL, SDA
AVIN = 8.6 V to 14.7 V
VIL2
Low level input voltage SCL, SDA
AVIN = 8.6 V to 14.7 V
1.5
V
0.5
2
V
V
0.8
V
INTERNAL OSCILLATOR
fOSC
Switching frequency for the boost, buck1
converters and the charge pumps
480
600
720
kHz
4.8
5.0
5.2
V
–2%
16.05
2%
V
90
165
mΩ
3.5
4.2
5
INTERNAL REGULATOR
VL
Internal regulator
No load
BOOST CONVERTER [VDD]
VDD_ACC
Output voltage accuracy
VDD default value
rDS(on)
N-MOSFET on-resistance
ISW = current limit
ILIM
N-MOSFET current limit
ISS
Soft-start current
VSS = 1.230 V
Line regulation
AVIN = 8.6 V to 14.7 V, IOUT = 700 mA
0.002
%/V
Load regulation
IOUT = 0 A to 1 A
0.066
%/A
10
A
µA
ISOLATION SWITCH
rDS(on)ISO
Isolation MOSFET on-resistance
ISWI = 1 A
100
ISC_ISO
Short circuit current limit
VSWI = 12 V, VSWO = 0 V
200
180
mΩ
mA
BUCK 1 CONVERTER [VCC]
4
Submit Documentation Feedback
Copyright © 2011–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS65178 TPS65178A
TI Confidential - NDA Restrictions
TPS65178
TPS65178A
www.ti.com
SLVSAP8D – JULY 2011 – REVISED JULY 2012
ELECTRICAL CHARACTERISTICS (continued)
AVIN = PVINB1 = PVINB3 = 12V, VDD = 16V, HVDD = 8V , VCC = 3.3V, VCORE = 1V, VEPI = 1.8V, VGH_LT = 28V, VGH_HT = 26V
VGL = –5V, TA = –40°C to 85°C, typical values are at TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC_ACC
Output voltage accuracy
VCC default value
rDS(on)
Switch on-resistance
ISWB1 = current limit
ILIM
Switch current limit
MIN
TYP
MAX
–3%
3.3
3%
V
180
300
mΩ
3.4
4.2
A
2.6
UNIT
Line regulation
VIN = AVIN = PVINB1 = 8.6 V to 14.7 V
ICC = 400 mA
0.001
%/V
Load regulation
ICC = 0 A to 1 A
0.033
%/A
BUCK 2 CONVERTER [VCORE]
VCORE_ACC
Output voltage accuracy
rDS(on)
MOSFET on-resistance
ILIM
Switch current limit
fSWB2
Switching frequency buck 2 converter
VCORE default value TPS65178
–3%
1.0
3%
VCORE default value TPS65178A
–3%
1.8
3%
ISBW2 = current limit
V
220
400
mΩ
1.1
1.4
1.8
A
1.1
1.7
2.3
MHz
Line regulation
OUT1 = 3.0 V to 3.7 V
ICORE = 300 mA
0.008
%/V
Load regulation
ICORE = 0 A to 500 mA
0.114
%/A
BUCK 3 CONVERTER [HVDD]
HVDD_ACC
Output voltage accuracy
HVDD default value
rDS(on)
MOSFET on-resistance
ISBW3 = current limit
ILIM
fSWB3
Switch current limit – source
Switch current limit – sink
Switching frequency buck 3 converter
–3%
8.03
3%
V
320
480
mΩ
0.9
1.3
1.7
-0.9
-1.3
-1.7
1.4
1.6
1.8
A
MHz
Line regulation
AVIN = PVINB3 = 8.6 V to 14.7 V
IOUT = ±300 mA
0.003
%/V
Load regulation
IOUT = –500 mA to 500 mA
0.007
%/A
BUCK 4 CONVERTER [VEPI]
VEPI_ACC
Output voltage accuracy
VEPI default value
rDS(on)
MOSFET on-resistance
ISBW4 = current limit
ILIM
Switch current limit
fSWB4
Switching frequency buck 4 converter
–3%
1.8
3%
V
250
450
mΩ
0.5
0.7
1.0
A
1.2
1.9
2.6
MHz
Line regulation
OUT1 = 3.0 V to 3.7 V
IEPI = 100 mA
0.029
%/V
Load regulation
IEPI = 0 A to 100 mA
0.190
%/A
POSITIVE CHARGE PUMP CONTROLLER [VGH]
VGH_LT_ACC
VGH_HT_ACC
Output voltage accuracy
ICTRLP_SC
Base current during short circuit
ICTRLP_max
Maximum base current
VGH_LT default value
–3.5%
28
3.5%
V
VGH_HT default value
–3.5%
26
3.5%
V
VGH = GND
40
75
µA
1
2
mA
Line regulation
AVIN = 8.6 V to 14.7 V, IGH = 50 mA
0.004
%/V
Load regulation
IGH = 0 A to 100 mA
0.414
%/A
NEGATIVE CHARGE PUMP CONTROLLER [VGL]
VGL
Output voltage accuracy
VGL default value
ICTRLN_SC
Base current during short circuit
VGL = GND
ICTRLN_max
Maximum base current
-3.5%
-5
200
1
3.5%
V
440
µA
3
mA
Line regulation
AVIN = 8.6 V to 14.7 V, IGL = 50 mA
0.001
%/V
Load regulation
IGL = 0 A to 100 mA
0.817
%/A
30
mA
GAMMA BUFFER [GMA]
IO
Continuous output current
10
Copyright © 2011–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS65178 TPS65178A
Submit Documentation Feedback
5
TI Confidential - NDA Restrictions
TPS65178
TPS65178A
SLVSAP8D – JULY 2011 – REVISED JULY 2012
www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
AVIN = PVINB1 = PVINB3 = 12V, VDD = 16V, HVDD = 8V , VCC = 3.3V, VCORE = 1V, VEPI = 1.8V, VGH_LT = 28V, VGH_HT = 26V
VGL = –5V, TA = –40°C to 85°C, typical values are at TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
VDD0.7
VDD0.5
MAX
UNIT
VOH1
Output voltage swing high GMA1,2,3
IOUT = 10mA
VOL1
Output voltage swing low GMA1,2,3
IOUT = 10mA
HVDD
+0.5
VOH2
Output voltage swing high GMA4,5,6
IOUT = 10mA
HVDD- HVDD0.7
0.5
VOL2
Output voltage swing low GMA4,5,6
IOUT = 10mA
INL_max
Maximum integral nonlinearity
±0.6
LSB
DNL_max
Maximum differential nonlinearity
±0.3
LSB
0.5
V
HVDD
+0.7
V
V
0.7
V
P-VCOM [VPOS]
VPOS
Output voltage accuracy
VPOS default value
-1.5%
6.5
1.5%
V
RESET GENERATOR [RST] (1)
VRST(ON)
Low voltage level
IRST(ON) = 1 mA
ILEAK_RST
Leakage current
VRST(ON) = VCC = 3.3 V
(1)
0.5
V
2
µA
External pull-up resistor to be chosen so that the current flowing into RST pin when active (VRST = 0 V) is below IRST(ON) = 1 mA.
I2C INTERFACE TIMING CHARACTERISTICS
PARAMETER
fSCL
TEST CONDITIONS
SCL clock frequency
tLOW
(1)
LOW period of the SCL clock
MAX
UNIT
Standard mode
MIN
TYP
100
kHz
Fast mode
400
kHz
Standard mode
4.7
µs
Fast mode
1.3
µs
Standard mode
4.0
µs
tHIGH
HIGH period of the SCL clock
Fast mode
600
ns
tBUF
Bus free time between a STOP and
START condition
Standard mode
4.7
µs
Fast mode
1.3
µs
Hold time for a repeated START
condition
Standard mode
4.0
µs
Fast mode
600
ns
Setup time for a repeated START
condition
Standard mode
4.7
µs
Fast mode
600
ns
Data setup time
Standard mode
250
ns
Fast mode
100
Standard mode
0.05
thd;STA
tsu;STA
tsu;DAT
thd;DAT
Data hold time
tRCL1
Rise time of SCL signal after a
repeated START condition and after
an acknowledge bit
Standard mode
Fast mode
µs
0.05
0.9
µs
20 + 0.1CB
1000
ns
20 + 0.1CB
1000
ns
Rise time of SCL signal
Standard mode
20 + 0.1CB
1000
ns
Fast mode
20 + 0.1CB
300
ns
Standard mode
20 + 0.1CB
300
ns
Fast mode
20 + 0.1CB
300
ns
Standard mode
20 + 0.1CB
1000
ns
Fast mode
20 + 0.1CB
300
ns
Standard mode
20 + 0.1CB
300
ns
Fast mode
20 + 0.1CB
300
ns
Fast mode
tRCL
tFCL
Fall time of SCL signal
tRDA
Rise time of SDA signal
tFDA
(1)
6
Fall time of SDA signal
ns
3.45
Industry standard I2C timing characteristics. Not tested in production.
Submit Documentation Feedback
Copyright © 2011–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS65178 TPS65178A
TI Confidential - NDA Restrictions
TPS65178
TPS65178A
www.ti.com
SLVSAP8D – JULY 2011 – REVISED JULY 2012
I2C INTERFACE TIMING CHARACTERISTICS (1) (continued)
PARAMETER
tsu;STO
TEST CONDITIONS
Setup time for STOP condition
CB
MIN
Standard mode
4.0
Fast mode
600
TYP
MAX
UNIT
µs
ns
Capacitive load for SDA and SCL
0.4
nF
I2C TIMING DIAGRAMS
SDA
tf
tLOW
tf
tsu;DAT
tr
tBUF
tr
thd;STA
SCL
S
thd;STA
thd;DAT
tsu;STA
tsu;STO
HIGH
Sr
P
S
Figure 1. Serial Interface Timing for F/S-Mode
GMA1
GMA2
GMA3
GMA4
GMA5
GMA6
VCOM
NEG
POS
VOCMFB
DYN
PGND4
DEVICE INFORMATION
OUT4
CTRLN
SWB4
VGL
RST
SWN
OUT1
SWP
OUT2
VGH
SWB2
CTRLP
PGND2
TCOMP
SWB1
VL
SWB1
SDA
NC
SCL
Copyright © 2011–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS65178 TPS65178A
AGND
SWO
SWI
SW
SW
PGND
PGND
PGND3
OUT3
SS
SWB3
PVINB1
PVINB3
COMP
AVIN
PVINB1
Submit Documentation Feedback
7
TI Confidential - NDA Restrictions
TPS65178
TPS65178A
SLVSAP8D – JULY 2011 – REVISED JULY 2012
www.ti.com
PIN FUNCTIONS
PIN
I/O
DESCRIPTION
NAME
NO.
OUT4
1
I
SWB4
2
I/O
Buck 4 converter (VEPI) switch pin
RST
3
O
Reset generator open drain output pin
OUT1
4
I
Buck 1 converter (VCC) output voltage sense pin. Buck 2 and buck 4 converters input pin
OUT2
5
I
Buck 2 converter (VCORE) output voltage sense pin
SWB2
6
I/O
PGND2
7
SWB1
8, 9
NC
10
PVINB1
Buck 4 converter (VEPI) output voltage sense pin
Buck 2 converter (VCORE) switch pin
Buck 2 converter (VCORE) power ground pin
I/O
Buck 1 converter (VCC) switch pin
Not connected
11, 12
I
Buck 1 converter (VCC) input supply pin
AVIN
13
I
Internal regulator supply pin
PVINB3
14
I
Buck 3 converter (HVDD) power input pin
SWB3
15
I/O
OUT3
16
I
PGND3
17
PGND
18, 19
SW
20, 21
I/O
SWI
22
I
Isolation switch input pin. The SWI pin is connected to the internal overvoltage protection comparator of
the boost converter
SWO
23
O
Isolation switch output pin (VDD)
AGND
24, exposed
pad
Buck 3 converter (HVDD) switch pin
Buck 3 converter (HVDD) output voltage sense pin
Buck 3 converter (HVDD) power ground pin
Boost converter (VDD) power ground pin
Boost converter (VDD) switch pin
Analog ground pin. Connect this pin to the PowerPAD™.
SS
25
O
Boost converter (VDD) soft-start pin. Connect a capacitor to this pin if a soft-start is needed. Open = no
soft-start.
COMP
26
I/O
Boost converter (VDD) compensation pin
SCL
27
I/O
I2C clock pin
SDA
28
I/O
I2C data pin
VL
29
O
Internal regulator output pin. Connect an output capacitor to this pin
TCOMP
30
I
Temperature compensation input pin. Connect the thermistor / pull-up resistor network to this pin
CTRLP
31
O
Positive charge pump (VGH) base drive signal pin
VGH
32
I
Positive charge pump (VGH) output voltage sense pin
SWP
33
I/O
Positive charge pump (VGH) switch pin
SWN
34
I/O
Negative charge pump (VGL) switch pin
VGL
35
I
Negative charge pump (VGL) output voltage sense pin
CTRLN
36
O
Negative charge pump (VGL) base drive signal pin
GMA1
37
O
Gamma buffer 1 output pin. DAC output
GMA2
38
O
Gamma buffer 2 output pin. DAC output
GMA3
39
O
Gamma buffer 3 output pin. DAC output
GMA4
40
O
Gamma buffer 4 output pin. DAC output
GMA5
41
O
Gamma buffer 5 output pin. DAC output
GMA6
42
O
Gamma buffer 6 output pin. DAC output
VCOM
43
I
VCOM output sense pin
NEG
44
O
VCOM inverting pin
POS
45
O
VCOM non-inverting pin. DAC output for the VCOM reference
VCOMFB
46
I
VCOM panel feedback pin
DYN
47
I
Dynamic VCOM gain select pin
PGND4
48
8
Buck 4 converter (VEPI) power ground pin
Submit Documentation Feedback
Copyright © 2011–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS65178 TPS65178A
TI Confidential - NDA Restrictions
TPS65178
TPS65178A
www.ti.com
SLVSAP8D – JULY 2011 – REVISED JULY 2012
VIN
8.6V to 14.7V
COMP
SWO
SWI
SW
SW
VDD
16V / 500mA
Boost Converter
(VDD)
+
Isolation Switch
SS
PGND
AVIN
AGND
SDA
DAC
+
I²C controller
Internal
Supply
VL
VCC
PGND
I²C
SCL
HVDD
8V / ±30mA
PVINB3
SWB3
Synchronous Buck Converter 3
(HVDD)
OUT3
PGND3
VCC
3.3V / 100mA
SWB1
PVINB1
PVINB1
SWB1
Buck Converter 1
(VCC)
VCC
OUT1
VEPI
1.8V / 50mA
RST
Reset
(RST)
RST
SWB4
Sync. Buck
Converter 4
(VEPI)
OUT4
VCORE
1.0V / 300mA
(* 1.8V for TPS65178A)
PGND4
VL
SWB2
Synchronous Buck Converter 2
(VCORE)
OUT2
PGND2
TCOMP
VDD
VGL
-5V / 50mA
Positive
Charge Pump
(VGH)
CTRLN
CTRLP
+
VGH
26V / 50mA
SWP
Temperature
Compensation
Negative
Charge Pump
(VGL)
SWN
VGL
VGH
VDD
GMA6
VCOM
POS
GMA1
...
VGMA1
VGMA2
VGMA3
VGMA4
VGMA5
VGMA6
Gamma Buffer
(VGMA)
P-VCOM
(VCOM)
NEG
VCOM
VCOMFB
DYN
Panel feedback
Dynamic gain control
Figure 2. Simple Application Schematic
Copyright © 2011–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS65178 TPS65178A
Submit Documentation Feedback
9
TI Confidential - NDA Restrictions
TPS65178
TPS65178A
SLVSAP8D – JULY 2011 – REVISED JULY 2012
www.ti.com
TYPICAL CHARACTERISTICS
Table 1. Table of Graphs
PARAMETER
Conditions
Figure
Buck 1 Converter - (VIN = 12 V, L = 10 µH, COUT = 40 µF)
Efficiency vs. Load Current
VCC = 3.3 V
Figure 3
PWM Switching – Light Load
VCC = 3.3 V/50 mA
Figure 4
PWM Switching – Heavy Load
VCC = 3.3 V/ 500 mA
Figure 5
Load Transient Response
VCC = 3.3 V/100 ~ 300 mA
Figure 6
Buck 2/4 Converters - (VIN = 12 V, L = 2.2 µH, COUT = 10 µF)
Efficiency vs. Load Current
VCORE/EPI = 1.0 V, 1.2 V, 1.5 V, 1.8 V
Figure 7
PWM Switching – Light Load
VCORE/EPI = 1.0 V/0 A
Figure 8
PWM Switching – Heavy Load
VCORE/EPI = 1.0 V/500 mA
Figure 9
Load Transient Response
VCORE/EPI = 3.3 V/100~ 400 mA
Figure 10
Buck 3 Converter - (VIN = 12 V, L = 6.8 µH, COUT = 10 µF)
Efficiency vs. Load Current
HVDD = 8 V
Figure 11
PWM Switching – Light Load
HVDD = 8 V/0 A
Figure 12
PWM Switching – Heavy Load (Source)
HVDD = 8 V/500 mA
Figure 13
PWM Switching – Heavy Load (Sink)
HVDD = 8 V/–500 mA
Figure 14
Load Transient Response
HVDD = 3.3 V/–200 ~ +200 mA
Figure 15
Boost Converter - (VIN = 12 V, L = 10 µH, COUT = 40 µF)
Efficiency vs. Load Current
VDD = 16 V
Figure 16
PWM Switching – Light Load
VDD = 16 V/0 A
Figure 17
PWM Switching – Heavy Load
VDD = 16 V/ 700 mA
Figure 18
Load Transient Response
VDD = 16 V/ 200 ~ 550 mA
Figure 19
VGH = 26 V/ 10 ~ 60 mA
Figure 20
VIN = 12 V, VGL = –5 V/ 10 ~ 50 mA
Figure 21
Voltage Adjustment - [–2°C ~ 25°C)
VGH_LT1 = 34 V, VGH_HT1 = 17 V
VGH_LT2 = 27 V, VGH_HT2 = 24 V
Figure 22
Temperature Adjustment
VGH_LT = 28 V, VGH_HT = 22 V
T°C Variation1: 2 °C ~ 18 °C
T°C Variation2: 16 °C ~ 32 °C
Figure 23
Power On Sequencing
VIN = 12 V, VLOGIC = 3.3 V, VGL= –5 V
VDD= 16 V, HVDD = 8 V, VGH = 26 V
Figure 24
Power On Sequencing VLOGIC
VIN = 12 V, VCC = 3.3 V, VCORE = 1.8 V, VCORE = 1.0
V
Figure 25
Power On Sequencing VDD dependency
VIN = 12 V, VDD = 16 V, VGMA1 = 14 V
HVDD = 8 V, VPOS = 6.5 V, VGMA6 = 2 V
Figure 26
Positive Charge Pump - (VIN = 12 V, COUT = 10 µF)
Load Transient Response
Negative Charge Pump - (VIN = 12 V, COUT = 10 µF)
Load Transient Response
Temperature Compensation
Sequencing
10
Submit Documentation Feedback
Copyright © 2011–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS65178 TPS65178A
TI Confidential - NDA Restrictions
TPS65178
TPS65178A
www.ti.com
SLVSAP8D – JULY 2011 – REVISED JULY 2012
100
90
Efficiency (%)
80
BUCK 1 (VCC) EFFICIENCY vs LOAD CURRENT
BUCK 1 (VCC) PWM SWITCHING – LIGHT LOAD
VIN = 12 V
VI/O = 3.3 V/50 mA
L = 10 µH
VIN = 12 V
VI O = 3.3 V
70
60
VSWB1
50
40
30
20
IL1
10
0
0.001
0.01
0.1
Load Current (A)
1
10
G001
G002
Figure 3.
Figure 4.
BUCK 1 (VCC) PWM SWITCHING – HEAVY LOAD
BUCK 1 (VCC) LOAD TRANSIENT RESPONSE
VIN = 12 V
VI/O = 3.3 V/500 mA
VIN = 12 V, COUT = 40 ìF
VCC = 3.3 V/100 ~ 300 mA
VCC (AC)
VSWB1
IL1
IOUT1
G003
G004
Figure 5.
Figure 6.
BUCK 2 (VCORE) EFFICIENCY vs LOAD CURRENT
BUCK 2 (VCORE) PWM SWITCHING – LIGHT LOAD
100
VCORE
90
EPI
VIN = 12 V
VCORE = 1 V/0 A
= 1.8 V
Efficiency (%)
80
70
VCORE
EPI
= 1.5 V
VCORE
60
EPI
VSWB2
= 1.0 V
50
40
30
VCORE
EPI
= 1.2 V
20
0
0.001
IL2
L = 2.2 µH
VIN = 12 V
10
0.01
0.1
Load Current (A)
1
G005
Figure 7.
G006
Figure 8.
Copyright © 2011–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS65178 TPS65178A
Submit Documentation Feedback
11
TI Confidential - NDA Restrictions
TPS65178
TPS65178A
SLVSAP8D – JULY 2011 – REVISED JULY 2012
www.ti.com
BUCK 2 (VCORE) PWM SWITCHING – HEAVY LOAD
VIN = 12 V
VCORE = 1 V/500 mA
BUCK 2 (VCORE) LOAD TRANSIENT RESPONSE
VIN = 12 V, COUT = 10 ìF
VCORE = 1 V/100 ~ 400 mA
VCORE (AC)
VSWB1
IL1
IOUT2
G007
G008
Figure 9.
Figure 10.
BUCK 3 (HVDD) EFFICIENCY vs LOAD CURRENT
BUCK 3 (HVDD) PWM SWITCHING - LIGHT LOAD
100
VSWB3
90
Efficiency (%)
80
70
60
50
VIN = 12 V
HVDD = 8 V/0 A
40
30
IL3
HVDD = 8 V
L = 6.8 µH
VIN = 12 V
20
10
0
0
0.1
0.2
0.3
0.4
Load Current (A)
0.5
0.6
G009
G010
Figure 11.
Figure 12.
BUCK 3 (HVDD) PWM SWITCHING – HEAVY LOAD
(SOURCE)
BUCK 3 (HVDD) PWM SWITCHING – HEAVY LOAD
(SINK)
VSWB3
VSWB3
VIN = 12 V
HVDD = 8 V/–500 mA
IL3
IL3
VIN = 12 V
HVDD = 8 V/500 mA
G011
G012
Figure 13.
12
Submit Documentation Feedback
Figure 14.
Copyright © 2011–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS65178 TPS65178A
TI Confidential - NDA Restrictions
TPS65178
TPS65178A
www.ti.com
SLVSAP8D – JULY 2011 – REVISED JULY 2012
BUCK 3 (HVDD) LOAD TRANSIENT RESPONSE
VIN = 12 V, COUT = 10 ìF
HVDD = 8 V/–200 ~ +300 mA
100
90
HVDD (AC)
Efficiency (%)
80
BOOST (VDD) EFFICIENCY vs LOAD CURRENT
L = 10 µH
VDD = 16 V
VIN = 12 V
70
60
50
40
30
20
IOUT3
10
0
0.001
0.01
0.1
Load Current (A)
G013
1
10
G014
Figure 15.
Figure 16.
BOOST (VDD) PWM SWITCHING – LIGHT LOAD
BOOST (VDD) PWM SWITCHING – HEAVY LOAD
VSW
VSW
VIN = 12 V
VDD = 16 V/0 A
IL
IL
VIN = 12 V
VDD = 16 V/700 mA
G016
G015
Figure 17.
Figure 18.
BOOST (VDD) LOAD TRANSIENT RESPONSE
VIN = 12 V, COUT = 40 ìF
VDD = 16 V/200 ~ 550 mA
CPP (VGH) LOAD TRANSIENT RESPONSE
VIN = 12 V, COUT = 10 ìF
VGH = 26 V/10 ~ 60 mA
VDD (AC)
VGH (AC)
IOUT
IGH
G017
Figure 19.
G018
Figure 20.
Copyright © 2011–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS65178 TPS65178A
Submit Documentation Feedback
13
TI Confidential - NDA Restrictions
TPS65178
TPS65178A
SLVSAP8D – JULY 2011 – REVISED JULY 2012
www.ti.com
TEMPERATURE COMPENSATION
VOLTAGE ADJUSTMENT
CPN (VGL) LOAD TRANSIENT RESPONSE
VIN = 12 V, COUT = 10 ìF
VGL = –5 V/10 ~ 50 mA
36
NTC = NCP18WB473F10RB
R5 = 47 kΩ
R6 = 120 kΩ
34
VGL (AC)
Output Voltage (V)
32
30
VGH(COLD) = 27 V
VGH(HOT) = 24 V
28
26
24
22
VGH(COLD) = 34 V
VGH(HOT) = 17 V
20
IGL
18
16
−12 −8
−4
0
G019
Figure 21.
NTC = NCP18WB473F10RB
VGH(COLD) = 28 V
VGH(HOT) = 22 V
Output Voltage (V)
26
28
32
G020
VIN
VLOGIC
RST
R5 = 47 kΩ
R6 = 1.5 MΩ
27
24
STARTUP SEQUENCING
30
28
20
Figure 22.
TEMPERATURE COMPENSATION
VOLTAGE ADJUSTMENT
29
4
8
12 16
Temperature (°C)
VGL
25
24
VDD
23
HVDD
22
R5 = 82 kΩ
R6 = 1.5 MΩ
21
20
VGH
0
2
4
6
8 10 12 14 16 18 20 22 24 26 28 30 32 34
Temperature (°C)
G021
10 ms /div
G022
Figure 23.
Figure 24.
STARTUP SEQUENCING
STARTUP SEQUENCING
VDD
VCC – 3.3 V
VGMA1
VEPI – 1.8 V
HVDD
VPOS
VGMA6
VCORE – 1 V
100 μs /div
2 ms /div
G023
Figure 25.
14
Submit Documentation Feedback
G024
Figure 26.
Copyright © 2011–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS65178 TPS65178A
TI Confidential - NDA Restrictions
TPS65178
TPS65178A
www.ti.com
SLVSAP8D – JULY 2011 – REVISED JULY 2012
DAC RANGE SUMMARY
All outputs are programmable using a two-wire interface.
Boost Converter (VDD)
Output voltage selection: programmable with I2C
Number of bits: 6
Output voltage range: 12.8V…19V
Step size: 100 mV
Buck 1 Converter (VCC)
Output voltage selection: programmable with I2C
Number of bits: 3
Output voltage range: 3.0V…3.7V
Step size: 100 mV
Buck 2 Converter (VCORE)
Output voltage selection: programmable with I2C
Number of bits: 4
Output voltage range: 0.9V…2.4V
Step size: 100 mV
Buck 3 Converter (HVDD)
Output voltage selection: not possible (VDD tracking)
Number of bits: Output voltage range: VDD/2
Step size: 50 mV
Buck 4 Converter (VEPI)
Output voltage selection: programmable with I2C
Number of bits: 4
Output voltage range: 0.9V…2.4V
Step size: 100 mV
Positive Charge Pump Controller (VGH_LT – low temperature)
Output voltage selection: programmable with I2C
Number of bits: 4
Output voltage range: 19V…34V
Step size: 1 V
Positive Charge Pump Controller (VGL_HT - high temperature)
Output voltage selection: programmable with I2C
Number of bits: 4
Output voltage range: 17V…32V
Step size: 1 V
Negative Charge Pump (VGL)
Output voltage selection: programmable with I2C
Number of bits: 4
Output voltage range: –1.8V…–8.1V
Step size: 100 mV
Copyright © 2011–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS65178 TPS65178A
Submit Documentation Feedback
15
TI Confidential - NDA Restrictions
TPS65178
TPS65178A
SLVSAP8D – JULY 2011 – REVISED JULY 2012
www.ti.com
Gamma Buffer (VGMA1,2,3) - (VDD dependency)
Output voltage selection: programmable with I2C
Number of bits: 9
Output voltage range: VDD/2…VDD (512 steps)
Step size: VDD/1023
Gamma Buffer (VGMA4,5,6) - (VDD dependency)
Output voltage selection: programmable with I2C
Number of bits: 9
Output voltage range: 0V…VDD/2 (512 steps)
Step size: VDD/1-23
Vcom Reference (VPOS) - (VDD dependency)
Output voltage selection: programmable with I2C
Number of bits: 9
Output voltage range: (VDD/1023)*250V ... (VDD/1023)*640V (391 steps)
Step size: VDD/1023
Vcom Fixed Gain
Gain voltage selection: programmable with I2C
Number of bits: 2
Gain levels: Buffer, –1x,–2x,–3x
Vcom Dynamic Gain
Gain voltage selection: logic levels on DYN pin (driven by T-CON)
Number of bits: 1
Gain levels: –2x, –4x
DYN = high: –2x
DYN = low: –4x
16
Submit Documentation Feedback
Copyright © 2011–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS65178 TPS65178A
TI Confidential - NDA Restrictions
TPS65178
TPS65178A
www.ti.com
SLVSAP8D – JULY 2011 – REVISED JULY 2012
SEQUENCING
The power-up sequence delays are programmable with a I2C. DLY1, DLY2 and DLY3 can be set per steps of
5 ms, up to 35 ms.
DLY1, 2, 3
Number of bits: 3
Timing delay range: 0ms…35ms (± 20% accuracy)
POWER-UP
1. When AVIN > 8.6 V the device is enabled, VL goes into regulation and the RST signal is set 'low'. The buck 1
(VCC) and buck 4 (VEPI) converters start up.
2. When PG1 and PG4 are reached, buck 2 (VCORE) strarts up.
3. When PG2 is reached and DLY1 has passed, RST is released and the negative charge pump controller
(VGL) starts.
4. When PGN is reached and DLY2 has passed, the boost converter (VDD) and the buck 3 converter (HVDD)
start. The Gamma Buffer outputs as well as the VPOS rise at a ratio metric rate of VDD.
5. When PG is reached and DLY3 has passed, the positive charge pump controller (VGH) starts.
POWER-DOWN
1. When VIN falls down below the UVLO threshold, all blocks are disabled and discharge at a rate driven by the
output load and the output capacitors.
UVLO
VIN
VL
UVLO
PG
VCC
PG
VEPI
PG
VCORE
T-CON enabled
DLY1
RST
PG
VGL
VDD
DLY2
PG
HVDD
VPOS
GMA1-6
DLY3
VGH
Copyright © 2011–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS65178 TPS65178A
Submit Documentation Feedback
17
TI Confidential - NDA Restrictions
TPS65178
TPS65178A
SLVSAP8D – JULY 2011 – REVISED JULY 2012
www.ti.com
DETAILED DESCRIPTION
BOOST CONVERTER (VDD)
The non-synchronous boost converter uses a current mode topology and operates at a fixed frequency of 600
kHz. A typical application circuit is shown in Figure 30. The external compensation allows designers to optimize
the performance for individual applications, and is easily implemented by connecting a suitable capacitor/resistor
network between the COMP pin and AGND (see design procedure section for more details).
Enable Signal (DLY2)
The boost converter is enabled when the power good signal from the negative charge pump controller (VGL) is
asserted and the programmed DLY2 has passed (see the Appendix section to set DLY2 timing).
Boost Converter Operation
The boost operates either in continuous conduction mode (CCM) or discontinuous conduction mode (DCM),
depending on the load current. The switch node waveforms for CCM and DCM operation are shown in Figure 4
and Figure 5. Note that the ringing seen during DCM operation (at light load) occurs because of parasitic
capacitance in the PCB layout and is normal for DCM operation. There is very little energy contained in the
ringing waveform and it does not significantly affect EMI performance.
Startup (Boost Converter)
The startup of the boost converter block operates in two steps:
1. Input-to-output isolation switch (IsoFET)
As soon as the internal enable signal of the boost converter is activated, the isolation switch is slowly turned
on, ramping up smoothly the current flowing from VIN into the output capacitors. The startup current is limited
to 200 mA typically until VSWO > 3.5 V (short-circuit condition), and increases linearly with the output voltage.
Once VSWO gets close to VSWI, the isolation switch is fully turned on and the boost converter starts switching.
The soft-start function is also enabled.
2. Soft-start (SS)
To minimize the inrush current during start-up an external capacitor connected to the soft-start pin SS is
used to slowly ramp up the internal current limit of the boost converter. It is charged with a constant current
of typically 10 µA. The inductor peak current limit is proportional to the SS voltage and the maximum load
current is available after the soft-start is completed (VSS = 0.8 V) or VDD has reached its Power Good value
(90% of its nominal voltage). The larger the SS capacitor, the slower the ramp of the current limit and the
longer the soft-start time. A 100-nF capacitor is usually sufficient for most applications. When VIN decreases
below the undervoltage lockout threshold, the soft-start capacitor is discharged to ground.
Protections (Boost Converter)
The boost converter is protected against potentially damaging conditions such as overvoltage and short circuits.
1. Short-Circuit Protection
The boost converter integrates a short-circuit protection circuit to prevent the inductor or the rectifier diode
from overheating when the output rail is shorted to GND. If the boost output is shorted to GND and the
voltage on SWO drops below VIN - 0.5 V, the boost converter shuts down and the input-to-output isolation is
turned-off. Only when the SWO voltage drops below 2 V typically, the switch turns on again and limits the
current to 200 mA typically (start-up behavior). The soft-start capacitor is also discharged to ground.
2. Overvoltage Protection
The boost converter integrates an overvoltage protection. If the output voltage VDD exceeds the OVP
threshold of 20.3 V typically , the boost converter stops switching. The output voltage will drop down by the
hysteresis and the boost converter will autonomously recover and switch again.
18
Submit Documentation Feedback
Copyright © 2011–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS65178 TPS65178A
TI Confidential - NDA Restrictions
TPS65178
TPS65178A
www.ti.com
SLVSAP8D – JULY 2011 – REVISED JULY 2012
NOTE
The boost converter stops switching while the positive charge pump is in a short circuit
condition. This condition is not latched and the boost converter autonomously resumes
normal operation once the short circuit condition has been removed from the positive
charge pump.
Setting the Output Voltage VDD
The output voltage of the boost converter is programmable via a two-wire interface between 12.8 V and 19 V
with a 6-bit resolution. See the Appendix section to set the VDD voltage.
Boost Converter Design Procedure
The first step in the design procedure is to verify whether the maximum possible output current of the boost
converter supports the specific application requirements. A simple approach is to estimate the converter
efficiency, by taking the efficiency number from the provided efficiency curves at the application's maximum load
or to use a worst case assumption for the expected efficiency, e.g., 85%.
1. Duty Cycle:
D=1 -
VIN_min ´ η
VS
2. Inductor ripple current: ΔIL =
VIN_min ´ D
fOSC ´ L
ΔIL ö
æ
3. Maximum output current: IOUT_max = ç I LIM_min - 2 ÷ ´ (1 - D)
è
ø
IOUT
ΔI
+ L
1 - D
2
η = Estimated boost converter efficiency (use the number from the efficiency plots or 85% as an estimation)
ƒOSC = Boost converter switching frequency (600 kHz)
L = Selected inductor value for the boost converter (see the Inductor Selection section)
ISWPEAK = Boost converter switch current at the desired output current (must be < ILIM_min = 3.5 A)
ΔIL = Inductor peak-to-peak ripple current
4. Peak switch current of the application: ISWPEAK =
The peak switch current is the current that the integrated switch, the inductor and the external Schottky diode
have to be able to handle. The calculation must be done for the minimum input voltage where the peak switch
current is highest.
Inductor Selection (Boost Converter)
Saturation current: the inductor must handle the maximum peak current (IL_SAT > ISWPEAK, or IL_SAT > ILIM_max as
conservative approach)
DC Resistance: the lower the DCR, the lower the losses
Inductor value: with a fixed frequency of 600 kHz, the recommended values are 10 µH ≤ L ≤ 22 µH. The boost
converter is optimized to work with 10 µH. The higher the inductor value, the lower the inductor ripple and output
voltage ripple but the slower the transient response.
Table 2. Inductor Selection Boost / Buck 1
L
(µH)
SUPPLIER
COMPONENT CODE
SIZE
(L x W x H mm)
DCR TYP
(mΩ)
ISAT
(A)
10
Sumida
CDRH8D43NP-100N
8.3 x 8.3 x 4.5
29
4
10
Murata
LQH6PPN100M43K
6.0 x 6.0 x 4.3
53
2.6
22
Sumida
CD105NP-100M
10.4 x 9.4 x 5.8
60
2.6
22
Sumida
CDRH129-220M
12.5 x 12.5 x 10
23
5
Copyright © 2011–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS65178 TPS65178A
Submit Documentation Feedback
19
TI Confidential - NDA Restrictions
TPS65178
TPS65178A
SLVSAP8D – JULY 2011 – REVISED JULY 2012
www.ti.com
Rectifier Diode Selection (Boost Converter)
Diode type: Schottky type for better efficiency
Reverse voltage: VR of the diode must block VOVP voltage (20 V recommended)
Forward current: the diode’s averaged rectified forward current IF must handle the output current since IF = IOUT
(2A recommended as conservative approach, 1A sufficient for lower output current).
Thermal characteristics: the diode must be chosen so that it can dissipate the power (PD = IF × VF, 500 mW
should be sufficient for most of the applications)
Table 3. Rectifier Diode Selection Boost / Buck 1
PART NUMBER
VR / IAVG
VF
RθJA
SIZE
COMPONENT SUPPLIER
MBRS320
20V / 3A
0.44V at 3A
46°C/W
SMC
International Rectifier
SL22
20V / 2A
0.44V at 2A
75°C/W
SMB
Vishay Semiconductor
SS22
20V / 2A
0.50V at 2A
75°C/W
SMB
Fairchild Semiconductor
Compensation (COMP)
The regulation loop can be compensated by adjusting the external components connected to the COMP pin. The
COMP pin is the output of the internal transconductance error amplifier. The compensation capacitor will adjust
the low frequency gain and the resistor value will adjust the high frequency gain. Lower output voltages require a
higher gain and therefore a lower compensation capacitor value. A good start, that will work for the majority of
the applications is RCOMP = 33 kΩ and CCOMP = 1 nF. In the case where a 22 uH inductor is used, RCOMP = 22 kΩ
and CCOMP = 1 nF are recommended.
Input Capacitor Selection
For good input voltage filtering low ESR ceramic capacitors are recommended. TPS65178/A has an analog input
AVIN. A 1-µF bypass capacitor is required as close as possible from AVIN to GND.
Two 10-µF (or one 22-µF) ceramic input capacitors are sufficient for most applications. For better input voltage
filtering this value can be increased. Refer to the Recommended Operation Conditions table, Table 4 and the
Typical Application section for input capacitor recommendations.
Output Capacitor Selection
For best output voltage filtering a low ESR output capacitor is recommended. Typically, four 10-µF (or two 22-µF)
ceramic output capacitors work for most of the applications. Higher capacitor values can be used to improve the
load transient response. A 10 µF capacitor is also required between the rectifier diode and the SWI pin (Refer to
the Recommended Operation Conditions table, Table 4 and the Typical Application section for output capacitor
recommendations).
Table 4. Input and Output Capacitor Selection Boost / Buck 1
CAPACITOR
VOLTAGE RATING
COMPONENT SUPPLIER
COMPONENT CODE
COMMENTS
1µF/0603
16V
Taiyo Yuden
EMK107BJ105KA
AVIN bypass
10µF/1206
16V
Taiyo Yuden
EMK212BJ106KG
CIN
10µF/1206
25V
Taiyo Yuden
TMK316BJ106KL
COUT
22µF/1210
25V
Murata
GRM32ER61E226KE15
CIN / COUT
To calculate the output voltage ripple, the following equations can be used:
I
- VIN
V
´ OUT
ΔVC = DD
ΔVC_ESR = ISWPEAK ´ RC_ESR
VDD ´ fOSC
COUT
(1)
∆VC_ESR can be neglected in many cases since ceramic capacitors provide very low ESR.
20
Submit Documentation Feedback
Copyright © 2011–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS65178 TPS65178A
TI Confidential - NDA Restrictions
TPS65178
TPS65178A
www.ti.com
SLVSAP8D – JULY 2011 – REVISED JULY 2012
BUCK 1 CONVERTER (VCC)
The buck 1 converter (step-down) used in TPS65178/A is a non-synchronous type current mode control that runs
at a fixed frequency of 600kHz. The converter features integrated soft-start, bootstrap, and compensation circuits
to minimize external component count.
Enable Signal (UVLO)
The buck 1 converter is enabled when the VIN voltage exceeds the UVLO threshold of 8.3 V typically.
Buck 1 Converter Operation
The buck 1 operates in either continuous conduction mode (CCM) or discontinuous conduction mode (DCM),
depending on the load current. The switch node waveforms for CCM and DCM operation are shown in Figure 4
and Figure 5. Note that the ringing seen during DCM operation (at light load) occurs because of parasitic
capacitance in the PCB layout and is normal for DCM operation. There is very little energy contained in the
ringing waveform and it does not significantly affect EMI performance.
The buck 1 converter uses a skip mode to regulate VCC at very low load currents. This mode allows the converter
to maintain its output at the required voltage while still meeting the requirement of a minimum on time. During
skip mode, the buck 1 converter switches for a few cycles, then stops switching for a few cycles, and then starts
switching again and so on, for as long as the output current is below the skip mode threshold. Output voltage
ripple can be a little higher during skip mode.
Startup and Short Circuit Protection (Buck 1 Converter)
The buck 1 converter is limiting its switching frequency when its output voltage VCC is below a certain threshold
(fSWB1 = 1/4 × fosc for VFB_internal < 400mV and fSWB1 = ½ × fosc for VFB_internal < 800mV - with VREF = 1.24 V).
This feature avoids run away of the inductor in case of short circuit and helps smoothing the buck converter
startup as well.
Setting the Output Voltage VCC
The output voltage of the buck 1 converter is programmable via a two-wire interface between 3.0 V and 3.7 V
with a 3-bit resolution. See the Appendix section to set the VCC voltage.
Buck 1 Converter Design Procedure
1. Duty Cycle:D =
VCC
VIN ´ η
2. Inductor ripple current: ΔIL =
(VIN_max - VCC ) ´ D
fOSC ´ L
3. Maximum output current:ICC_max = ILIM_min -
ΔIL
2
ΔIL
2
η = Estimated buck 1 converter efficiency (use the number from the efficiency plots or 85% as an estimation)
ƒOSC = Buck 1 converter switching frequency (600 kHz)
L = Selected inductor value for the boost converter (see the Inductor Selection section)
ISWPEAK = Buck 1 converter switch current (must be < ILIM_min = 2.6 A)
ΔIL = Inductor peak-to-peak ripple current
4. Peak switch current:ISWPEAK = ICC_max +
Inductor Selection (Buck 1 Converter)
Refer to the boost converter Inductor Selection.
Inductor value: as for the boost converter, the buck 1 converter is designed to work with an inductor range as
10 µH ≤ L ≤ 22 µH. The buck 1 converter is optimized to work with 10 µH.
Copyright © 2011–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS65178 TPS65178A
Submit Documentation Feedback
21
TI Confidential - NDA Restrictions
TPS65178
TPS65178A
SLVSAP8D – JULY 2011 – REVISED JULY 2012
www.ti.com
Rectifier Diode Selection (Buck 1 Converter)
Refer to the boost converter rectifier Diode Rectifier Selection.
Input Capacitor Selection (Buck 1 Converter)
Two 10-µF (or one 22-µF) ceramic input capacitor is sufficient for most of the applications. For better input
voltage filtering this value can be increased. Refer to the Recommended Operation Conditions table, Table 4 and
the Typical Application section for input capacitor recommendations.
Output Capacitor Selection (Buck 1 Converter)
For best output voltage filtering a low ESR output capacitor is recommended. Typically, four 10-µF (or two 22-µF)
ceramic output capacitors work for most of the applications. Higher capacitor values can be used to improve the
load transient response. Refer to the Recommended Operation Conditions table, Table 4 and the Typical
Application section for input capacitor recommendations.
BUCK 2 & 4 CONVERTER (VCORE & VEPI)
The TPS65178/A integrates two synchronous buck converters (step-down) 2 and 4 that include a unique hysteric
PWM controller scheme which enables switching frequencies over 3MHz, excellent transient and ac load
regulation as well as operation with tiny and cost competitive external components like chip inductors. The
TPS65178/A’s buck 2 and 4 converters offer adjustable output voltage down to 0.9 V, ideal to support the most
recent timing controllers and panel interfaces. The internal switch current limit of 1.1 A minimum supports output
currents of up to 1 A for the buck 2 and a lower limit to support current up to 400 mA for the buck 4. .
Enable Signal (UVLO & Power Good)
The buck 4 converter is enabled together with the buck 1 converter when the VIN voltage exceeds the UVLO
threshold of 8.3 V typically. The buck 2 converter is enabled with the power good signals of the buck 2 and 4.
Buck 2 & 4 Converter Operation
The converters operate in a hysteretic mode. The high side transistor (PMOS) remains turned on until a minimum
on time of tON min expires and the output voltage trips the threshold of the error comparator or the inductor current
reaches the high side switch current limit. Once the high side switch turns off, the low side switch rectifier is
turned on and the inductor current ramps down. As the output voltage falls below the threshold of the error
comparator, a switch pulse is initiated and the high side switch is turned on again. If the inductor current falls
down to zero, will continue operating with tON min and tOFF min in order to maintain the proper output voltage.
Startup and Short Circuit Protection (Buck 2 & 4 Converters)
The buck 4 converter tracks the buck 1 converter output voltage during startup until it has reached its
programmed value. The buck 2 converter starts operation after the Power Good signals of buck 1 and 4
converters have been asserted. In the event of a short circuit, the converters will operate with maximum duty
cycle and the output current will be limited by the internal current limit.
Startup Sequence (Buck 1, 2 & 4)
As the buck 1 supplies the inputs of buck 2 and buck 4 via the OUT1 pin, it is not possible to have VCORE or VEPI
exceeding their input voltage VCC. Buck 4 and buck 1 start simultaneously and buck 4 operates with maximum
duty cycle during startup (it behaves as a LDO) until VEPI has reached its programmed value. Buck 2 will only
start when buck 1 and buck 4 Power Good signals have been asserted by reaching their target values.
The startup durations depending on output load, output capacitance, inductor value, input voltage and output
voltage, a typical example can be seen on Figure 25 (refer to the typical application conditions on Figure 30 for
the external components used - no output load on this measurement).
Buck 2 or Buck 4 Not used
In the case where buck 2/4 are not used (one or both of them), the following connections need to be made:
OUT2/4 = OUT1 and SWB2/4 = PGND2/4 = N.C. This will ensure that both converters will generate their Power
Good signal allowing the rest of the sequencing to happen (RST and Negative Charge Pump).
22
Submit Documentation Feedback
Copyright © 2011–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS65178 TPS65178A
TI Confidential - NDA Restrictions
TPS65178
TPS65178A
www.ti.com
SLVSAP8D – JULY 2011 – REVISED JULY 2012
Setting the Output Voltage VCORE & VEPI
The output voltages of the buck 2 and 4 converters are programmable via a two-wire interface between 0.9 V
and 2.4 V with a 4-bit resolution. See the Appendix section to set the VCORE voltage.
Buck 2 and 4 Converter Design Procedure
VEPI output voltage can be calculated using the following equations by replacing VCORE values.
1. Duty Cycle: D =
VCORE
VCC ´ η
2. Inductor ripple current: ΔIL =
VCC - VCORE
V
- VCORE
´ t ON = CC
´ D
L
L ´ f
3. Maximum output current: ICORE_max = ILIM_min -
ΔIL
2
ΔIL
2
η = Estimated buck 2 converter efficiency (use the number from the efficiency plots or 80% as an estimation)
´ (1-D)
V
fSW2 = CORE -6
0.37e
ƒ = Buck 2 converter switching frequency
L = Selected inductor value for the buck 2 converter (see the Inductor Selection section)
ISWPEAK = Buck 2 converter switch current (must be < ILIM_min = 1.1 A)
ΔIL = Inductor peak-to-peak ripple current
4. Peak switch current: ISWPEAK = ICORE_max +
The peak switch current is the steady state current that the integrated switches and the inductor have to be able
to handle.
Inductor Selection (Buck 2 & 4 Converter)
Refer to the boost converter inductor selection.
Inductor value: the buck 2 and 4 converters are designed to work with small inductors in the following range: 1.0
µH ≤ L ≤ 2.2 µH. The buck 2 and 4 converters are optimized to work with 2.2 µH.
Table 5. Inductor Selection Buck 2 and 4 (Chip Inductors)
L
(µH)
SUPPLIER
COMPONENT CODE
SIZE
(LxWxH mm)
DCR TYP
(mΩ)
ISAT
(A)
2.2
2.2
Murata
LQM21PN2R2
2 x 1.2 x 0.55
340
0.6
FDK
MPSZ2012D2R2
2 x 1.2 x 1
230
0.7
1.0
FDK
MIPSZ2012D1R0
2 x 1.2 x 1
90
1.1
2.2
Murata
LQM2HPN2R2MG0
2.5 x 2 x 1
80
1.3
1.0
Murata
LQM2HPN1R0MG0
2.5 x 2 x 1
90
1.5
Input Capacitor Selection
Because of the nature of the buck 2 and 4 converter having a pulsating input current, a low ESR input capacitor
is required for best input voltage filtering and minimizing the interference with other circuits caused by high input
voltage spikes. For most applications a minimum of 1 µF ceramic capacitor is recommended. The input capacitor
connected as close as possible to the IC on OUT1 pin can be increased without any limit for better input voltage
filtering. Refer to Table 6 for the selection of the filtering capacitors.
Output Capacitor Selection
The unique hysteric PWM control scheme of the TPS65178/A’s buck 2 converter allows the use of tiny ceramic
capacitors. Ceramic capacitors with low ESR values have the lowest output voltage ripple and are
recommended. Refer to Table 6 for the selection of the output capacitors.
Copyright © 2011–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS65178 TPS65178A
Submit Documentation Feedback
23
TI Confidential - NDA Restrictions
TPS65178
TPS65178A
SLVSAP8D – JULY 2011 – REVISED JULY 2012
www.ti.com
Table 6. Input and Output Capacitor Selection Buck 2 and 4
CAPACITOR
VOLTAGE RATING
COMPONENT SUPPLIER
COMPONENT CODE
COMMENTS
1µF/0603
16V
Taiyo Yuden
EMK107 BJ 105KA
CIN
4.7µF/0603
10V
Taiyo Yuden
LMK107 BJ 475KA
CIN
4.7µF/0603
6.3V
Taiyo Yuden
JMK107 BJ 475_A
COUT
Note: If the buck 2 or 4 are not used, OUT2 (pin 5) or OUT4 (pin 1) must be connected to OUT1 (pin 4) for
proper startup.
BUCK 3 CONVERTER (HVDD)
The TPS65178/A integrates also a synchronous buck 3 (step-down) converter that uses a PWM able to sink and
source current up to 500 mA.
Enable Signal (DLY2)
The buck 3 converter is enabled together with the boost converter when the power good of the negative charge
pump (VGL) is asserted and that the DLY2 has passed. See the Appendix section to set the DLY2 timing.
Startup and Short Circuit Protection (Buck 3 Converter)
The buck 3 converter output voltage tracks the boost converter output voltage at a ratio metric pace during
startup. To prevent Source Driver damages, the TPS65178/A implements a protection feature that disables both
the boost (VDD) and the buck 3 (HVDD) converters when short-circuits or over voltages occur on one of the two
converters. The converters will autonomously recover after the failure has gone.
Setting the output voltage HVDD
The output voltage of the buck 3 converter is programmable via a two-wire interface between 6.4 V and 9.55 V
with a 6-bit resolution. See the Appendix section to set the HVDD voltage.
Buck 3 Converter Design Procedure
1. Duty Cycle: D =
HVDD
VIN ´ η
2. Inductor ripple current: ΔIL =
1.85e-6
L
3. Maximum output current: IHVDD_max = ILIM_min -
ΔIL
2
ΔI
4. Peak switch current: ISWPEAK = IHVDD_max + L
2
η = Estimated buck 3 converter efficiency (use the number from the efficiency plots or 80% as an estimation)
HVDD ´ (1-D)
fSW3 =
1.85e -6
ƒ = Buck 3 converter switching frequency
L = Selected inductor value for the buck 3 converter (in µH – for value see the Inductor Selection section)
ISWPEAK = Buck 3 converter switch current (must be < ILIM_min = 0.8 A)
ΔIL = Inductor peak-to-peak ripple current
The peak switch current is the steady state current that the integrated switches and the inductor have to be able
to handle.
Inductor Selection (Buck 3 Converter)
Refer to the boost converter Inductor Selection section, for more details.
Inductor value: the buck 3 converter is designed to work with small inductors in the following range: 4.7µH ≤ L ≤
10 µH. The buck 3 converter is optimized to work with 6.8 µH.
24
Submit Documentation Feedback
Copyright © 2011–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS65178 TPS65178A
TI Confidential - NDA Restrictions
TPS65178
TPS65178A
www.ti.com
SLVSAP8D – JULY 2011 – REVISED JULY 2012
Table 7. Inductor Selection Buck 3 (Chip Inductors)
L
(µH)
SUPPLIER
COMPONENT CODE
SIZE
(LxWxH mm)
DCR TYP
(mΩ)
ISAT
(A)
4.7, 6.8, 10
Taiyo Yuden
CBC2518T series
2.5 x 1.8 x 1.8
260 ~ 460
480 ~ 680
4.7, 6.8, 10
Taiyo Yuden
CBC3225T series
3.2 x 2.5 x 2.5
100 ~ 133
900 ~ 1250
Input Capacitor Selection
Typically, one 10-µF ceramic capacitor on PVINB3 pin is recommended. For better input voltage filtering this
value can be increased. Refer to the Recommended Operation Conditions table, Table 4 and the Typical
Application section for input capacitor recommendations.
Output Capacitor Selection
Typically, one 10-µF ceramic output capacitor works for most of the applications. Refer to the Recommended
Operation Conditions table, Table 4 and the Typical Application section for output capacitor recommendations.
POSITIVE CHARGE PUMP CONTROLLER (VGH) and TEMPERATURE COMPENSATION
The positive charge pump (CPP) flying capacitor is driven from SWP pin with an intergated 50% duty cycle pushpull stage. The regulation is achieved using an external PNP transistor controlled by the CTRLP pin. The
TPS65178/A also includes a temperature compensation feature that controls the output voltage depending on the
temperature sense by an external Negative Thermistor (NTC).
Enable Signal (DLY3)
The positive charge pump controller as well as the push-pull stage on SWP pin are enabled when the boost and
buck 3 converters’ power good signals are asserted and that the DLY3 has passed. See the Appendix section to
set the DLY3 timing.
Positive Charge Pump Controller Operation
During normal operation, the TPS65178/A is able to provide up to 1.5 mA of base current typically and is
designed to work best with transistors whose DC gain (hFE) is between 100 and 300. The charge pump is
protected against short-circuits on its output, which are detected for voltages below 1 V. During short-circuit
mode, the base current available from the CTRLP pin is limited to 60 µA typically. Note that if a short-circuit is
detected during normal operation, the boost converter switching activity is also halted until VGH is above 1 V.
Typical application circuits are shown in Figure 27.
VDD
VDD
VGH
VGH
CTRLP
SWP
SWP
CTRLP
VGH
VGH
Input Regulation
Output Regulation
Figure 27. Positive Charge Pump Application Circuits
Copyright © 2011–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS65178 TPS65178A
Submit Documentation Feedback
25
TI Confidential - NDA Restrictions
TPS65178
TPS65178A
SLVSAP8D – JULY 2011 – REVISED JULY 2012
www.ti.com
Positive Charge Pump Design Procedure
The regulation of the positive charge pump (CPP) can be done either on the input (transistor placed between VDD
and the diode) or on the output. For better regulation and fewer interactions between the boost converter and the
CPP controller, it is recommended to place the transistor on the output. During startup, the inrush current is
limited by the SWP push-pull stage that limits the current to 300 mA typically. For proper operation, it is
recommended to have a headroom (2xVDD-2xVDIODE-VGH) of 1 V minimum.
Diodes selection (CPP)
Small-signal diodes can be used for most low current applications (
工商网监
湘ICP备2023018690号
