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TPS65180, TPS65181, TPS65180B, TPS65181B
SLVSA76G – MARCH 2010 – REVISED JANUARY 2016
TPS6518xx PMIC for E Ink® Vizplex™-Enabled Electronic Paper Display
1 Features
2 Applications
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Single-Chip Power Management Solution for
E Ink® Vizplex™ Electronic Paper Displays
Generates Positive and Negative Gate and
Source Driver Voltages and Back-Plane Bias from
a Single, Low-Voltage Input Supply
3-V to 6-V Input Voltage Range
Boost Converter for Positive Rail Base
Inverting Buck-Boost Converter for Negative Rail
Base
Two Adjustable LDOs for Source Driver Supply
– LDO1: 15 V, 120 mA (VPOS)
– LDO2: –15 V, 120 mA (VNEG)
Accurate Output Voltage Tracking
– VPOS - VNEG = ±50 mV
Two Charge Pumps for Gate Driver Supply
– CP1: 22 V, 10 mA (VDDH)
– CP2: –20 V, 12 mA, (VEE)
Adjustable VCOM Driver for Accurate PanelBackplane Biasing
– –0.3 V to –2.5 V
– ±1.5% Accuracy (±18 mV)
– 8-Bit Control (11-mV Nominal Step Size)
– 15-mA Maximum Integrated Switch
Integrated 3.3-V Power Switch for Disabling
System Power Rail
Thermistor Monitoring
– –10°C to +85°C Temperature Range
– ±1°C Accuracy from 0°C to 50°C
I2C Serial Interface
– Slave Address 0x48h (1001000)
Flexible Power-Up Sequencing
Interrupt and Sleep Mode Support
Thermally-Enhanced Package for Efficient Heat
Management
(48-Pin 7 mm × 7 mm × 0.9 mm VQFN)
•
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Power Supply for Active Matrix E Ink Vizplex
Panels
EPD Power Supply
E-Book Readers
EPSON® S1D13522 (ISIS) Timing Controller
EPSON S1D13521 (Broadsheet) Timing
Controller
Application Processors With Integrated or
Software Timing Controller (OMAP™)
3 Description
The TPS6518x and TPS65181xB family of devices
are single-chip power supplies designed to for E Ink
Vizplex displays used in portable e-reader
applications and support panel sizes up to 9.7 inches.
Two high-efficiency DC–DC boost converters
generate ±17-V rails which are boosted to 22 V and
–20 V by two change pumps to provide the gate
driver supply for the Vizplex panel. Two tracking
LDOs create the ±15-V source driver supplies which
support up to 120-mA of output current. All rails are
adjustable through the I2C interface to accommodate
specific panel requirements.
Device Information(1)
PART NUMBER
TPS65180
PACKAGE
BODY SIZE (NOM)
(2)
TPS65180B
VQFN (48)
TPS65181(2)
7.00 mm × 7.00 mm
TPS65181B
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
(2) Not recommended for new design (NRND).
Typical Application Schematic
VDDH_D
VIN
From Input
Supply
(3 V to 6 V)
TS
Positive
Charge
Pump
Temperature
Sensor
VDDH_DRV
VDDH_FB
VPOS
VIN_SW
LDO1
VCOM
VN
DCDC2
VCOM
From Input
Supply
(3 V to 6 V)
VB_SW
VB
DCDC2
VCOM_Panel
VNEG
LDO2
VEE_D
I/O Control
VCOM
Positive
Charge
Pump
VEE_DRV
VEE_FB
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS65180, TPS65181, TPS65180B, TPS65181B
SLVSA76G – MARCH 2010 – REVISED JANUARY 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Description (continued).........................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
8.1
8.2
8.3
8.4
8.5
8.6
8.7
9
1
1
1
2
3
3
4
6
Absolute Maximum Ratings ...................................... 6
ESD Ratings.............................................................. 6
Recommended Operating Conditions....................... 6
Thermal Information .................................................. 7
Electrical Characteristics.......................................... 8
Data Transmission Timing ..................................... 11
Typical Characteristics ............................................ 11
Detailed Description ............................................ 12
9.1 Overview ................................................................. 12
9.2 Functional Block Diagram ....................................... 13
9.3 Feature Description................................................. 14
9.4 Device Functional Modes........................................ 17
9.5 Register Maps ......................................................... 18
10 Application and Implementation........................ 33
10.1 Application Information.......................................... 33
10.2 Typical Application ............................................... 41
11 Power Supply Recommendations ..................... 42
12 Layout................................................................... 43
12.1 Layout Guidelines ................................................. 43
12.2 Layout Example .................................................... 43
13 Device and Documentation Support ................. 45
13.1
13.2
13.3
13.4
13.5
13.6
13.7
Device Support......................................................
Documentation Support ........................................
Related Links ........................................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
45
45
45
45
45
45
46
14 Mechanical, Packaging, and Orderable
Information ........................................................... 46
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision F (February 2011) to Revision G
•
2
Page
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section. ................................................................................................. 1
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Copyright © 2010–2016, Texas Instruments Incorporated
Product Folder Links: TPS65180 TPS65181 TPS65180B TPS65181B
TPS65180, TPS65181, TPS65180B, TPS65181B
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SLVSA76G – MARCH 2010 – REVISED JANUARY 2016
5 Description (continued)
Accurate back-plane biasing is provided by a linear amplifier and can be adjusted either by an external resistor or
the I2C interface. The VCOM driver can source or sink current depending on panel condition. For automatic
VCOM adjustment in production line, VCOM can be set from –0.3 V to –2.5 V with 8-bit control through the serial
interface. The power switch is integrated to isolate VCOM driver from E Ink® panel.
The TPS6518x and TPS65181xB devices provide precise temperature measurement function to monitor the
panel temperature during operation. The TPS65180 and TPS65180B requires the host processor to trigger the
temperature acquisition through an I2C write whereas the TPS65181 and TPS65181B automatically updates the
temperature every 60 s.
6 Device Comparison Table
TPS65180
TPS65180B
FUNCTION
EPSON ISIS (S1D113522)
Compatibility
TPS65181
TPS65181B
EPSON ISIS (S1D113522)
EPSON Broadsheet (S1D13521)
OMAP
Temperature sensor
OMAP
ST
ST
Triggered by host
Automatically triggers every 60 s
I2C interface
Standard
Supports standard and Broadsheet protocol
Fault recovery
INT register must be read before rails can be re-enabled
after a fault
Interrupts are automatically reset when faults
clear. No need to read INT register.
VCOM adjust default
I2C control
External potentiometer
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SLVSA76G – MARCH 2010 – REVISED JANUARY 2016
www.ti.com
7 Pin Configuration and Functions
25 - VN_SW
27 - VIN_P
26 - N/C
29 - VEE_IN
28 - VN
31 - VEE_D
30 - VEE_DRV
33 - PGND2
32 - VEE_FB
34 - VDDH_FB
36 - VDDH_DRV
35 - VDDH_D
RGZ Package
48-Pin VQFN With Exposed Thermal Pad
Top View
R G Z
P A C K A G E
24 - PWR_GOOD
23 - PBKG
VDDH_IN - 37
N/C - 38
22 - PWR0
N/C - 39
VB_SW - 40
21 - PWR1
20 - PWR2
PGND3 - 41
VB - 42
VPOS_IN - 43
19 - PWR3
18 - SDA
17 - SCL
16 - VCOM_PWR
15 - VCOM
VPOS - 44
VIN3P3 - 45
V3P3 - 46
TS - 47
14 - VCOM_PANEL
13 - N/C
VCOM_CTRL - 12
AGND1 - 8
INT_LDO1 -9
VIN – 10
VCOM_XADJ - 11
DGND - 6
INT_LDO2 - 7
VNEG - 3
VNEG_IN - 4
WAKEUP - 5
VREF - 1
nINT - 2
AGND2 - 48
Pin Functions
PIN
I/O
DESCRIPTION
NO.
NAME
1
VREF
O
Filter pin for 2.25-V internal reference to ADC
2
nINT
O
Open-drain interrupt pin (active low)
3
VNEG
O
Negative supply output pin for panel source drivers
4
VNEG_IN
I
Input pin for LDO2 (VNEG)
5
WAKEUP
I
Wake-up pin (active high). Pull this pin high to wake up from sleep mode.
6
DGND
—
Digital ground
7
INT_LDO2
O
Internal supply (digital circuitry) filter pin
8
AGND1
—
Analog ground for general analog circuitry
9
INT_LDO1
O
Internal supply (analog circuitry) filter pin
10
VIN
I
Input power supply to general circuitry
11
VCOM_XADJ
I
Analog input for conventional VCOM setup method. Tie this pin to ground if VCOM is set
through I2C interface.
12
VCOM_CTRL
I
VCOM_PANEL gate driver enable (active high)
4
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SLVSA76G – MARCH 2010 – REVISED JANUARY 2016
Pin Functions (continued)
PIN
NO.
I/O
NAME
DESCRIPTION
13
N/C
—
Not connected
14
VCOM_PANEL
O
Panel common-voltage output pin
15
VCOM
O
Filter pin for panel common-voltage driver
16
VCOM_PWR
I
Internal supply input pin to VCOM buffer. Connect to the output of DCDC2.
17
SCL
I
Serial interface (I2C) clock input
18
SDA
I/O
19
PWR3
I
Enable pin for CP1 (VDDH) (active-high)
20
PWR2
I
Enable pin for LDO1 (VPOS) (active-high)
21
PWR1
I
Enable pin for CP2 (VEE) (active-high)
22
PWR0
I
Enable pin for LDO2 (VNEG) and VCOM (active-high)
23
PowerPAD
(PBKG)
—
Die substrate/thermal pad. Connect to VN with short, wide trace. Wide copper trace
improves heat dissipation. PowerPad must not be connected to ground.
24
PWR_GOOD
O
Open-drain power-good output pin (active-low)
25
VN_SW
O
Inverting buck-boost converter switch out (DCDC2)
26
N/C
—
Not connected
27
VIN_P
I
Input power supply to inverting buck-boost converter (DCDC2)
28
VN
I
Feedback pin for inverting buck-boost converter (DCDC2)
29
VEE_IN
I
Input supply pin for CP1 (VEE)
30
VEE_DRV
O
Driver output pin for negative charge pump (CP2)
31
VEE_D
O
Base voltage output pin for negative charge pump (CP2)
32
VEE_FB
I
Feedback pin for negative charge pump (CP2)
33
PGND2
—
34
VDDH_FB
I
Feedback pin for positive charge pump (CP1)
35
VDDH_D
O
Base voltage output pin for positive charge pump (CP1)
36
VDDH_DRV
O
Driver output pin for positive charge pump (CP1)
37
VDDH_IN
I
Input supply pin for positive charge pump (CP1)
38
N/C
—
Not connected
39
N/C
—
Not connected
40
VB_SW
O
Boost converter switch out (DCDC1)
41
PGND3
—
Power ground for DCDC1
42
VB
I
Feedback pin for boost converter (DCDC1)
43
VPOS_IN
I
Input pin for LDO1 (VPOS)
44
VPOS
O
Positive supply output pin for panel source drivers
45
VIN3P3
I
Input pin to 3.3-V power switch
46
V3P3
O
Output pin of 3.3-V power switch
47
TS
I
Thermistor input pin. Connect a 10k NTC thermistor and a 43k linearization resistor
between this pin and AGND2.
48
AGND2
—
Copyright © 2010–2016, Texas Instruments Incorporated
Serial interface (I2C) data input and output
Power ground for CP1 (VDDH) and CP2 (VEE) charge pumps
Reference point to external thermistor and linearization resistor
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SLVSA76G – MARCH 2010 – REVISED JANUARY 2016
www.ti.com
8 Specifications
8.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1) (2)
MIN
MAX
UNIT
Input voltage at VIN, VINP, VIN3P3
–0.3
7
V
Ground pins to system ground
–0.3
0.3
V
Voltage range at SDA, SCL, WAKEUP, PWR3, PWR2, PWR1, PWR0,
VCOM_CTRL, VDDH_FB, VEE_FB, PWR_GOOD, nINT
–0.3
3.6
V
VCOM_XADJ
–3.6
0.3
V
Voltage on VB, VB_SW, VPOS_IN, VDDH_IN
–0.3
20
V
Voltage on VN, VNEG_IN, VEE_IN, VCOM_PWR
–20
0.3
V
Voltage from VINP to VN_SW
–0.3
Peak output current
30
Continuous total power dissipation
2
W
°C
–10
85
°C
–65
150
°C
Operating junction temperature
–10
TA
Operating ambient temperature (3)
Tstg
Storage temperature
(2)
(3)
mA
125
TJ
(1)
V
Internally limited
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability.
All voltage values are with respect to network ground terminal.
TI recommends that copper plane in proper size on board be in contact with die thermal pad to dissipate heat efficiently. Thermal pad is
electrically connected to PBKG, which is supposed to be tied to the output of buck-boost converter. Thus wide copper trace in the buckboost output helps heat dissipated efficiently.
8.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic
discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
8.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
Input voltage at VIN, VINP, VIN3P3
3
3.7
6
V
Voltage at SDA, SCL, WAKEUP, PWR3, PWR2, PWR1, PWR0,
VCOM_CTRL, VDDH_FB, VEE_FB, VCOM_XADJ, PWR_GOOD, nINT
0
3.6
V
TA
Operating ambient temperature
–10
85
°C
TJ
Operating junction temperature
–10
125
°C
6
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www.ti.com
SLVSA76G – MARCH 2010 – REVISED JANUARY 2016
8.4 Thermal Information
THERMAL METRIC
TPS6518x
TPS6518xB
(1)
RGZ (VQFN)
UNIT
48 PINS
(2)
RθJA
Junction-to-ambient thermal resistance
30.5
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
16.2
°C/W
RθJB
Junction-to-board thermal resistance
7.1
°C/W
ψJT
Junction-to-top characterization parameter
0.2
°C/W
ψJB
Junction-to-board characterization parameter
7.1
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
°C/W
(1)
(2)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
Estimated when mounted on high K JEDEC board per JESD 51-7 with thickness of 1.6 mm, 4 layers, size of 76.2 mm × 114.3 mm, and
2-oz. copper for top and bottom plane. Actual thermal impedance depends on PCB used in the application.
Copyright © 2010–2016, Texas Instruments Incorporated
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TPS65180, TPS65181, TPS65180B, TPS65181B
SLVSA76G – MARCH 2010 – REVISED JANUARY 2016
8.5
www.ti.com
Electrical Characteristics
VIN = 3.7 V, TA = –10°C to 85ºC, Typical values are at TA = 25ºC (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
3
3.7
6
UNIT
INPUT VOLTAGE
VIN
Input voltage range
VUVLO
Undervoltage lockout threshold
VIN falling
2.9
V
V
VHYS
Undervoltage lockout hysteresis
VIN rising
400
mV
INPUT CURRENT
IQ
Operating quiescent current into
VIN
Device switching, no load
5.5
mA
ISTD
Operating quiescent current into
VIN
Device in standby mode
130
µA
ISLEEP
Shutdown current
Device in sleep mode
2.8
10
µA
INTERNAL SUPPLIES
VINT_LDO1
Internal supply
2.7
V
VINT_LDO2
Internal supply
2.7
V
VREF
Internal supply
2.25
V
DCDC1 (POSITIVE BOOST REGULATOR)
VIN
Input voltage range
3
Output voltage range
VOUT
–5%
Output current
RDS(ON)
MOSFET on resistance
6
17
DC set tolerance
IOUT
VIN = 3.7 V
Switch current accuracy
fSW
Switching frequency
L
Inductor
C
Capacitor
ESR
Capacitor ESR
V
V
5%
160
Switch current limit
ILIMIT
3.7
mA
350
mΩ
1.5
A
–30%
30%
1
MHz
2.2
µH
2 × 4.7
µF
20
mΩ
DCDC2 (INVERTING BUCK-BOOST REGULATOR)
VIN
Input voltage range
3
Output voltage range
VOUT
DC set tolerance
–5%
IOUT
Output current
RDS(ON)
MOSFET on resistance
VIN = 3.7 V
Inductor
C
Capacitor
ESR
Capacitor ESR
V
V
5%
350
–30%
mA
mΩ
1.5
Switch current accuracy
L
6
160
Switch current limit
ILIMIT
3.7
–17
A
30%
4.7
µH
2 × 4.7
µF
20
mΩ
LDO1 (VPOS)
VPOS_IN
Input voltage range
16.15
17
17.85
V
14.25
15
15.75
V
VSET
Output voltage set value
VIN = 17 V,
VPOS_SET[2:0] = 0x0h to 0x7h
VINTERVAL
Output voltage set resolution
VIN = 17 V
VPOS_OUT
Output voltage range
VSET = 15 V, ILOAD = 20 mA
14.85
VOUTTOL
Output tolerance
VSET = 15 V, ILOAD = 20 mA
–1%
VDROPOUT
Dropout voltage
ILOAD = 120 mA
250
VLOADREG
Load regulation – DC
ILOAD = 10% to 90%
1%
ILOAD
Load current range
8
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250
15
mV
15.15
V
1%
120
mV
mA
Copyright © 2010–2016, Texas Instruments Incorporated
Product Folder Links: TPS65180 TPS65181 TPS65180B TPS65181B
TPS65180, TPS65181, TPS65180B, TPS65181B
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SLVSA76G – MARCH 2010 – REVISED JANUARY 2016
Electrical Characteristics (continued)
VIN = 3.7 V, TA = –10°C to 85ºC, Typical values are at TA = 25ºC (unless otherwise noted)
PARAMETER
TEST CONDITIONS
ILIMIT
Output current limit
TSS
Soft-start time
C
Recommended output capacitor
MIN
TYP
MAX
200
UNIT
mA
1
ms
4.7
µF
LDO2 (VNEG)
VNEG_IN
Input voltage range
–17.85
–17
–16.15
V
–15.75
–15
–14.25
V
VSET
Output voltage set value
VIN = –17 V,
VNEG_SET[2:0] = 0x0h to 0x7h
VINTERVAL
Output voltage set resolution
VIN = –17 V
VNEG_OUT
Output voltage range
VSET = –15 V, ILOAD = –20 mA
–15.15
VOUTTOL
Output tolerance
VSET = –15 V, ILOAD = –20 mA
–1%
VDROPOUT
Dropout voltage
ILOAD = 120 mA
250
VLOADREG
Load regulation – DC
ILOAD = 10% to 90%
1%
ILOAD
Load current range
ILIMIT
Output current limit
TSS
Soft-start time
C
Recommended output capacitor
250
–15
mV
–14.85
V
1%
120
mV
mA
200
mA
1
ms
4.7
µF
LD01 (POS) AND LDO2 (VNEG) TRACKING
VDIFF
Difference between VPOS and
VNEG
VSET = ±15 V,
ILOAD = ±20 mA, 0°C to 60°C
–50
50
VCOM_SET[7:0] = 0x74h (–1.25 V)
VIN = 3.4 V to 4.2 V, no load
–0.8%
0.8%
VCOM_SET[7:0] = 0x74h (–1.25 V)
VIN = 3.0 V to 6.0 V, no load
–1.5%
1.5%
mV
VCOM DRIVER
Accuracy
VCOM
Output voltage range
G
–2.5
Resolution
VCOM_ADJ = 1 V, 1 LSB
VCOM gain (VCOM_XADJ/VCOM)
VCOM_ADJ = 0 V
–0.3
11
17
1
V
mV
V/V
VCOM SWITCH
TON
Switch ON-time
VCOM = –1.25 V, VCOM_PANEL = 0 V
CVCOM = 4.7 µF, CVCOM_PANEL = 4.7 µF
RDS(ON)
MOSFET ON-resistance
VCOM = –1.245 V, ICOM = 30 mA
ILIMIT
MOSFET current limit
Not tested in production
Switch leakage current
VCOM = 0 V,
VCOM_PANEL = –2.5 V
ISWLEAK
20
1
ms
35
Ω
200
mA
8.3
nA
VIN3P3 TO V3P3 SWITCH
RDS(ON)
MOSFET ON-resistance
VIN3P3 = 3.3 V, ID = 2 mA
Ω
50
CP1 (VDDH) CHARGE PUMP
VDDH_IN
VFB
Input voltage range
16.15
Feedback voltage
17
17.85
1
Accuracy
–3%
VDDH_OUT
Output voltage range
ILOAD
Load current range
fSW
Switching frequency
CD
CO
VSET = 22 V, ILOAD = 2 mA
21
V
V
3%
22
23
10
V
mA
560
KHz
Recommended driver capacitor
10
nF
Recommended output capacitor
4.7
µF
CP2 (VEE) NEGATIVE CHARGE PUMP
VEE_IN
Input voltage range
Copyright © 2010–2016, Texas Instruments Incorporated
–17.75
–17
–16.15
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SLVSA76G – MARCH 2010 – REVISED JANUARY 2016
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Electrical Characteristics (continued)
VIN = 3.7 V, TA = –10°C to 85ºC, Typical values are at TA = 25ºC (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
Feedback voltage
VFB
TYP
MAX
UNIT
–1
Accuracy
–3%
VSET = –20 V, ILOAD = 3 mA
–21
V
3%
VEE_OUT
Output voltage range
–20
–19
V
ILOAD
Load current range
fSW
Switching frequency
CD
Recommended driver capacitor
10
nF
CO
Recommended output capacitor
4.7
µF
12
560
mA
KHz
THERMISTOR MONITOR (1)
ATMS
Temperature to voltage ratio
Not tested in production
OffsetTMS
Offset
Temperature = 0°C
–0.0158
1.575
V/°C
V
VTMS_HOT
Temp hot trip voltage (T = 50°C)
TEMP_HOT_SET = 0x8C
0.768
V
VTMS_COOL
Temp hot escape voltage (T =
45°C)
TEMP_COOL_SET = 0x82
0.845
V
VTMS_MAX
Maximum input level
2.25
V
RNTC_PU
Internal pullup resistor
7.307
KΩ
RLINEAR
External linearization resistor
ADCRES
ADC resolution
Not tested in production, 1 bit
ADCDEL
ADC conversion time
Not tested in production
TMSTTOL
Accuracy
Not tested in production
43
KΩ
8.75
mV
19
–2
µs
2
LSB
LOGIC LEVELS AND TIMING CHARTERISTICS (SCL, SDA, nINT, PWR_GOOD, PWRx, WAKEUP)
IO = 3 mA, sink current
(SDA, nINT, PWR_GOOD)
VOL
Output low threshold level
VIL
Input low threshold level
VIH
Input high threshold level
I(bias)
Input bias current
VIO = 1.8 V
tlow,WAKEUP
WAKEUP low time
minimum low time for WAKEUP pin
fSCL
SCL clock frequency
0.4
V
0.4
V
1.2
V
1
µA
150
ms
400
KHz
OSCILLATOR
fOSC
Oscillator frequency
Frequency accuracy
9
TA = –40°C to 85°C
–10%
MHz
10%
THERMAL SHUTDOWN
TSHTDWN
Thermal trip point
Thermal hysteresis
(1)
10
150
°C
20
°C
10-kΩ Murata NCP18XH103F03RB thermistor (1%) in parallel with a linearization resistor (43 kΩ, 1%) are used at TS pin for panel
temperature measurement.
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8.6
SLVSA76G – MARCH 2010 – REVISED JANUARY 2016
Data Transmission Timing
VBAT = 3.6 V ±5%, TA = 25ºC, CL = 100 pF (unless otherwise noted)
MIN
f(SCL)
Serial clock frequency
tHD;STA
Hold time (repeated) START condition. After this
period, the first clock pulse is generated.
MAX
UNIT
400
KHz
100
tLOW
LOW period of the SCL clock
tHIGH
HIGH period of the SCL clock
tSU;STA
Set-up time for a repeated START condition
tHD;DAT
NOM
Data hold time
tSU;DAT
Data set-up time
tr
Rise time of both SDA and SCL signals
tf
Fall time of both SDA and SCL signals
tSU;STO
Set-up time for STOP condition
tBUF
Bus free time between stop and start condition
tSP
Pulse width of spikes which mst be suppressed
by the input filter
SCL = 100 KHz
4
µs
SCL = 400 KHz
600
ns
SCL = 100 KHz
4.7
SCL = 400 KHz
1.3
µs
SCL = 100 KHz
4
µs
SCL = 400 KHz
600
ns
SCL = 100 KHz
4.7
µs
SCL = 400 KHz
600
SCL = 100 KHz
0
3.45
µs
SCL = 400 KHz
0
900
ns
SCL = 100 KHz
250
SCL = 400 KHz
100
ns
ns
SCL = 100 KHz
1000
SCL = 400 KHz
300
SCL = 100 KHz
300
SCL = 400 KHz
300
ns
ns
SCL = 100 KHz
4
µs
SCL = 400 KHz
600
ns
SCL = 100 KHz
4.7
SCL = 400 KHz
1.3
SCL = 100 KHz
n/a
n/a
SCL = 400 KHz
0
50
µs
ns
8.7 Typical Characteristics
100
0.78
90
0.76
80
0.74
Efficiency (%)
Efficiency (%)
70
60
50
40
30
0.72
0.70
0.68
20
0
0.00
0.66
Buck-Boost
10
Boost
0.05
0.10
0.15
0.20
Load Current (A)
Figure 1. Efficiency vs Load Current
Copyright © 2010–2016, Texas Instruments Incorporated
0.25
C002
0.64
0.00
0.02
0.04
0.06
0.08
0.10
0.12
0.14
0.16
Load Current (mA)
0.18
C007
Figure 2. Load Current vs Efficiency
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9 Detailed Description
9.1 Overview
The TPS6518x and TPS65181xB family of devices provides two adjustable LDOs, inverting buck-boost
converter, boost converter, thermistor monitoring, and flexible power-up and power-down sequencing. The
system can be supplied by a regulated input voltage ranging from 3 V to 6 V. The device is characterized across
a –10°C to 85°C temperature range, best suited for personal electronic applications.
The I2C interface provides comprehensive features for using the TPS6518x and TPS65181xB family of devices.
All rails can be enabled or disabled. Power-up and power-down sequences can also be programmed through the
I2C interface, as well as thermistor and interrupt configurations. Voltage adjustment can also be controlled by the
I2C interface. The adjustable LDOs can supply up to 120 mA of current. The default output voltages for each
LDO can be adjusted through the I2C interface. LDO1 (VPOS) and LDO2 (VNEG) track each other in a way that
they are of opposite sign but same magnitude. The sum of VLDO1 and VLOD2 is guaranteed to be less than 50
mV.
There are two charge pumps: VDDH and VEE 10 mA and 12 mA respectively. These charge pumps boost the
DC-DC boost converters ±16-V rails to provide a gate channel supply. The power-good functionality is open-drain
output, if any of the four power rails (CP1, CP2, LDO1, LDO2) are not in regulation, encounters a fault, or is
disabled the pin is pulled low. PWR_GOOD remains low if one of the rails is not enabled by the host and only
after all rails are in regulation PWR_GOOD is released to Hi-Z state (pulled up by external resistor).
The TPS6518x and TPS65181xB family of devices provides circuitry to bias and measure an external NTC to
monitor the display panel temperature in a range from –10°C to 85°C with and accuracy of ±1°C from 0°C to
50°C. Temperature measurements are triggered by the controlling host and the last temperature reading is
always stored in the TMST_VALUE register.
Interrupts are issued when the temperature exceeds the programmable HOT, or drops below the programmable
COLD threshold, or when the temperature has changed by more than a user-defined threshold from the baseline
value.
12
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SLVSA76G – MARCH 2010 – REVISED JANUARY 2016
9.2 Functional Block Diagram
10uF
10uF
2.2uH
From Input Supply
(3.0V-6.0V)
4.7uF
VIN_P
VB_SW
PGND3
VB
DCDC1
DCDC2
From Input Supply
(3.0V-6.0V)
4.7uF
VN_SW
VN
10uF
PBKG
4.7uF
Gate driver Supply
(22V, 10mA)
VDDH_IN
VDDH_D
VDDH_DRV
1M
10nF VDDH_FB
4.7
uF
4.7uF
VEE_IN
POSITIVE
CHARGE
PUMP
NEGATIVE
CHARGE
PUMP
VEE_D
VEE_DRV
10nF
VEE_FB
47.5k
Gate driver Supply
(-20V, 12mA)
1M
4.7
uF
53.6k
PGND2
VPOS_IN
Source Driver Supply
(15V,120mA)
VNEG_IN
4.7uF
4.7uF
4.7uF
VPOS
LDO1
LDO2
VNEG
4.7uF
Source Driver Supply
(-15V, 120mA)
10k NTC
TS
TEMP
SENSOR
INT_LDO1
INT_LDO1
4.7uF
43k
ADC
From Input Supply
(3.0V-6.0V)
INT_LDO2
INT_LDO2
10uF
4.7uF
VIN
VREF
VREF
4.7uF
VCOM
4.7uF
To panel backplane
(-0.3 to -2.5V, 15mA)
DAC
MUX
AGND1
AGND2
DGND
VCOM_XADJ
VCOM_PWR
4.7uF
VIN3P3
GATE DRIVER
VNEG
4.7uF
From system
VCOM_PANEL
GATE DRIVER
From uC or DSP
From uC or DSP
From uC or DSP
From uC or DSP
From uC or DSP
From uC or DSP
VCOM_CTRL
PWR[3]
PWR[2]
PWR[1]
PWR[0]
WAKEUP
Copyright © 2010–2016, Texas Instruments Incorporated
V3P3
PWR_GOOD
10k VIO
nINT
DIGITAL
CORE
10k VIO
SDA
I2C
10k VIO
SCL
To system
To uC or DSP
To uC or DSP
From uC or DSP
From/to uC or DSP
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9.3 Feature Description
9.3.1 Modes of Operation
The TPS6518x and TPS65181xB have three modes of operation, SLEEP, STANDBY, and ACTIVE. SLEEP
mode is the lowest-power mode in which all internal circuitry is turned off. In STANDBY, all power rails are shut
down but the device is ready to accept commands through PWR[3:0] pins and/or I2C interface. In ACTIVE mode
one or more power rails are enabled.
SLEEP
This is the lowest power mode of operation. All internal circuitry is turned off, registers are reset to
default values and the device does not respond to I2C communications. TPS6518x and
TPS65181xB enter SLEEP mode whenever WAKEUP pin is pulled low.
STANDBY
In STANDBY all internal support circuitry is powered up and the device is ready to accept
commands either through GPIO or I2C control but none of the power rails are enabled. To enter
STANDBY mode the WAKEUP pin must be pulled high and all PWRx pins must be pulled low or
the STANDBY bit of the ENABLE register must be set high. The device also enters STANDBY
mode if input undervoltage lockout (UVLO), positive boost undervoltage (VB_UV), or inverting buckboost undervoltage (VN_UV) is detected, or thermal shutdown occurs.
ACTIVE
The device is in ACTIVE mode when any of the output rails are enabled and no fault condition is
present. This is the normal mode of operation while the device is powered up. In ACTIVE mode, a
falling edge on any PWRx pin shuts down and a rising edge powers up the corresponding rail.
9.3.2 Mode Transisitons
SLEEP → ACTIVE WAKEUP pin is pulled high (rising edge) with any PWRx pin high. Rails come up in the order
defined by the PWR_SEQx registers.
SLEEP → STANDBY WAKEUP pin is pulled high (rising edge) with all PWRx pins low. Rails remain down until
one or more PWRx pin is pulled high.
ACTIVE → SLEEP WAKEUP pin is pulled low (falling edge). Rails are shut down in the reverse power-up order
defined by PWR_SEQ registers.
ACTIVE → STANDBY WAKEUP pin is high. All PWRx pins are pulled low (falling edge). Rails shut down in the
order in which PWRx pins are pulled low. In the event of thermal shut down (TSD), undervoltage
lockout (UVLO), positive boost or inverting buck-boost undervoltage (UV), or when STANDBY bit is
set to 1, the device shuts down all rails in the reverse power-up order defined by the PWR_SEQx
registers.
STANDBY → ACTIVE WAKEUP pin is high and any PWRx pin is pulled high (rising edge). Rails come up in the
same order as PWRx pins are pulled high. Alternatively, if ACTIVE bit is set to 1, output rails power
up in the order defined by the PWR_SEQx registers.
STANDBY → SLEEP WAKEUP pin is pulled low (falling edge) while none of the output rails are enabled.
14
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SLVSA76G – MARCH 2010 – REVISED JANUARY 2016
Feature Description (continued)
POWER DOWN
Battery removed
All rails = OFF
I2C
= NO
Registers à default
WAKEUP ( ) & any PWRx pin = high(*)
?
WAKEUP ( ) &
All PWRx pins= low
WAKEUP (?)
All rails
I2C
STANDBY
= OFF
= YES
?
WAKEUP = high &
(STANDBY bit = 1(*) ||
all PWRx pins= (?) (**) ||
(**)
FAULT )
WAKEUP = high &
(ACTIVE bit= 1(*) ||
any PWRx pin( ) (**))
?
WAKEUP (?) (*)
SLEEP
ACTIVE
Rails
I2C
= ON
= YES
NOTES:
||, &
= logic OR, logic AND.
(?), ( ) = rising edge, falling edge.
FAULT = UVLO || TSD (thermal shutdown)|| BOOST UV.
(*)
= Power sequencing is register controlled
.
(**)
= Power sequencing is GPIO controlled
.
?
Figure 3. Global State Diagram
9.3.3 Wake-Up and Power Up Sequencing
The TPS6518x and TPS65181xB support flexible power-up sequencing through GPIO control using the PWR3,
2, 1, 0 pins or I2C control using the PWR_SEQ0, 1, 2 registers. Using GPIO control, the output rails are
enabled/disabled in the order in which the PWRx pins are asserted or de-asserted, respectively, and the powerup timing is controlled by the host only.
In I2C control mode the power-up and power-down order and timing are defined by user register settings. The
default settings support the E Ink Vizplex panel and typically do not need to be charged by the user.
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Feature Description (continued)
9.3.4 GPIO Control
Under GPIO control the system host in E Ink Vizplex panel module enables the TPS6518x and TPS65181xB
output rails by asserting the PWR0, PWR1, PWR2, PWR3 signals and the host has full control over the order
and timing in which the output rails are powered up and down. Rails are in regulation 2 ms after their respective
PWRx pin has been asserted with the exception of the first rail, which takes 6 ms to power up. The additional
time is needed to power up the positive and inverting buck-boost regulator which need to be turned on before
any other rail can be enabled. When all rails are enabled and in regulation the PWR_GOOD pin is released
(pin status = Hi-Z and power-good line is pulled high by external pullup resistor). The PWRx pins are assigned to
the rails as follows:
• PWR0: LDO2 (VNEG) and VCOM
• PWR1: CP2 (VEE)
• PWR2: LDO2 (VPOS)
• PWR3: CP1 (VDDH)
Rails are powered down whenever the host de-asserts the respective PWRx pin, and when all rails are disabled
the device enters STANDBY mode. The next step is then to de-assert the WAKEUP pin to enter SLEEP mode
which is the lowest-power mode of operation.
It is possible for the host to force the TPS6518x and TPS65181xB directly into SLEEP mode from ACTIVE mode
by de-asserting the WAKEUP pin in which case the device follows the power-down sequence defined by the
PWR_SEQx registers before entering SLEEP mode.
9.3.5 I2C Control
Under I2C control the power-up sequence is defined by the PWR_SEQx registers rather than through GPIO
control. In SLEEP mode the TPS6518x and TPS65181xB are completely turned off, the I2C registers are reset,
and the device does not accept any I2C transaction. Pull the WAKEUP pin high while all PWRx pins are held low
and the device enters STANDBY mode which enables the I2C interface. Write to the PWR_SEQ0 register to
define the order in which the output rails is enabled at power-up and to the PWR_SEQ1 and PWR_SEQ2
registers to define the power-up delays between rails. Finally, set the ACTIVE bit in the ENABLE register to 1 to
execute the power-up sequence and bring up all power rails.
It is possible for the host to force the TPS6518x and TPS65181xB directly into ACTIVE mode from SLEEP mode
by pulling the WAKEUP pin high while at least one of the PWRx pins is pulled high. In this case the default
power-up sequence defined by the PWR_SEQx registers applies and the device starts powering up the rails 5.5
ms after the WAKEUP signal has been pulled high.
To power-down the device, set the STANDBY bit of the ENABLE register to 1 then the TPS6518x and
TPS65181xB follows the reverse power-up sequence to bring down all power rails. While the sequencer is busy
powering up the power rails, any activity on the PWRx pins is ignored. When all rails are up, any of the output
rails can be disabled by applying a negative edge on the PWRx input pins, that is, if the host toggles the PWRx
pin high-low or low-high-low, the respective rail is disabled regardless of how it has been enabled.
16
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SLVSA76G – MARCH 2010 – REVISED JANUARY 2016
Feature Description (continued)
WAKEUP
DLY0 + 5.5ms
DLY1
STROBE 1
SEQ = 00
DLY2
STROBE 2
SEQ = 01
DLY3
STROBE 3
SEQ = 10
STROBE 4
SEQ = 11
WAKEUP
DLY0
DLY3
STROBE 4
SEQ = 11
DLY2
STROBE 3
SEQ = 10
DLY1
STROBE 2
SEQ = 01
STROBE 1
SEQ = 00
TOP: Power-up sequence is defined by assigning strobes to individual rails. STROBE1 is the first
strobe to occur after WAKEUP has been pulled high and STROBE4 is the last event in the sequence.
STROBES are assigned to rails in PWR_SEQ0 register and delays between states are defined in
PWR_SEQ1 and PWR_SEQ2 registers.
BOTTOM: Power-down sequence follows reverse power-up sequence.
Figure 4. I2C Control
9.4 Device Functional Modes
9.4.1 The FIX_RD_PTR Bit
The TPS65181 and TPS65181B devices support a special I2C mode, making them compatible with the EPSON
Broadsheet S1D13521 timing controller. Standard I2C protocol requires the following steps to read data from a
register:
1. Send device slave address, R/nW bit set low (write command)
2. Send register address
3. Send device slave address, R/nW set high (read command)
4. The slave responds with data from the specified register address.
The EPSON Broadsheet S1D13521 controller does not support I2C writes nor I2C reads from addressed
registers (step 1. and 2. above) but needs to access the temperature data from the TPS65181 or TPS65181B
TMST_VALUE register. To support Broadsheet based systems, the TPS65181 and TPS65181B automatically
trigger temperature acquisition every 60s and stores the result in TMST_VALUE register. With the FIX_RD_PTR
bit in the FIX_RD_POINTER register set to 1 the device responds to any I2C read command with data from the
TMST_VALUE register. No write command with the register address is required and address auto increment
feature is disabled in this mode. Therefore reading the temperature data is reduced to two steps:
1. Send device address, R/nW set high (read command)
2. Read the data from the slave. The slave responds with data from TMST_VALUE register address.
Write functionality is not affected by the FIX_RD_PTR bit and the main controller in the system maintains full
control of the PMIC. Interrupts and error flags are issued and need to be handled the same way as for the
TPS65180 and TPS65180B with two exceptions:
1. The FIX_RD_PTR bit in the FIX_RD_POINTER register needs to be set to 0 before the main controller can
read any register different from the TMST_VALUE register.
2. Thermal Shutdown (TSD), positive boost undervoltage (VB_UV), inverting buck-boost undervoltage
(VN_UV), and input undervoltage lockout (UVLO) interrupt bits do not have to be cleared before output rails
can be re-enabled.
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Device Functional Modes (continued)
At system power-up the main processor sets up the PMIC by accessing the I2C registers and setting the control
parameters as needed. When the system is setup correctly the main controller sets the FIX_READ_POINTER bit
and the display controller can start accessing the temperature information. During normal operation the main
controller can write to the PMIC at any time but before it can read access registers the FIX_READ_POINTER bit
must be written 0.
9.5 Register Maps
Table 1. Register Address Map
18
DEFAULT
VALUE
REGISTER
ADDRESS (HEX)
NAME
0
0x00
TMST_VALUE
N/A
Thermistor value read by ADC
1
0x01
ENABLE
0001 1111
Enable/disable bits for regulators
2
0x02
VP_ADJUST
0010 0011
Voltage settings for VPOS, VDDH
3
0x03
VN_ADJUST
1010 0011
Voltage settings for VNEG, VEE
4
0x04
VCOM_ADJUST
0111 0100
Voltage settings for VCOM
5
0x05
INT_ENABLE1
0111 0100
Interrupt enable group1
6
0x06
INT_ENABLE2
1111 1011
Interrupt enable group2
7
0x07
INT_STATUS1
0xxx xx00
Interrupt status group1
8
0x08
INT_STATUS2
xxxx x0xx
Interrupt status group2
9
0x09
PWR_SEQ0
1110 0100
Power up sequence
10
0x0A
PWR_SEQ1
0010 0010
DLY0, DLY1 time set
11
0x0B
PWR_SEQ2
0010 0010
DLY2, DLY3 time set
12
0x0C
TMST_CONFIG
0010 0000
Thermistor configuration
13
0x0D
TMST_OS
0011 0010
Thermistor hot temp set
14
0x0E
TMST_HYST
0010 1101
Thermistor cool temp set
15
0x0F
PG_STATUS
0000 0000
Power-good status each rails
16
0x10
REVID
0100 0001
Device revision ID information
17
0x11
FIX_READ_POINTER
0000 0000
I2C read pointer control
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DESCRIPTION
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9.5.1
SLVSA76G – MARCH 2010 – REVISED JANUARY 2016
Thermistor Readout (TMST_VALUE) Register (Offset = 0x00h)
DATA BIT
D7
D6
D5
READ/WRITE
R
R
R
R
R
R
R
R
RESET VALUE
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
FIELD NAME
D4
D3
D2
D1
D0
TMST_VALUE[7:0]
FIELD NAME
BIT DEFINITION
Temperature read-out
1111 0110 – < -10°C
1111 0110 – -10°C
1111 0111 – -9°C
...
1111 1110 – -2°C
1111 1111 – -1 °C
TMST_VALUE[7:0]
0000 0000 – 0 °C
0000 0001 – 1°C
0000 0010 – 2°C
...
0001 1001 – 25°C
...
0101 0101 – 85°C
0101 0101 – > 85°C
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9.5.2
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Enable (ENABLE) Register (Offset = 0x01h)
DATA BIT
D7
D6
D5
D4
D3
D2
D1
D0
FIELD NAME
ACTIVE
STANDBY
V3P3_SW
_EN
VCOM_EN
VDDH_EN
VPOS_EN
VEE_EN
VNEG_EN
READ/WRITE
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RESET VALUE
0
0
0
1
1
1
1
1
BIT DEFINITION (1)
FIELD NAME
STANDBY to ACTIVE transition bit
ACTIVE
1 – Transition from STANDBY to ACTIVE mode. Rails power up as defined by PWR_SEQx registers.
0 – No effect
NOTE: After transition bit is cleared automatically.
ACTIVE to STANDBY transition bit
STANDBY
1 – Transition from ACTIVE to STANDBY mode. Rails power down as defined by PWR_SEQx
registers.
0 – No effect
NOTE: After transition bit is cleared automatically. STANDBY bit has priority over AVTIVE.
VIN3P3 to V3P3 switch enable
V3P3_SW_EN
1 – Switch is ON
0 – Switch id OFF
VCOM buffer enable
VCOM_EN
1 – Enabled
0 – Disabled
VDDH charge pump enable
VDDH_EN
1 – Enabled
0 – Disabled
VPOS LDO regulator enable
VPOS_EN
1 – Enabled
0 – Disabled
NOTE: VPOS cannot be enabled before VNEG is enabled.
VEE charge pump enable
VEE_EN
1 – Enabled
0 – Disabled
VNEG LDO regulator enable
VNEG_EN
1 – Enabled
0 – Disabled
NOTE: When VNEG is disabled VPOS is also disabled.
(1)
20
Enable/disable bits for regulators are AND’d with PWRx signals.
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9.5.3
SLVSA76G – MARCH 2010 – REVISED JANUARY 2016
Positive Voltage Rail Adjustment (VP_ADJUST) Register (Offset = 0x02h)
DATA BIT
D7
D6
D5
D4
VDDH_SET[2:0]
D3
D2
D0
FIELD NAME
Not used
READ/WRITE
R
R/W
R/W
R/W
R
R/W
R/W
R/W
RESET VALUE
0
0
1
0
0
0
1
1
VPOS_SET[2:0]
BIT DEFINITION (1)
FIELD NAME
Not used
not used
D1
N/A
VDDH voltage setting
000 – VDDH increase by 10%
001 – VDDH increase by 5%
010 – Nominal
VDDH_SET[2:0]
011 – VDDH decrease by 5%
100 – VDDH decrease by 10%
101 – Reserved
110 – Reserved
111 – Reserved
Not used
N/A
VPOS voltage setting
000 : |VNEG| - 0.75 V
001 : |VNEG| - 0.5 V
010 : |VNEG| - 0.25 V
011 : |VNEG|
VPOS_SET[2:0]
100 : |VNEG| + 0.25 V
101 : |VNEG| + 0.5 V
110 : |VNEG| + 0.75 V
111 – Reserved
NOTE: For proper tracking of the VPOS and VNEG supply these bits must remain set at their default
value of 011b. VPOS tracks VNEG automatically when VNEG_SET[2:0] bits of VN_ADJUST register
are changed.
(1)
VDDH is decreased from set value defined by resistor divider. Decreased VDDH value must be within spec range.
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SLVSA76G – MARCH 2010 – REVISED JANUARY 2016
9.5.4
(1)
www.ti.com
Negative Voltage Rail Adjustment (VN_ADJUST) Register (Offset = 0x03h)
DATA BIT
D7
D6
D5
D4
VEE_SET[2:0]
D3
D2
Not used
D1
D0
FIELD NAME
VCOM_ADJ
READ/WRITE
R/W
R/W
R/W
R/W
R
R/W
VNEG_SET[2:0]
R/W
R/W
RESET VALUE
1 (1)
0
1
0
0
0
1
1
TPS65180/TPS65180B: Bit defaults to 1; TPS65181/TPS65181B: Bit defaults to 0
FIELD NAME
BIT DEFINITION
VCOM output adjustment method
VCOM_ADJ
0 – VCOM_XADJ pin
1 – I2C interface
VDDH voltage setting
000 – VEE decrease by 10%
001 – VEE decrease by 5%
010 – Nominal
VEE_SET[2:0] (1)
011 – VEE increase by 5%
100 – VEE increase by 10%
101 – Reserved
110 – Reserved
111 – Reserved
not used
N/A
VNEG voltage setting
000 – -15.75 V
001 – -15.50 V
010 – -15.25 V
VNEG_SET[2:0]
011 – -15.00 V
100 – -14.75 V
101 – -14.50 V
110 – -14.25 V
111 – Reserved
(1)
22
VEE is decreased from set value defined by resistor divider. Decreased VEE value must be within spec range.
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9.5.5
SLVSA76G – MARCH 2010 – REVISED JANUARY 2016
VCOM Adjustment (VCOM_ADJUST) Register (Offset = 0x04h)
DATA BIT
D7
D6
D5
D4
FIELD NAME
D3
D2
D1
D0
VCOM_SET[7:0]
READ/WRITE
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RESET VALUE
0
1
1
1
0
1
0
0
FIELD NAME
BIT DEFINITION
VCOM voltage adjustment
0000 0000 – 0 V
0000 0001 – 11 mV
0000 0010 – 22 mV
...
0111 0011 – 1239 mV
VCOM_SET[7:0]
0111 0100 – 1250 mV
0111 0101 – 1261 mV
...
1111 1111 – 2750 mV
NOTE: step size is rounded to 11 mV. Theoretical step size is 2750 mV / 255 mV = 10.78 mV.
Parametric performance is guranteed from -0.3 V to -2.5 V only.
9.5.6
Interrupt Enable 1 (INT_ENABLE1) Register (Offset = 0x05h)
DATA BIT
D7
D6
D5
D4
D3
D2
D1
D0
TMST_COOL
_EN
UVLO_EN
Not used
Not used
FIELD NAME
Not used
TSD_EN
HOT_EN
TMST_HOT
_EN
READ/WRITE
R
R/W
R/W
R/W
R/W
R/W
R
R
RESET VALUE
0
1
1
1
0
1
0
0
FIELD NAME
Not used
BIT DEFINITION
N/A
Thermal shutdown interrupt enable
TSD_EN
1 – Enabled
0 – Disabled
Thermal shutdown early warning enable
HOT_EN
1 – Enabled
0 – Disabled
Thermistor hot warning enable
TMST_HOT_EN
1 – Enabled
0 – Disabled
Thermistor hot escape interrupt enable
TMST_COOL_EN
1 – Enabled
0 – Disabled
VIN undervoltage detect interrupt enable
UVLO_EN
1 – Enabled
0 – Disabled
Not used
N/A
Not used
N/A
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SLVSA76G – MARCH 2010 – REVISED JANUARY 2016
9.5.7
www.ti.com
Interrupt Enable 2 (INT_ENABLE2) Register (Offset = 0x06h)
DATA BIT
D7
D6
D5
D4
D3
D2
D1
D0
FIELD NAME
VB_UV_EN
VDDH_UV
_EN
VN_UV_EN
VPOS_UV
_EN
VEE_UV
_EN
not used
VNEG_UV
_EN
EOC_EN
READ/WRITE
R/W
R/W
R/W
R/W
R/W
R
R/W
R/W
RESET VALUE
1
1
1
1
1
0
1
1
FIELD NAME
BIT DEFINITION
Positive boost converter undervoltage detect interrupt enable
VB_UV_EN
1 – Enabled
0 – Disabled
VDDH undervoltage detect interrupt enable
VDDH_UV_EN
1 – Enabled
0 – Disabled
Inverting buck-boost converter undervoltage detect interrupt enable
VN_UV_EN
1 – Enabled
0 – Disabled
VPOS undervoltage detect interrupt enable
VPOS_UV_EN
1 – Enabled
0 – Disabled
VEE undervoltage detect interrupt enable
VEE_UV_EN
1 – Enabled
0 – Disabled
not used
N/A
VNEG undervoltage detect interrupt enable
VNEG_UV_EN
1 – Enabled
0 – Disabled
ADC end of conversion interrupt enable
EOC_EN
1 – Enabled
0 – Disabled
24
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9.5.8
SLVSA76G – MARCH 2010 – REVISED JANUARY 2016
Interrupt INT_STATUS1 (INT_STATUS1) Register (Offset = 0x07h)
DATA BIT
D7
D6
D5
D4
D3
D2
D1
D0
FIELD NAME
Not used
TSDN
HOT
TMST_HOT
TMST_COOL
UVLO
Not used
Not used
READ/WRITE
R
R
R
R
R
R
R
R
RESET VALUE
0
N/A
N/A
N/A
N/A
N/A
0
0
FIELD NAME
Not used
TSD
Thermal shutdown interrupt
HOT
Thermal shutdown early warning
TMST_HOT
TMST_COOL
UVLO
9.5.9
BIT DEFINITION
N/A
Thermistor hot warning
Thermistor hot escape interrupt
VIN undervoltage detect interrupt
Not used
N/A
Not used
N/A
Interrupt Status 2 (INT_STATUS2) Register (Offset = 0x08h)
DATA BIT
D7
D6
D5
D4
D3
D2
D1
D0
FIELD NAME
VB_UV
VDDH_UV
VN_UV
VPOS_UV
VEE_UV
Not used
VNEG_UV
EOC
READ/WRITE
R
R
R
R
R
R
R
R
RESET VALUE
N/A
N/A
N/A
N/A
N/A
0
N/A
N/A
BIT DEFINITION (1)
FIELD NAME
VB_UV
VDDH_UV
VN_UV
VPOS_UV
VDDH undervoltage detect interrupt
Inverting buck-boost converter undervoltage detect interrupt
VPOS undervoltage detect interrupt
VEE_UV
VEE undervoltage detect interrupt
not used
N/A
VNEG_UV
EOC
(1)
Positive boost converter undervoltage detect interrupt
VNEG undervoltage detect interrupt
ADC end of conversion interrupt
Undervoltage detect bit is set if the corresponding rail does not come up 5 ms after it is enabled except for DCDC1 and 2 which are set
10 ms after they are enabled.
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SLVSA76G – MARCH 2010 – REVISED JANUARY 2016
9.5.10
www.ti.com
Power Sequence Register 0 (PWR_SEQ0) Register (Offset = 0x09h)
DATA BIT
D7
D6
D5
D4
D3
D2
VEE_SEQ[1:0]
D1
D0
FIELD NAME
VDDH_SEQ[1:0]
VPOS_SEQ[1:0]
VNEG_SEQ[1:0]
READ/WRITE
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RESET VALUE
1
1
1
0
0
1
0
0
BIT DEFINITION (1)
FIELD NAME
VDDH power-up/down order
00 – Power-up/down on STROBE1
VDDH_SEQ[1:0]
01 – Power-up/down on STROBE2
10 – Power-up/down on STROBE3
11 – Power-up/down on STROBE4
VPOS power-up/down order
00 – Power-up/down on STROBE1
VPOS_SEQ[1:0]
01 – Power-up/down on STROBE2
10 – Power-up/down on STROBE3
11 – Ppower-up/down on STROBE4
VEE power-up/down order
00 – Power-up/down on STROBE1
VEE_SEQ[1:0]
01 – Power-up/down on STROBE2
10 – Power-up/down on STROBE3
11 – Power-up/down on STROBE4
VNEG power-up/down order
00 – Power-up/down on STROBE1
VNEG_SEQ[1:0]
01 – Power-up/down on STROBE2
10 – Power-up/down on STROBE3
11 – Power-up/down on STROBE4
(1)
26
Power-down sequence follows the reverse order of power-up.
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9.5.11
SLVSA76G – MARCH 2010 – REVISED JANUARY 2016
Power Sequence Register 1 (PWR_SEQ1) Register (Offset = 0x0Ah)
DATA BIT
D7
D6
FIELD NAME
D5
D4
D3
D2
DLY1[3:0]
D1
D0
DLY0[3:0]
READ/WRITE
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RESET VALUE
0
0
1
0
0
0
1
0
FIELD NAME
BIT DEFINITION
DLY1 delay time set; defines the delay time from STROBE1 to STROBE2 during power-up and from
STROBE2 to STROBE1 during power-down.
0000 – 0 ms
0001 – 1 ms
DLY1[3:0]
0010 – 2 ms
0011 – 3 ms
...
1110 – 14 ms
1111 – 15 ms
DLY0 delay time set; defines the delay time from WAKEUP high to STROBE1 during power-up and
from WAKEUP low to STROBE4 during power-down.
0000 – 0 ms
0001 – 1 ms
DLY0[3:0]
0010 – 2 ms
0011 – 3 ms
...
1110 – 14 ms
1111 – 15 ms
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9.5.12
www.ti.com
Power Sequence Register 2 (PWR_SEQ2) Register (Offset = 0x0Bh)
DATA BIT
D7
D6
FIELD NAME
D5
D4
D3
D2
DLY3[3:0]
D1
D0
DLY2[3:0]
READ/WRITE
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RESET VALUE
0
0
1
0
0
0
1
0
FIELD NAME
BIT DEFINITION
DLY3 delay time set; defines the delay time from STROBE3 to STROBE4 during power-up and from
STROBE4 to STROBE3 during power-down.
0000 – 0 ms
0001 – 1 ms
DLY3[3:0]
0010 – 2 ms
0011 – 3 ms
...
1110 – 14 ms
1111 – 15 ms
DLY2 delay time set; defines the delay time from STROBE2 to STROBE3 during power-up and from
STROBE3 to STROBE2 during power-down.
0000 – 0 ms
0001 – 1 ms
DLY2[3:0]
0010 – 2 ms
0011 – 3 ms
...
1110 – 14 ms
1111 – 15 ms
28
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9.5.13
SLVSA76G – MARCH 2010 – REVISED JANUARY 2016
Thermistor Configuration Register (TMST_CONFIG) (Offset = 0x0Ch)
DATA BIT
D7
FIELD NAME
READ_
THERM
D6
D5
Not used
CONV_END
READ/WRITE
R/W
R
R
R/W
RESET VALUE
0
0
1
0
FIELD NAME
D4
D3
D2
D1
D0
FAULT_QUE
_CLR
Not used
Not used
R/W
R/W
R
R
0
0
0
0
FAULT_QUE [1:0]
BIT DEFINITION
Read thermistor value
READ_THERM
1 – Initiates temperature acquisition
0 – No effect
NOTE: bit is self-cleared after acquisition is completed
Not used
N/A
ADC conversion done flag
CONV_END
1 – Conversion is finished
0 – Conversion is not finished
Number of faults to detect before TMST_HOT interrupt is asserted
00 – 1 time
FAULT_QUE [1:0]
01 – 2 times
10 – 4 times
11 – 6 times
Fault counter clear
FAULT_QUE_CLR
1 – Clears fault counter
0 – Fault counter is cleared automatically if thermistor reading is less than TMST_HOT_SET[7:0]
Not used
N/A
Not used
N/A
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SLVSA76G – MARCH 2010 – REVISED JANUARY 2016
9.5.14
www.ti.com
Thermistor Hot Threshold (TMST_OS) Register (Offset = 0x0Dh)
DATA BIT
D7
D6
D5
FIELD NAME
D4
D3
D2
D1
D0
TMST_HOT_SET[7:0]
READ/WRITE
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RESET VALUE
0
0
1
1
0
0
1
0
FIELD NAME
BIT DEFINITION
Defined the thermistor HOT threshold
1000 0000 – Reserved
...
1111 0101 – Reserved
1111 0110 – -10°C
1111 0111 – -9°C
...
1111 1110 – -2°C
1111 1111 – -1°C
0000 0000 – 0°C
TMST_HOT_SET[7:0]
0000 0001 – 1°C
0000 0010 – 2°C
...
0001 1001 – 25°C
...
0011 0010 – 50°C
...
0101 0101 – 85°C
0101 0110 – Reserved
...
0111 1111 – Reserved
30
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9.5.15
SLVSA76G – MARCH 2010 – REVISED JANUARY 2016
Thermistor Cool Threshold (TMST_HYST) Register (Offset = 0x0Eh)
DATA BIT
D7
D6
D5
D4
FIELD NAME
D3
D2
D1
D0
TMST_COOL_SET[7:0]
READ/WRITE
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RESET VALUE
0
0
1
0
1
1
0
1
FIELD NAME
BIT DEFINITION
Defined the thermistor HOT threshold
1000 0000 – Reserved
...
1111 0101 – Reserved
1111 0110 – -10°C
1111 0111 – -9°C
...
1111 1110 – -2°C
1111 1111 – -1°C
0000 0000 – 0°C
TMST_HOT_SET[7:0]
0000 0001 – 1°C
0000 0010 – 2°C
...
0001 1001 – 25°C
...
0010 1101 – 45°C
...
0101 0101 – 85°C
0101 0110 – Reserved
...
0111 1111 – Reserved
9.5.16
Power-Good Status (PG_STATUS) Register (Offset = 0x0Fh)
DATA BIT
D7
D6
D5
D4
D3
D2
D1
D0
FIELD NAME
VB_PG
VDDH_PG
VN_PG
VPOS_PG
VEE_PG
Not used
VNEG_PG
Not used
READ/WRITE
R
R
R
R
R
R
R
R
RESET VALUE
0
0
0
0
0
0
0
0
FIELD NAME
VB_PG
VDDH_PG
VN_PG
VPOS_PG
BIT DEFINITION
Positive boost converter power-good
VDDH power-good
Inverting buck-boost power-good
VPOS power-good
VEE_PG
VEE power-good
not used
N/A
VNEG_PG
not used
VNEG power-good
N/A
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SLVSA76G – MARCH 2010 – REVISED JANUARY 2016
9.5.17
www.ti.com
Revision and Version Control (REVID) Register (Offset = 0x10h)
DATA BIT
D7
D6
D5
D4
FIELD NAME
D3
D2
D1
D0
REVID[7:0]
READ/WRITE
R
R
R
R
R
R
R
R
RESET VALUE
0
1
1
1
0
0
0
0
FIELD NAME
BIT DEFINITION
0101 0000 - TPS65180 1p1
0110 0000 - TPS65180 1p2
0111 0000 - TPS65180B (TPS65180 1p3)
REVID [7:0]
1000 0000 - TPS65180B (TPS65180 1p4)
0101 0001 - TPS65181 1p1
0110 0001 - TPS65181 1p2
0111 0001 - TPS65181B (TPS65181 1p3)
1000 0001 - TPS65181B (TPS65181 1p4)
9.5.18 I2C Read Pointer Control (FIX_READ_POINTER) Register (Offset = 0x11h) (TPS65181 and
TPS65181B ONLY)
DATA BIT
D7
D6
D5
D4
D3
D2
D1
D0
FIELD NAME
Not used
Not used
Not used
Not used
Not used
Not used
Not used
FIX_RD_PTR
READ/WRITE
R
R
R
R
R
R
R
R/W
RESET VALUE
0
0
0
0
0
0
0
0
FIELD NAME
BIT DEFINITION
Not used
N/A
Not used
N/A
Not used
N/A
Not used
N/A
Not used
N/A
Not used
N/A
Not used
N/A
I2C read pointer control
FIX_RD_PTR
1 – Read pointer is fixed to 0x00
0 – read pointer is controlled through I2C
32
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SLVSA76G – MARCH 2010 – REVISED JANUARY 2016
10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
10.1.1 Dependencies Between Rails
Charge pumps, LDOs, and VCOM driver are dependent on the positive and inverting buck-boost converters and
several dependencies exist that affect the power-up sequencing. These dependencies are listed as follows:
1. Inverting buck-boost (DCDC2) must be in regulation before positive boost (DCDC1) can be enabled.
Internally, DCDC1 enable is gated by DCDC2 power-good.
2. Positive boost (DCDC1) must be in regulation before LDO2 (VNEG) can be enabled. Internally LDO2 enable
is gated DCDC1 power-good.
3. Positive boost (DCDC1) must be in regulation before VCOM can be enabled; Internally VCOM enable is
gated by DCDC1 power-good.
4. Positive boost (DCDC1) must be in regulation before negative charge pump (CP2) can be enabled. Internally
CP2 enable is gated by DCDC1 power-good.
5. Positive boost (DCDC1) must be in regulation before positive charge pump (CP1) can be enabled. Internally
CP1 enable is gated by DCDC1 power-good.
6. LDO2 must be in regulation before LDO1 can be enabled. Internally LDO1 enable is gated by LDO2 powergood.
7. The minimum delay time between any two PWRx pins must be > 62.5 µs in order to follow the power up
sequence defined by GPIO control. If any two PWRx pins are pulled up together (< 62.5 µs apart) or the
sequencer tries to bring up the rails at the same time by assigning the same STROBE to rails in PWR_SEQ0
register, rails is staggered in a manner that an enable od the subsequent rail is gated by PG of a preceding
rail. In this case, the default order of power-up is LDO2 (VNEG), CP2 (VEE), LDO1 (VPOS), and
CP1(VDDH). If any two PWRx pins are pulled low together or the sequencer tries to bring down the rails at
the same time by assigning the same STROBE to rails in PWR_SEQ0 register, then all rails goes down at
the same time.
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Application Information (continued)
VIN
PWR0
PWR1
D0
1.8ms (1)
D1
PWR2
D2
PWR3
D3
WAKEUP
SLEEP
STANDBY
ACTIVE
ACTIVE
VN
VB
VNEG
DLY 1
VCOM
6ms (2,5)
DLY 2
DLY 0 + 4ms (2)
VEE
1ms (5)
DLY 3
DLY 1
VPOS
2ms (5)
DLY 0
DLY 2
VDDH
1ms (5)
DLY 3
PWR_GOOD
300 us (max)
11 .8ms (min)
(1) Minimum delay time between WAKEUP rising edge and IC rady to accept I 2C transaction .
(2) It takes 2ms minimum for each internal boost regulator to start up before VNEG can be enabled .
(5) It takes up to 2ms for LDOs (VPOS,VNEG) and 1ms for charge pumps (VDDH,VEE), to reach their steady state after being enabled.
DLY 0-DLY 3 are power up /down delays defined in register PWR _SEQ 1 and PWR _SEQ2.
In this example the first power-up sequence is determined by GPIO control (WAKEUP is pulled high while PWRx pins are low).
Power-down and 2nd power-up sequence is controlled by register settings (WAKEUP pin is toggled with at least one PWR pin
held high).
Figure 5. Power-Up and Power-Down Timing Diagram
10.1.2 Soft-Start
Soft-start for DCDC1, DCDC2, LDO1, and LDO2 is accomplished by lowering the current limits during start-up. If
DCDC1 or DCDC2 are unable to reach power-good status within 10 ms, the corresponding UV flag is set in the
interrupt registers, the interrupt pin is pulled low, and the device enters STANDBY mode. LDO1, LDO2, positive
and negative charge pumps have a 5-ms power-good timeout limit. If either rail is unable to power up within 5 ms
after it has been enabled, the corresponding UV flag is set and the interrupt pin is pulled low. However, the
device remains in ACTIVE mode in this case.
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Application Information (continued)
10.1.3 VCOM Adjustment
Through the I2C interface the user can select between two methods of VCOM voltage adjustment:
1. Using the internal 8-bit DAC and register control.
2. Using an external voltage source (resistor divider) connected to the VCOM_XADJ pin.
10.1.4 VCOM Adjustment Through Register Control
By default the TPS65180x is setup for internal VCOM control through the I2C interface. The default setting for the
8-bit DAC is 0x74h which results in 1.25 V ±0.8% for VCOM. VCOM can be adjusted up or down in steps of
11 mV (typical) by writing to the VCOM_ADJUST register. The output range for VCOM is limited to –0.3 V to
–2.5 V.
10uF
VIN
From Input Supply
(3.0V-6.0V)
4.7uF
VREF (2.25V)
VREF
VCOM_SET[7:0]
VCOM_ADJ
4.7uF
-0.3...-2.5V
VCOM
-0.3...-2.5V
-0.3...-2.5V
MUX
-0.3...-2.5V
DAC
-17V
VCOM_XADJ
VCOM_PWR
VNEG
4.7uF
GATE DRIVER
4.7uF
To Eiink
®
VIXPLEX
TM
VCOM_CTRL
From DCDC 2 (-17V)
From uC or DSP
VCOM_PANEL
Panel
Figure 6. Block Diagram of VCOM Circuit
10.1.5 VCOM Adjustment Through External Potentiometer
VCOM can be adjusted by an external potentiometer by setting the VCOM_ADJ bit of the VN_ADJUST register
to 0 and connecting a potentiometer to the VCOM_XADJ pin. The potentiometer must be connected between
ground and a negative supply as shown in Figure 6. The gain from VCOM_XADJ to VCOM is 1 and therefore the
voltage applied to VCOM_XADJ pin must range from –0.3 V to –2.5 V.
10.1.6 VPOS and VNEG Supply Tracking
LDO1 (VPOS) and LDO2 (VNEG) track each other in a way that they are of opposite sign but same magnitude.
The sum of VLDO1 and VLOD2 is guaranteed to be < 50 mV. To ensure proper tracking of the supplies the
VPOS_SET[2:0] bits of the VP_ADUST register must remain at the default setting of 010b. To adjust the VPOS
and VNEG output voltage, write to the VN_ADJUST register only and keep the VPOS_SET[2:0] bits of the
VP_ADUST register unchanged.
10.1.7 Fault Handling and Recovery
The TPS6518x and TPS65181xB monitor input and output voltages and die temperature and takes action if
operating conditions are outside normal limits. Whenever the TPS6518x and TPS65181xB encounter:
• Thermal shutdown (TSD)
• Positive boost undervoltage (VB_UV)
• Inverting buck-boost undervoltage (VN_UV)
• Input undervoltage lockout (UVLO)
it shuts down all power rails and enter STANDBY mode. Shutdown follows the reverse power-up sequence
defined by the PWR_SEQx registers. When a fault is detected, the PWR_GOOD and nINT pin are pulled low
and the corresponding interrupt bit is set in the interrupt register.
Whenever the TPS6518x and TPS65181xB encounter undervoltage on VNEG (VNEG_UV), VPOS (VPOS_UV),
VEE (VEE_UV) or VDDH (VDDH_UV) it shuts down the corresponding rail (plus any dependent rail) only and
remain in ACTIVE mode, allowing the DCDC converters to remain up. Again, the PWR_GOOD and nINT pins is
pulled low and the corresponding interrupt bit is set.
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Application Information (continued)
10.1.8 TPS65180 and TPS65180B Fault Handling
When a fault is detected, the TPS65180 and TPS65180B set the appropriate interrupt flags in the INT_STATUS1
and INT_STATUS2 registers and pull the INT pin low to signal an interrupt to the host processor. None of the
power rails can be re-enabled before the host has read the INT_STATUSx bits and the fault has been removed.
As the PWRx inputs are edge-sensitive, the host must also toggle the PWRx pins to re-enable the rails through
GPIO control, that is, it must bring the PWRx pins low before asserting them again.
10.1.9 TPS65181 and TPS65181B Fault Handling
The TPS65181 and TPS65181 do not require the host processor to access the INT_STATUS registers before reenabling the output rails. Rails can be re-enabled as soon as the fault condition has been removed. Again, as the
PWRx inputs are edge-sensitive, the host must also toggle the PWRx pins to re-enable the rails through GPIO
control, that is, it must bring the PWRx pins low before asserting them again.
10.1.10 Power-Good Pin
The power-good pin (PWR_GOOD) is an open-drain output that is pulled high when all four power rails (CP1,
CP2, LDO1, LDO2) are in regulation and is pulled low if any of the rails encounters a fault. PWR_GOOD remains
low if one of the rails is not enabled by the host and only after all rails are in regulation PWR_GOOD is released
to Hi-Z state (pulled up by external resistor).
10.1.11 Interrupt Pin
The interrupt pin (nINT) is an open-drain output that is pulled low whenever one or more of the INT_STATUS1 or
INT_STATUS2 bits are set. The nINT pin is released (returns to Hi-Z state) and fault bits are cleared when the
register with the set bit has been read by the host. If the fault persists, the INT_pin is pulled low again after a
maximum of 32 µs.
Interrupt events can be masked by re-setting the corresponding enable bit in the INT_ENABLE1 and
INT_ENABLE2 register, that is, the user can determine which events cause the nINT pin to be pulled low. The
status of the enable bits affects the nINT pin only and has no effect on any of the protection and monitoring
circuits or the INT_STATUSx bits themselves.
Note that persisting fault conditions such as thermal shutdown can cause the nINT pin to be pulled low for an
extended period of time which can keep the host in a loop trying to resolve the interrupt. If this behavior is not
desired, set the corresponding mask bit after receiving the interrupt and keep polling the INT_STATUSx register
to see when the fault condition has disappeared. After the fault is resolved, unmask the interrupt bit again.
10.1.12 Panel Temperature Monitoring
The TPS6518x and TPS65181xB provide circuitry to bias and measure an external negative temperature
coefficient resistor (NTC) to monitor device temperature in a range from –10°C to 85°C with and accuracy of
±1°C from 0°C to 50°C. The TPS65180 and TPS65180B require the host to trigger the temperature acquisition
through an I2C command whereas the TPS65181 and TPS65181B trigger the temperature acquisition
automatically once every 60 s.
10.1.13 NTC Bias Circuit
Figure 7 below shows the block diagram of the NTC bias and measurement circuit. The NTC is biased from an
internally generated 2.25-V reference voltage through an integrated 7.307-kΩ bias resistor. A 43-kΩ resistor is
connected parallel to the NTC to linearize the temperature response curve. The circuit is designed to work with a
nominal 10-kΩ NTC and achieves accuracy of ±1°C from 0°C to 50°C. The voltage drop across the NTC is
digitized by a 10-bit SAR ADC and translated into an 8-bit two’s complement by digital per Table 2.
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Application Information (continued)
Table 2. ADC Output Value vs Termperature
TEMPERATURE
TMST_VALUE[7:0]
< –10°C
1111 0110
–10°C
1111 0110
–9°C
1111 0111
...
...
–2°C
1111 1110
–1°C
1111 1111
0°C
0000 0000
1°C
0000 0001
2°C
0000 0010
...
...
25°C
0001 1001
...
85°C
0101 0101
> 85°C
0101 0101
2.25V
7.307 kW
10
Digital
10 bit ADC
43 kW
10 kW NTC
TPS6518x
Figure 7. NTC Bias and Measurement Circuit
10.1.14 TPS65180 and TPS65180B Temperature Acquisition
The TPS65180 and TPS65180B require the host to trigger the temperature acquisition before reading the
temperature value from register TMST_VALUE. A standard temperature measurement involves the following
steps:
1. The host sets the READ_THERM bit of the TMST_CONFIG register to 1. This enabled the NTC bias circuit
and internal ADC.
2. The analog to digital conversion is automatically started after a fixed 250-µs delay. While the conversion is in
progress the CONV_END bit of the TMST_CONFIG register is held low and returns to 1 after the conversion
result is available.
3. After the conversion is complete the READ_THERM bit is automatically reset, the EOC bit of the
INT_STATUS2 register is set, and the interrupt pin (nINT) is pulled low.
4. The host services the interrupt by reading the INT_STATUS2 register. This clears the interrupt pin (nINT pin
returns high). The host sees the EOC bit set and knows that the temperature data is available in the
TMST_VALUE register.
5. The host reads the temperature data from the TMST_VALUE register.
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10.1.15 TPS65181 and TPS65181B Temperature Acquisition
The TPS65181 and TPS65181B trigger temperature acquisition once every 60s to reduce the number of required
I2C writes. The host or display timing controller can read the temperature at any time by accessing the
TMST_VALUE register without having to set the READ_THERM bit first. However, the host can always trigger an
additional temperature reading the same way as for the TPS65180 and TPS65180B.
NOTE
At the end of each temperature acquisition, the EOC interrupt is set and an interrupt is
issued. Although the interrupt is automatically cleared, the nINT pin is pulled low for a
short amount of time (6 µs). To avoid seeing the EOS interrupt every 60s, TI recommends
to mask the EOC interrupt by setting the EOC_EN bit of the INT_ENABLE2 register to 0.
10.1.16 Overtemperature Reporting
The user has the option of setting HOT and COOL (not HOT) temperature thresholds as well as controlling
interrupt behavior as the NTC exceeds HOT and cools down below COOL (not-HOT) threshold.
By default, TPS6518x and TPS65181xB compare the temperature conversion result to the HOT threshold after
each conversion. If the NTC temperature is above the HOT threshold, the TMST_HOT bit in the INT_STATUS1
register is set to 1 and the interrupt pin (nINT) is pulled low. HOT temperature threshold is set by the host by
writing to the TMST_OS register and the HOT interrupt can be disabled by setting the HOT_EN bit of the
INT_ENABLE1 register to 0.
When the device has detected that the NTC is above the HOT threshold it compares subsequent temperature
acquisitions against the COOL threshold and pull the interrupt pin low when the NTC temperature drops below
the COOL threshold. However, the interrupt is issued only if the host has unmasked the COOL interrupt by
setting TMST_COOL_EN bit of INT_ENABLE1 register to 1. The COOL threshold is set by the host by writing to
the TMST_HYST register.
To use the full functionality of the HOT/COOL interrupts the following actions are required:
1. The host sets the HOT and COOL (not HOT) thresholds by writing the TMST_OS and TMST_HYST
registers.
2. (2) For TPS65180 and TPS65180B only: The host sets the READ_THERM bit of the TMST_CONFIG
register to 1. This initiates the temperature acquisition.
3. TPS6518x and TPS65181xB compare the result against the TMST_OS threshold and pulls the nINT pin low
if the NTC temperature exceeds the HOT threshold.
4. If the TPS6518x and TPS65181xB report a HOT condition, the host unmasks the TMST_COOL_EN bit by
setting it to 1 (INT_ENABLE1 register).
5. The host initiates a new temperature conversion by setting the READ_THERM bit of the TMST_CONFIG
register to 1. If the new temperature is still above the HOT threshold, a new HOT interrupt is issued. If the
temperature is below HOT but above COOL threshold, no interrupt is issued (except for EOC which is issued
at the end of each conversion). If the temperature is below COOL threshold, a COOL interrupt is issued.
6. After the temperature drops below the COOL threshold the host must set the TMST_COOL_EN bit in the
INT_ENABLE1 register to 0 to mask additional COOL interrupts after subsequent temperature acquisitions.
10.1.17 Overtemperature Fault Queuing
The user can specify the number of consecutive HOT temperature reads required to issue a HOT interrupt. The
user can set the FAULT_QUE[1:0] bits of the TMST_CONFIG register to specify 1, 2, 4, or 6 consecutive reads
that all must be above the HOT threshold before a HOT interrupt is issued. The fault queue is reset each time
the acquired temperature drops below the HOT threshold and can also be reset by the host by setting the
FAULT_QUE_CLR bit 1. Only if the specified number of readings have been detected which all need to be above
the HOT threshold, a HOT interrupt is issued. This function is useful to reduce noise in the temperature
measurements.
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10.1.18 TPS65181 and TPS65181B Temperature Sensor
The TPS65181 and TPS65181B automates the temperature monitoring process and is specifically designed to
operate in multi-host systems where one of the I2C hosts, for eaxmple, the display controller, has limited I2C
capability. Standard I2C protocol requires the following steps to read data from a register:
1. Send device and register address, R/nW bit set low (write command).
2. Send device address, R/nW set high (read command).
3. The slave responds with data from the specified register address.
Some display controllers support I2C read commands only and need to access the temperature data from the
TPS65181 and TPS65181B TMST_VALUE register. To support these systems the TPS65181 and TPS65181B
automatically trigger temperature acquisition every 60s (for other acquisition intervals contact the factory) and
stores the result in TMST_VALUE register. With the FIX_RD_PTR bit in the FIX_RD_POINTER register set to 1
the device responds to any I2C read command with data from the TMST_VALUE register. No write command
with the register address is required and address auto increment feature is disabled in this mode. Therefore
reading the temperature data is reduced to two steps:
1. Send device address, R/nW set high (read command).
2. Read the data from the slave. The slave responds with data from TMST_VALUE register address.
Write functionality is not affected by the FIX_RD_PTR bit and the main controller in the system maintains full
control of the PMIC. Interrupts and error flags are issued and need to be handled the same way as for the
TPS65180 and TPS65180B with two exceptions:
1. The FIX_RD_PTR bit in the FIX_RD_POINTER register needs to be set to 0 before the main controller can
read any register different from the TMST_VALUE register.
2. Thermal shutdown (TSD), positive boost undervoltage (VB_UV), inverting buck-boost undervoltage (VN_UV),
and input undervoltage lockout (UVLO) interrupt bits do not have to be cleared before output rails can be reenabled.
At system power-up the main processor sets up the PMIC by accessing the I2C registers and setting the control
parameters as needed. When the system is set up correctly, the main controller sets the FIX_READ_POINTER
bit and the display controller can start accessing the temperature information. During normal operation the main
controller can write to the PMIC at any time but before it can read access registers the FIX_READ_POINTER bit
must be written 0.
The temperature range and representation of the temperature data is the same between the TPS65180 and
TPS65180B or the TPS65181 and TPS65181B.
10.1.19 I2C Bus Operation
The TPS6518x and TPS65181xB host a slave I2C interface that supports data rates up to 400 kbps and autoincrement addressing and is compliant to I2C standard 3.0.
Slave Address + R/nW
Sub Address
S
A6 A5 A4 A3 A2 A1 A0
S
Start Condition
A
Acknowledge
A6 ... A0 Device Address
Read / not Write
P
Stop Condition
S7 ... S0 Sub-Address
R/nW
R/nW
A
S7 S6 S5 S4 S3 S2 S1 S0
Data
A
D7 D6 D5 D4 D3 D2 D1 D0
A
P
D7 ... D0 Data
Figure 8. Subaddress in I2C Transmission
Start – Start condition
ACK – Acknowledge
G(3:0) – Group ID: Address fixed at 1001.
S(7:0) – Subaddress: defined per register map.
A(2:0) – Device Address: Address fixed at 000.
D(7:0) – Data; Data to be loaded into the device.
R/nW – Read / not Write Select Bit
Stop – Stop condition
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The I2C Bus is a communications link between a controller and a series of slave terminals. The link is established
using a two-wired bus consisting of a serial clock signal (SCL) and a serial data signal (SDA). The serial clock is
sourced from the controller in all cases where the serial data line is bidirectional for data communication between
the controller and the slave terminals. Each device has an open-drain output to transmit data on the serial data
line. An external pullup resistor must be placed on the serial data line to pull the drain output high during data
transmission.
Data transmission is initiated with a start bit from the controller as shown in Figure 10. The start condition is
recognized when the SDA line transitions from high to low during the high portion of the SCL signal. Upon
reception of a start bit, the device receives serial data on the SDA input and check for valid address and control
information. If the appropriate group and address bits are set for the device, then the device issues an
acknowledge pulse and prepare the receive subaddress data. Subaddress data is decoded and responded to as
per the Register Maps section of this document. Data transmission is completed by either the reception of a stop
condition or the reception of the data word sent to the device. A stop condition is recognized as a low to high
transition of the SDA input during the high portion of the SCL signal. All other transitions of the SDA line must
occur during the low portion of the SCL signal. An acknowledge is issued after the reception of valid address,
sub-address and data words. The I2C interface auto-sequences through register addresses, so that multiple data
words can be sent for a given I2C transmission. Reference Figure 10.
NOTE
Auto-increment is not supported when the FIX_RD_PTR bit is set (TPS65181/TPS65181B
only).
S
SLAVE ADDRESS
W A
SUB ADDRESS
A S
SLAVE ADDRESS
R A
DATA SUBADDR +n
A
DATA SUBADDR
A
DATA SUBADDR +n+1
Ā P
n bytes + ACK
S
SLAVE ADDRESS
R A
DATA 0
A
DATA 0
A
DATA 0
Ā P
n bytes + ACK
From master to slave
R Read
S Start
Ā Not Acknowlege
From slave to master
W Write (not read)
P Stop
A Acknowlege
A.
Top: Standard I2C READ data transmission with address auto-increment.
Bottom: I2C READ data transmission with FIX_RD_PTR bit set for EPSON Broadsheet support.
Only address 0x00h can be read. FIX_RD_PTR bit has no impact on WRITE transaction.
Figure 9. Standard I2C READ Data Transmission With Address Auto-Increment or With FIX_RD_PTR Bit
Set for Epson Broadsheet Support
SDA
SCL
1-7
8
9
1-7
8
9
1-7
8
9
S
START
P
ADDRESS
R/W
ACK
DATA
ACK
DATA
ACK/
nACK
STOP
Figure 10. I2C Start, Stop, and Acknowledge Protocol
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SDA
tf
tLOW
tr
tSU;DAT
tHD;STA
tSP
tr
tBUF
SCL
tHD;STA
S
tSU;STA
tHD;DAT tHIGH
tSU;STO
Sr
tf
P
S
Figure 11. I2C Data Transmission Timing
10.2 Typical Application
VIN
From Input Supply
(3.0 V-6.0 V)
TS
VDDH_D
POSITIVE
CHARGE
PUMP
TEMP
SENSOR
VN_SW
VN
LDO1
VDDH_DRV
VDDH_FB
VPOS
DCDC2
VCOM
VCOM
VB_SW
From Input Supply
(3.0 V-6.0 V)
VB
VCOM_PANEL
DCDC1
LDO2
I/O Control
NEGATIVE
CHARGE
PUMP
VCOM
VNEG
VEE_D
VEE_DRV
VEE_FB
Figure 12. Typical Application
10.2.1 Design Requirements
For this design example, use the parameters listed in Table 3.
Table 3. Design Parameters
VOLTAGE
SEQUENCE (STROBE)
VNEG (LDO2)
–15 V
1
VEE (Charge pump 2)
–20 V
2
VPOS (LDO1)
15 V
3
VDDH (charge pump 1)
22 V
4
10.2.2 Detailed Design Procedure
For the positive boost regulator (DCDC1) a 10-µF capacitor can be used as the input capacitor value; two 4.7-µF
capacitor are used as output capacitors to reduce ESR along with a 2.2-µH inductor. For the inverting buck-boost
regulator (DCDC2) an 10-µF capacitor can be used at the input capacitor value; A 10-µF and 4.7-µF capacitor
are used as output capacitors to reduce ESR, with a 4.7-µH inductor. Capacitor ESR for all capacitors should be
around 20 mΩ, and ceramic X5R material. These are the typical the values used, additional inductor and
capacitor values can be used for improved functionality, but the parts should be rated the same as the
recommended external components listed in Table 4.
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Table 4. Recommended External Components
PART NUMBER
VALUE
SIZE
MANUFACTURER
LQH44PN4R7MP0
4.7 µH
4.00 mm × 4.00 mm × 1.65 mm
Murata
VLS252012T-2R2M1R3
2.2 µH
2.00 mm × 2.50 mm × 1.20 mm
TDK
GRM21BC81E475KA12L
4.7-µF, 25-V, X6S
805
Murata
GRM32ER71H475KA88L
4.7-µF, 50-V, X7R
1210
Murata
INDUCTORS
CAPACITORS
All other caps
X5R or better
DIODES
BAS3010
SOD-323
Infineon
MBR130T1
SOD-123
ON-Semi
603
Murata
THERMISTOR
NCP18XH103F03RB
10 kΩ
10.2.3 Application Curves
0.1
±14.94
0.0
Load Regulation (%)
±14.92
VNEG (V)
±14.96
±14.98
±15.00
±15.02
±0.1
±0.2
±0.3
±0.4
±0.5
±15.04
±0.6
±15.06
±20
0
20
40
60
80
100
120
140
Load Current (mA)
±20
160
0
20
40
60
80
100
120
140
Load Current (mA)
C003
160
C004
Figure 14. Load Current vs Load Regulation
Figure 13. Load Current vs VNEG
0.05
15.03
15.02
Load Regulation (%)
VPOS (V)
15.01
15.00
14.99
14.98
14.97
±0.05
±0.15
±0.25
14.96
14.95
±0.35
±20
0
20
40
60
80
100
120
140
Load Current (mA)
Figure 15. Load Current vs VPOS
160
C005
±20
0
20
40
60
80
100
120
140
Load Current (mA)
160
C006
Figure 16. Load Current vs Load Regulation
11 Power Supply Recommendations
The device is designed to operate with an input voltage supply range from 3 V to 6 V. This input supply can be
from a externally regulated supply. If the input supply is located more than a few inches from the TPS6518x and
TPS65181xB, additional bulk capacitance may be required in addition to the ceramic bypass capacitors. An
electrolytic capacitor with a value of 10 μF is a typical choice.
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12 Layout
12.1 Layout Guidelines
The layout guidelines are listed as follows.
• PBKG die substrate must connect to VN (–16 V) with short, wide trace. Wide copper trace improves heat
dissipation.
• The PowerPAD is internally connected to PBKG and must be connected to ground, but connected to VN with
a short, wide copper trace.
• Inductor traces must be kept on the PCB top layer free of any vias.
• Feedback traces must be routed away from any potential noise source to avoid coupling.
• Output caps must be placed immediately at output pin.
• VIN pins must be bypassed to ground with low-ESR ceramic bypass capacitors.
12.2 Layout Example
Inductor Trace
Top Layer of
PCB
Figure 17. Layout Top Layer
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TPS65180, TPS65181, TPS65180B, TPS65181B
SLVSA76G – MARCH 2010 – REVISED JANUARY 2016
www.ti.com
Layout Example (continued)
TPS6518x
Thermal Pad
Bottom Layer
VN connection
Figure 18. Layout Bottom Layer
44
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Copyright © 2010–2016, Texas Instruments Incorporated
Product Folder Links: TPS65180 TPS65181 TPS65180B TPS65181B
TPS65180, TPS65181, TPS65180B, TPS65181B
www.ti.com
SLVSA76G – MARCH 2010 – REVISED JANUARY 2016
13 Device and Documentation Support
13.1 Device Support
13.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
13.2 Documentation Support
13.2.1 Related Documentation
For related documentation, see the following:
• Basic Calculation of a Boost Converter's Power Stage, SLVA372
• Basic Calculation of a Buck Converter's Power Stage, SLVA477
13.3 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 5. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
TPS65180
Click here
Click here
Click here
Click here
Click here
TPS65181
Click here
Click here
Click here
Click here
Click here
TPS65180B
Click here
Click here
Click here
Click here
Click here
TPS65181B
Click here
Click here
Click here
Click here
Click here
13.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
13.5 Trademarks
OMAP, E2E are trademarks of Texas Instruments.
Vizplex is a trademark of E Ink Corporation.
E Ink is a registered trademark of E Ink Corporation.
EPSON is a registered trademark of Seiko Epson Corporation.
All other trademarks are the property of their respective owners.
13.6 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Copyright © 2010–2016, Texas Instruments Incorporated
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Product Folder Links: TPS65180 TPS65181 TPS65180B TPS65181B
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TPS65180, TPS65181, TPS65180B, TPS65181B
SLVSA76G – MARCH 2010 – REVISED JANUARY 2016
www.ti.com
13.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
46
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Copyright © 2010–2016, Texas Instruments Incorporated
Product Folder Links: TPS65180 TPS65181 TPS65180B TPS65181B
PACKAGE OPTION ADDENDUM
www.ti.com
23-Oct-2015
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TPS65180BRGZR
ACTIVE
VQFN
RGZ
48
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-10 to 85
E INK
TPS65180B
TPS65180BRGZT
ACTIVE
VQFN
RGZ
48
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-10 to 85
E INK
TPS65180B
TPS65180RGZR
NRND
VQFN
RGZ
48
TBD
Call TI
Call TI
-10 to 85
E INK
TPS65180
TPS65180RGZT
NRND
VQFN
RGZ
48
TBD
Call TI
Call TI
-10 to 85
E INK
TPS65180
TPS65181BRGZR
ACTIVE
VQFN
RGZ
48
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-10 to 85
E INK
TPS65181B
TPS65181BRGZT
ACTIVE
VQFN
RGZ
48
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-10 to 85
E INK
TPS65181B
TPS65181RGZR
NRND
VQFN
RGZ
48
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-10 to 85
E INK
TPS65181
TPS65181RGZT
NRND
VQFN
RGZ
48
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-10 to 85
E INK
TPS65181
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
(4)
23-Oct-2015
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Oct-2015
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
TPS65180BRGZR
VQFN
RGZ
48
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
2500
330.0
16.4
7.3
7.3
1.1
12.0
16.0
Q2
TPS65180BRGZT
VQFN
RGZ
48
250
180.0
16.4
7.3
7.3
1.1
12.0
16.0
Q2
TPS65181BRGZR
VQFN
RGZ
48
2500
330.0
16.4
7.3
7.3
1.1
12.0
16.0
Q2
TPS65181BRGZT
VQFN
RGZ
48
250
180.0
16.4
7.3
7.3
1.1
12.0
16.0
Q2
TPS65181RGZR
VQFN
RGZ
48
2500
330.0
16.4
7.3
7.3
1.1
12.0
16.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Oct-2015
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPS65180BRGZR
VQFN
RGZ
48
2500
367.0
367.0
38.0
TPS65180BRGZT
VQFN
RGZ
48
250
210.0
185.0
35.0
TPS65181BRGZR
VQFN
RGZ
48
2500
367.0
367.0
38.0
TPS65181BRGZT
VQFN
RGZ
48
250
210.0
185.0
35.0
TPS65181RGZR
VQFN
RGZ
48
2500
367.0
367.0
38.0
Pack Materials-Page 2
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TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
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