TPS65235-1
SLVSDP1E – JANUARY 2017 – REVISED MAY 2021
TPS65235-1 LNB Voltage Regulator With I2C Interface
1 Features
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Complete integrated solution for LNB and I2C
interface
DiSEqC 2.x, and DiSEqC 1.x compatible
Supports 5-V, 12-V, and 15-V power rail
Up to 1000-mA accurate output current limit
adjustable by external resistor
Boost switch peak current limit proportional to LDO
current limit
Boost converter with 140-mΩ low Rds(on) internal
power switch
Boost switching frequency 1-MHz or 500-kHz
selectable
Audible noise avoided at force PWM mode
Dedicated enable pin for non-I2C application
Low-dropout (LDO) regulator with push-pull output
stage for VLNB output
Built-in accurate 22-kHz tone generator and
external tone input support
Supports both external 44-kHz and 22-kHz tone
input
Adjustable soft start and 13-V to 18-V voltage
transition time
650-mV to 750-mV 22-kHz tone amplitude
selection
I2C registers accessible with EN low
Short circuit dynamic protection
Diagnostics for output voltage level, DiSEqC
tone input and output, current level, and cable
connection
Thermal protection available
20-pin WQFN 3-mm × 3-mm (RUK) package
3 Description
Designed for analog and digital satellite receivers,
the TPS65235-1 is a monolithic voltage regulator
with I2C interface; specifically to provide the 13-V to
18-V power supply and the 22-kHz tone signal to
the LNB down converter in the antenna dish or to
the multi-switch box. The device offers a complete
solution with minimum component count, low power
dissipation together with simple design and I2C
standard interface.
The TPS65235-1 features high power efficiency. The
boost converter integrates a 140-mΩ power MOSFET
running at 1 MHz or 500 kHz selectable switching
frequency. Drop out voltage at the linear regulator
is 0.8 V to minimize power loss. The TPS65235-1
provides multiple ways to generate the 22 kHz signal.
Integrated linear regulator with push-pull output stage
generates 22-kHz tone signal superimposed at the
output even at zero loading. Current limit of linear
regulator can be programmed by external resistor with
±10% accuracy. Full range of diagnostic read by I2C is
available for system monitoring.
The TPS65235-1 has a special design at FCCM mode
to avoid the audible noise especially when VIN is
higher or closer to the VLNB output.
The TPS65235-1 supports advanced DiSEqC 2.x
standard with 22-kHz tone detection circuit and output
interface.
Device Information(1)
PART NUMBER
2 Applications
TPS65235-1
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(1)
Set top box satellite receiver
TV satellite receiver
PC card satellite receiver
Satellite TV
PACKAGE
BODY SIZE (NOM)
WQFN
3.00 mm × 3.00 mm
For all available packages, see the orderable addendum at
the end of the data sheet.
TPS65235-1
100 nF
VOUT
VLNB
0.1 PF
VCP
ISET
BOOST
2×
22 PF
110 k
PGND
TCAP
22 nF
AGND
10 PH
VIN
LX
VCC
VIN
10 PF
1 PF
1 PF
Simplified Schematic
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS65235-1
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Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................4
6.4 Thermal Information....................................................4
6.5 Electrical Characteristics.............................................5
6.6 Timing Requirements.................................................. 7
6.7 Typical Characteristics................................................ 8
7 Detailed Description........................................................9
7.1 Overview..................................................................... 9
7.2 Functional Block Diagram........................................... 9
7.3 Feature Description.....................................................9
7.4 Device Functional Modes..........................................18
7.5 Programming............................................................ 19
7.6 Register Maps...........................................................21
8 Application and Implementation.................................. 24
8.1 Application Information............................................. 24
8.2 Typical Application.................................................... 24
9 Power Supply Recommendations................................30
10 Layout...........................................................................31
10.1 Layout Guidelines................................................... 31
10.2 Layout Example...................................................... 31
11 Device and Documentation Support..........................32
11.1 Device Support........................................................32
11.2 Documentation Support.......................................... 32
11.3 Receiving Notification of Documentation Updates.. 32
11.4 Support Resources................................................. 32
11.5 Trademarks............................................................. 32
11.6 Electrostatic Discharge Caution.............................. 32
11.7 Glossary.................................................................. 32
12 Mechanical, Packaging, and Orderable
Information.................................................................... 33
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision D (July 2019) to Revision E (May 2021)
Page
• Updated the numbering format for tables, figures, and cross-references throughout the document. ................1
• Changed V(drop) min and max values..................................................................................................................5
• Changed I(rev_dis) min and max values................................................................................................................5
Changes from Revision C (July 2018) to Revision D (July 2019)
Page
• Changed V(drop) at TONEAMP = 0b From: MIN = 0.44 TYP = 0.7 MAX = 1 To: MIN = 0.49 TYP = 0.8 MAX =
1.1 in the Electrical Characteristics ....................................................................................................................5
• Changed V(drop) at TONEAMP = 1b From: MIN = 0.55 TYP = 0.8 MAX = 1.12 To: MIN = 0.65 TYP = 0.9 MAX
= 1.2 in the Electrical Characteristics .................................................................................................................5
Changes from Revision B (June 2018) to Revision C (July 2018)
Page
• Changed the GDR TONE_TRANS = 1b value From: MAX = 24.03V To: MAX = 24.33V in the Electrical
Characteristics ................................................................................................................................................... 5
Changes from Revision A (January 2017) to Revision B (December 2017)
Page
• Changed bit 4 (T125) in Table 7-8 From: 0b = Die temperature > 125°C To: 0b = Die temperature > 125°C
and From: 1b = Die temperature < 125°C To: 1b = Die temperature > 125°C..................................................23
Changes from Revision * (January 2017) to Revision A (December 2017)
Page
• Changed the VCP values From: VLNB to 7 V To: –0.3 V to 7 V in the Absolute Maximum Ratings ................. 4
• Changed the GDR values From: VLNB to VCP To: –0.3 V to 7 Vin the Absolute Maximum Ratings ............... 4
• Changed the A(tone) TONEAMP = 0b values From: MIN = 667 TYP = 700 MAX = 746 To: MIN = 617 TYP =
650 MAX = 696 in the Electrical Characteristics ................................................................................................5
• Changed the A(tone) TONEAMP = 1b values From: MIN = 753 TYP = 800 MAX = 853 To: MIN = 703 TYP =
750 MAX = 803 in the Electrical Characteristics ................................................................................................5
2
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DIN
DOUT
EXTM
SCL
SDA
15
14
13
12
11
5 Pin Configuration and Functions
VLNB
16
10
VCTRL
VCP
17
9
ADDR
BOOST
18
8
FAULT
Thermal
Pad
4
5
TCAP
ISET
AGND
6
3
20
VCC
PGND
2
EN
VIN
7
1
19
LX
GDR
Not to scale
Figure 5-1. RUK Package 20-Pin WQFN With Exposed Thermal Pad Top View
Table 5-1. Pin Functions
PIN
NO.
NAME
TYPE(1)
DESCRIPTION
1
LX
I
Switching node of the boost converter
2
VIN
S
Input of internal linear regulator
3
VCC
O
Internal 6.3-V power supply. Connect a 1-μF ceramic capacitor from this pin to ground. When VIN is 5 V,
connect the VCC pin to the VIN pin.
4
AGND
S
Analog ground. Connect all ground pins and power pad together.
5
TCAP
O
Connect a capacitor to this pin to set the rise time of the LNB output.
6
ISET
O
Connect a resistor to this pin to set the LNB output current limit.
7
EN
I
Enable this pin to enable the VLNB output. pull this pin to ground to disable the output. The output is then
pulled to ground, and, when the EN pin is low, the I2C interface can be accessed.
8
FAULT
O
Open drain output pin, it goes low if any fault flag is set.
9
ADDR
I
Connect a different resistor to this pin to set different I2C addresses (see the Table 7-4 table).
10
VCTRL
I
Voltage level at this pin to set the output voltage (see the Table 7-3).
11
SDA
I/O
12
SCL
I
I2C compatible clock input
13
EXTM
I
External modulation logic input pin that activates the 22-kHz tone output. The feeding signal can be
22-kHz tone or logic high or low.
14
DOUT
O
Tone detection output
15
DIN
I
Tone detection input
16
VLNB
O
Output of the power supply connected to satellite receiver or switch
I2C compatible bidirectional data
17
VCP
O
Gate drive supply voltage and output of charge pump. Connect a capacitor between this pin and the VLNB
pin.
18
BOOST
O
Output of the boost regulator and Input voltage of the internal linear regulator
19
GDR
O
Control the gate of the external MOSFET for DiSEqc 2.x support
20
PGND
S
Power ground for the boost converter
—
Thermal Pad
—
The thermal pad must be soldered to the printed circuit board (PCB) for optimal thermal performance. Use
thermal vias on the PCB to enhance power dissipation.
(1)
I = input, O = output, I/O = input and output, S = power supply
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
1
30
VCP, GDR (referenced to VLNB pin)
–0.3
7
VCC, EN, ADDR, FAULT, SCL, SDA, VCTRL, EXTM, DOUT, DIN,
TCAP
–0.3
7
ISET
–0.3
3.6
PGND
–0.3
0.3
VIN, LX, BOOST, VLNB
Voltage
Operating junction temperature, TJ
–40
150
Storage temperature, Tstg
–55
150
(1)
UNIT
V
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic
discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC
JS-001(1)
±4000
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
UNIT
V
±1500
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
VIN
Input operating voltage
4.5
20
V
TA
Operating junction temperature
–40
125
°C
6.4 Thermal Information
TPS65235-1
THERMAL METRIC(1)
RUK (WQFN)
UNIT
20 PINS
RθJA
Junction-to-ambient thermal resistance
44.8
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
47.3
°C/W
RθJB
Junction-to-board thermal resistance
16.5
°C/W
ψJT
Junction-to-top characterization parameter
0.5
°C/W
ψJB
Junction-to-board characterization parameter
16.4
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
3.6
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Electrical Characteristics
–40°C ≤ TJ ≤ 125°C, VIN = 12 V, fSW = 1 MHz (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INPUT SUPPLY
VIN
Input voltage range
IDD(SDN)
Shutdown supply current
EN = 0b
ILDO(Q)
LDO quiescent current
EN = 1b, IO = 0 A, VVLNB = 18.2 V
UVLO
VIN undervoltage lockout
4.5
12
20
V
90
120
150
µA
mA
1.5
5
8.5
VIN rising
4.15
4.3
4.45
V
Hysteresis
280
480
550
mV
V(ctrl) = 1, IO = 500 mA
18
18.2
18.4
V
V(ctrl) = 0, IO = 500 mA
13.25
13.4
13.55
V
SCL = 1b, V(ctrl) = 1, IO = 500 mA (Non
I2C)
19.18
19.4
19.62
V
SCL = 1b, V(ctrl) = 0, IO = 500 mA (Non
I2C)
14.44
14.6
14.76
V
R(SET) = 200 kΩ, Full temperature
580
650
720
OUTPUT VOLTAGE
VOUT
Regulated output voltage
mA
I(OCP)
Output short circuit current limit
TJ = 25°C
629
650
688
mA
fSW
Boost switching frequency
f = 1 MHz
977
1060
1134
kHz
I(limitsw) (1)
Switching current limit
VIN = 12 V, VOUT = 18.2 V, R(SET) = 200
kΩ
Rds(on)_LS
On resistance of low side FET
VIN = 12 V
V(drop)
Linear regulator voltage dropout
I(cable)
Cable good detection current threshold
3
A
90
140
210
mΩ
IO = 500 mA, TONEAMP = 0b
0.44
0.8
1.15
V
IO = 500 mA, TONEAMP = 1b
0.55
0.9
1.2
V
0.9
5
8.8
mA
VIN = 12 V, VOUT = 13.4 V or 18.2 V
I(rev)
Reverse bias current
EN = 1b, VVLNB = 21 V
49
58
65
mA
I(rev_dis)
Disabled reverse bias current
EN = 0b, VVLNB = 21 V
2.9
4.6
6.3
mA
0.8
V
LOGIC SIGNALS
Enable threshold (V(EN)), high
1.6
V
Enable threshold (V(EN)), low
V(EN) = 1.5 V
5
6
7
µA
V(EN) = 1 V
2
3
4
µA
I(EN)
Enable internal pullup current
V(VCTRL_H)
VCTRL logic threshold level for high-level
input voltage
V(VCTRL_L)
VCTRL logic threshold level for low-level
input voltage
V(EXTM_H)
EXTM logic threshold level for high-level
input voltage
V(EXTM_L)
EXTM logic threshold level for low-level
input voltage
VOL(FAULT)
FAULT output low voltage
FAULT open drain, IOL = 1 mA
Tone frequency
22-kHz tone output
2
V
0.8
2
V
V
0.8
V
0.4
V
TONE
f(tone)
A(tone)
D(tone)
f(EXTM)
Tone amplitude
20
22
24
kHz
0 mA ≤ IO ≤ 500 mA, CO = 100 nF,
TONEAMP = 0b
617
650
696
mV
0 mA ≤ IO ≤ 500 mA, CO = 100 nF,
TONEAMP = 1b
703
750
803
mV
Tone duty cycle
External tone input frequency range
45%
50%
55%
22-kHz tone output
17.6
22
26.4
kHz
44-kHz tone output
35.2
44
52.8
kHz
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–40°C ≤ TJ ≤ 125°C, VIN = 12 V, fSW = 1 MHz (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
22
26.4
kHz
TONE DETECTION
f(DIN)
Tone detector frequency capture range
0.4-VPP sine wave
17.6
V(DIN)
Tone detector input amplitude
Sine wave, 22 kHz
0.3
V(DOUT)
DOUT output voltage
Tone present, Iload = 2 mA
GDR
Bypass FET gate voltage, LNB
1.5
V
0.4
V
TONE_TRANS = 1b, V(LNB) = 18.2 V
23.11
23.5
24.33
V
TONE_TRANS = 0b, V(LNB) = 18.2 V
18.17
18.2
18.23
V
THERMAL SHUT-DOWN (JUNCTION TEMPERATURE)
T(TRIP)
Thermal protection trip point
T(HYST)
Thermal protection hysteresis
Temperature rising
160
°C
20
°C
I2C READ BACK FAULT STATUS
Feedback voltage UVP low
V(PGOOD)
T(warn)
PGOOD trip levels
94%
96%
97.1%
Feedback voltage UVP high
93%
94.5%
95.5%
Feedback voltage OVP high
104%
106.6%
108%
Feedback voltage OVP low
102%
104.6%
106%
Temperature warning threshold
125
°C
I2C INTERFACE
VIH
SDA,SCL input high voltage
VIL
SDA,SCL input low voltage
II
Input current
SDA, SCL, 0.4 V ≤ VI ≤ 4.5 V
VOL
SDA output low voltage
SDA open drain, IOL = 2 mA
f(SCL)
Maximum SCL clock frequency
(1)
6
2
–10
V
0.8
V
10
µA
0.4
400
V
kHz
Specified by design
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6.6 Timing Requirements
MIN
NOM
75
102
MAX
UNIT
OUTPUT VOLTAGE
tr, tf
13-V to 18-V transition rising falling time
tON(min)
Minimum on time for the Low side FET
C(TCAP) = 22 nF
2
ms
130
ns
TONE
Tone rise time
0 mA ≤ IO ≤ 500 mA, CO = 100 nF,
Control Reg1[0] = 0b
tr(tone)
0 mA ≤ IO ≤ 500 mA, CO = 100 nF,
Control Reg1[0] = 1b, and EXTM has
44-kHz input
Tone fall time
0 mA ≤ IO ≤ 500 mA, CO = 100 nF,
Control Reg1[0] = 0b
tf(tone)
0 mA ≤ IO ≤ 500 mA, CO = 100 nF,
Control Reg1[0] = 1b, and EXTM has
44 kHz input
11
µs
5.5
µs
10.8
µs
5.4
µs
OVERCURRENT PROTECTION
tON
Overcurrent protection ON time
TIMER = 0b
2.3
3.75
5.52
ms
tOFF
Overcurrent protection OFF time
TIMER = 0b
98.5
118
133.5
ms
I2C INTERFACE
tBUF
Bus free time between a STOP and START
condition
1.3
µs
tHD_STA
Hold time (repeated) START condition
0.6
µs
tSU_STO
Setup time for STOP condition
0.6
µs
tLOW
LOW period of the SCL clock
1
µs
tHIGH
HIGH period of the SCL clock
0.6
µs
tSU_STA
Setup time for a repeated START condition
0.6
µs
tSU_DAT
Data setup time
0.1
µs
tHD_DAT
Data hold time
tRCL
Rise time of SCL signal
Capacitance of one bus line (pF)
tRCL1
Rise time of SCL Signal after a Repeated START
condition and after an acknowledge BIT
Capacitance of one bus line (pF)
0
0.9
µs
20 + 0.1 CB
300
ns
20 + 0.1 CB
300
ns
tFCL
Fall time of SCL signal
Capacitance of one bus line (pF)
20 + 0.1 CB
300
ns
tRDA
Rise time of SDA signal
Capacitance of one bus line (pF)
20 + 0.1 CB
300
ns
tFDA
Fall time of SDA signal
Capacitance of one bus line (pF)
20 + 0.1 CB
300
ns
CB
Capacitance of one bus line(SCL and SDA)
400
pF
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6.7 Typical Characteristics
TA = 25°C, VIN = 12 V, fSW = 1 MHz, CBoost = (2 × 22 µF / 35 V) (unless otherwise noted)
95%
13.45
13.44
90%
13.43
Output Voltage (V)
Efficiency
85%
80%
75%
70%
13.42
13.41
13.4
13.39
13.38
13.37
65%
13.36
V(LNB) = 13.4 V
V(LNB) = 18.2 V
13.35
60%
0
0.1
0.2
0.3
0.4 0.5 0.6 0.7
Output Current (A)
0.8
0.9
0
1
D001
0.4 0.5 0.6 0.7
Output Current (A)
0.8
0.9
1
D002
7
18.3
18.28
6.5
IDD Quiesent Current (mA)
18.26
Output Voltage (V)
0.3
Figure 6-2. Load Regulation
Figure 6-1. Power Efficiency
18.24
18.22
18.2
18.18
18.16
18.14
18.12
6
5.5
5
4.5
4
3.5
18.1
0
0.1
0.2
0.3
0.4 0.5 0.6 0.7
Output Current (A)
0.8
0.9
3
-40
1
0
20
40
60
80
100
Junction Temperature (qC)
120
140
D004
Figure 6-4. Input Supply Quiescent Current vs
Junction Temperature
Figure 6-3. Load Regulation
680
130
670
IDD Current Limit (mA)
135
125
120
115
110
105
-40
-20
D003
VVLNB =18.2 V
IDD Shutdown Current (mA)
0.2
VVLNB = 13.4 V
L = 4.7 µH
660
650
640
630
-20
0
20
40
60
80
100
Junction Temperature (qC)
120
140
Figure 6-5. Shutdown Current vs Junction
Temperature
8
0.1
620
-40
-20
D005
0
20
40
60
80
100
Junction Temperature (qC)
120
140
D006
ILOAD = 650 mA
Figure 6-6. LNB Current Limit vs Junction
Temperature
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7 Detailed Description
7.1 Overview
The TPS65235-1 device is the power management IC (PMIC) that integrates a boost converter, an LDO
regulator, and a 22-kHz tone generator to serve as a LNB power supply. This solution compiles the DiSEqC
2.x standard with or without I2C interface. An external resistor allows for precise programming of the output
current limit. The 22-kHz tone signal can be generated in one of two ways, either with or without I2C. The
integrated boost features low Rds(on) MOSFET and internal compensation. A selectable switching frequency of 1
MHz or 500 kHz is designed to reduce the size of passive components and be flexible for design.
The TPS65235-1 device can support the 44-kHz tone output. When the EXTM pin has a 44-kHz tone input,
and the EXTM TONE bit in the Control Register 1 is set to 1b, the LNB tone output is 44 kHz. By default, the
TPS65235-1 device has a typical 22-kHz tone output.
LX
VIN
7.2 Functional Block Diagram
EN
REF_Boost
VCC
Internal Regulator
PWM Controller
PGND
REF_Boost
TCAP
BOOST
REF
VCTRL
VCP
Charge Pump
VLNB
REF_LDO
I2C Interface
I2C EN
EN
Tone
Generator
VLNB
OCP
Fault Diagnose
OTP
Tone_Auto
Tone_Trans
EXTM
GDR
Logic
ISET
EXTM
AGND
FAULT
VLNB
PGOOD
Tone
Det
DIN
DOUT
ADDR
VCP
SDA
SCL
7.3 Feature Description
7.3.1 Boost Converter
The TPS65235-1 device has an internal compensated boost converter and low-dropout (LDO) linear regulator.
The boost converter tracks the LNB output voltage within 800 mV even at loading 1000 mA, which minimizes
power loss.
The boost converter operates at 1 MHz by default. The TPS65235-1 device has internal cycle-by-cycle peak
current limit in the boost converter and DC current limit in the LNB output to help protect the device from short
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circuits and over loading. When the LNB output is shorted to ground, the LNB output current is clamped at the
LDO current limit. The LDO current limit is set by the external resistor at the ISET pin. The current limit of the
boost switch is proportional to the LDO current limit. If an overcurrent condition occurs for more than 4 ms, the
boost converter enters hiccup mode and retries startup in 128 ms. This hiccup mode ON time and OFF time are
selectable through the I2C control register (address 0x01) to be either 4 ms and 128 ms or 8 ms and 256 ms,
respectively. At extremely light loads, the boost converter automatically operates in a pulse-skipping mode.
The boost converter is stable with either ceramic capacitor or electrolytic capacitor.
If two or more set-top box LNB outputs are connected together, one output voltage can be set higher than
others. The output with the lower set voltage is then effectively turned off. When the voltage drops to the set
level, the LNB output with the lower set output voltage returns to normal conditions.
7.3.2 Linear Regulator and Current Limit
The linear regulator is used to generate the 22-kHz tone signal by changing the LDO reference voltage. The
linear regulator features low-dropout voltage to minimize power loss while maintaining enough head room
for the 22-kHz tone with 650-mV amplitude. The linear regulator also implements a tight current limit for
overcurrent protection. The current limit is set by an external resistor connected to ISET pin. Figure 7-1 shows
the relationship between the current limit threshold and the resistor value.
550
y = 117.08x-1.267
500
450
RSET (K)
400
350
300
250
200
150
100
0.3
0.4
0.5
0.6
0.7
0.8
ISET (A)
0.9
1
1.1
1.2
D007
Figure 7-1. Linear Regulator Current Limit Vs Resistor
RSET (k:) 117.08 x ISET 1.267 (A)
(1)
A 200-kΩ resistor sets the current to 0.65 A, and 110-kΩ resistor sets the current to approximately 1 A.
10
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7.3.3 Boost Converter Current Limit
The boost converter has the cycle-by-cycle peak current limit on the internal Power MOSFET switch to serve as
the secondary protection when LNB output is hard short. With ISW bit default setting 0b on I2C control register
0x01, the switch current limit ISW is proportional as LDO current limit I(OCP) set by ISET pin resistor, and the
relationship can be expressed as:
ISW
3 x I(OCP)
0.8A
(2)
For the 5 V VIN, if LNB current load is up to 1 A, the ISW bit should be written as 1b, the switch current limit ISW
for the internal Power MOSFET is:
ISW
5 x I(OCP)
0.8A
(3)
While due to the high power loss at 5 V, VIN, it has a chance to trigger the thermal shutdown before the loading is
up to 1 A, especially the VLNB output is high.
7.3.4 Charge Pump
The charge pump circuitry generates a voltage to drive the NMOS of the linear regulator. The voltage across the
charge pump capacitor between VLNB and VCP is about 5.4 V, so the absolute value of the VCP voltage will be
VLNB + 5.4 V.
7.3.5 Slew Rate Control
When LNB output voltage transits from 13.4 V to 18.2 V or 18.2 V to 13.4 V , the cap at pin TCAP controls the
transition time. This transition time makes sure the boost converter output to follow LNB output change. Usually
boost converter has low bandwidth and can’t response fast. The voltage at TCAP acts as the reference voltage
of the linear regulator. The boost converter’s reference is also based on TCAP with additional fixed voltage to
generate a 0.8 V above the LNB output.
The charging and discharging current is 10 µA, thus the transition time can be estimated as:
t TCAP (ms)
0.8 x
CSS (nF)
ISS (PA)
(4)
A 22-nF capacitor generates about 2 ms transition time.
In light load conditions, when LNB output voltage is set from 18.2 V to 13.4 V, the voltage drops very slow, which
causes wrong VOUT_GOOD (Bit 0 at status register 0x02) logic for LNB output voltage detection. TPS65235-1
has integrated a pull down circuit to pull down the output during the transition. This ensures the voltage change
can follow the voltage at TCAP. When the 22-kHz tone signal is superimposing on the LNB output voltage, the
pull down current can also provide square wave instead of a distorted waveforms.
7.3.6 Short Circuit Protection, Hiccup and Overtemperature Protection
The LNB output current limit can be set by an external resistor. When short circuit conditions occur or current
limit is triggered, the output current is clamped at the current limit for 4 ms with LDO on. If the condition retains,
the converter will shut down for 128 ms and then restart. This hiccup behavior prevents IC from being overheat.
The hiccup ON/OFF time can be set by I2C register. Refer to Control Register 1 for detail.
The low side MOSFET of the boost converter has a peak current limit threshold which serves as the secondary
protection. If boost converter’s peak current limit is triggered, the peak current will be clamped as high as 3.8 A
when setting ISW default and LNB current limit up to 1 A. If loading current continues to increase, output voltage
starts to drop and output power drops.
Thermal shutdown prevents the chip from operating at exceedingly high temperatures. When the junction
temperature exceeds 160°C, the output shuts down. When the die temperature drops below its lower threshold
typically 140°C, the output is enabled.
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When the chip is in overcurrent protection or thermal shutdown, the I2C interface and logic are still active. The
FAULT pin is pulled down to signal the processor. The FAULT pin signal remains low unless the following action
is taken:
1. If I2C interface is not used to control, EN pin must be recycled to pull the FAULT pin back to high.
2. If I2C interface is used, the I2C master need to read the status Control Register 2, then the FAULT pin will be
back to high.
7.3.7 Tone Generation
A 22-kHz tone signal is implemented at the LNB output voltage as a carrier for DiSEqC command. This tone
signal can be generated by feeding an external 22-kHz clock at the EXTM pin, and it can also be generated with
its internal tone generator controlled by EXTM pin. If EXTM pin is toggled to high, the internal tone signal will
be superimposed at the LNB output, if EXTM pin is low, there will be no tone superimposed at the output stage
of the regulator facilitates a push-pull circuit, so even at zero loading; the 22-kHz tone at the output is still clean
without distortion.
There are two ways to generate the 22-kHz tone signal at the output.
For option1, if the EXTM has 44-kHz tone input, and the bit EXTM TONE of the Control Register 1 is set to 1b,
the LNB tone output is 44 kHz.
EXTM
TONE
VLNB(V)
Option 1. Use external tone, gated by EXTM logic pulse
EXTM
TONE
VLNB(V)
Option 2. Use internal tone, gated by EXTM logic envelop
Figure 7-2. Two Ways to Generate 22-kHz tone
7.3.8 Tone Detection
A 22-kHz tone detector is implemented in the TPS65235-1 solution. The detector extracts the AC-coupled tone
signal from the DIN input and provides it as an open-drain signal on the DOUT pin. When the DOUTMODE bit
in the Control Register 2 is set to the default setting, if a tone is present, the DOUT output is logic low. If a tone
is not present, the internal output FET is off. If a pullup resistor is connected to the DOUT pin, the output is logic
high. The maximum tone out delay with respect to the input is one and a half of the tone cycle.
The DOUTMODE bit in the Control Register 2 is reserved and should not be used.
12
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7.3.9 Audio Noise Rejection
When the TPS65235-1 operates in PSM mode, locating the switching frequency at the range of audio frequency
is possible. Which causes audible noise, especially when the VLNB voltage is lower or closer to the VIN voltage,
and the current load is light.
When audible noise occurs, setting the TPS65235-1 device to operate in force PWM mode is recommended. In
force PWM mode, a special design is implemented to avoid the audible noise.
7.3.10 Disable and Enable
The TPS65235-1 device has a dedicated EN pin to disable and enable the LNB output. In a non-I2C application,
when the EN pin is pulled high, the LNB output is enabled. When the EN pin is pulled low, the LNB output
is disabled. In an I2C application, when the EN pin is either low or high, the I2C registers can be accessed,
which allows users to change the default LNB output at system power-up. When the I2C_CON bit in the Control
Register 1 is set to 1b, the LNB output enable or disable is controlled by the EN bit in the Control Register 2. By
default, the I2C_CON bit of the control register is set to 0b, which makes the LNB output is controlled by the EN
pin. Figure 7-3 and Figure 7-4 shows the detailed control behavior.
V(EN) = 0 V
I2C_CON = 1b
I2C_CON = 0b
Figure 7-3. VLNB Output Controlled by bit EN of
Control Register 2
Figure 7-4. VLNB Output Controlled by EN Pin
7.3.11 Component Selection
7.3.11.1 Boost Inductor
The TPS65235-1 device is recommended to operate with a boost inductor value of 4.7 µH or 10 µH. The boost
inductor must be able to support the peak current requirement to maintain the maximum LNB output current
without saturation. Use Equation 5 to estimate the peak current of the boost inductor (Ipeak).
IOUT
1- D
Ipeak
V xD
1
x IN
2
L x fS
(5)
where
•
D
1-
VIN
VLNB 0.8
(6)
With a different inductance, the system has different gain and phase margins. Figure 7-5 shows a Bode plot of
boost loop with 2 × 10 µF / 35 V of boost capacitor and 4.7 µH, 5.6 µH, 6.8 µH, 8.2 µH, and 10 µH of boost
inductance. As the boost inductance increases, the 0-dB crossover frequency keeps relatively constant while
reducing the phase and gain margins. With a 4.7-µH boost inductance, the phase margin is 66.96° and with a
10-µH inductance, the phase margin is 39.63°.
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Loop Gain (dB)
4.7 mH
5.6 mH
6.8 mH
8.2 mH
10 mH
4.7 mH, 66.96 deg
10 mH, 39.63 deg
4.7 mH
5.6 mH
6.8 mH
8.2 mH
10 mH
Figure 7-5. Gain and Phase Margin of the Boost Loop with Different Inductance (VIN = 12 V, VOUT = 18.2 V,
ILOAD = 1 A, fSW = 1 MHz, 5 µF, Typical Bode Plot)
7.3.11.2 Capacitor Selection
The TPS65235-1 device has a 1-MHz nonsynchronous boost converter integrated and the boost converter
features the internal compensation network. The TPS65235-1 device works well with both ceramic capacitor and
electrolytic capacitor.
The recommended ceramic capacitors for the TPS65235-1 application are, at the minimum, rated as X7R/X5R,
with a 35-V rating, and a 1206 size for the achieving lower LNB output ripple. Table 7-1 lists the recommended
ceramic capacitors list for both 4.7-µH and 10-µH boost inductors.
If more cost-effictive design is needed, use a 100-µF electrolytic (low ESR) and a 10-µF or 35-V ceramic
capacitor.
Table 7-1. Boost Inductor and Capacitor Selections
BOOST INDUCTOR
CAPACITORS
TOLERANCE (%)
RATING (V)
SIZE
10 µH
4.7 µH
14
2 × 22 µF
±10
35
1206
2 × 10 µF
±10
35
1206
2 × 22 µF
±10
35
1206
2 × 10 µF
±10
35
1206
22 µF
±10
35
1206
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Loop Gain (dB)
Figure 7-6 and Figure 7-7 show a bode plot of boost loop with 4.7-µH and 10-µH inductance and 4 µF, 5 µF,
7.5 µF, 10 µF, 15 µF, and 20 µF of boost capacitance after degrading. As the boost capacitance increases, the
phase margin increases.
4 mF
4 mF
5 mF
7.5 mF
10 mF
15 mF
20 mF
20 mF
4 mF, 57.45 deg
20 mF, 84.49 deg
4 mF
5 mF
7.5 mF
10 mF
15 mF
20 mF
Figure 7-6. Gain and Phase Margin of the Boost Loop With Different Boost Capacitance (VIN = 12 V, VOUT
= 18.2 V, ILOAD = 1 A, fSW = 1 MHz, 4.7 µH, Typical Bode Plot)
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Loop Gain (dB)
5 mF
7.5 mF
10 mF
15 mF
20 mF
5 mF
20 mF
5 mF, 37.23 deg
20 mF, 78.74 deg
5 mF
7.5 mF
10 mF
15 mF
20 mF
Figure 7-7. Gain and Phase Margin of the Boost Loop With Different Boost Capacitance (VIN = 12 V, VOUT
=18.2 V, ILOAD = 1 A, fSW = 1 MHz, 10 µH, Typical Bode Plot)
16
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7.3.11.3 Surge Components
If a surge test is required for the application, the D0 and D2 diodes should be added as the external protection
components. If no surge test is required, remove the D0 and D2 diodes.Table 7-2 lists the recommended surge
components.
Table 7-2. Surge Components
(1)
DESIGNATOR
DESCRIPTION
PART NUMBER
MANUFACTURER (1)
D0
Diode, TVS, Uni, 28 V, 1500 W, SMC
SMCJ28A
Fairchild Semiconductor
D2
Diode, Schottky, 40 V, 2 A, SMA
B240A-13-F
Diodes Inc.
See Third-party Products Disclaimer
100 nF
0.1 µF
16 VLNB
VOUT
D0
D2
D3
17 VCP
18 BOOST
20 PGND
10 µH
TPS65235-1
VIN
D1
19 GDR
LX
2x22 µF
1
2
VIN
10 µF
1 µF
Figure 7-8. Surge Components Selection
7.3.11.4 Consideration for Boost Filtering and LNB Noise
Smaller capacitance on the BOOST pin reduces the cost of the system. However, when the inductor in system is
the same, the smaller capacitance on the boost and the larger ripple on the LNB output.
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7.4 Device Functional Modes
Table 7-3 is the logic table for the device.
Table 7-3. Logic table
(1)
(2)
(3)
(4)
(5)
18
EN
I2C_CON(1) (2) (3)
SCL
VCTRL
VLNB(4)
H
0
H
H
19.4 V
H
0
H
L
14.6 V
H
0
L
H
18.2 V
H
0
L
L
13.4 V
X
1
X
X
Controlled by VSET[3:0]
bits at 0x01 register(5)
L
0
X
X
0V
I2C_CON is the bit7 of the I2C control register 0x01, which is used to set the VLNB output controlled by the I2C register or not.
When I2C interface is used in design, all the I2C registers are accessible even if the I2C_CON bit is 0b.
When I2C_CON is 1b, the VLNB output is controlled by the I2C control register even if the EN pin is low.
When I2C interface is used in design, it is recommended to set the I2C_CON with 1b, if not, the LNB output will be variable because
the SCL is toggled by the I2C register access as the clock signal.
Bit EN of the control register2 is used to disable or enable the LNB output, by default , the bit EN is 1b which enable the LNB output
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7.5 Programming
7.5.1 Serial Interface Description
I2C is a 2-wire serial interface developed by Philips Semiconductor (see I2C-Bus Specification, Version 2.1,
January 2000). The bus consists of a data line (SDA) and a clock line (SCL) with pullup structures. When the
bus is idle, both SDA and SCL lines are pulled high external. All the I2C compatible devices connect to the I2C
bus through open drain I/O pins, SDA and SCL. A master device, usually a microcontroller (MCU) or a digital
signal processor (DSP), controls the bus. The master device is responsible for generating the SCL signal and
device addresses. The master device also generates specific conditions that indicate the START and STOP of
data transfer. A slave device receives, transmits data, or both on the bus under control of the master device.
The TPS65235-1 device works as a slave and supports the following data transfer modes, as defined in
the I2CBus Specification: standard mode (100 kbps), and fast mode (400 kbps). The interface adds flexibility
to the power supply solution, enabling most functions to be programmed to new values depending on the
instantaneous application requirements. Register contents remain intact as long as supply voltage remains
above 4.5 V (typical).
The data transfer protocol for standard and fast modes is exactly the same; therefore, they are referred to as
F/S-mode in this document. The TPS65235-1 device supports 7-bit addressing; 10-bit addressing and general
call address are not supported.
The TPS65235-1 device has a 7-bit address set by ADDR pin. Table 7-4 shows how to set the I2C address.
Table 7-4. I2C Address Selection
I2C ADDRESS
ADDRESS FORMAT (A6 ≥ A0)
Connect to VCC
0x08
000 1000b
Floating
0x09
000 1001b
Connected to GND
0x10
001 0000b
Resistor divider to make ADDR pin voltage in 3 V ~ VCC - 0.8 V
0x11
001 0001b
ADDR PIN
SDA
tSU, DAT
tLOW
tHD, DAT
tSU, STA
tHD, STA
tBUF
tSU, STO
SCL
tHD, STA
Start
Condition
tHIGH
tr
tSP
tf
Repeated Start
Condition
Stop
Condition
Start
Condition
Figure 7-9. I2C Interface Timing Diagram
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7.5.2 TPS65235-1 I2C Update Sequence
The TPS65235-1 requires a start condition, a valid I2C address, a register address byte, and a data byte for
a single update. After the receipt of each byte, TPS65235-1 device acknowledges by pulling the SDA line low
during the high period of a single clock pulse. TPS65235-1 performs an update on the falling edge of the LSB
byte.
When the TPS65235-1 is disabled (EN pin tied to ground) the device cannot be updated via the I2C interface.
S
7-Bit Slave Address
A6«.A0
0
A
A
Register Address
A
Data Byte
P
Figure 7-10. I2C Write Data Format
S
7-Bit Slave Address
A6«.A0
0
A
Register1 Address
N
Data Byte
A Sr
7-Bit Slave Address
1
A
P
A: Acknowledge
N: Not Acknowledge
S: Start
System Host
P: Stop
Sr: Repeated Start
Chip
Figure 7-11. I2C Read Data Format
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7.6 Register Maps
7.6.1 Control Register 1 (address = 0x00) [reset = 0x08]
Figure 7-10. Control Register 1
7
6
5
4
3
2
1
0
I2C_CON
PWM/PSM
RESERVED
VSET[3:0]
EXTM TONE
R/W-0b
R/W-0b
R/W-0b
R/W-0100b
R/W-0b
Table 7-5. Control Register 1
Bit
Field
Type
Reset
Description
7
I2C_CON
R/W
0b
0b = I2C control disabled
1b = I2C control enabled
6
PWM/PSM
R/W
0b
0b = PSM at light load
1b = Forced PWM
5
RESERVED
R/W
0b
Reserved
0100b
LNB output voltage selection
0000b = 11 V
0001b = 11.6 V
0010b = 12.2 V
0011b = 12.8 V
0100b = 13.4 V
0101b = 14 V
0110b = 14.6 V
0111b = 15.2 V
1000b = 15.8 V
1001b = 16.4 V
1010b = 17 V
1011b = 17.6 V
1100b = 18.2 V
1101b = 18.8 V
1110b = 19.4 V
1111b = 20 V
0b
0b = EXTM 44-kHz tone input not support, with only 22-kHz tone
output at VLNB
1b = EXTM 44-kHz tone input support, with 44-kHz tone output
at VLNB
4-1
VSET[3:0]
R/W
0
EXTM TONE
R/W
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7.6.2 Control Register 2 (address = 0x01) [reset = 0x09]
Figure 7-11. Control Register 2
7
6
5
4
3
2
1
0
TONEAMP
TIMER
ISW
FSET
EN
DOUTMODE
TONE_AUTO
TONE_TRANS
R/W-0b
R/W-0b
R/W-0b
R/W-0b
R/W-1b
R/W-0b
R/W-0b
R/W-1b
Table 7-6. Control Register 2
Bit
Field
Type
Reset
Description
7
TONEAMP
R/W
0b
0b = 22-kHz tone amplitude is 650 mV (typ)
1b = 22-kHz tone amplitude is 750 mV (typ)
6
TIMER
R/W
0b
0b = Hiccup ON time set to 4 ms and OFF time set to 128 ms
1b = Hiccup ON time set to 8 ms and OFF time set to 256 ms
5
ISW
R/W
0b
0b = Boost switch peak current limit set to 3 × IOCP + 0.8 A
1b = Boost switch peak current limit set to 5 × IOCP + 0.8 A
4
FSET
R/W
0b
0b = 1-MHz switching frequency
1b = 500-kHz switching frequency
3
EN
R/W
1b
0b = LNB output disabled
1b = LNB output voltage Enabled
2
DOUTMODE
R/W
0b
0b = DOUT is kept to low when DIN has the tone input
1b = Reserved, cannot set to 1b
1
TONE_AUTO
0b
0b = GDR (External bypass FET control) is controlled by
TONE_TRANS
1b = GDR (External bypass FET control) is automatically
controlled by 22-kHz tones transmit
1b
0b = GDR output with VLNB voltage for tone receive. Bypass
FET is OFF for tone receiving from satellite
1b = GDR output with VCP voltage. Bypass FET is ON for tone
transmit from TPS65235-1
R/W
0
TONE_TRANS
R/W
Table 7-7. 22-kHz Tone Receive Mode Selection
TONE_AUTO
TONE_TRANS
BYPASS FET
0b
0b
OFF
0b
1b
ON
1b
x
Auto Detect
The TPS65235-1 has full range of diagnostic flags for operation and debug. Processor can read the status
register to check the error conditions. Once the error happens, the flags are changed, once the errors are gone,
the flags are set back without I2C access.
If the TSD and OCP flags are triggered, FAULT pin will be pulled low, so FAULT pin can be the interrupt signal to
processor. Once TSD and OCP are set to 1b, the FAULT pin logic is latched to low, processor need to read this
status register to release the fault conditions.
22
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7.6.3 Status Register (address = 0x02) [reset = 0x29]
Figure 7-12. Status Register
7
6
5
4
3
2
1
0
Reserved
0
LDO_ON
R-0b
R-0b
R-0b
T125
TSD
OCP
CABLE_GOOD
VOUT_GOOD
R-0b
R-1b
R-0b
R-0b
R-1b
Table 7-8. Status Register
Bit
Field
Type
Reset
Description
7
Reserved
R
0b
Reserved
6
TDETGOOD
R
0b
0b = 22-kHz tone detected on DIN pin is out of range
1b = 22-kHz tone detected on DIN pin is in range
5
LDO_ON
R
1b
0b = Internal LDO is turned off but boost converter is on
1b = Internal LDO is turned on and boost converter is on
4
T125
R
0b
0b = Die temperature < 125°C
1b = Die temperature > 125°C
3
TSD
1b
0b = No thermal shutdown triggered
1b = Thermal shutdown triggered. The FAULT pin logic is
latched to low, processor need to read this register to release
the fault conditions
R
0b
0b = Overcurrent protection conditions released
1b = Overcurrent protection triggered. The FAULT pin logic is
latched to low, processor need to read this register to release
the fault conditions
R
0b
0b = Cable not connected
1b = Cable connection good
R
1b
0b = LNB output voltage out of range
1b = LNB output voltage in range
R
2
OCP
1
CABLE_GOOD
0
VOUT_GOOD
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8 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and
TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
8.1 Application Information
The TPS65235 supports both DisEqc1.x and DisEqc2.x application. When the input voltage VIN is greater than
the expected output voltage VLNB, the linear regulator drops the voltage difference between VIN and VLNB,
which causes the lower efficiency and the higher power loss on the internal linear regulator if the current loading
is high. For care must be taken to ensure that the safe operating temperature range of the TPS65235-1 is not
exceeded. TI recommends operating the device in force PWM mode when VIN > VOUT to reduce output ripple.
8.2 Typical Application
8.2.1 DiSEqc1.x Support
100 nF
VOUT
15
14
13
12
11
DIN
DOUT
EXTM
SCL
SDA
TPS65235-1 can operate in I2C and non-I2C interface mode. Figure 8-1 shows the application with the device in
I2C interface mode to support DiSEqC 1.x application. In non-I2C mode, the SCL, SDA, and ADDR pins can be
floating.
0.1 PF
16
VLNB
17
VCP
18
BOOST
19
GDR
20
PGND
VCTRL 10
D0
ADDR
9
FAULT
8
EN
7
ISET
6
10 k
LX
VIN
VCC
AGND
TCAP
2×
22 PF
TPS65235-1
1
2
3
4
5
110 k
10 PH
VIN
1 PF
10 PF
22 nF
1 PF
1 PF
Figure 8-1. Application for DiSEqc1.x Support
24
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8.2.1.1 Design Requirements
For this design example, use the parameters in Table 8-1.
Table 8-1. Design Parameters
PARAMETER
VALUE
Input voltage range, VIN
4.5 V to 20 V
Output voltage range VLNB
11 V to 20 V
Output current range
0 A to 1 A
8.2.1.2 Detailed Design Procedure
To begin the design process, the following component values must be selected:
• Inductor
– Choose the appropriate value of the inductor based on application cost requirements, ripple requirements,
and Section 7.3.11.
• BOOST capacitor
– Choose the appropriate BOOST capacitor value based on application cost requirements, ripple
requirements, and Section 7.3.11.
• Diodes
– The D0 and D2 diodes are used to help meet the surge-protection requirement of the application. If the
application does not require surge protection, remove these diodes. For diode component selection, refer
to Section 7.3.11.3.
– The D1 diode is used for the boost loop. A Schottky diode is recommended for D1. The application
requirements, which include input power range, output power range, and the current requirement,
determine the current and voltage capability of the D1 diode.
– The D3 diode is to help with the output protection for the VLNB voltage. A Schottky diode is recommended
for D3. The application requirements determine the current and voltage capability of the D3 diode.
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8.2.1.3 Application Curves
TA = 25°C, VIN = 12 V, fSW = 1 MHz, CBoost = (2 × 22 µF / 35 V) (unless otherwise noted)
VVLNB = 13.4 V
VVLNB = 13.4 V
Figure 8-2. Soft Start, Delay from EN High to LNB
Output High
VVLNB = 18.2 V
VVLNB = 18.2 V
Figure 8-4. Soft-Start, Delay from EN High to LNB
Output High
EN = 0b
VVLNB =13.4 V
Figure 8-5. Disabled, Delay From EN Low to LNB
Output Low
EN = 0b
Figure 8-6. Soft Start, Delay From I2C Enable
(I2C_CON = 1b) to LNB Output High
26
Figure 8-3. Disabled, Delay from EN Low to LNB
Output Low
VVLNB = 13.4 V
Figure 8-7. Delay From I2C Disable (I2C_CON = 0b)
to LNB Output Low
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VVLNB = 13.4 V
VVLNB = 13.4 V
Figure 8-8. No Load, 22-kHz Tone Output
VVLNB = 18.2 V
Figure 8-9. 950-mA Load, 22-kHz Tone Output
VVLNB = 18.2 V
Figure 8-10. No Load, 22-kHz Tone Output
Figure 8-11. 950-mA Load, 22-kHz Tone Output
Figure 8-12. No load, 22-kHz Tone Delay from
EXTM 22-kHz Input Turns High to Output Tone On
Figure 8-13. No load, 22-kHz Tone Delay from
EXTM 22-kHz Input Turns Low to Output Tone Off
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28
Figure 8-14. No Load, 22-kHz Tone Delay from
EXTM Tone Envelop Input Turns High to Output
Tone On
Figure 8-15. No Load, 22-kHz Tone Delay from
EXTM Tone Envelop Input Turns Low to Output
Tone Off
Figure 8-16. No Load, 44-kHz Tone Delay from
EXTM 22-kHz Input Turns High to Output Tone On
Figure 8-17. No Load, 44-kHz Tone Delay from
EXTM 22-kHz Input Turns Low to Output Tone Off
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8.2.2 DiSEqc2.x Support
The TPS65235-1 can support both DiSEqC 1.x application and DiSEqC 2.x application. Figure 8-18 shows the
application for supporting DiSEqC 2.x application.
10 k
10 nF
220 PH
15
14
13
12
11
DIN
DOUT
EXTM
SCL
SDA
10 k
0.1 PF
VOUT
16
VLNB
17
VCP
18
BOOST
19
GDR
20
PGND
VCTRL 10
100 nF
D2
22 nF
D3
ADDR
9
FAULT
8
EN
7
ISET
6
10 k
15
VIN
VCC
AGND
TCAP
D1
LX
2×
22PF
TPS65235-1
1
2
3
4
5
110 k
10 PH
VIN
1 PF
10 PF
22 nF
1 PF
Figure 8-18. Application Schematic for DiSEqc2.x Support
8.2.2.1 Design Requirements
Refer to the Section 8.2.1 section for design requirements.
8.2.2.2 Detailed Design Procedure
Refer to the Section 8.2.1 section for detailed design procedures.
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8.2.2.3 Application Curve
Refer to the Section 8.2.1 section for typical application curves. Figure 8-19 is the unique tone-detection curve
for the DiSEqC 2.x application.
Figure 8-19. DOUT Tone Detection Output
9 Power Supply Recommendations
The device is designed to operate from an input supply ranging from 4.5 V to 20 V. The input supply should
be well regulated. If the input supply is located more than a few inches from the converter, an additional bulk
capacitance, typically with a value 100 µF, may be required in addition to the ceramic bypass capacitors.
30
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10 Layout
10.1 Layout Guidelines
The TPS65235-1 is designed to layout in 2‐layer PCB. To ensure reliability of the device, following common
printed-circuit board layout guidelines is recommended.
• It is critical to make sure the ground of input capacitor, output capacitor, and the boost converter are
connected at one point at same layer.
• The PGND and AGND pins are located in different regions. Connect these grounds to the thermal pad. Other
components are connected the AGND pin.
• Put the BOOST capacitors as close as possible.
• The loop from the VIN inductor to the LX pin should be as short as possible.
• The loop from the VIN inductor to D1 Schottky diode to the BOOST should be as short as possible.
• The loop for boost capacitors to the PGND pin should be within the loop from the LX pin to D1 Schottky diode
to the BOOST pin.
10.2 Layout Example
Polygonal Copper Pour
13
12
11
EXTM
SCL
SDA
100nF
14
DOUT
D3
15
DIN
VIA to GND Plane (Inner Layer)
VOUT
16 VLNB
0.1uF
D2
17 VCP
VCTRL
10
ADDR
9
10k
18 BOOST
2x22uF
19 GDR
VIN
10uH
1uF
TCAP
2
AGND
1
VCC
VIN
D1
LX
20 PGND
3
4
5
FAULT
8
EN
7
ISET
6
110k
1uF
22nF
10uF
Figure 10-1. Layout
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11 Device and Documentation Support
11.1 Device Support
11.2 Documentation Support
11.2.1 Related Documentation
For related documentation see the following:
• Texas Instruments, Evaluation Module for the TPS65235-1 LNB Voltage Regulator With I2C Interface for
DiSEqC2.x Application user's guide
• Texas Instruments, Evaluation Module for the TPS65235-1 LNB Voltage Regulator With I2C Interface for
DiSEqC1.x Application user's guide
11.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
11.4 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.5 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
11.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.7 Glossary
TI Glossary
32
This glossary lists and explains terms, acronyms, and definitions.
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12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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17-May-2021
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS65235-1RUKR
ACTIVE
WQFN
RUK
20
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
652351
TPS65235-1RUKT
ACTIVE
WQFN
RUK
20
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
652351
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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