Order
Now
Product
Folder
Support &
Community
Tools &
Software
Technical
Documents
Reference
Design
TPS65251
SLVSAA4G – JUNE 2010 – REVISED FEBRUARY 2018
TPS65251 4.5-V to 18-V Input, High-Current, Synchronous Step-Down Three Buck
Switcher With Integrated FET
1 Features
3 Description
•
•
•
The TPS65251 features three synchronous wide
input range high efficiency buck converters. The
converters are designed to simplify its application
while giving the designer the option to optimize their
usage according to the target application.
1
•
•
•
•
•
•
•
•
•
•
•
Wide Input Supply Voltage Range (4.5 to 18 V)
0.8 V, 1% Accuracy Reference
Continuous Loading: 3 A (Buck 1),
2 A (Buck 2 and 3)
Maximum Current: 3.5 A (Buck 1),
2.5 A (Buck 2 and 3)
Adjustable Switching Frequency
300 kHz to 2.2 MHz Set by External Resistor
Dedicated Enable for Each Buck
External Synchronization Pin for Oscillator
External Enable/Sequencing and Soft-Start Pins
Adjustable Current Limit Set By External Resistor
Soft-Start Pins
Current-Mode Control With Simple Compensation
Circuit
Powergood
Optional Low-Power Mode Operation for Light
Loads
VQFN Package, 40-Pin 6 mm × 6 mm RHA
The converters can operate in 5-, 9-, 12- or 15-V
systems and have integrated power transistors. The
output voltage can be set externally using a resistor
divider to any value between 0.8 V and close to the
input supply. Each converter features enable pin that
allows a delayed start-up for sequencing purposes,
soft-start pin that allows adjustable soft-start time by
choosing the soft-start capacitor, and a current limit
(RLIMx) pin that enables designer to adjust current
limit by selecting an external resistor and optimize the
choice of inductor. The current mode control allows a
simple RC compensation.
The switching frequency of the converters can either
be set with an external resistor connected to ROSC
pin or can be synchronized to an external clock
connected to SYNC pin if needed. The switching
regulators are designed to operate from 300 kHz to
2.2 MHz. 180° out of phase operation between Buck
1 and Buck 2, 3 (Buck 2 and 3 run in phase)
minimizes the input filter requirements.
2 Applications
•
•
•
•
•
•
Set Top Boxes
Blu-ray DVD
DVR
DTV
Car Audio/Video
Security Camera
Device Information(1)
PART NUMBER
PACKAGE
TPS65251
VQFN (40)
BODY SIZE (NOM)
6.00 mm × 6.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Typical Application Schematic
V2
GPIO or
GND
C1
C2
PG
FB2
R22 C24
C25
C21
C26
R23
R20
FB2
L3
4.7 µH
V3
C31 C30
GND
VIN
VIN
VIN
GND
LX3
VIN3 LX3
VIN3
BST3
EN3
C37
R30
C33
R33
120 k
TPS 65251
EN2
BST2
VIN2
LX2
LX2
LX1
LX1
VIN1
BST1
EN1
RLIM3
SS3
CMP3
FB3
SYNC
ROSC
FB1
CMP1
SS1
RLIM1
VIN
AGND
V3V
V7V
PGOOD
GND
LOW_P
FB2
CMP2
SS2
RLIM2
C23
C27
4.7 nF
VIN2
C20
R21
L2
L1
VIN1
C10
V1
C11
C17
R13
C13
R10
R1
R31
C34 R32
C35
R12 C14
C36
C16
R11
GPIO
or GND
C15
Copyright © 2018, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS65251
SLVSAA4G – JUNE 2010 – REVISED FEBRUARY 2018
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Description (continued).........................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
3
5
7.1
7.2
7.3
7.4
7.5
7.6
5
5
5
5
6
8
Absolute Maximum Ratings .....................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Detailed Description ............................................ 11
8.1 Overview ................................................................. 11
8.2 Functional Block Diagram ....................................... 11
8.3 Feature Description................................................. 12
8.4 Device Functional Modes........................................ 15
9
Application and Implementation ........................ 17
9.1 Application Information............................................ 17
9.2 Typical Application .................................................. 17
10 Power Supply Recommendations ..................... 24
11 Layout................................................................... 24
11.1 Layout Guidelines ................................................. 24
11.2 Layout Example .................................................... 25
11.3 Power Dissipation ................................................. 25
12 Device and Documentation Support ................. 27
12.1
12.2
12.3
12.4
12.5
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
27
27
27
27
27
13 Mechanical, Packaging, and Orderable
Information ........................................................... 27
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision F (July 2015) to Revision G
•
Page
Changed the values for Voltage at LX1, LX2, LX3 From: MIN = –1 V, MAX = 20 V To: MIN = –3 V, MAX = 23 V in
the Absolute Maximum Ratings ............................................................................................................................................. 5
Changes from Revision E (December 2014) to Revision F
Page
•
Changed the MAX value for Voltage at VIN1,VIN2, VIN3, LX1, LX2, LX3 From: 18 V To: 20 V in the Absolute
Maximum Ratings .................................................................................................................................................................. 5
•
Added Community Resources ............................................................................................................................................. 27
Changes from Revision D (December 2012) to Revision E
•
2
Page
Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1
Submit Documentation Feedback
Copyright © 2010–2018, Texas Instruments Incorporated
Product Folder Links: TPS65251
TPS65251
www.ti.com
SLVSAA4G – JUNE 2010 – REVISED FEBRUARY 2018
5 Description (continued)
TPS65251 features a supervisor circuit that monitors each converter output. The PGOOD pin is asserted once
sequencing is done, all PG signals are reported and a selectable end of reset time lapses. The polarity of the
PGOOD signal is active high.
TPS65251 also features a light load pulse skipping mode (PSM) by allowing the LOW_P pin tied to V3V. The
PSM mode allows for a reduction on the input power supplied to the system when the host processor is in
standby (low-activity) mode.
6 Pin Configuration and Functions
AGND
V3V
V7V
PGOOD
GND
LOW_P
FB2
COMP2
SS2
RLIM2
RHA Package
40-Pin VQFN
Top View
30
29
28
27
26
25
24
23
22
21
GND
31
20
EN2
VIN
32
19
BST2
VIN
33
18
VIN2
VIN
34
17
LX2
GND
35
16
LX2
LX3
36
15
LX1
LX3
37
14
LX1
VIN3
38
13
VIN1
BST3
39
12
BST1
EN3
40
11
EN1
FB3
7
8
9
10
RLIM1
CMP3
6
SS1
SS3
5
CMP1
4
FB1
3
ROSC
2
SYNC
1
RLIM3
(power pad connected to ground)
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
RLIM3
1
I
Current limit setting for Buck 3. Fit a resistor from this pin to ground to set the peak current limit on the output
inductor.
SS3
2
I
Soft-start pin for Buck 3. Fit a small ceramic capacitor to this pin to set the converter soft-start time.
COMP3
3
O
Compensation for Buck 3. Fit a series RC circuit to this pin to complete the compensation circuit of this
converter.
FB3
4
I
Feedback input for Buck 3. Connect a divider set to 0.8V from the output of the converter to ground.
Submit Documentation Feedback
Copyright © 2010–2018, Texas Instruments Incorporated
Product Folder Links: TPS65251
3
TPS65251
SLVSAA4G – JUNE 2010 – REVISED FEBRUARY 2018
www.ti.com
Pin Functions (continued)
PIN
NAME
NO.
I/O
DESCRIPTION
SYNC
5
I
Synchronous clock input. If there is a sync clock in the system, connect to the pin. When not used connect to
GND.
ROSC
6
I
Oscillator set. This resistor sets the frequency of internal autonomous clock. If external synchronization is used
resistor should be fitted and set to about 70% of external clock frequency.
FB1
7
I
Feedback pin for Buck 1. Connect a divider set to 0.8 V from the output of the converter to ground.
COMP1
8
O
Compensation pin for Buck 1. Fit a series RC circuit to this pin to complete the compensation circuit of this
converter.
SS1
9
I
Soft-start pin for Buck 1. Fit a small ceramic capacitor to this pin to set the converter soft-start time.
RLIM1
10
I
Current limit setting pin for Buck 1. Fit a resistor from this pin to ground to set the peak current limit on the
output inductor.
EN1
11
I
Enable pin for Buck 1. A low level signal on this pin disables it. If pin is left open a weak internal pullup to V3V
will allow for automatic enable. For a delayed start-up add a small ceramic capacitor from this pin to ground.
BST1
12
I
Bootstrap capacitor for Buck 1. Fit a 47-nF ceramic capacitor from this pin to the switching node.
VIN1
13
I
Input supply for Buck 1. Fit a 10-µF ceramic capacitor close to this pin.
14
LX1
15
16
LX2
17
O
O
Switching node for Buck 1
Switching node for Buck 2
VIN2
18
I
Input supply for Buck 2. Fit a 10-µF ceramic capacitor close to this pin.
BST2
19
I
Bootstrap capacitor for Buck 2. Fit a 47-nF ceramic capacitor from this pin to the switching node.
EN2
20
I
Enable pin for Buck 2. A low level signal on this pin disables it. If pin is left open a weak internal pullup to V3V
will allow for automatic enable. For a delayed start-up add a small ceramic capacitor from this pin to ground.
RLIM2
21
I
Current limit setting for Buck 2. Fit a resistor from this pin to ground to set the peak current limit on the output
inductor.
SS2
22
I
Soft-start pin for Buck 2. Fit a small ceramic capacitor to this pin to set the converter soft-start time.
COMP2
23
O
Compensation pin for Buck 2. Fit a series RC circuit to this pin to complete the compensation circuit of this
converter
FB2
24
I
Feedback input for Buck 2. Connect a divider set to 0.8 V from the output of the converter to ground.
LOW_P
25
I
Low-power operation mode (active high) input for TPS65251
GND
26
PGOOD
27
O
Powergood. Open-drain output asserted after all converters are sequenced and within regulation. Polarity is
factory selectable (active high default).
V7V
28
O
Internal supply. Connect a 10-μF ceramic capacitor from this pin to ground.
V3V
29
O
Internal supply. Connect a 3.3-μF to 10-μF ceramic capacitor from this pin to ground.
AGND
30
GND
31
VIN
32
I
Input supply
VIN
33
I
Input supply
VIN
34
I
Input supply
GND
35
LX3
36
37
Ground pin
Analog ground. Connect all GND pins and the power pad together.
Ground pin
Ground pin
O
Switching node for Buck 3
VIN3
38
BST3
39
I
Bootstrap capacitor for Buck 3. Fit a 47-nF ceramic capacitor from this pin to the switching node.
EN3
40
I
Enable pin for Buck 3. A low level signal on this pin disables it. If pin is left open a weak internal pullup to V3V
will allow for automatic enable. For a delayed start-up add a small ceramic capacitor from this pin to ground.
PAD
—
—
4
Input supply for Buck 3. Fit a 10-µF ceramic capacitor close to this pin.
Power pad. Connect to ground.
Submit Documentation Feedback
Copyright © 2010–2018, Texas Instruments Incorporated
Product Folder Links: TPS65251
TPS65251
www.ti.com
SLVSAA4G – JUNE 2010 – REVISED FEBRUARY 2018
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature (unless otherwise noted) (1)
Voltage at VIN1,VIN2, VIN3, LX1, LX2, LX3
Voltage at LX1, LX2, LX3 (maximum withstand voltage transient < 10 ns)
MIN
MAX
UNIT
–0.3
20
V
–3
23
V
Voltage at BST1, BST2, BST3, referenced to Lx pin
–0.3
7
V
Voltage at V7V, COMP1, COMP2, COMP3
–0.3
7
V
Voltage at V3V, RLIM1, RLIM2, RLIM3, EN1,EN2,EN3, SS1, SS2,SS3, FB1, FB2, FB3,
PGOOD, SYNC, ROSC, LOW_P
–0.3
3.6
V
Voltage at AGND, GND
–0.3
0.3
V
TJ
Operating virtual junction temperature
–40
125
°C
Tstg
Storage temperature
–55
150
°C
(1)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
VIN
Input operating voltage
4.5
18
UNIT
V
TJ
Junction temperature
–40
125
°C
7.4 Thermal Information
TPS65251
THERMAL METRIC (1)
RHA (VQFN)
UNIT
40 PINS
RθJA
Junction-to-ambient thermal resistance
RθJC(top)
Junction-to-case (top) thermal resistance
30
°C/W
25.3
RθJB
°C/W
Junction-to-board thermal resistance
73
°C/W
ψJT
Junction-to-top characterization parameter
0.2
°C/W
ψJB
Junction-to-board characterization parameter
7.6
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
1.9
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
Submit Documentation Feedback
Copyright © 2010–2018, Texas Instruments Incorporated
Product Folder Links: TPS65251
5
TPS65251
SLVSAA4G – JUNE 2010 – REVISED FEBRUARY 2018
www.ti.com
7.5 Electrical Characteristics
TJ = –40°C to 125°C, VIN = 12 V, fSW = 1 MHz (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INPUT SUPPLY UVLO AND INTERNAL SUPPLY VOLTAGE
VIN
Input Voltage range
IDDSDN
Shutdown
EN pin = low for all converters
4.5
1.3
mA
IDDQ
Quiescent, low-power disabled (Lo)
Converters enabled, no load
Buck 1 = 3.3 V, Buck 2 = 2.5 V,
Buck 3 = 7.5 V,
L = 4.7 µH , fSW = 800 kHz
20
mA
IDDQ_LOW_P
Quiescent, low-power enabled (Hi)
Converters enabled, no load
Buck 1 = 3.3 V, Buck 2 = 2.5 V,
Buck 3 = 7.5 V,
L = 4.7 µH , fSW = 800 kHz
1.5
mA
UVLOVIN
VIN under voltage lockout
UVLODEGLITCH
Rising VIN
4.22
Falling VIN
4.1
Both edges
V3V
Internal biasing supply
ILOAD = 0 mA
I3V
Biasing supply output current
VIN = 12 V
V7V
Internal biasing supply
ILOAD = 0 mA
I7V
Biasing supply output current
VIN = 12 V
V7VUVLO
UVLO for internal V7V rail
V7VUVLO_DEGLITCH
18
V
110
3.2
5.63
3.3
6.25
µs
3.4
V
10
mA
6.88
10
Rising V7V
3.8
Falling V7V
3.6
Falling edge
110
V
V
mA
V
µs
BUCK CONVERTERS (ENABLE CIRCUIT, CURRENT LIMIT, SOFT-START, SWITCHING FREQUENCY AND SYNC CIRCUIT, LOW-POWER MODE)
VIH
VIL
Enable threshold high
V3p3 = 3.2 V - 3.4 V, VENX rising
Enable high level
External GPIO, VENX rising
Enable threshold low
V3p3 = 3.2 V - 3.4 V, VENX falling
Enable low level
External GPIO, VENX falling
1.55
1.82
0.66 x V3V
0.98
1.24
0.33 x V3V
REN_DIS
Enable discharge resistor
ICHEN
Pullup current enable pin
–10%
tD
Discharge time enable pins
ISS
Soft-start pin current source
FSW_BK
Converter switching frequency range
Set externally with resistor
RFSW
Frequency setting resistor
Depending on set frequency
fSW_TOL
Internal oscillator accuracy
fSW = 800 kHz
VSYNCH
External clock threshold high
V3p3 = 3.3 V
VSYNCL
External clock threshold Low
V3p3 = 3.3 V
SYNCRANGE
Synchronization range
SYNCCLK_MIN
Sync signal minimum duty cycle
SYNCCLK_MAX
Sync signal maximum duty cycle
VIHLOW_P
Low-power mode threshold high
V3p3 = 3.3 V, VENX rising
1.55
VILLOW_P
Low-power mode threshold Low
V3p3 = 3.3 V, VENX falling
0.98
VIN = 12V TJ = 25°C
–1%
0.8
1%
VIN = 4.5 to 18 V
–2%
0.8
2%
Power-up
2.1
10%
V
V
kΩ
1.1
µA
10
ms
5
0.3
µA
2.2
MHz
50
600
kΩ
–10%
10%
1.55
V
0.2
1.24
V
2.2
MHz
40%
60%
V
1.24
V
FEEDBACK, REGULATION, OUTPUT STAGE
VFB
Feedback voltage
IFB
Feedback leakage current
tON_MIN
Minimum on-time
(current sense blanking)
VLINEREG
Line regulation - DC
∆VOUT/∆VINB
VINB = 4.5 to 18 V,
IOUT = 1000 mA
0.5
% VOUT
VLOADREG
Load regulation - DC
∆VOUT/∆IOUT
IOUT = 10 % - 90%
IOUT,MAX
0.5
% VOUT/A
H.S. Switch
Turn-On resistance high-side FET on CH1
VIN = 12 V, TJ = 25°C
95
mΩ
L.S. Switch
Turn-On resistance low-side FET on CH1
VIN = 12 V, TJ = 25°C
50
mΩ
80
V
50
nA
120
ns
MOSFET (BUCK 1)
6
Submit Documentation Feedback
Copyright © 2010–2018, Texas Instruments Incorporated
Product Folder Links: TPS65251
TPS65251
www.ti.com
SLVSAA4G – JUNE 2010 – REVISED FEBRUARY 2018
Electrical Characteristics (continued)
TJ = –40°C to 125°C, VIN = 12 V, fSW = 1 MHz (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
MOSFET (BUCK 2)
H.S. Switch
Turn-On resistance high-side FET on CH2
VIN = 12 V, TJ = 25°C
120
mΩ
L.S. Switch
Turn-On resistance low-side FET on CH2
VIN = 12 V, TJ = 25°C
80
mΩ
H.S. Switch
Turn-On resistance high-side FET on CH3
VIN = 12 V, TJ = 25°C
120
mΩ
L.S. Switch
Turn-On resistance low-side FET on CH3
VIN = 12 V, TJ = 25°C
80
mΩ
gM
Error amplifier transconductance
–2 µA < ICOMP < 2 µA
130
µS
gmPS
COMP to ILX gM
ILX = 0.5 A
10
A/V
MOSFET (BUCK 3)
ERROR AMPLIFIER
POWERGOOD RESET GENERATOR
Output falling (device will be
disabled after tON_HICCUP )
85%
Output rising (PG will be asserted)
90%
VUVBUCKX
Threshold voltage for buck under voltage
tUV_deglitch
Deglitch time (both edges)
Each buck
11
ms
tON_HICCUP
Hiccup mode ON time
VUVBUCKX asserted
12
ms
tOFF_HICCUP
Hiccup mode OFF time before restart is
attempted
All converters disabled. Once
tOFF_HICCUP elapses, all converters
will go through sequencing again.
15
ms
VOVBUCKX
Threshold voltage for buck overvoltage
tRP
Minimum reset period
Output rising (high-side FET will be
forced off)
109%
Output falling (high-side FET will be
allowed to switch )
107%
Measured after minimum reset
period of all bucks power-up
successfully
1
s
THERMAL SHUTDOWN
TTRIP
Thermal shutdown trip point
Rising temperature
THYST
Thermal shutdown hysteresis
Device restarts
TTRIP_DEGLITCH
Thermal shutdown deglitch
160
°C
20
°C
110
µs
CURRENT LIMIT PROTECTION
RLIM1
Limit resistance range Buck 1
RLIM2&3
Limit resistance range Bucks 2 and 3
75
300
kΩ
100
300
kΩ
1.2
5.5
A
ILIM1
Buck 1 adjustable current limit range
VIN = 12 V, fSW = 500 kHz,
see Figure 17
ILIM2
Buck 2 adjustable current limit range
VIN = 12 V, fSW = 500 kHz,
see Figure 18
1
4.1
A
ILIM3
Buck 3 adjustable current limit range
VIN = 12 V, fSW = 500 kHz,
see Figure 19
1.3
4.4
A
Submit Documentation Feedback
Copyright © 2010–2018, Texas Instruments Incorporated
Product Folder Links: TPS65251
7
TPS65251
SLVSAA4G – JUNE 2010 – REVISED FEBRUARY 2018
www.ti.com
7.6 Typical Characteristics
TA = 25°C, VIN = 12 V, fSW = 500 kHz (unless otherwise noted)
fSW = 500 kHz, VOUT = 3.3 V, L= 4.7 µH, DCR = 28 mΩ
fSW = 500 kHz, VOUT = 1.2 V, L = 4.7 µH, DCR = 28 mΩ
Figure 1. BUCK1 Efficiency
Figure 2. BUCK1 Efficiency
fSW = 500 kHz, VOUT = 3.3 V, L = 4.7 µH, DCR = 28 mΩ
(Also Applies to Buck 3)
CO = 22 µF, VOUT = 3.3 V, L = 4.7 µH
Figure 4. BUCK2 Efficiency
Figure 3. BUCK1 Efficiency Low-Power Enabled
fSW = 500 kHz, VOUT = 1.8 V, L = 4.7 µH, DCR = 28 mΩ
(Also Applies to Buck 3)
Figure 5. BUCK2 Efficiency
8
VOUT = 2.5 V, L = 4.7 µF
Figure 6. BUCK2 Efficiency Low-Power Enabled
Submit Documentation Feedback
Copyright © 2010–2018, Texas Instruments Incorporated
Product Folder Links: TPS65251
TPS65251
www.ti.com
SLVSAA4G – JUNE 2010 – REVISED FEBRUARY 2018
Typical Characteristics (continued)
TA = 25°C, VIN = 12 V, fSW = 500 kHz (unless otherwise noted)
VOUT = 2.5 V, L = 4.7 µH, DCR = 28 mΩ
(Also Applies to Buck 2)
VOUT = 2.5 V, L = 4.7 µF
Figure 7. BUCK3 Efficiency
Figure 8. BUCK3 Efficiency Low-Power Enabled
Figure 9. BUCK1 Line Regulation
Figure 10. BUCK1 Load Regulation
Figure 11. BUCK2 Line Regulation
Figure 12. BUCK2 Load Regulation
Submit Documentation Feedback
Copyright © 2010–2018, Texas Instruments Incorporated
Product Folder Links: TPS65251
9
TPS65251
SLVSAA4G – JUNE 2010 – REVISED FEBRUARY 2018
www.ti.com
Typical Characteristics (continued)
TA = 25°C, VIN = 12 V, fSW = 500 kHz (unless otherwise noted)
Figure 13. BUCK3 Line Regulation
10
Submit Documentation Feedback
Figure 14. BUCK3 Load Regulation
Copyright © 2010–2018, Texas Instruments Incorporated
Product Folder Links: TPS65251
TPS65251
www.ti.com
SLVSAA4G – JUNE 2010 – REVISED FEBRUARY 2018
8 Detailed Description
8.1 Overview
TPS65251 is a power management IC with three step-down buck converters. Both high-side and low-side
MOSFETs are integrated to provide fully synchronous conversion with higher efficiency. TPS65251 can support
4.5-V to 18-V input supply, high load current, 300-kHz to 2.2-MHz clocking. The buck converters have an
optional PSM mode, which can improve power dissipation during light loads. Alternatively, the device implements
a constant frequency mode by connecting the LOW_P pin to ground. The wide switching frequency of 300 kHz to
2.2 MHz allows for efficiency and size optimization. The switching frequency is adjustable by selecting a resistor
to ground on the ROSC pin. The SYNC pin also provides a means to synchronize the power converter to an
external signal. Input ripple is reduced by 180 degree out-of-phase operation between Buck 1 and Buck 2. Buck
3 operates in phase with Buck 2.
All three buck converters have peak current mode control which simplifies external frequency compensation. A
traditional type II compensation network can stabilize the system and achieve fast transient response. Moreover,
an optional capacitor in parallel with the upper resistor of the feedback divider provides one more zero and
makes the crossover frequency over 100 kHz.
Each buck converter has an individual current limit, which can be set up by a resistor to ground from the RLIM
pin. The adjustable current limiting enables high efficiency design with smaller and less expensive inductors.
The device has two built-in LDO regulators. During a standby mode, the 3.3-V LDO and the 6.5-V LDO can be
used to drive MCU and other active loads. By this, the system is able to turn off the three buck converters and
improve the standby efficiency.
The device has a powergood comparator monitoring the output voltage. Each converter has its own soft-start and
enable pins, which provide independent control and programmable soft-start.
8.2 Functional Block Diagram
AGND
ROSC
V3V
V7V
OSC
INTERNAL
VOLTAGE RAILS
SYNC
12V DC Supply
BST1
VIN1
LX1
Vout BUCK1
LX1
SS1
BUCK1
FB1
from enable logic EN1
COMP1
Rlim1
BST2
LX2
VIN2
Vout BUCK2
LX2
SS2
BUCK2
FB2
from enable logic EN2
COMP2
Rlim2
BST3
VIN3
LX3
SS3
from enable logic
Vout BUCK3
LX3
BUCK3
EN3
FB3
Rlim3
COMP3
VIN
PFM mode
PGOOD
LOW_P
PG
Generator
GND
Copyright © 2018, Texas Instruments Incorporated
Submit Documentation Feedback
Copyright © 2010–2018, Texas Instruments Incorporated
Product Folder Links: TPS65251
11
TPS65251
SLVSAA4G – JUNE 2010 – REVISED FEBRUARY 2018
www.ti.com
8.3 Feature Description
8.3.1 Adjustable Switching Frequency
To select the internal switching frequency connect a resistor from ROSC to ground. Figure 15 shows the required
resistance for a given switching frequency.
Figure 15. ROSC vs Switching Frequency
5OSC N:
u ¦ 0+]
±
(1)
For operation at 800 kHz a 230-kΩ resistor is required.
8.3.2 Synchronization
The status of the SYNC pin will be ignored during start-up and the TPS65251’s control will only synchronize to
an external signal after the PGOOD signal is asserted. The status of the SYNC pin will be ignored during start-up
and the TPS65251 will only synchronize to an external clock if the PGOOD signal is asserted. When
synchronization is applied, the PWM oscillator frequency must be lower than the sync pulse frequency to allow
the external signal trumping the oscillator pulse reliably. When synchronization is not applied, the SYNC pin
should be connected to ground.
8.3.3 Out-of-Phase Operation
Buck 1 has a low conduction resistance compared to Buck 2 and 3. Normally Buck 1 is used to drive higher
system loads. Buck 2 and 3 are used to drive some peripheral loads like I/O and line drivers . The combination of
loads from Buck 2 and 3 may be on par with the load of Buck 1. To reduce input ripple current, Buck 2 operates
in phase with Buck 3; Buck 1 and Buck 2 operate 180° out-of-phase. This enables the system, having less input
ripple, to lower component cost, save board space and reduce EMI.
8.3.4 Delayed Start-Up
If a delayed start-up is required on any of the buck converters fit a ceramic capacitor to the ENx pins. The delay
added is about 1.67 ms per nF connected to the pin. Note that the EN pins have a weak 1-µA pullup to the 3V3
rail.
8.3.5 Soft-Start Time
The device has an internal pullup current source of 5 µA that charges an external slow start capacitor to
implement a slow start time. Equation 2 shows how to select a slow start capacitor based on an expected slow
start time. The voltage reference (VREF) is 0.8 V and the slow start charge current (Iss) is 5 µA. The soft-start
circuit requires 1 nF per 200 µS to be connected at the SS pin. A 1-ms soft-start time is implemented for all
converters fitting 4.7 nF to the relevant pins.
12
Submit Documentation Feedback
Copyright © 2010–2018, Texas Instruments Incorporated
Product Folder Links: TPS65251
TPS65251
www.ti.com
SLVSAA4G – JUNE 2010 – REVISED FEBRUARY 2018
Feature Description (continued)
tSS (ms)
§ C (nF) ·
VREF (V) u ¨ SS
¸
© ISS (µA) ¹
(2)
8.3.6 Adjusting the Output Voltage
The output voltage is set with a resistor divider from the output node to the FB pin. TI recommends to use 1%
tolerance or better divider resistors. In order to improve efficiency at light load, start with 40.2 kΩ for the R1
resistor and use the Equation 3 to calculate R2.
R2
§ 0.8 V
·
R1 u ¨
¸
9¹
© 9O ±
(3)
Vo
TPS65251
R1
FB
R2
0.8V
+
Figure 16. Voltage Divider Circuit
8.3.7 Input Capacitor
Use 10-µF X7R/X5R ceramic capacitors at the input of the converter inputs. These capacitors should be
connected as close as physically possible to the input pins of the converters.
8.3.8 Bootstrap Capacitor
The device has three integrated boot regulators and requires a small ceramic capacitor between the BST and LX
pin to provide the gate drive voltage for the high-side MOSFET. The value of the ceramic capacitor should be
0.047 µF. A ceramic capacitor with an X7R or X5R grade dielectric is recommended because of the stable
characteristics over temperature and voltage.
8.3.9 Error Amplifier
The device has a transconductance error amplifier. The frequency compensation network is connected between
the COMP pin and ground.
8.3.10 Loop Compensation
TPS65251 is a current mode control DC - DC converter. The error amplifier is a transconductance amplifier with
a of 130 µA/V.
8.3.11 Slope Compensation
The device has a built-in slope compensation ramp. The slope compensation can prevent subharmonic
oscillations in peak current mode control.
8.3.12 Powergood
The PGOOD pin is an open-drain output. The PGOOD pin is pulled low when any buck converter is pulled below
85% of the nominal output voltage. The PGOOD is pulled up when all three buck converters’ outputs are more
than 90% of its nominal output voltage and reset time of 1 second elapses. The polarity of the PGOOD is active
high.
Submit Documentation Feedback
Copyright © 2010–2018, Texas Instruments Incorporated
Product Folder Links: TPS65251
13
TPS65251
SLVSAA4G – JUNE 2010 – REVISED FEBRUARY 2018
www.ti.com
Feature Description (continued)
8.3.13 Current Limit Protection
Figure 17 shows the (peak) inductor current limit for Buck 1. The typical limit can be approximated with the
following graph.
Figure 17. Buck 1
Figure 18 shows the (peak) inductor current limit for Buck 2. The typical limit can be approximated with the
following graph.
Figure 18. Buck 2
Figure 19 shows the (peak) inductor current limit for Buck 3. The typical limit can be approximated with the
following graph.
14
Submit Documentation Feedback
Copyright © 2010–2018, Texas Instruments Incorporated
Product Folder Links: TPS65251
TPS65251
www.ti.com
SLVSAA4G – JUNE 2010 – REVISED FEBRUARY 2018
Feature Description (continued)
Figure 19. Buck 3
All converters operate in hiccup mode: Once an over-current lasting more than 10 ms is sensed in any of the
converters, all the converters will shut down for 10 ms and then the start-up sequencing will be tried again. If the
overload has been removed, the converter will ramp up and operate normally. If this is not the case the converter
will see another over-current event and shuts-down again repeating the cycle (hiccup) until the failure is cleared.
If an overload condition lasts for less than 10 ms, only the relevant converter affected will go into and out of
under-voltage and no global hiccup mode will occur. The converter will be protected by the cycle-by-cycle current
limit during that time.
8.3.14 Overvoltage Transient Protection
The device incorporates an overvoltage transient protection (OVP) circuit to minimize voltage overshoot. The
OVP feature minimizes the output overshoot by implementing a circuit to compare the FB pin voltage to OVP
threshold which is 109% of the internal voltage reference. If the FB pin voltage is greater than the OVP threshold,
the high-side MOSFET is disabled preventing current from flowing to the output and minimizing output overshoot.
When the FB voltage drops below the lower OVP threshold which is 107%, the high-side MOSFET is allowed to
turn on the next clock cycle.
8.3.15 Thermal Shutdown
The device implements an internal thermal shutdown to protect itself if the junction temperature exceeds 160°C.
The thermal shutdown forces the device to stop switching when the junction temperature exceeds thermal trip
threshold. Once the die temperature decreases below 140°C, the device reinitiates the power-up sequence. The
thermal shutdown hysteresis is 20°C.
8.4 Device Functional Modes
8.4.1 Low-Power Mode Operation
By pulling the LOW_P pin high all converters will operate in pulse-skipping mode, greatly reducing the overall
power consumption at light and no load conditions. Although each buck converter has a skip comparator that
makes sure regulation is not lost when a heavy load is applied and low-power mode is enabled, system design
needs to make sure that the LP pin is pulled low for continuous loading in excess of 100 mA.
When low-power is implemented, the peak inductor current used to charge the output capacitor is:
Submit Documentation Feedback
Copyright © 2010–2018, Texas Instruments Incorporated
Product Folder Links: TPS65251
15
TPS65251
SLVSAA4G – JUNE 2010 – REVISED FEBRUARY 2018
www.ti.com
Device Functional Modes (continued)
IN - VOUT
ILIMIT = 0.25 · TSLEEP_CLK · V
¾
L
(4)
Where TSLEEP_CLK is half of the converter switching period, 2/fSW.
The size of the additional ripple added to the output is:
1 ·
DVOUT = ¾
C
(
VIN
L · ILIMIT2
ILOAD
- ¾
¾· ¾
2
VOUT · (VIN - VOUT) fSLEEP_CLK
)
(5)
And the peak output voltage during low-power operation is:
DVOUT
VOUT_PK = VOUT + ¾
2
(6)
VOUT_PK
VOUT
Figure 20. Peak Output Voltage During Low-Power Operation
16
Submit Documentation Feedback
Copyright © 2010–2018, Texas Instruments Incorporated
Product Folder Links: TPS65251
TPS65251
www.ti.com
SLVSAA4G – JUNE 2010 – REVISED FEBRUARY 2018
9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The device is triple synchronous step down dc/dc converter. It is typically used to convert a higher dc voltage to
lower dc voltages with continuous available output current of 3A/2A/2A.
9.2 Typical Application
The following design procedure can be used to select component values for the TPS65251.
1.8V 2A V2
R22
C1
20K
C24
4700pF
C21
22uF
10uF
C2
PG
LP FB2
3.3uF
C25
C26
100pF
4.7nF
R23
R20
C37
40.2K
4.7nF
C33
R33
4.7nF
120K
12.7K
L2
47nF
32K
4.7uH
L1
1.2V 3A V1
4.7uH
CMP2
SS2
RLIM2
GND
LOW_P
FB2
LX1
VIN1
BST1
VIN1
C11
22uF
C10
47nF
EN1
C17
4.7nF
R13
100K
R1
R31
R21
C20
VIN2
VIN2
LX2
LX2
LX1
SS1
RLIM1
VIN3
BST3
EN3
SYNC
ROSC
FB1
CMP1
VIN3
47nF
R30
4.7nF
TPS65251
SS3
CMP3
FB3
C31
22uF C30
GND
LX3
LX3
RLIM3
L3
C34
R32
4700pF
20K
C36
FB2
C27
EN2
BST2
VIN
VIN
4.7uH
40.2K
C23
4.7nF
VIN
VIN
V3 3.3V 2A
V7V
PGOOD
GND
AGND
V3V
150K
383K
4.7nF
R12
C14
20K
4700pF
C13
R10
4.7nF
40.2K
C16
4.7nF
R11
80.6K
C15
100pF
C35
100pF
Copyright © 2018, Texas Instruments Incorporated
A.
VIN pins require local decoupling capacitors.
Figure 21. Typical Application Circuit
9.2.1 Design Requirements
DESIGN PARAMETERS
VALUE
Output voltage
1.2 V
Transient response 0.5-A to 2-A load step
120 mV
Maximum output current
3A
Submit Documentation Feedback
Copyright © 2010–2018, Texas Instruments Incorporated
Product Folder Links: TPS65251
17
TPS65251
SLVSAA4G – JUNE 2010 – REVISED FEBRUARY 2018
www.ti.com
DESIGN PARAMETERS
VALUE
Input voltage
12 V nom, 9.6 V to 14.4 V
Output voltage ripple
< 30 mV p-p
Switching frequency
500 kHz
9.2.2 Detailed Design Procedure
9.2.2.1 Loop Compensation Circuit
A typical compensation circuit could be type II (Rc and Cc) to have a phase margin between 60 and 90 degrees,
or type III (Rc, Cc and Cff) to improve the converter transient response. CRoll adds a high frequency pole to
attenuate high-frequency noise when needed. It may also prevent noise coupling from other rails if there is
possibility of cross coupling in between rails when layout is very compact.
Vo
iL
Co
RL
Gm=10A/V
RESR
Cff
R1
Current Sense
I/V Gain
FBx
g M = 130 u
Vref = 0.8V
COMPx
R2
Rc
CRoll
Cc
Figure 22. Loop Compensation
To calculate the external compensation components use Table 1:
Table 1. Design Guideline for the Loop Compensation
TYPE II CIRCUIT
TYPE III CIRCUIT
Select switching frequency that is appropriate for
application depending on L, C sizes, output ripple, EMI
concerns and etc. Switching frequencies between 500 kHz
and 1 MHz give best trade off between performance and
cost. When using smaller L and Cs, switching frequency
can be increased. To optimize efficiency, switching
frequency can be lowered.
Type III circuit recommended for
switching frequencies higher than
500 kHz.
Select cross over frequency (fc) to be less than 1/5 to 1/10
of switching frequency.
Set and calculate Rc.
18
Suggested
fc = fs/10
RC =
Suggested
fc = fs/10
2p ´ ƒc ´ VO ´ CO
gM ´ Vref ´ gmps
Submit Documentation Feedback
RC =
(7)
2p ´ ƒc ´ CO
gM ´ gmps
(8)
Copyright © 2010–2018, Texas Instruments Incorporated
Product Folder Links: TPS65251
TPS65251
www.ti.com
SLVSAA4G – JUNE 2010 – REVISED FEBRUARY 2018
Table 1. Design Guideline for the Loop Compensation (continued)
TYPE II CIRCUIT
Calculate Cc by placing a compensation zero at or before
the converter dominant pole
¦S
1
CO u RL u 2S
Cc =
(9)
Add CRoll if needed to remove large signal coupling to high
impedance COMP node. Make sure that
1
2 u S u RC u CRoll
¦SRoll
RL ´ Co
Rc
CRoll
(12)
Resr u CO
RC
TYPE III CIRCUIT
Cc =
(10)
CRoll
(13)
RL ´ Co
Rc
Resr u CO
RC
(11)
(14)
is at least twice the cross over frequency.
Calculate Cff compensation zero at low frequency to boost
the phase margin at the crossover frequency. Make sure
that the zero frequency (fzff is smaller than soft-start
equivalent frequency (1/Tss).
NA
C¦¦
1
u S u ¦] ¦¦ u 5
(15)
9.2.2.2 Selecting the Switching Frequency
The first step is to decide on a switching frequency for the regulator. Typically, you will want to choose the
highest switching frequency possible since this will produce the smallest solution size. The high switching
frequency allows for lower valued inductors and smaller output capacitors compared to a power supply that
switches at a lower frequency. However, the highest switching frequency causes extra switching losses, which
hurt the converter’s performance. The converter is capable of running from 300 kHz to 2.2 MHz. Unless a small
solution size is an ultimate goal, a moderate switching frequency of 500 kHz is selected to achieve both a small
solution size and a high efficiency operation. Using Figure 15, R1 is determined to be 383 kΩ
9.2.2.3 Output Inductor Selection
To calculate the value of the output inductor, use Equation 16. KIND is a coefficient that represents the amount
of inductor ripple current relative to the maximum output current. In general, KIND is normally from 0.1 to 0.3 for
the majority of applications.
For this design example, use KIND = 0.2 and the inductor value is calculated to be 3.6 µH. For this design, a
nearest standard value was chosen: 4.7 µH. For the output filter inductor, it is important that the RMS current
and saturation current ratings not be exceeded. The RMS and peak inductor current can be found from
Equation 17 and Equation 18.
Vin - Vout
Vout
Lo =
´
Io ´ K ind
Vin ´ ƒsw
(16)
Iripple =
Vin - Vout
Vout
´
Lo
Vin ´ fsw
ILrms = Io2 +
ILpeak = Iout +
(17)
1 æ Vo ´ (Vinmax - Vo) ö
´ç
÷
12 è Vinmax ´ Lo ´ ƒsw ø
2
(18)
Iripple
2
(19)
9.2.2.4 Output Capacitor
There are two primary considerations for selecting the value of the output capacitor. The output capacitors are
selected to meet load transient and output ripple’s requirements.
Equation 20 gives the minimum output capacitance to meet the transient specification. For this example,
LO = 4.7 µH, ΔIOUT = 1.5 A – 0.75 A = 0.75 A and ΔVOUT = 120 mV. Using these numbers gives a minimum
capacitance of 18 µF. A standard 22-µF ceramic capacitor is chose in the design.
Co >
DIOUT 2 ´ Lo
Vout ´ DVout
(20)
Submit Documentation Feedback
Copyright © 2010–2018, Texas Instruments Incorporated
Product Folder Links: TPS65251
19
TPS65251
SLVSAA4G – JUNE 2010 – REVISED FEBRUARY 2018
www.ti.com
Equation 21 calculates the minimum output capacitance needed to meet the output voltage ripple specification.
Where fsw is the switching frequency, VRIPPLE is the maximum allowable output voltage ripple, and IRIPPLE is the
inductor ripple current. In this case, the maximum output voltage ripple is 30 mV. From Equation 17, the output
current ripple is 0.46 A. From Equation 21, the minimum output capacitance meeting the output voltage ripple
requirement is 1.74 µF.
1
1
´
Co >
8 ´ ƒsw Vripple
Iripple
(21)
Additional capacitance de-rating for aging, temperature and DC bias should influence this minimum value. For
this example, one 22-µF, 6.3-V X7R ceramic capacitor with 3 mΩ of ESR will be used.
9.2.2.5 Input Capacitor
A minimum 10-µF X7R/X5R ceramic input capacitor is recommended to be added between VIN and GND. These
capacitors should be connected as close as physically possible to the input pins of the converters as they handle
the RMS ripple current shown in Equation 22. For this example, IOUT = 3 A, VOUT = 1.2 V, VINmin = 9.6 V, from
Equation 22, the input capacitors must support a ripple current of 0.99 A RMS.
Icirms = Iout ´
(Vinmin - Vout )
Vout
´
Vinmin
Vinmin
(22)
The input capacitance value determines the input ripple voltage of the regulator. The input voltage ripple can be
calculated using Equation 23. Using the design example values, IOUTmax = 3 A, CIN = 10 µF, fSW = 500 kHz, yields
an input voltage ripple of 150 mV.
Iout max ´ 0.25
DVin =
Cin ´ ƒsw
(23)
9.2.2.6 Soft-Start Capacitor
The soft-start capacitor determines the minimum amount of time it will take for the output voltage to reach its
nominal programmed value during power-up. This is useful if the output capacitance is very large and would
require large amounts of current to quickly charge the capacitor to the output voltage level.
The soft-start capacitor value can be calculated using Equation 24. In this example, the converter’s soft-start time
is 0.8 ms. In TPS65251, Iss is 5 µA and Vref is 0.8 V. From Equation 24, the soft-start capacitance is 5 nF. A
standard 4.7-nF ceramic capacitor is chosen in this design. In this example, C16 is 4.7nF
Tss(ms) ´ Iss(µA)
Css(nF) =
Vref(V)
(24)
9.2.2.7 Bootstrap Capacitor Selection
A 0.047-µF ceramic capacitor must be connected between the BST to LX pin for proper operation. It is
recommended to use a ceramic capacitor with X5R or better grade dielectric. The capacitor should have 10-V or
higher voltage rating.
9.2.2.8 Adjustable Current Limiting Resistor Selection
The converter uses the voltage drop on the high-side MOSFET to measure the inductor current. The over current
protection threshold can be optimized by changing the trip resistor. Figure 17 governs the threshold of over
current protection for Buck 1. When selecting a resistor, do not exceed the graph limits. In this example, the over
current threshold is 3.2 A. In order to prevent a premature limit trip, the minimum line is used and the resistor is
100 kΩ.
When setting high-side current limit to large current values, ensure that the additional load immediately prior to
an overcurrent condition will not cause the switching node voltage to exceed 20 V. Additionally, ensure during
worst case operation, with all bucks loaded immediately prior to current limit, the maximum virtual junction
temperature of the device does not exceed 125°C.
20
Submit Documentation Feedback
Copyright © 2010–2018, Texas Instruments Incorporated
Product Folder Links: TPS65251
TPS65251
www.ti.com
SLVSAA4G – JUNE 2010 – REVISED FEBRUARY 2018
9.2.2.9 Output Voltage and Feedback Resistors Selection
For the example design, 40.2 kΩ was selected for R10. Vout is 1.2 V, Vref = 0.8 V. Using Equation 25, R11 is
calculated as 80.4 kΩ. A standard 80.6-kΩ resistor is chose in this design.
Vout - Vref
´ R10
R11 =
Vref
(25)
9.2.2.10 Compensation
A type-II compensation circuit is adequate for the converter to have a phase margin between 60 and 90 degrees.
The following equations show the procedure of designing a peak current mode control dc/dc converter.
The compensation design takes the following steps:
1. Set up the anticipated cross-over frequency. In this example, the anticipated cross-over frequency (fc) is 65
kHz. The power stage gain (gmPS ) is 10 A/V and the GM amplifier gain (gM ) is 130 µA/V.
2p ´ ƒc ´ Vo ´ Co
R12 =
gM ´ Vref ´ gmps
(26)
2. Place compensation zero at low frequency to boost the phase margin at the crossover frequency. From the
procedures above, the compensation network includes a 20-kΩ resistor (R12) and a 4700-pF capacitor (C1).
3. An additional pole can be added to attenuate high frequency noise.
From the procedures above, the compensation network includes a 20-kΩ resistor (R12) and a 4700-pF capacitor
(C14).
9.2.2.11 3.3-V and 6.5-V LDO Regulators
The following ceramic capacitor (X7R/X5R) should be connected as close as possible to the described pins:
• 10 µF for V7V pin 28
• 3.3 µF to 10 µF for V3V pin 29
9.2.3 Application Curves
Figure 23. BUCK1 Start-Up
LO = 4.7 µH, CO = 22 µF, VOUT = 3.3 V, 2 A
Figure 24. BUCK1 Ripple
VOUT = 3.3 V, 1.5 A, fSW = 800 kHz, 20 mV/div
Submit Documentation Feedback
Copyright © 2010–2018, Texas Instruments Incorporated
Product Folder Links: TPS65251
21
TPS65251
SLVSAA4G – JUNE 2010 – REVISED FEBRUARY 2018
22
www.ti.com
Figure 25. BUCK1 Transient Load Response
LO = 4.7 µH, CO = 22 µF, VOUT = 3.3 V, ∆I = 1 A to 1.5 A, 100
mV/div
Figure 26. BUCK1 Transient Supply Response
LO = 4.7 µH, CO = 22 µF, VOUT = 3.3 V, ∆VIN = 8 V to 16.5 V,
20 mV/div
Figure 27. BUCK2 Start-Up
LO = 4.7 µH, CO = 22 µF, VOUT = 2.5 V, 1.5 A
Figure 28. BUCK2 Ripple
VOUT = 2.5 V, 1.5 A, fSW = 800 kHz, 10 mV/div
Figure 29. BUCK2 Transient Load Response
LO = 4.7 µH, CO = 22 µF, VOUT = 2.5 V, ∆I = 1 A to 1.5 A
Figure 30. BUCK2 Transient Supply Response
LO = 4.7 µH, CO = 22 µF, VOUT = 2.5 V, ∆VIN = 9 V to 8 V
Submit Documentation Feedback
Copyright © 2010–2018, Texas Instruments Incorporated
Product Folder Links: TPS65251
TPS65251
www.ti.com
SLVSAA4G – JUNE 2010 – REVISED FEBRUARY 2018
Figure 31. BUCK3 Start-Up
VOUT = 7.5 V, 0.7 A
Figure 32. BUCK3 Ripple
VOUT = 7.5 V, 0.5 A, fSW = 800 kHz 10 mV/div
Figure 33. BUCK3 Transient Load Response
LO = 4.7 µH, CO = 22 µF, VOUT = 7.5 V, ∆I = 1 A to 1.5 A
Figure 34. BUCK3 Transient Supply Response
VOUT = 2.5 V, ∆VIN = 9 V to 8 V
Submit Documentation Feedback
Copyright © 2010–2018, Texas Instruments Incorporated
Product Folder Links: TPS65251
23
TPS65251
SLVSAA4G – JUNE 2010 – REVISED FEBRUARY 2018
www.ti.com
10 Power Supply Recommendations
The device is designed to operate from an input voltage supply range between 4.5 V and 18 V. This input power
supply should be well regulated. If the input supply is located more than a few inches from the TPS65251
converter, additional bulk capacitance may be required in addition to the ceramic bypass capacitors. An
electrolytic capacitor with a value of 47 μF is a typical choice.
11 Layout
11.1 Layout Guidelines
Layout is a critical portion of PMIC designs.
• Place VOUT, and LX on the top layer and an inner power plane for VIN.
• Fit also on the top layer connections for the remaining pins of the PMIC and a large top side area filled with
ground.
• The top layer ground area sould be connected to the internal ground layer(s) using vias at the input bypass
capacitor, the output filter cpacitor and directly under the TPS65251 device to provide a thermal path from the
Powerpad land to ground.
• The AGND pin should be tied directly to the power pad under the IC and the power pad.
• For operation at full rated load, the top side ground area together with the internal ground plane, must provide
adequate heat dissipating area.
• There are several signals paths that conduct fast changing currents or voltages that can interact with stray
inductance or parasitic capacitance to generate noise or degrade the power supplies performance. To help
eliminate these problems, the VIN pin should be bypassed to ground with a low ESR ceramic bypass
capacitor with X5R or X7R dielectric. Care should be taken to minimize the loop area formed by the bypass
capacitor connections, the VIN pins, and the ground connections. Since the LX connection is the switching
node, the output inductor should be located close to the LX pins, and the area of the PCB conductor
minimized to prevent excessive capacitive coupling.
• The output filter capacitor ground should use the same power ground trace as the VIN input bypass capacitor.
Try to minimize this conductor length while maintaining adequate width.
• The compensation should be as close as possible to the COMP pins. The COMP and OSC pins are sensitive
to noise so the components associated to these pins should be located as close as possible to the IC and
routed with minimal lengths of trace.
24
Submit Documentation Feedback
Copyright © 2010–2018, Texas Instruments Incorporated
Product Folder Links: TPS65251
TPS65251
www.ti.com
SLVSAA4G – JUNE 2010 – REVISED FEBRUARY 2018
11.2 Layout Example
Figure 35. Layout Schematic
11.3 Power Dissipation
The total power dissipation inside TPS65251 should not to exceed the maximum allowable junction temperature
of 125°C. The maximum allowable power dissipation is a function of the thermal resistance of the package (RJA)
and ambient temperature.
To
1.
2.
3.
calculate the temperature inside the device under continuous loading use the following procedure.
Define the set voltage for each converter.
Define the continuous loading on each converter. Make sure do not exceed the converter maximum loading.
Determine from the graphs below the expected losses (Y axis) in watts per converter inside the device. The
losses depend on the input supply, the selected switching frequency, the output voltage and the converter
chosen.
4. To calculate the maximum temperature inside the IC use the following formula:
THOT _ SPOT = TA + PDIS ´ R qJA
where
•
•
•
TA is the ambient temperature
PDIS is the sum of losses in all converters
θJA is the junction to ambient thermal impedance of the device and it is heavily dependant on board layout (27)
Submit Documentation Feedback
Copyright © 2010–2018, Texas Instruments Incorporated
Product Folder Links: TPS65251
25
TPS65251
SLVSAA4G – JUNE 2010 – REVISED FEBRUARY 2018
www.ti.com
Power Dissipation (continued)
VO (from top to bottom) = 5 V , 3.3 V, 2.5 V, 1.8 V, 1.2 V
Figure 36. Buck 1 Losses (W) vs Output Current
VIN = 12 V, ƒSW = 500 kHz
VO (from top to bottom) = 5 V , 3.3 V, 2.5 V, 1.8 V, 1.2 V
Figure 38. Buck 2 and 3 Losses (W) vs Output Current
VIN = 12 V, ƒSW = 500 kHz
26
VO (from top to bottom) = 5 V , 3.3 V, 2.5 V, 1.8 V, 1.2 V
Figure 37. Buck 1 Losses (W) vs Output Current
VIN = 12 V, ƒSW = 1.1 MHz
VO (from top to bottom) = 5 V , 3.3 V, 2.5 V, 1.8 V, 1.2 V
Figure 39. Buck 2 and 3 Losses (W) vs Output Current
VIN = 12 V, ƒSW = 1.1 MHz
Submit Documentation Feedback
Copyright © 2010–2018, Texas Instruments Incorporated
Product Folder Links: TPS65251
TPS65251
www.ti.com
SLVSAA4G – JUNE 2010 – REVISED FEBRUARY 2018
12 Device and Documentation Support
12.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Submit Documentation Feedback
Copyright © 2010–2018, Texas Instruments Incorporated
Product Folder Links: TPS65251
27
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
905-6525100
ACTIVE
VQFN
RHA
40
2500
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
TPS
65251
TPS65251RHAR
ACTIVE
VQFN
RHA
40
2500
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
TPS
65251
TPS65251RHAT
ACTIVE
VQFN
RHA
40
250
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
TPS
65251
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
工商网监
湘ICP备2023018690号
